coreboot November 2008

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[PATCH] v3: Poison RAM
by Carl-Daniel Hailfinger 19 Nov '08

19 Nov '08

Poison RAM and continuously report on status if stack checking is enabled. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: corebootv3-poison/include/arch/x86/cpu.h =================================================================== --- corebootv3-poison/include/arch/x86/cpu.h (Revision 1046) +++ corebootv3-poison/include/arch/x86/cpu.h (Arbeitskopie) @@ -329,5 +329,12 @@ void setup_resource_map(const struct rmap *rm, u32 max); EXPORT_SYMBOL(setup_resource_map); +#ifdef CONFIG_CHECK_STACK_USAGE +/* POISON_BYTE could be a special value like 0x6b. Just make sure the stage0 + * code fills the complete CAR area with it. And the stack switching needs to + * overwrite the unused parts of the stack with POISON_BYTE as well. + */ +#define POISON_BYTE 0x6b +#endif #endif /* ARCH_X86_CPU_H */ Index: corebootv3-poison/lib/stage2.c =================================================================== --- corebootv3-poison/lib/stage2.c (Revision 1046) +++ corebootv3-poison/lib/stage2.c (Arbeitskopie) @@ -28,6 +28,9 @@ #include <device/device.h> #include <tables.h> +/* FIXME: Figure out the proper include file for this function. */ +void find_lowest_unpoisoned_memory(int msg_level); + /** * Main function of the DRAM part of coreboot. * @@ -46,6 +49,9 @@ void *mbi; post_code(POST_STAGE2_BEGIN); +#ifdef CONFIG_CHECK_STACK_USAGE + find_lowest_unpoisoned_memory(BIOS_DEBUG); +#endif dev_init(); /* Phase 1 was console init and making printk work. Both functions are @@ -54,6 +60,9 @@ post_code(POST_STAGE2_PHASE1_START); dev_phase1(); show_all_devs(BIOS_DEBUG, "After phase 1."); +#ifdef CONFIG_CHECK_STACK_USAGE + find_lowest_unpoisoned_memory(BIOS_DEBUG); +#endif /* Here is where weird stuff like init_timer handling should be * done. This is for ANYTHING that might have to happen before @@ -62,6 +71,9 @@ post_code(POST_STAGE2_PHASE2_START); dev_phase2(); show_all_devs(BIOS_DEBUG, "After phase 2."); +#ifdef CONFIG_CHECK_STACK_USAGE + find_lowest_unpoisoned_memory(BIOS_DEBUG); +#endif /* Walk physical devices and add any dynamic devices to the * device tree. @@ -69,26 +81,41 @@ post_code(POST_STAGE2_PHASE3_START); dev_root_phase3(); show_all_devs_tree(BIOS_DEBUG, "After phase 3."); +#ifdef CONFIG_CHECK_STACK_USAGE + find_lowest_unpoisoned_memory(BIOS_DEBUG); +#endif /* Compute and assign the bus resources. */ post_code(POST_STAGE2_PHASE4_START); dev_phase4(); show_all_devs(BIOS_DEBUG, "After phase 4."); +#ifdef CONFIG_CHECK_STACK_USAGE + find_lowest_unpoisoned_memory(BIOS_DEBUG); +#endif /* Now actually enable devices on the bus. */ post_code(POST_STAGE2_PHASE5_START); dev_root_phase5(); show_all_devs(BIOS_DEBUG, "After phase 5."); +#ifdef CONFIG_CHECK_STACK_USAGE + find_lowest_unpoisoned_memory(BIOS_DEBUG); +#endif /* Initialize devices on the bus. */ post_code(POST_STAGE2_PHASE6_START); dev_phase6(); show_all_devs(BIOS_DEBUG, "After phase 6."); +#ifdef CONFIG_CHECK_STACK_USAGE + find_lowest_unpoisoned_memory(BIOS_DEBUG); +#endif /* Write tables to pass information to the payloads. */ post_code(POST_STAGE2_WRITE_TABLES); mbi = write_tables(); show_all_devs(BIOS_DEBUG, "After writing tables."); +#ifdef CONFIG_CHECK_STACK_USAGE + find_lowest_unpoisoned_memory(BIOS_DEBUG); +#endif return mbi; } Index: corebootv3-poison/arch/x86/Kconfig =================================================================== --- corebootv3-poison/arch/x86/Kconfig (Revision 1046) +++ corebootv3-poison/arch/x86/Kconfig (Arbeitskopie) @@ -246,5 +246,6 @@ The monitoring code is invoked from printk because printk is a leaf function and consumes quite a bit of stack for itself. This slows down booting a LOT. + This does not work in CAR stage until the asm is changed. endmenu Index: corebootv3-poison/arch/x86/stage1.c =================================================================== --- corebootv3-poison/arch/x86/stage1.c (Revision 1046) +++ corebootv3-poison/arch/x86/stage1.c (Arbeitskopie) @@ -106,11 +106,6 @@ } #ifdef CONFIG_CHECK_STACK_USAGE -/* STACKFILL_BYTE could be a special value like 0x6b. Just make sure the stage0 - * code fills the complete CAR area with it. And the stack switching needs to - * overwrite the unused parts of the stack with STACKFILL_BYTE as well. - */ -#define STACKFILL_BYTE 0x0 void check_stack() { unsigned long stacksize, i; @@ -121,7 +116,7 @@ stacksize = CAR_STACK_SIZE; lowestaddr = bottom_of_stack() - stacksize; for (i = 0; i < stacksize; i++) - if (lowestaddr[i] != STACKFILL_BYTE) + if (lowestaddr[i] != POISON_BYTE) break; global_vars()->loweststack = lowestaddr + i; } @@ -139,6 +134,22 @@ return; } +#ifdef CONFIG_CHECK_STACK_USAGE +void find_lowest_unpoisoned_memory(int msg_level) +{ + char *addr; + for (addr = NULL; (unsigned long)addr < 1024*1024; addr++) { + if (*addr != POISON_BYTE) { + printk(msg_level, "lowest unpoisoned mem is at %p\n", + addr); + dump_mem_range(msg_level, (unsigned char *)((unsigned long)addr & (~0xf)), 64); + break; + } + } + return; +} +#endif + /** cycles * provide 64-bit high precision counter * @returns Time in 64 bits @@ -290,6 +301,18 @@ */ void stage1_phase2(void) { +#ifdef CONFIG_CHECK_STACK_USAGE +#define max(a,b) (((a) > (b)) ? (a) : (b)) +#define min(a,b) (((a) < (b)) ? (a) : (b)) + /* We poison the area between 0x00000 and 1 MB, but we exclude + * the CAR area. If devices are mapped there, we lose. + */ + memset(NULL, POISON_BYTE, min(CONFIG_CARBASE, 1024 * 1024)); + if (CONFIG_CARBASE + CONFIG_CARSIZE < 1024 * 1024) + memset((void *)CONFIG_CARBASE + CONFIG_CARSIZE, POISON_BYTE, + 1024 * 1024 - (CONFIG_CARBASE + CONFIG_CARSIZE)); + find_lowest_unpoisoned_memory(BIOS_DEBUG); +#endif #ifdef CONFIG_CONSOLE_BUFFER /* Move the printk buffer to PRINTK_BUF_ADDR_RAM */ printk_buffer_move((void *)PRINTK_BUF_ADDR_RAM, PRINTK_BUF_SIZE_RAM); @@ -332,6 +355,10 @@ /* Provide an easy way to check whether RAM is available. */ global_vars()->ram_available = 1; +#ifdef CONFIG_CHECK_STACK_USAGE + find_lowest_unpoisoned_memory(BIOS_DEBUG); +#endif + // location and size of image. init_archive(&archive); @@ -354,6 +381,7 @@ #ifdef CONFIG_CHECK_STACK_USAGE printk(BIOS_DEBUG, "Before handoff to payload, lowest stack is %p\n", global_vars()->loweststack); + find_lowest_unpoisoned_memory(BIOS_DEBUG); #endif if (entry != (void*)-1) { /* Final coreboot call before handing off to the payload. */ -- http://www.hailfinger.org/ Index: corebootv3-poison/include/arch/x86/cpu.h =================================================================== --- corebootv3-poison/include/arch/x86/cpu.h (Revision 1046) +++ corebootv3-poison/include/arch/x86/cpu.h (Arbeitskopie) @@ -329,5 +329,12 @@ void setup_resource_map(const struct rmap *rm, u32 max); EXPORT_SYMBOL(setup_resource_map); +#ifdef CONFIG_CHECK_STACK_USAGE +/* POISON_BYTE could be a special value like 0x6b. Just make sure the stage0 + * code fills the complete CAR area with it. And the stack switching needs to + * overwrite the unused parts of the stack with POISON_BYTE as well. + */ +#define POISON_BYTE 0x6b +#endif #endif /* ARCH_X86_CPU_H */ Index: corebootv3-poison/lib/stage2.c =================================================================== --- corebootv3-poison/lib/stage2.c (Revision 1046) +++ corebootv3-poison/lib/stage2.c (Arbeitskopie) @@ -28,6 +28,9 @@ #include <device/device.h> #include <tables.h> +/* FIXME: Figure out the proper include file for this function. */ +void find_lowest_unpoisoned_memory(int msg_level); + /** * Main function of the DRAM part of coreboot. * @@ -46,6 +49,9 @@ void *mbi; post_code(POST_STAGE2_BEGIN); +#ifdef CONFIG_CHECK_STACK_USAGE + find_lowest_unpoisoned_memory(BIOS_DEBUG); +#endif dev_init(); /* Phase 1 was console init and making printk work. Both functions are @@ -54,6 +60,9 @@ post_code(POST_STAGE2_PHASE1_START); dev_phase1(); show_all_devs(BIOS_DEBUG, "After phase 1."); +#ifdef CONFIG_CHECK_STACK_USAGE + find_lowest_unpoisoned_memory(BIOS_DEBUG); +#endif /* Here is where weird stuff like init_timer handling should be * done. This is for ANYTHING that might have to happen before @@ -62,6 +71,9 @@ post_code(POST_STAGE2_PHASE2_START); dev_phase2(); show_all_devs(BIOS_DEBUG, "After phase 2."); +#ifdef CONFIG_CHECK_STACK_USAGE + find_lowest_unpoisoned_memory(BIOS_DEBUG); +#endif /* Walk physical devices and add any dynamic devices to the * device tree. @@ -69,26 +81,41 @@ post_code(POST_STAGE2_PHASE3_START); dev_root_phase3(); show_all_devs_tree(BIOS_DEBUG, "After phase 3."); +#ifdef CONFIG_CHECK_STACK_USAGE + find_lowest_unpoisoned_memory(BIOS_DEBUG); +#endif /* Compute and assign the bus resources. */ post_code(POST_STAGE2_PHASE4_START); dev_phase4(); show_all_devs(BIOS_DEBUG, "After phase 4."); +#ifdef CONFIG_CHECK_STACK_USAGE + find_lowest_unpoisoned_memory(BIOS_DEBUG); +#endif /* Now actually enable devices on the bus. */ post_code(POST_STAGE2_PHASE5_START); dev_root_phase5(); show_all_devs(BIOS_DEBUG, "After phase 5."); +#ifdef CONFIG_CHECK_STACK_USAGE + find_lowest_unpoisoned_memory(BIOS_DEBUG); +#endif /* Initialize devices on the bus. */ post_code(POST_STAGE2_PHASE6_START); dev_phase6(); show_all_devs(BIOS_DEBUG, "After phase 6."); +#ifdef CONFIG_CHECK_STACK_USAGE + find_lowest_unpoisoned_memory(BIOS_DEBUG); +#endif /* Write tables to pass information to the payloads. */ post_code(POST_STAGE2_WRITE_TABLES); mbi = write_tables(); show_all_devs(BIOS_DEBUG, "After writing tables."); +#ifdef CONFIG_CHECK_STACK_USAGE + find_lowest_unpoisoned_memory(BIOS_DEBUG); +#endif return mbi; } Index: corebootv3-poison/arch/x86/Kconfig =================================================================== --- corebootv3-poison/arch/x86/Kconfig (Revision 1046) +++ corebootv3-poison/arch/x86/Kconfig (Arbeitskopie) @@ -246,5 +246,6 @@ The monitoring code is invoked from printk because printk is a leaf function and consumes quite a bit of stack for itself. This slows down booting a LOT. + This does not work in CAR stage until the asm is changed. endmenu Index: corebootv3-poison/arch/x86/stage1.c =================================================================== --- corebootv3-poison/arch/x86/stage1.c (Revision 1046) +++ corebootv3-poison/arch/x86/stage1.c (Arbeitskopie) @@ -106,11 +106,6 @@ } #ifdef CONFIG_CHECK_STACK_USAGE -/* STACKFILL_BYTE could be a special value like 0x6b. Just make sure the stage0 - * code fills the complete CAR area with it. And the stack switching needs to - * overwrite the unused parts of the stack with STACKFILL_BYTE as well. - */ -#define STACKFILL_BYTE 0x0 void check_stack() { unsigned long stacksize, i; @@ -121,7 +116,7 @@ stacksize = CAR_STACK_SIZE; lowestaddr = bottom_of_stack() - stacksize; for (i = 0; i < stacksize; i++) - if (lowestaddr[i] != STACKFILL_BYTE) + if (lowestaddr[i] != POISON_BYTE) break; global_vars()->loweststack = lowestaddr + i; } @@ -139,6 +134,22 @@ return; } +#ifdef CONFIG_CHECK_STACK_USAGE +void find_lowest_unpoisoned_memory(int msg_level) +{ + char *addr; + for (addr = NULL; (unsigned long)addr < 1024*1024; addr++) { + if (*addr != POISON_BYTE) { + printk(msg_level, "lowest unpoisoned mem is at %p\n", + addr); + dump_mem_range(msg_level, (unsigned char *)((unsigned long)addr & (~0xf)), 64); + break; + } + } + return; +} +#endif + /** cycles * provide 64-bit high precision counter * @returns Time in 64 bits @@ -290,6 +301,18 @@ */ void stage1_phase2(void) { +#ifdef CONFIG_CHECK_STACK_USAGE +#define max(a,b) (((a) > (b)) ? (a) : (b)) +#define min(a,b) (((a) < (b)) ? (a) : (b)) + /* We poison the area between 0x00000 and 1 MB, but we exclude + * the CAR area. If devices are mapped there, we lose. + */ + memset(NULL, POISON_BYTE, min(CONFIG_CARBASE, 1024 * 1024)); + if (CONFIG_CARBASE + CONFIG_CARSIZE < 1024 * 1024) + memset((void *)CONFIG_CARBASE + CONFIG_CARSIZE, POISON_BYTE, + 1024 * 1024 - (CONFIG_CARBASE + CONFIG_CARSIZE)); + find_lowest_unpoisoned_memory(BIOS_DEBUG); +#endif #ifdef CONFIG_CONSOLE_BUFFER /* Move the printk buffer to PRINTK_BUF_ADDR_RAM */ printk_buffer_move((void *)PRINTK_BUF_ADDR_RAM, PRINTK_BUF_SIZE_RAM); @@ -332,6 +355,10 @@ /* Provide an easy way to check whether RAM is available. */ global_vars()->ram_available = 1; +#ifdef CONFIG_CHECK_STACK_USAGE + find_lowest_unpoisoned_memory(BIOS_DEBUG); +#endif + // location and size of image. init_archive(&archive); @@ -354,6 +381,7 @@ #ifdef CONFIG_CHECK_STACK_USAGE printk(BIOS_DEBUG, "Before handoff to payload, lowest stack is %p\n", global_vars()->loweststack); + find_lowest_unpoisoned_memory(BIOS_DEBUG); #endif if (entry != (void*)-1) { /* Final coreboot call before handing off to the payload. */

1 0

r3761 build service
by coreboot information 19 Nov '08

19 Nov '08

Dear coreboot readers! This is the automated build check service of coreboot. The developer "uwe" checked in revision 3761 to the coreboot source repository and caused the following changes: Change Log: Coding-style and whitespace fixes (also to make the code more similar the Lippert Cool SpaceRunner LX which is already in svn). Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Build Log: Compilation of supermicro:x6dhe_g has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3761&device=x6dhe_g&vendor… Compilation of tyan:s2885 has been fixed If something broke during this checkin please be a pain in uwe's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

1 0

subsystem IDs
by Myles Watson 19 Nov '08

19 Nov '08

This patch makes subsystem ids work. Here are the changes by file: device/pci_device.c: Only update IDs if: - The device is on the mainboard - The device has a Vendor ID and Device ID - The device has a set_subsystem function in ops_pci(dev) util/dtc/flattree.c: Make devices from the dts be on_mainboard. If they're plugged in, they shouldn't be in the dts. mainboard/amd/serengeti/dts: Add subsystem_vendor and subsystem_device. Build tested on Serengeti. Getting closer :) Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Thanks, Myles

3 4

r3761 - in trunk/coreboot-v2: src/mainboard/lippert/roadrunner-lx targets/lippert/roadrunner-lx
by svn＠coreboot.org 19 Nov '08

19 Nov '08

Author: uwe Date: 2008-11-19 14:42:14 +0100 (Wed, 19 Nov 2008) New Revision: 3761 Modified: trunk/coreboot-v2/src/mainboard/lippert/roadrunner-lx/Config.lb trunk/coreboot-v2/src/mainboard/lippert/roadrunner-lx/Options.lb trunk/coreboot-v2/src/mainboard/lippert/roadrunner-lx/cache_as_ram_auto.c trunk/coreboot-v2/src/mainboard/lippert/roadrunner-lx/chip.h trunk/coreboot-v2/src/mainboard/lippert/roadrunner-lx/irq_tables.c trunk/coreboot-v2/src/mainboard/lippert/roadrunner-lx/mainboard.c trunk/coreboot-v2/targets/lippert/roadrunner-lx/Config.lb Log: Coding-style and whitespace fixes (also to make the code more similar the Lippert Cool SpaceRunner LX which is already in svn). Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/coreboot-v2/src/mainboard/lippert/roadrunner-lx/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/lippert/roadrunner-lx/Config.lb 2008-11-19 12:19:09 UTC (rev 3760) +++ trunk/coreboot-v2/src/mainboard/lippert/roadrunner-lx/Config.lb 2008-11-19 13:42:14 UTC (rev 3761) @@ -3,8 +3,6 @@ ## ## Copyright (C) 2008 LiPPERT Embedded Computers GmbH ## -## Based on Config.lb from AMD's DB800 and DBM690T mainboards. -## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by ## the Free Software Foundation; either version 2 of the License, or @@ -20,15 +18,17 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +## Based on Config.lb from AMD's DB800 and DBM690T mainboards. + ## ## Compute the location and size of where this firmware image ## (coreboot plus bootloader) will live in the boot rom chip. ## if USE_FALLBACK_IMAGE default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE ) + default ROM_SECTION_OFFSET = (ROM_SIZE - FALLBACK_SIZE) else - default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) + default ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE) default ROM_SECTION_OFFSET = 0 end @@ -38,12 +38,12 @@ ## default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) -default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) +default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE) ## ## Compute where this copy of coreboot will start in the boot rom ## -default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) +default _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE) ## ## Compute a range of ROM that can cached to speed up coreboot, @@ -52,8 +52,8 @@ ## XIP_ROM_SIZE must be a power of 2. ## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE ## -default XIP_ROM_SIZE=65536 -default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE ) +default XIP_ROM_SIZE = 64 * 1024 +default XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE) ## @@ -73,12 +73,12 @@ end if USE_DCACHE_RAM - #compile cache_as_ram.c to auto.inc + # compile cache_as_ram.c to auto.inc makerule ./cache_as_ram_auto.inc - depends "$(MAINBOARD)/cache_as_ram_auto.c" - action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@" - action "perl -e 's/.rodata/.rom.data/g' -pi $@" - action "perl -e 's/.text/.section .rom.text/g' -pi $@" + depends "$(MAINBOARD)/cache_as_ram_auto.c" + action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@" + action "perl -e 's/.rodata/.rom.data/g' -pi $@" + action "perl -e 's/.text/.section .rom.text/g' -pi $@" end end @@ -136,97 +136,100 @@ end ## -## Include the secondary Configuration files +## Include the secondary configuration files ## dir /pc80 config chip.h -register "sio_gp1x_config" = "0x20" # bit1 switches Com1 to RS485, bit2 same for Com2, bit5 turns off Live LED +# Bit1 switches Com1 to RS485, bit2 same for Com2, bit5 turns off Live LED. +register "sio_gp1x_config" = "0x20" + chip northbridge/amd/lx - device pci_domain 0 on - device pci 1.0 on end # Northbridge - device pci 1.1 on end # Graphics - device pci 1.2 on end # AES - chip southbridge/amd/cs5536 - # IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK - # SIRQ Mode = Active(Quiet) mode. Save power.... - # Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse, UARTs, etc IRQs. OK - register "lpc_serirq_enable" = "0x000012DA" # 00010010 11011010 - register "lpc_serirq_polarity" = "0x0000ED25" # inverse of above - register "lpc_serirq_mode" = "1" - register "enable_gpio_int_route" = "0x0D0C0700" - register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash - register "enable_USBP4_device" = "0" # 0: host, 1:device - register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381) - register "com1_enable" = "0" - register "com1_address" = "0x3E8" - register "com1_irq" = "6" - register "com2_enable" = "0" - register "com2_address" = "0x2E8" - register "com2_irq" = "6" - register "unwanted_vpci[0]" = "0" # End of list has a zero - device pci 8.0 on end # Slot4 - device pci 9.0 on end # Slot3 - device pci a.0 on end # Slot2 - device pci b.0 on end # Slot1 - device pci c.0 on end # IT8888 - device pci e.0 on end # Ethernet - device pci f.0 on # ISA Bridge - chip superio/ite/it8712f - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.2 on # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.3 on # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.4 on # EC - io 0x60 = 0x290 - io 0x62 = 0x230 - irq 0x70 = 9 - end - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - end - device pnp 2e.6 on # Mouse - irq 0x70 = 12 - end - device pnp 2e.7 on # GPIO - io 0x62 = 0x1220 - #io 0x64 = 0x1200 - end - device pnp 2e.8 off # MIDI - io 0x60 = 0x300 - irq 0x70 = 9 - end - device pnp 2e.9 off # GAME - io 0x60 = 0x220 - end - device pnp 2e.a off end # CIR - end - end - device pci f.2 on end # IDE Controller - device pci f.3 on end # Audio - device pci f.4 on end # OHCI - device pci f.5 on end # EHCI - end - end - # APIC cluster is late CPU init. - device apic_cluster 0 on - chip cpu/amd/model_lx - device apic 0 on end - end - end + device pci_domain 0 on + device pci 1.0 on end # Northbridge + device pci 1.1 on end # Graphics + device pci 1.2 on end # AES + chip southbridge/amd/cs5536 # Southbridge + # IRQ 12 and 1 unmasked, keyboard and mouse IRQs. OK + # SIRQ Mode = Active(Quiet) mode. Save power... + # Invert mask = IRQ 12 and 1 are active high. Keyboard and mouse, + # UARTs, etc IRQs. OK + register "lpc_serirq_enable" = "0x000012DA" # 00010010 11011010 + register "lpc_serirq_polarity" = "0x0000ED25" # inverse of above + register "lpc_serirq_mode" = "1" + register "enable_gpio_int_route" = "0x0D0C0700" + register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash + register "enable_USBP4_device" = "0" # 0: host, 1:device + register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381) + register "com1_enable" = "0" + register "com1_address" = "0x3E8" + register "com1_irq" = "6" + register "com2_enable" = "0" + register "com2_address" = "0x2E8" + register "com2_irq" = "6" + register "unwanted_vpci[0]" = "0" # End of list has a zero + device pci 8.0 on end # Slot4 + device pci 9.0 on end # Slot3 + device pci a.0 on end # Slot2 + device pci b.0 on end # Slot1 + device pci c.0 on end # IT8888 + device pci e.0 on end # Ethernet + device pci f.0 on # ISA bridge + chip superio/ite/it8712f + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.2 on # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.3 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.4 on # EC + io 0x60 = 0x290 + io 0x62 = 0x230 + irq 0x70 = 9 + end + device pnp 2e.5 on # PS/2 keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + device pnp 2e.6 on # PS/2 mouse + irq 0x70 = 12 + end + device pnp 2e.7 on # GPIO + io 0x62 = 0x1220 + # io 0x64 = 0x1200 + end + device pnp 2e.8 off # MIDI + io 0x60 = 0x300 + irq 0x70 = 9 + end + device pnp 2e.9 off # Game port + io 0x60 = 0x220 + end + device pnp 2e.a off end # CIR + end + end + device pci f.2 on end # IDE controller + device pci f.3 on end # Audio + device pci f.4 on end # OHCI + device pci f.5 on end # EHCI + end + end + # APIC cluster is late CPU init. + device apic_cluster 0 on + chip cpu/amd/model_lx + device apic 0 on end + end + end end Modified: trunk/coreboot-v2/src/mainboard/lippert/roadrunner-lx/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/lippert/roadrunner-lx/Options.lb 2008-11-19 12:19:09 UTC (rev 3760) +++ trunk/coreboot-v2/src/mainboard/lippert/roadrunner-lx/Options.lb 2008-11-19 13:42:14 UTC (rev 3761) @@ -3,8 +3,6 @@ ## ## Copyright (C) 2008 LiPPERT Embedded Computers GmbH ## -## Based on Options.lb from AMD's DB800 mainboard. -## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by ## the Free Software Foundation; either version 2 of the License, or @@ -20,6 +18,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +## Based on Options.lb from AMD's DB800 mainboard. + uses HAVE_MP_TABLE uses HAVE_PIRQ_TABLE uses USE_FALLBACK_IMAGE @@ -80,71 +80,71 @@ uses PIRQ_ROUTE ## ROM_SIZE is the size of boot ROM that this board will use. -default ROM_SIZE = 512*1024 +default ROM_SIZE = 512 * 1024 ### ### Build options ### -default CONFIG_CONSOLE_VGA=0 -default CONFIG_VIDEO_MB=8 -default CONFIG_PCI_ROM_RUN=0 +default CONFIG_CONSOLE_VGA = 0 +default CONFIG_VIDEO_MB = 8 +default CONFIG_PCI_ROM_RUN = 0 ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT=1 +default HAVE_FALLBACK_BOOT = 1 ## ## no MP table ## -default HAVE_MP_TABLE=0 +default HAVE_MP_TABLE = 0 ## ## Build code to reset the motherboard from coreboot ## -default HAVE_HARD_RESET=0 +default HAVE_HARD_RESET = 0 ## Delay timer options ## -default CONFIG_UDELAY_TSC=1 -default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1 +default CONFIG_UDELAY_TSC = 1 +default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=7 -default PIRQ_ROUTE=1 +default HAVE_PIRQ_TABLE = 1 +default IRQ_SLOT_COUNT = 7 +default PIRQ_ROUTE = 1 ## ## Build code to export a CMOS option table ## -default HAVE_OPTION_TABLE=0 +default HAVE_OPTION_TABLE = 0 ### ### coreboot layout values ### ## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = 65536 -default FALLBACK_SIZE = 131072 +default ROM_IMAGE_SIZE = 64 * 1024 +default FALLBACK_SIZE = 128 * 1024 ## ## enable CACHE_AS_RAM specifics ## -default USE_DCACHE_RAM=1 -default DCACHE_RAM_BASE=0xc8000 -default DCACHE_RAM_SIZE=0x08000 +default USE_DCACHE_RAM = 1 +default DCACHE_RAM_BASE = 0xc8000 +default DCACHE_RAM_SIZE = 0x08000 ## ## Use a small 8K stack ## -default STACK_SIZE=0x2000 +default STACK_SIZE = 8 * 1024 ## ## Use a small 16K heap ## -default HEAP_SIZE=0x4000 +default HEAP_SIZE = 16 * 1024 ## ## Only use the option table in a normal image @@ -159,36 +159,36 @@ ## ## The default compiler ## -default CROSS_COMPILE="" -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CROSS_COMPILE = "" +default CC = "$(CROSS_COMPILE)gcc -m32" +default HOSTCC = "gcc" ## ## The Serial Console ## # To Enable the Serial Console -default CONFIG_CONSOLE_SERIAL8250=1 +default CONFIG_CONSOLE_SERIAL8250 = 1 ## Select the serial console baud rate -default TTYS0_BAUD=115200 -#default TTYS0_BAUD=57600 -#default TTYS0_BAUD=38400 -#default TTYS0_BAUD=19200 -#default TTYS0_BAUD=9600 -#default TTYS0_BAUD=4800 -#default TTYS0_BAUD=2400 -#default TTYS0_BAUD=1200 +default TTYS0_BAUD = 115200 +#default TTYS0_BAUD = 57600 +#default TTYS0_BAUD = 38400 +#default TTYS0_BAUD = 19200 +#default TTYS0_BAUD = 9600 +#default TTYS0_BAUD = 4800 +#default TTYS0_BAUD = 2400 +#default TTYS0_BAUD = 1200 # Select the serial console base port -default TTYS0_BASE=0x3f8 +default TTYS0_BASE = 0x3f8 # Select the serial protocol # This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 +default TTYS0_LCS = 0x3 # Compile extra debugging code -default DEBUG=1 +default DEBUG = 1 ## ### Select the coreboot loglevel @@ -204,8 +204,8 @@ ## SPEW 9 Way too many details ## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL=8 +default DEFAULT_CONSOLE_LOGLEVEL = 8 ## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL=8 +default MAXIMUM_CONSOLE_LOGLEVEL = 8 end Modified: trunk/coreboot-v2/src/mainboard/lippert/roadrunner-lx/cache_as_ram_auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/lippert/roadrunner-lx/cache_as_ram_auto.c 2008-11-19 12:19:09 UTC (rev 3760) +++ trunk/coreboot-v2/src/mainboard/lippert/roadrunner-lx/cache_as_ram_auto.c 2008-11-19 13:42:14 UTC (rev 3761) @@ -4,8 +4,6 @@ * Copyright (C) 2008 LiPPERT Embedded Computers GmbH * Copyright (C) 2007 Advanced Micro Devices, Inc. * - * Based on cache_as_ram_auto.c from AMD's DB800 and DBM690T mainboards. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or @@ -21,6 +19,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +/* Based on cache_as_ram_auto.c from AMD's DB800 and DBM690T mainboards. */ + #define ASSEMBLY 1 #include <stdlib.h> @@ -52,7 +52,9 @@ static inline int spd_read_byte(unsigned int device, unsigned int address) { - if (device != DIMM0) return 0xFF; // no DIMM1, don't even try + if (device != DIMM0) + return 0xFF; /* No DIMM1, don't even try. */ + return smbus_read_byte(device, address); } @@ -120,11 +122,12 @@ { int i; - /* Init SuperIO WDT, GPIOs. Done early, WDT init may trigger reset! */ + /* Init Super I/O WDT, GPIOs. Done early, WDT init may trigger reset! */ it8712f_enter_conf(); - for (i=0; i<ARRAY_SIZE(sio_init_table); i++) { + for (i = 0; i < ARRAY_SIZE(sio_init_table); i++) { u16 val = sio_init_table[i]; - outb((u8)val, SIO_INDEX); outb(val>>8, SIO_DATA); + outb((u8)val, SIO_INDEX); + outb(val >> 8, SIO_DATA); } it8712f_exit_conf(); } @@ -142,10 +145,11 @@ cs5536_early_setup(); - /* Note: must do this AFTER the early_setup! It is counting on some + /* + * Note: must do this AFTER the early_setup! It is counting on some * early MSR setup for CS5536. */ - it8712f_enable_serial(0, TTYS0_BASE); // does not use its 1st parameter + it8712f_enable_serial(0, TTYS0_BASE); // Does not use its 1st parameter mb_gpio_init(); uart_init(); console_init(); Modified: trunk/coreboot-v2/src/mainboard/lippert/roadrunner-lx/chip.h =================================================================== --- trunk/coreboot-v2/src/mainboard/lippert/roadrunner-lx/chip.h 2008-11-19 12:19:09 UTC (rev 3760) +++ trunk/coreboot-v2/src/mainboard/lippert/roadrunner-lx/chip.h 2008-11-19 13:42:14 UTC (rev 3761) @@ -3,8 +3,6 @@ * * Copyright (C) 2008 LiPPERT Embedded Computers GmbH * - * Based on chip.h from AMD's DB800 mainboard. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or @@ -20,10 +18,13 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +/* Based on chip.h from AMD's DB800 mainboard. */ + #include <stdint.h> extern struct chip_operations mainboard_lippert_roadrunner_lx_ops; struct mainboard_lippert_roadrunner_lx_config { - u8 sio_gp1x_config; // bit5=Live LED, bit2=RS485_EN2, bit1=RS485_EN1 + /* bit5 = Live LED, bit2 = RS485_EN2, bit1 = RS485_EN1 */ + u8 sio_gp1x_config; }; Modified: trunk/coreboot-v2/src/mainboard/lippert/roadrunner-lx/irq_tables.c =================================================================== --- trunk/coreboot-v2/src/mainboard/lippert/roadrunner-lx/irq_tables.c 2008-11-19 12:19:09 UTC (rev 3760) +++ trunk/coreboot-v2/src/mainboard/lippert/roadrunner-lx/irq_tables.c 2008-11-19 13:42:14 UTC (rev 3761) @@ -3,8 +3,6 @@ * * Copyright (C) 2008 LiPPERT Embedded Computers GmbH * - * Based on irq_tables.c from AMD's DB800 mainboard. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or @@ -20,6 +18,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +/* Based on irq_tables.c from AMD's DB800 mainboard. */ + #include <arch/pirq_routing.h> #include <console/console.h> #include <arch/io.h> @@ -47,7 +47,7 @@ const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, /* u32 signature */ PIRQ_VERSION, /* u16 version */ - 32 + 16 * IRQ_SLOT_COUNT, /* there can be total 7 devices on the bus */ + 32 + 16 * IRQ_SLOT_COUNT,/* there can be total 7 devices on the bus */ 0x00, /* Where the interrupt router lies (bus) */ (0x0F << 3) | 0x0, /* Where the interrupt router lies (dev) */ 0x00, /* IRQs devoted exclusively to PCI usage */ @@ -55,17 +55,17 @@ 0x002B, /* Device */ 0, /* Crap (miniport) */ {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* u8 rfu[11] */ - 0xE0, /* u8 checksum , this has to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ + 0xE0, /* u8 checksum, this has to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ { - /* If you change the number of entries, change the IRQ_SLOT_COUNT above! */ - /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ - {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* cpu */ - {0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0}, /* chipset */ - {0x00, (0x0E << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* ethernet */ - {0x00, (0x0B << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x1, 0x0}, /* slot1 */ - {0x00, (0x0A << 3) | 0x0, {{L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}}, 0x2, 0x0}, /* slot2 */ - {0x00, (0x09 << 3) | 0x0, {{L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}}, 0x3, 0x0}, /* slot3 */ - {0x00, (0x08 << 3) | 0x0, {{L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}}, 0x4, 0x0}, /* slot4 */ + /* If you change the number of entries, change the IRQ_SLOT_COUNT above! */ + /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* CPU */ + {0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0}, /* chipset */ + {0x00, (0x0E << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* ethernet */ + {0x00, (0x0B << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x1, 0x0}, /* slot1 */ + {0x00, (0x0A << 3) | 0x0, {{L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}}, 0x2, 0x0}, /* slot2 */ + {0x00, (0x09 << 3) | 0x0, {{L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}}, 0x3, 0x0}, /* slot3 */ + {0x00, (0x08 << 3) | 0x0, {{L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}}, 0x4, 0x0}, /* slot4 */ } }; Modified: trunk/coreboot-v2/src/mainboard/lippert/roadrunner-lx/mainboard.c =================================================================== --- trunk/coreboot-v2/src/mainboard/lippert/roadrunner-lx/mainboard.c 2008-11-19 12:19:09 UTC (rev 3760) +++ trunk/coreboot-v2/src/mainboard/lippert/roadrunner-lx/mainboard.c 2008-11-19 13:42:14 UTC (rev 3761) @@ -3,8 +3,6 @@ * * Copyright (C) 2008 LiPPERT Embedded Computers GmbH * - * Based on mainboard.c from AMD's DB800 mainboard. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or @@ -20,6 +18,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +/* Based on mainboard.c from AMD's DB800 mainboard. */ + #include <stdlib.h> #include <stdint.h> #include <console/console.h> @@ -29,13 +29,13 @@ #include <device/pci_ids.h> #include "chip.h" -static const u16 ec_init_table[] = { // hi=data, lo=index - 0x1900, // enable monitoring - 0x0351, // TMPIN1,2 diode mode, TMPIN3 off - 0x805C, // unlock zero adjust - 0x7056, 0x3C57, // zero adjust TMPIN1,2 - 0x005C, // lock zero adjust - 0xD014 // also set FAN_CTL polarity to Active High +static const u16 ec_init_table[] = { /* hi=data, lo=index */ + 0x1900, /* Enable monitoring */ + 0x0351, /* TMPIN1,2 diode mode, TMPIN3 off */ + 0x805C, /* Unlock zero adjust */ + 0x7056, 0x3C57, /* Zero adjust TMPIN1,2 */ + 0x005C, /* Lock zero adjust */ + 0xD014 /* Also set FAN_CTL polarity to Active High */ }; static void init(struct device *dev) @@ -44,22 +44,24 @@ unsigned int gpio_base, i; printk_debug("LiPPERT RoadRunner-LX ENTER %s\n", __FUNCTION__); - /* Init CS5536 GPIOs */ - gpio_base = pci_read_config32(dev_find_device(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, 0), - PCI_BASE_ADDRESS_1) - 1; - outl(0x00000040, gpio_base + 0x00); // GPIO6 value 1 - LAN_PD# - outl(0x00000040, gpio_base + 0x04); // GPIO6 output 1 - LAN_PD# - outl(0x00000400, gpio_base + 0x34); // GPIO10 in aux1 1 - THRM_ALRM# - outl(0x00000400, gpio_base + 0x20); // GPIO10 input 1 - THRM_ALRM# - outl(0x08000000, gpio_base + 0x98); // GPIO27 pull up 0 - PM-LED + /* Init CS5536 GPIOs. */ + gpio_base = pci_read_config32(dev_find_device(PCI_VENDOR_ID_AMD, + PCI_DEVICE_ID_AMD_CS5536_ISA, 0), PCI_BASE_ADDRESS_1) - 1; - /* Init Environment Controller */ - for (i=0; i<ARRAY_SIZE(ec_init_table); i++) { + outl(0x00000040, gpio_base + 0x00); // GPIO6 value 1 - LAN_PD# + outl(0x00000040, gpio_base + 0x04); // GPIO6 output 1 - LAN_PD# + outl(0x00000400, gpio_base + 0x34); // GPIO10 in aux1 1 - THRM_ALRM# + outl(0x00000400, gpio_base + 0x20); // GPIO10 input 1 - THRM_ALRM# + outl(0x08000000, gpio_base + 0x98); // GPIO27 pull up 0 - PM-LED + + /* Init Environment Controller. */ + for (i = 0; i < ARRAY_SIZE(ec_init_table); i++) { u16 val = ec_init_table[i]; - outb((u8)val, 0x0295); outb(val>>8, 0x0296); + outb((u8)val, 0x0295); + outb(val >> 8, 0x0296); } - outb(mb->sio_gp1x_config, 0x1220); // Simple-I/O GP17-10 + outb(mb->sio_gp1x_config, 0x1220); /* Simple-I/O GP17-10 */ printk_debug("LiPPERT RoadRunner-LX EXIT %s\n", __FUNCTION__); } Modified: trunk/coreboot-v2/targets/lippert/roadrunner-lx/Config.lb =================================================================== --- trunk/coreboot-v2/targets/lippert/roadrunner-lx/Config.lb 2008-11-19 12:19:09 UTC (rev 3760) +++ trunk/coreboot-v2/targets/lippert/roadrunner-lx/Config.lb 2008-11-19 13:42:14 UTC (rev 3761) @@ -25,24 +25,24 @@ mainboard lippert/roadrunner-lx # HACK to get the right TSC support. -option CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1 +option CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 -option CONFIG_COMPRESSED_PAYLOAD_NRV2B=0 -option CONFIG_COMPRESSED_PAYLOAD_LZMA=0 +option CONFIG_COMPRESSED_PAYLOAD_NRV2B = 0 +option CONFIG_COMPRESSED_PAYLOAD_LZMA = 0 ## Load payload (e.g. Linux) from IDE. -#option CONFIG_ROM_PAYLOAD=0 -#option CONFIG_IDE=1 -#option CONFIG_FS_PAYLOAD=1 -#option CONFIG_FS_EXT2=1 -#option AUTOBOOT_DELAY=0 -#option AUTOBOOT_CMDLINE="hda1:/payload.elf" +#option CONFIG_ROM_PAYLOAD = 0 +#option CONFIG_IDE = 1 +#option CONFIG_FS_PAYLOAD = 1 +#option CONFIG_FS_EXT2 = 1 +#option AUTOBOOT_DELAY = 0 +#option AUTOBOOT_CMDLINE = "hda1:/payload.elf" # Leave 36k for VSA. Usually board is equipped with a 512 KB FWH (LPC) flash, # however it can be replaced with a 1 MB chip. -option ROM_SIZE=512*1024-36*1024 -#option ROM_SIZE=1024*1024-36*1024 -option FALLBACK_SIZE=ROM_SIZE +option ROM_SIZE = (512 * 1024) - (36 * 1024) +#option ROM_SIZE = (1024 * 1024) - (36 * 1024) +option FALLBACK_SIZE = ROM_SIZE #option DEFAULT_CONSOLE_LOGLEVEL = 4 #option MAXIMUM_CONSOLE_LOGLEVEL = 4 @@ -51,12 +51,12 @@ option CONFIG_COMPRESS = 1 romimage "image" - option USE_FALLBACK_IMAGE=1 - option ROM_IMAGE_SIZE=64*1024 - option COREBOOT_EXTRA_VERSION=".0" + option USE_FALLBACK_IMAGE = 1 + option ROM_IMAGE_SIZE = 64 * 1024 + option COREBOOT_EXTRA_VERSION = ".0" payload ../payload.elf # If getting payload from IDE - #payload /dev/null + # payload /dev/null end buildrom ./coreboot.rom ROM_SIZE "image"

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r3760 build service
by coreboot information 19 Nov '08

19 Nov '08

Dear coreboot readers! This is the automated build check service of coreboot. The developer "stepan" checked in revision 3760 to the coreboot source repository and caused the following changes: Change Log: Add support for the LiPPERT Cool RoadRunner-LX embedded PC board: - PC/104+ form factor - AMD Geode-LX CPU/northbridge - AMD CS5536 southbridge - ITE IT8712F superio http://www.lippert-at.com/index.php?id=408 Signed-off-by: Jens Rottmann <JRottmann(a)LiPPERTEmbedded.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Build Log: Compilation of bcom:winnetp680 has been fixed Compilation of sunw:ultra40 has been fixed Compilation of tyan:s2885 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3760&device=s2885&vendor=t… If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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GRUB / Initrd problem fixed
by Robert Millan 19 Nov '08

19 Nov '08

Hi, As it's been recently found out (thanks to Ward for spotting this), there was a problem in the Linux loader of GRUB that is used on coreboot, that prevented Linux from finding its Initrd images under certain setups (when both Initrd and amount of RAM surpassed a certain limit). It seems that Linux has certain requirements on Initrd location which our new loader didn't know about. This problem has just been fixed in latest SVN. I've tested with a few different images (including those from Debian and Ubuntu), and everything seems to be fine now. I'd like to encourage you folks to try the latest revision. If coreboot specific problems are found, feel free to let grub-devel(a)gnu.org know (or mail me directly if you like). -- Robert Millan The DRM opt-in fallacy: "Your data belongs to us. We will decide when (and how) you may access your data; but nobody's threatening your freedom: we still allow you to remove your data and not access it at all."

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r3760 - in trunk/coreboot-v2: src/mainboard/lippert src/mainboard/lippert/roadrunner-lx targets/lippert targets/lippert/roadrunner-lx
by svn＠coreboot.org 19 Nov '08

19 Nov '08

Author: stepan Date: 2008-11-19 13:19:09 +0100 (Wed, 19 Nov 2008) New Revision: 3760 Added: trunk/coreboot-v2/src/mainboard/lippert/roadrunner-lx/ trunk/coreboot-v2/src/mainboard/lippert/roadrunner-lx/Config.lb trunk/coreboot-v2/src/mainboard/lippert/roadrunner-lx/Options.lb trunk/coreboot-v2/src/mainboard/lippert/roadrunner-lx/cache_as_ram_auto.c trunk/coreboot-v2/src/mainboard/lippert/roadrunner-lx/chip.h trunk/coreboot-v2/src/mainboard/lippert/roadrunner-lx/irq_tables.c trunk/coreboot-v2/src/mainboard/lippert/roadrunner-lx/mainboard.c trunk/coreboot-v2/targets/lippert/roadrunner-lx/ trunk/coreboot-v2/targets/lippert/roadrunner-lx/Config.lb Log: Add support for the LiPPERT Cool RoadRunner-LX embedded PC board: - PC/104+ form factor - AMD Geode-LX CPU/northbridge - AMD CS5536 southbridge - ITE IT8712F superio http://www.lippert-at.com/index.php?id=408 Signed-off-by: Jens Rottmann <JRottmann(a)LiPPERTEmbedded.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Added: trunk/coreboot-v2/src/mainboard/lippert/roadrunner-lx/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/lippert/roadrunner-lx/Config.lb (rev 0) +++ trunk/coreboot-v2/src/mainboard/lippert/roadrunner-lx/Config.lb 2008-11-19 12:19:09 UTC (rev 3760) @@ -0,0 +1,232 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2008 LiPPERT Embedded Computers GmbH +## +## Based on Config.lb from AMD's DB800 and DBM690T mainboards. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +## +## Compute the location and size of where this firmware image +## (coreboot plus bootloader) will live in the boot rom chip. +## +if USE_FALLBACK_IMAGE + default ROM_SECTION_SIZE = FALLBACK_SIZE + default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE ) +else + default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) + default ROM_SECTION_OFFSET = 0 +end + +## +## Compute the start location and size size of +## The coreboot bootloader. +## + +default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) +default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) + +## +## Compute where this copy of coreboot will start in the boot rom +## +default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) + +## +## Compute a range of ROM that can cached to speed up coreboot, +## execution speed. +## +## XIP_ROM_SIZE must be a power of 2. +## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE +## +default XIP_ROM_SIZE=65536 +default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE ) + + +## +## Set all of the defaults for an x86 architecture +## + +arch i386 end + +## +## Build the objects we have code for in this directory. +## + +driver mainboard.o + +if HAVE_PIRQ_TABLE + object irq_tables.o +end + +if USE_DCACHE_RAM + #compile cache_as_ram.c to auto.inc + makerule ./cache_as_ram_auto.inc + depends "$(MAINBOARD)/cache_as_ram_auto.c" + action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@" + action "perl -e 's/.rodata/.rom.data/g' -pi $@" + action "perl -e 's/.text/.section .rom.text/g' -pi $@" + end +end + + +## +## Build our 16 bit and 32 bit coreboot entry code +## +mainboardinit cpu/x86/16bit/entry16.inc +mainboardinit cpu/x86/32bit/entry32.inc +ldscript /cpu/x86/16bit/entry16.lds +ldscript /cpu/x86/32bit/entry32.lds + +## +## Build our reset vector (This is where coreboot is entered) +## +if USE_FALLBACK_IMAGE + mainboardinit cpu/x86/16bit/reset16.inc + ldscript /cpu/x86/16bit/reset16.lds +else + mainboardinit cpu/x86/32bit/reset32.inc + ldscript /cpu/x86/32bit/reset32.lds +end + +### Should this be in the northbridge code? +#not in serengeti_cheetah mainboardinit arch/i386/lib/cpu_reset.inc + +## +## Include an id string (For safe flashing) +## +mainboardinit arch/i386/lib/id.inc +ldscript /arch/i386/lib/id.lds + +### +### This is the early phase of coreboot startup +### Things are delicate and we test to see if we should +### failover to another image. +### +if USE_FALLBACK_IMAGE + ldscript /arch/i386/lib/failover.lds +# mainboardinit ./failover.inc +end + +### +### O.k. We aren't just an intermediary anymore! +### + +## +## Setup RAM +## +mainboardinit cpu/x86/fpu/enable_fpu.inc + +if USE_DCACHE_RAM + mainboardinit cpu/amd/model_lx/cache_as_ram.inc + mainboardinit ./cache_as_ram_auto.inc +end + +## +## Include the secondary Configuration files +## +dir /pc80 +config chip.h +register "sio_gp1x_config" = "0x20" # bit1 switches Com1 to RS485, bit2 same for Com2, bit5 turns off Live LED + +chip northbridge/amd/lx + device pci_domain 0 on + device pci 1.0 on end # Northbridge + device pci 1.1 on end # Graphics + device pci 1.2 on end # AES + chip southbridge/amd/cs5536 + # IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK + # SIRQ Mode = Active(Quiet) mode. Save power.... + # Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse, UARTs, etc IRQs. OK + register "lpc_serirq_enable" = "0x000012DA" # 00010010 11011010 + register "lpc_serirq_polarity" = "0x0000ED25" # inverse of above + register "lpc_serirq_mode" = "1" + register "enable_gpio_int_route" = "0x0D0C0700" + register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash + register "enable_USBP4_device" = "0" # 0: host, 1:device + register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381) + register "com1_enable" = "0" + register "com1_address" = "0x3E8" + register "com1_irq" = "6" + register "com2_enable" = "0" + register "com2_address" = "0x2E8" + register "com2_irq" = "6" + register "unwanted_vpci[0]" = "0" # End of list has a zero + device pci 8.0 on end # Slot4 + device pci 9.0 on end # Slot3 + device pci a.0 on end # Slot2 + device pci b.0 on end # Slot1 + device pci c.0 on end # IT8888 + device pci e.0 on end # Ethernet + device pci f.0 on # ISA Bridge + chip superio/ite/it8712f + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.2 on # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.3 on # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.4 on # EC + io 0x60 = 0x290 + io 0x62 = 0x230 + irq 0x70 = 9 + end + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + device pnp 2e.6 on # Mouse + irq 0x70 = 12 + end + device pnp 2e.7 on # GPIO + io 0x62 = 0x1220 + #io 0x64 = 0x1200 + end + device pnp 2e.8 off # MIDI + io 0x60 = 0x300 + irq 0x70 = 9 + end + device pnp 2e.9 off # GAME + io 0x60 = 0x220 + end + device pnp 2e.a off end # CIR + end + end + device pci f.2 on end # IDE Controller + device pci f.3 on end # Audio + device pci f.4 on end # OHCI + device pci f.5 on end # EHCI + end + end + # APIC cluster is late CPU init. + device apic_cluster 0 on + chip cpu/amd/model_lx + device apic 0 on end + end + end +end Added: trunk/coreboot-v2/src/mainboard/lippert/roadrunner-lx/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/lippert/roadrunner-lx/Options.lb (rev 0) +++ trunk/coreboot-v2/src/mainboard/lippert/roadrunner-lx/Options.lb 2008-11-19 12:19:09 UTC (rev 3760) @@ -0,0 +1,211 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2008 LiPPERT Embedded Computers GmbH +## +## Based on Options.lb from AMD's DB800 mainboard. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +uses HAVE_MP_TABLE +uses HAVE_PIRQ_TABLE +uses USE_FALLBACK_IMAGE +uses HAVE_FALLBACK_BOOT +uses HAVE_HARD_RESET +uses HAVE_OPTION_TABLE +uses USE_OPTION_TABLE +uses CONFIG_ROM_PAYLOAD +uses CONFIG_IDE +uses CONFIG_FS_PAYLOAD +uses CONFIG_FS_EXT2 +uses AUTOBOOT_DELAY +uses AUTOBOOT_CMDLINE +uses IRQ_SLOT_COUNT +uses MAINBOARD +uses MAINBOARD_VENDOR +uses MAINBOARD_PART_NUMBER +uses COREBOOT_EXTRA_VERSION +uses ARCH +uses FALLBACK_SIZE +uses STACK_SIZE +uses HEAP_SIZE +uses ROM_SIZE +uses ROM_SECTION_SIZE +uses ROM_IMAGE_SIZE +uses ROM_SECTION_SIZE +uses ROM_SECTION_OFFSET +uses CONFIG_ROM_PAYLOAD_START +uses CONFIG_COMPRESS +uses CONFIG_COMPRESSED_PAYLOAD_NRV2B +uses CONFIG_COMPRESSED_PAYLOAD_LZMA +uses CONFIG_PRECOMPRESSED_PAYLOAD +uses PAYLOAD_SIZE +uses _ROMBASE +uses _RAMBASE +uses XIP_ROM_SIZE +uses XIP_ROM_BASE +uses HAVE_MP_TABLE +uses CROSS_COMPILE +uses CC +uses HOSTCC +uses OBJCOPY +uses DEBUG +uses DEFAULT_CONSOLE_LOGLEVEL +uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_CONSOLE_SERIAL8250 +uses TTYS0_BAUD +uses TTYS0_BASE +uses TTYS0_LCS +uses CONFIG_UDELAY_TSC +uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 +uses CONFIG_CONSOLE_VGA +uses CONFIG_PCI_ROM_RUN +uses CONFIG_VIDEO_MB +uses USE_DCACHE_RAM +uses DCACHE_RAM_BASE +uses DCACHE_RAM_SIZE +uses PIRQ_ROUTE + +## ROM_SIZE is the size of boot ROM that this board will use. +default ROM_SIZE = 512*1024 + +### +### Build options +### +default CONFIG_CONSOLE_VGA=0 +default CONFIG_VIDEO_MB=8 +default CONFIG_PCI_ROM_RUN=0 + +## +## Build code for the fallback boot +## +default HAVE_FALLBACK_BOOT=1 + +## +## no MP table +## +default HAVE_MP_TABLE=0 + +## +## Build code to reset the motherboard from coreboot +## +default HAVE_HARD_RESET=0 + +## Delay timer options +## +default CONFIG_UDELAY_TSC=1 +default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1 + +## +## Build code to export a programmable irq routing table +## +default HAVE_PIRQ_TABLE=1 +default IRQ_SLOT_COUNT=7 +default PIRQ_ROUTE=1 + +## +## Build code to export a CMOS option table +## +default HAVE_OPTION_TABLE=0 + +### +### coreboot layout values +### + +## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default ROM_IMAGE_SIZE = 65536 +default FALLBACK_SIZE = 131072 + +## +## enable CACHE_AS_RAM specifics +## +default USE_DCACHE_RAM=1 +default DCACHE_RAM_BASE=0xc8000 +default DCACHE_RAM_SIZE=0x08000 + +## +## Use a small 8K stack +## +default STACK_SIZE=0x2000 + +## +## Use a small 16K heap +## +default HEAP_SIZE=0x4000 + +## +## Only use the option table in a normal image +## +#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE +default USE_OPTION_TABLE = 0 + +default _RAMBASE = 0x00004000 + +default CONFIG_ROM_PAYLOAD = 1 + +## +## The default compiler +## +default CROSS_COMPILE="" +default CC="$(CROSS_COMPILE)gcc -m32" +default HOSTCC="gcc" + +## +## The Serial Console +## + +# To Enable the Serial Console +default CONFIG_CONSOLE_SERIAL8250=1 + +## Select the serial console baud rate +default TTYS0_BAUD=115200 +#default TTYS0_BAUD=57600 +#default TTYS0_BAUD=38400 +#default TTYS0_BAUD=19200 +#default TTYS0_BAUD=9600 +#default TTYS0_BAUD=4800 +#default TTYS0_BAUD=2400 +#default TTYS0_BAUD=1200 + +# Select the serial console base port +default TTYS0_BASE=0x3f8 + +# Select the serial protocol +# This defaults to 8 data bits, 1 stop bit, and no parity +default TTYS0_LCS=0x3 + +# Compile extra debugging code +default DEBUG=1 + +## +### Select the coreboot loglevel +## +## EMERG 1 system is unusable +## ALERT 2 action must be taken immediately +## CRIT 3 critical conditions +## ERR 4 error conditions +## WARNING 5 warning conditions +## NOTICE 6 normal but significant condition +## INFO 7 informational +## DEBUG 8 debug-level messages +## SPEW 9 Way too many details + +## Request this level of debugging output +default DEFAULT_CONSOLE_LOGLEVEL=8 +## At a maximum only compile in this level of debugging +default MAXIMUM_CONSOLE_LOGLEVEL=8 + +end Added: trunk/coreboot-v2/src/mainboard/lippert/roadrunner-lx/cache_as_ram_auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/lippert/roadrunner-lx/cache_as_ram_auto.c (rev 0) +++ trunk/coreboot-v2/src/mainboard/lippert/roadrunner-lx/cache_as_ram_auto.c 2008-11-19 12:19:09 UTC (rev 3760) @@ -0,0 +1,164 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 LiPPERT Embedded Computers GmbH + * Copyright (C) 2007 Advanced Micro Devices, Inc. + * + * Based on cache_as_ram_auto.c from AMD's DB800 and DBM690T mainboards. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define ASSEMBLY 1 + +#include <stdlib.h> +#include <stdint.h> +#include <device/pci_def.h> +#include <arch/io.h> +#include <device/pnp_def.h> +#include <arch/hlt.h> +#include "pc80/serial.c" +#include "arch/i386/lib/console.c" +#include "ram/ramtest.c" +#include "cpu/x86/bist.h" +#include "cpu/x86/msr.h" +#include <cpu/amd/lxdef.h> +#include <cpu/amd/geode_post_code.h> +#include "southbridge/amd/cs5536/cs5536.h" + +#define POST_CODE(x) outb(x, 0x80) + +#include "southbridge/amd/cs5536/cs5536_early_smbus.c" +#include "southbridge/amd/cs5536/cs5536_early_setup.c" +#include "superio/ite/it8712f/it8712f_early_serial.c" + +#define ManualConf 1 /* No automatic strapped PLL config */ +#define PLLMSRhi 0x0000049C /* Manual settings for the PLL */ +#define PLLMSRlo 0x00DE6001 +#define DIMM0 0xA0 +#define DIMM1 0xA2 + +static inline int spd_read_byte(unsigned int device, unsigned int address) +{ + if (device != DIMM0) return 0xFF; // no DIMM1, don't even try + return smbus_read_byte(device, address); +} + +#include "northbridge/amd/lx/raminit.h" +#include "northbridge/amd/lx/pll_reset.c" +#include "northbridge/amd/lx/raminit.c" +#include "sdram/generic_sdram.c" +#include "cpu/amd/model_lx/cpureginit.c" +#include "cpu/amd/model_lx/syspreinit.c" + +static void msr_init(void) +{ + msr_t msr; + + /* Setup access to the cache for under 1MB. */ + msr.hi = 0x24fffc02; + msr.lo = 0x1000A000; /* 0-A0000 write back */ + wrmsr(CPU_RCONF_DEFAULT, msr); + + msr.hi = 0x0; /* Write back */ + msr.lo = 0x0; + wrmsr(CPU_RCONF_A0_BF, msr); + wrmsr(CPU_RCONF_C0_DF, msr); + wrmsr(CPU_RCONF_E0_FF, msr); + + /* Setup access to the cache for under 640K. Note MC not setup yet. */ + msr.hi = 0x20000000; + msr.lo = 0xfff80; + wrmsr(MSR_GLIU0 + 0x20, msr); + + msr.hi = 0x20000000; + msr.lo = 0x80fffe0; + wrmsr(MSR_GLIU0 + 0x21, msr); + + msr.hi = 0x20000000; + msr.lo = 0xfff80; + wrmsr(MSR_GLIU1 + 0x20, msr); + + msr.hi = 0x20000000; + msr.lo = 0x80fffe0; + wrmsr(MSR_GLIU1 + 0x21, msr); +} + +static const u16 sio_init_table[] = { // hi=data, lo=index + 0x0707, // select LDN 7 (GPIO, SPI, watchdog, ...) + 0x1E2C, // disable ATXPowerGood - will cause a reboot! + 0x0423, // don't delay POWerOK1/2 + 0x9072, // watchdog triggers POWOK, counts seconds +#if !USE_WATCHDOG_ON_BOOT + 0x0073, 0x0074, // disable watchdog by setting timeout to 0 +#endif + 0xBF25, 0x372A, 0xF326, // select GPIO function for most pins + 0xBF27, 0xFF28, 0x2529, // (GP36=FAN_CTL3, GP13=PWROK1) + 0x1E2C, // VIN6=enabled?, FAN4/5 enabled, VIN7=internal, VIN3=enabled + 0x46B8, 0x0CB9, // enable pullups + 0x36C0, // enable Simple-I/O for GP15,14,12,11= LIVE_LED, WD_ACTIVE, RS485_EN2,1 + 0xFFC3, // enable Simple-I/O for GP47-40 (GPIOs on Supervisory Connector) + 0x26C8, // config GP15,12,11 as output; GP14 as input + 0x2DF5, // map Hw Monitor Thermal Output to GP55 + 0x0DF8, // map GP LED Blinking 1 to GP15=LIVE_LED (deactivate Simple-I/O to use) +}; + +/* Early mainboard specific GPIO setup. */ +static void mb_gpio_init(void) +{ + int i; + + /* Init SuperIO WDT, GPIOs. Done early, WDT init may trigger reset! */ + it8712f_enter_conf(); + for (i=0; i<ARRAY_SIZE(sio_init_table); i++) { + u16 val = sio_init_table[i]; + outb((u8)val, SIO_INDEX); outb(val>>8, SIO_DATA); + } + it8712f_exit_conf(); +} + +void cache_as_ram_main(void) +{ + POST_CODE(0x01); + + static const struct mem_controller memctrl[] = { + {.channel0 = {(0xa << 3) | 0, (0xa << 3) | 1}} + }; + + SystemPreInit(); + msr_init(); + + cs5536_early_setup(); + + /* Note: must do this AFTER the early_setup! It is counting on some + * early MSR setup for CS5536. + */ + it8712f_enable_serial(0, TTYS0_BASE); // does not use its 1st parameter + mb_gpio_init(); + uart_init(); + console_init(); + + pll_reset(ManualConf); + + cpuRegInit(); + + sdram_initialize(1, memctrl); + + /* Check memory. */ + /* ram_check(0x00000000, 640 * 1024); */ + + /* Memory is setup. Return to cache_as_ram.inc and continue to boot. */ + return; +} Added: trunk/coreboot-v2/src/mainboard/lippert/roadrunner-lx/chip.h =================================================================== --- trunk/coreboot-v2/src/mainboard/lippert/roadrunner-lx/chip.h (rev 0) +++ trunk/coreboot-v2/src/mainboard/lippert/roadrunner-lx/chip.h 2008-11-19 12:19:09 UTC (rev 3760) @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 LiPPERT Embedded Computers GmbH + * + * Based on chip.h from AMD's DB800 mainboard. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> + +extern struct chip_operations mainboard_lippert_roadrunner_lx_ops; + +struct mainboard_lippert_roadrunner_lx_config { + u8 sio_gp1x_config; // bit5=Live LED, bit2=RS485_EN2, bit1=RS485_EN1 +}; Added: trunk/coreboot-v2/src/mainboard/lippert/roadrunner-lx/irq_tables.c =================================================================== --- trunk/coreboot-v2/src/mainboard/lippert/roadrunner-lx/irq_tables.c (rev 0) +++ trunk/coreboot-v2/src/mainboard/lippert/roadrunner-lx/irq_tables.c 2008-11-19 12:19:09 UTC (rev 3760) @@ -0,0 +1,75 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 LiPPERT Embedded Computers GmbH + * + * Based on irq_tables.c from AMD's DB800 mainboard. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/pirq_routing.h> +#include <console/console.h> +#include <arch/io.h> +#include <arch/pirq_routing.h> +#include "../../../southbridge/amd/cs5536/cs5536.h" + +/* Platform IRQs */ +#define PIRQA 10 +#define PIRQB 11 +#define PIRQC 5 +#define PIRQD 15 + +/* Map */ +#define M_PIRQA (1 << PIRQA) /* Bitmap of supported IRQs */ +#define M_PIRQB (1 << PIRQB) /* Bitmap of supported IRQs */ +#define M_PIRQC (1 << PIRQC) /* Bitmap of supported IRQs */ +#define M_PIRQD (1 << PIRQD) /* Bitmap of supported IRQs */ + +/* Link */ +#define L_PIRQA 1 /* Means Slot INTx# Connects To Chipset INTA# */ +#define L_PIRQB 2 /* Means Slot INTx# Connects To Chipset INTB# */ +#define L_PIRQC 3 /* Means Slot INTx# Connects To Chipset INTC# */ +#define L_PIRQD 4 /* Means Slot INTx# Connects To Chipset INTD# */ + +const struct irq_routing_table intel_irq_routing_table = { + PIRQ_SIGNATURE, /* u32 signature */ + PIRQ_VERSION, /* u16 version */ + 32 + 16 * IRQ_SLOT_COUNT, /* there can be total 7 devices on the bus */ + 0x00, /* Where the interrupt router lies (bus) */ + (0x0F << 3) | 0x0, /* Where the interrupt router lies (dev) */ + 0x00, /* IRQs devoted exclusively to PCI usage */ + 0x100B, /* Vendor */ + 0x002B, /* Device */ + 0, /* Crap (miniport) */ + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* u8 rfu[11] */ + 0xE0, /* u8 checksum , this has to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ + { + /* If you change the number of entries, change the IRQ_SLOT_COUNT above! */ + /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* cpu */ + {0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0}, /* chipset */ + {0x00, (0x0E << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* ethernet */ + {0x00, (0x0B << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x1, 0x0}, /* slot1 */ + {0x00, (0x0A << 3) | 0x0, {{L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}}, 0x2, 0x0}, /* slot2 */ + {0x00, (0x09 << 3) | 0x0, {{L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}}, 0x3, 0x0}, /* slot3 */ + {0x00, (0x08 << 3) | 0x0, {{L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}}, 0x4, 0x0}, /* slot4 */ + } +}; + +unsigned long write_pirq_routing_table(unsigned long addr) +{ + return copy_pirq_routing_table(addr); +} Added: trunk/coreboot-v2/src/mainboard/lippert/roadrunner-lx/mainboard.c =================================================================== --- trunk/coreboot-v2/src/mainboard/lippert/roadrunner-lx/mainboard.c (rev 0) +++ trunk/coreboot-v2/src/mainboard/lippert/roadrunner-lx/mainboard.c 2008-11-19 12:19:09 UTC (rev 3760) @@ -0,0 +1,74 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 LiPPERT Embedded Computers GmbH + * + * Based on mainboard.c from AMD's DB800 mainboard. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdlib.h> +#include <stdint.h> +#include <console/console.h> +#include <device/device.h> +#include <arch/io.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include "chip.h" + +static const u16 ec_init_table[] = { // hi=data, lo=index + 0x1900, // enable monitoring + 0x0351, // TMPIN1,2 diode mode, TMPIN3 off + 0x805C, // unlock zero adjust + 0x7056, 0x3C57, // zero adjust TMPIN1,2 + 0x005C, // lock zero adjust + 0xD014 // also set FAN_CTL polarity to Active High +}; + +static void init(struct device *dev) +{ + struct mainboard_lippert_roadrunner_lx_config *mb = dev->chip_info; + unsigned int gpio_base, i; + printk_debug("LiPPERT RoadRunner-LX ENTER %s\n", __FUNCTION__); + + /* Init CS5536 GPIOs */ + gpio_base = pci_read_config32(dev_find_device(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, 0), + PCI_BASE_ADDRESS_1) - 1; + outl(0x00000040, gpio_base + 0x00); // GPIO6 value 1 - LAN_PD# + outl(0x00000040, gpio_base + 0x04); // GPIO6 output 1 - LAN_PD# + outl(0x00000400, gpio_base + 0x34); // GPIO10 in aux1 1 - THRM_ALRM# + outl(0x00000400, gpio_base + 0x20); // GPIO10 input 1 - THRM_ALRM# + outl(0x08000000, gpio_base + 0x98); // GPIO27 pull up 0 - PM-LED + + /* Init Environment Controller */ + for (i=0; i<ARRAY_SIZE(ec_init_table); i++) { + u16 val = ec_init_table[i]; + outb((u8)val, 0x0295); outb(val>>8, 0x0296); + } + + outb(mb->sio_gp1x_config, 0x1220); // Simple-I/O GP17-10 + printk_debug("LiPPERT RoadRunner-LX EXIT %s\n", __FUNCTION__); +} + +static void enable_dev(struct device *dev) +{ + dev->ops->init = init; +} + +struct chip_operations mainboard_lippert_roadrunner_lx_ops = { + CHIP_NAME("LiPPERT RoadRunner-LX Mainboard") + .enable_dev = enable_dev, +}; Added: trunk/coreboot-v2/targets/lippert/roadrunner-lx/Config.lb =================================================================== --- trunk/coreboot-v2/targets/lippert/roadrunner-lx/Config.lb (rev 0) +++ trunk/coreboot-v2/targets/lippert/roadrunner-lx/Config.lb 2008-11-19 12:19:09 UTC (rev 3760) @@ -0,0 +1,62 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2008 LiPPERT Embedded Computers GmbH +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +# Config file for the LiPPERT Cool RoadRunner-LX, --JR 10/2008 +# based on Config.lb for the AMD Geode LX/5536 DB800 platform. + +target roadrunner-lx +mainboard lippert/roadrunner-lx + +# HACK to get the right TSC support. +option CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1 + +option CONFIG_COMPRESSED_PAYLOAD_NRV2B=0 +option CONFIG_COMPRESSED_PAYLOAD_LZMA=0 + +## Load payload (e.g. Linux) from IDE. +#option CONFIG_ROM_PAYLOAD=0 +#option CONFIG_IDE=1 +#option CONFIG_FS_PAYLOAD=1 +#option CONFIG_FS_EXT2=1 +#option AUTOBOOT_DELAY=0 +#option AUTOBOOT_CMDLINE="hda1:/payload.elf" + +# Leave 36k for VSA. Usually board is equipped with a 512 KB FWH (LPC) flash, +# however it can be replaced with a 1 MB chip. +option ROM_SIZE=512*1024-36*1024 +#option ROM_SIZE=1024*1024-36*1024 +option FALLBACK_SIZE=ROM_SIZE + +#option DEFAULT_CONSOLE_LOGLEVEL = 4 +#option MAXIMUM_CONSOLE_LOGLEVEL = 4 + +# Saves space on ROM_IMAGE_SIZE, but decompression costs a second on boot. +option CONFIG_COMPRESS = 1 + +romimage "image" + option USE_FALLBACK_IMAGE=1 + option ROM_IMAGE_SIZE=64*1024 + option COREBOOT_EXTRA_VERSION=".0" + payload ../payload.elf + # If getting payload from IDE + #payload /dev/null +end + +buildrom ./coreboot.rom ROM_SIZE "image"

1 0

[PATCH] new board: LiPPERT Cool RoadRunner-LX
by Jens Rottmann 19 Nov '08

19 Nov '08

Add support for the LiPPERT Cool RoadRunner-LX embedded PC board: - PC/104+ form factor - AMD Geode-LX CPU/northbridge - AMD CS5536 southbridge - ITE IT8712F superio http://www.lippert-at.com/index.php?id=408 Signed-off-by: Jens Rottmann <JRottmann(a)LiPPERTEmbedded.de> --- I had developed this at the same time as our SpaceRunner-LX support, and now got permission to release this, too, so here it is. :) Best regards, Jens Rottmann Signed-off-by: Jens Rottmann <JRottmann(a)LiPPERTEmbedded.de> Index: src/mainboard/lippert/roadrunner-lx/cache_as_ram_auto.c =================================================================== --- src/mainboard/lippert/roadrunner-lx/cache_as_ram_auto.c (revision 0) +++ src/mainboard/lippert/roadrunner-lx/cache_as_ram_auto.c (working copy) @@ -0,0 +1,164 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 LiPPERT Embedded Computers GmbH + * Copyright (C) 2007 Advanced Micro Devices, Inc. + * + * Based on cache_as_ram_auto.c from AMD's DB800 and DBM690T mainboards. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define ASSEMBLY 1 + +#include <stdlib.h> +#include <stdint.h> +#include <device/pci_def.h> +#include <arch/io.h> +#include <device/pnp_def.h> +#include <arch/hlt.h> +#include "pc80/serial.c" +#include "arch/i386/lib/console.c" +#include "ram/ramtest.c" +#include "cpu/x86/bist.h" +#include "cpu/x86/msr.h" +#include <cpu/amd/lxdef.h> +#include <cpu/amd/geode_post_code.h> +#include "southbridge/amd/cs5536/cs5536.h" + +#define POST_CODE(x) outb(x, 0x80) + +#include "southbridge/amd/cs5536/cs5536_early_smbus.c" +#include "southbridge/amd/cs5536/cs5536_early_setup.c" +#include "superio/ite/it8712f/it8712f_early_serial.c" + +#define ManualConf 1 /* No automatic strapped PLL config */ +#define PLLMSRhi 0x0000049C /* Manual settings for the PLL */ +#define PLLMSRlo 0x00DE6001 +#define DIMM0 0xA0 +#define DIMM1 0xA2 + +static inline int spd_read_byte(unsigned int device, unsigned int address) +{ + if (device != DIMM0) return 0xFF; // no DIMM1, don't even try + return smbus_read_byte(device, address); +} + +#include "northbridge/amd/lx/raminit.h" +#include "northbridge/amd/lx/pll_reset.c" +#include "northbridge/amd/lx/raminit.c" +#include "sdram/generic_sdram.c" +#include "cpu/amd/model_lx/cpureginit.c" +#include "cpu/amd/model_lx/syspreinit.c" + +static void msr_init(void) +{ + msr_t msr; + + /* Setup access to the cache for under 1MB. */ + msr.hi = 0x24fffc02; + msr.lo = 0x1000A000; /* 0-A0000 write back */ + wrmsr(CPU_RCONF_DEFAULT, msr); + + msr.hi = 0x0; /* Write back */ + msr.lo = 0x0; + wrmsr(CPU_RCONF_A0_BF, msr); + wrmsr(CPU_RCONF_C0_DF, msr); + wrmsr(CPU_RCONF_E0_FF, msr); + + /* Setup access to the cache for under 640K. Note MC not setup yet. */ + msr.hi = 0x20000000; + msr.lo = 0xfff80; + wrmsr(MSR_GLIU0 + 0x20, msr); + + msr.hi = 0x20000000; + msr.lo = 0x80fffe0; + wrmsr(MSR_GLIU0 + 0x21, msr); + + msr.hi = 0x20000000; + msr.lo = 0xfff80; + wrmsr(MSR_GLIU1 + 0x20, msr); + + msr.hi = 0x20000000; + msr.lo = 0x80fffe0; + wrmsr(MSR_GLIU1 + 0x21, msr); +} + +static const u16 sio_init_table[] = { // hi=data, lo=index + 0x0707, // select LDN 7 (GPIO, SPI, watchdog, ...) + 0x1E2C, // disable ATXPowerGood - will cause a reboot! + 0x0423, // don't delay POWerOK1/2 + 0x9072, // watchdog triggers POWOK, counts seconds +#if !USE_WATCHDOG_ON_BOOT + 0x0073, 0x0074, // disable watchdog by setting timeout to 0 +#endif + 0xBF25, 0x372A, 0xF326, // select GPIO function for most pins + 0xBF27, 0xFF28, 0x2529, // (GP36=FAN_CTL3, GP13=PWROK1) + 0x1E2C, // VIN6=enabled?, FAN4/5 enabled, VIN7=internal, VIN3=enabled + 0x46B8, 0x0CB9, // enable pullups + 0x36C0, // enable Simple-I/O for GP15,14,12,11= LIVE_LED, WD_ACTIVE, RS485_EN2,1 + 0xFFC3, // enable Simple-I/O for GP47-40 (GPIOs on Supervisory Connector) + 0x26C8, // config GP15,12,11 as output; GP14 as input + 0x2DF5, // map Hw Monitor Thermal Output to GP55 + 0x0DF8, // map GP LED Blinking 1 to GP15=LIVE_LED (deactivate Simple-I/O to use) +}; + +/* Early mainboard specific GPIO setup. */ +static void mb_gpio_init(void) +{ + int i; + + /* Init SuperIO WDT, GPIOs. Done early, WDT init may trigger reset! */ + it8712f_enter_conf(); + for (i=0; i<ARRAY_SIZE(sio_init_table); i++) { + u16 val = sio_init_table[i]; + outb((u8)val, SIO_INDEX); outb(val>>8, SIO_DATA); + } + it8712f_exit_conf(); +} + +void cache_as_ram_main(void) +{ + POST_CODE(0x01); + + static const struct mem_controller memctrl[] = { + {.channel0 = {(0xa << 3) | 0, (0xa << 3) | 1}} + }; + + SystemPreInit(); + msr_init(); + + cs5536_early_setup(); + + /* Note: must do this AFTER the early_setup! It is counting on some + * early MSR setup for CS5536. + */ + it8712f_enable_serial(0, TTYS0_BASE); // does not use its 1st parameter + mb_gpio_init(); + uart_init(); + console_init(); + + pll_reset(ManualConf); + + cpuRegInit(); + + sdram_initialize(1, memctrl); + + /* Check memory. */ + /* ram_check(0x00000000, 640 * 1024); */ + + /* Memory is setup. Return to cache_as_ram.inc and continue to boot. */ + return; +} Index: src/mainboard/lippert/roadrunner-lx/chip.h =================================================================== --- src/mainboard/lippert/roadrunner-lx/chip.h (revision 0) +++ src/mainboard/lippert/roadrunner-lx/chip.h (working copy) @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 LiPPERT Embedded Computers GmbH + * + * Based on chip.h from AMD's DB800 mainboard. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> + +extern struct chip_operations mainboard_lippert_roadrunner_lx_ops; + +struct mainboard_lippert_roadrunner_lx_config { + u8 sio_gp1x_config; // bit5=Live LED, bit2=RS485_EN2, bit1=RS485_EN1 +}; Index: src/mainboard/lippert/roadrunner-lx/Config.lb =================================================================== --- src/mainboard/lippert/roadrunner-lx/Config.lb (revision 0) +++ src/mainboard/lippert/roadrunner-lx/Config.lb (working copy) @@ -0,0 +1,232 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2008 LiPPERT Embedded Computers GmbH +## +## Based on Config.lb from AMD's DB800 and DBM690T mainboards. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +## +## Compute the location and size of where this firmware image +## (coreboot plus bootloader) will live in the boot rom chip. +## +if USE_FALLBACK_IMAGE + default ROM_SECTION_SIZE = FALLBACK_SIZE + default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE ) +else + default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) + default ROM_SECTION_OFFSET = 0 +end + +## +## Compute the start location and size size of +## The coreboot bootloader. +## + +default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) +default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) + +## +## Compute where this copy of coreboot will start in the boot rom +## +default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) + +## +## Compute a range of ROM that can cached to speed up coreboot, +## execution speed. +## +## XIP_ROM_SIZE must be a power of 2. +## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE +## +default XIP_ROM_SIZE=65536 +default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE ) + + +## +## Set all of the defaults for an x86 architecture +## + +arch i386 end + +## +## Build the objects we have code for in this directory. +## + +driver mainboard.o + +if HAVE_PIRQ_TABLE + object irq_tables.o +end + +if USE_DCACHE_RAM + #compile cache_as_ram.c to auto.inc + makerule ./cache_as_ram_auto.inc + depends "$(MAINBOARD)/cache_as_ram_auto.c" + action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@" + action "perl -e 's/.rodata/.rom.data/g' -pi $@" + action "perl -e 's/.text/.section .rom.text/g' -pi $@" + end +end + + +## +## Build our 16 bit and 32 bit coreboot entry code +## +mainboardinit cpu/x86/16bit/entry16.inc +mainboardinit cpu/x86/32bit/entry32.inc +ldscript /cpu/x86/16bit/entry16.lds +ldscript /cpu/x86/32bit/entry32.lds + +## +## Build our reset vector (This is where coreboot is entered) +## +if USE_FALLBACK_IMAGE + mainboardinit cpu/x86/16bit/reset16.inc + ldscript /cpu/x86/16bit/reset16.lds +else + mainboardinit cpu/x86/32bit/reset32.inc + ldscript /cpu/x86/32bit/reset32.lds +end + +### Should this be in the northbridge code? +#not in serengeti_cheetah mainboardinit arch/i386/lib/cpu_reset.inc + +## +## Include an id string (For safe flashing) +## +mainboardinit arch/i386/lib/id.inc +ldscript /arch/i386/lib/id.lds + +### +### This is the early phase of coreboot startup +### Things are delicate and we test to see if we should +### failover to another image. +### +if USE_FALLBACK_IMAGE + ldscript /arch/i386/lib/failover.lds +# mainboardinit ./failover.inc +end + +### +### O.k. We aren't just an intermediary anymore! +### + +## +## Setup RAM +## +mainboardinit cpu/x86/fpu/enable_fpu.inc + +if USE_DCACHE_RAM + mainboardinit cpu/amd/model_lx/cache_as_ram.inc + mainboardinit ./cache_as_ram_auto.inc +end + +## +## Include the secondary Configuration files +## +dir /pc80 +config chip.h +register "sio_gp1x_config" = "0x20" # bit1 switches Com1 to RS485, bit2 same for Com2, bit5 turns off Live LED + +chip northbridge/amd/lx + device pci_domain 0 on + device pci 1.0 on end # Northbridge + device pci 1.1 on end # Graphics + device pci 1.2 on end # AES + chip southbridge/amd/cs5536 + # IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK + # SIRQ Mode = Active(Quiet) mode. Save power.... + # Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse, UARTs, etc IRQs. OK + register "lpc_serirq_enable" = "0x000012DA" # 00010010 11011010 + register "lpc_serirq_polarity" = "0x0000ED25" # inverse of above + register "lpc_serirq_mode" = "1" + register "enable_gpio_int_route" = "0x0D0C0700" + register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash + register "enable_USBP4_device" = "0" # 0: host, 1:device + register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381) + register "com1_enable" = "0" + register "com1_address" = "0x3E8" + register "com1_irq" = "6" + register "com2_enable" = "0" + register "com2_address" = "0x2E8" + register "com2_irq" = "6" + register "unwanted_vpci[0]" = "0" # End of list has a zero + device pci 8.0 on end # Slot4 + device pci 9.0 on end # Slot3 + device pci a.0 on end # Slot2 + device pci b.0 on end # Slot1 + device pci c.0 on end # IT8888 + device pci e.0 on end # Ethernet + device pci f.0 on # ISA Bridge + chip superio/ite/it8712f + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.2 on # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.3 on # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.4 on # EC + io 0x60 = 0x290 + io 0x62 = 0x230 + irq 0x70 = 9 + end + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + device pnp 2e.6 on # Mouse + irq 0x70 = 12 + end + device pnp 2e.7 on # GPIO + io 0x62 = 0x1220 + #io 0x64 = 0x1200 + end + device pnp 2e.8 off # MIDI + io 0x60 = 0x300 + irq 0x70 = 9 + end + device pnp 2e.9 off # GAME + io 0x60 = 0x220 + end + device pnp 2e.a off end # CIR + end + end + device pci f.2 on end # IDE Controller + device pci f.3 on end # Audio + device pci f.4 on end # OHCI + device pci f.5 on end # EHCI + end + end + # APIC cluster is late CPU init. + device apic_cluster 0 on + chip cpu/amd/model_lx + device apic 0 on end + end + end +end Index: src/mainboard/lippert/roadrunner-lx/irq_tables.c =================================================================== --- src/mainboard/lippert/roadrunner-lx/irq_tables.c (revision 0) +++ src/mainboard/lippert/roadrunner-lx/irq_tables.c (working copy) @@ -0,0 +1,75 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 LiPPERT Embedded Computers GmbH + * + * Based on irq_tables.c from AMD's DB800 mainboard. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/pirq_routing.h> +#include <console/console.h> +#include <arch/io.h> +#include <arch/pirq_routing.h> +#include "../../../southbridge/amd/cs5536/cs5536.h" + +/* Platform IRQs */ +#define PIRQA 10 +#define PIRQB 11 +#define PIRQC 5 +#define PIRQD 15 + +/* Map */ +#define M_PIRQA (1 << PIRQA) /* Bitmap of supported IRQs */ +#define M_PIRQB (1 << PIRQB) /* Bitmap of supported IRQs */ +#define M_PIRQC (1 << PIRQC) /* Bitmap of supported IRQs */ +#define M_PIRQD (1 << PIRQD) /* Bitmap of supported IRQs */ + +/* Link */ +#define L_PIRQA 1 /* Means Slot INTx# Connects To Chipset INTA# */ +#define L_PIRQB 2 /* Means Slot INTx# Connects To Chipset INTB# */ +#define L_PIRQC 3 /* Means Slot INTx# Connects To Chipset INTC# */ +#define L_PIRQD 4 /* Means Slot INTx# Connects To Chipset INTD# */ + +const struct irq_routing_table intel_irq_routing_table = { + PIRQ_SIGNATURE, /* u32 signature */ + PIRQ_VERSION, /* u16 version */ + 32 + 16 * IRQ_SLOT_COUNT, /* there can be total 7 devices on the bus */ + 0x00, /* Where the interrupt router lies (bus) */ + (0x0F << 3) | 0x0, /* Where the interrupt router lies (dev) */ + 0x00, /* IRQs devoted exclusively to PCI usage */ + 0x100B, /* Vendor */ + 0x002B, /* Device */ + 0, /* Crap (miniport) */ + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* u8 rfu[11] */ + 0xE0, /* u8 checksum , this has to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ + { + /* If you change the number of entries, change the IRQ_SLOT_COUNT above! */ + /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* cpu */ + {0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0}, /* chipset */ + {0x00, (0x0E << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* ethernet */ + {0x00, (0x0B << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x1, 0x0}, /* slot1 */ + {0x00, (0x0A << 3) | 0x0, {{L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}}, 0x2, 0x0}, /* slot2 */ + {0x00, (0x09 << 3) | 0x0, {{L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}}, 0x3, 0x0}, /* slot3 */ + {0x00, (0x08 << 3) | 0x0, {{L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}}, 0x4, 0x0}, /* slot4 */ + } +}; + +unsigned long write_pirq_routing_table(unsigned long addr) +{ + return copy_pirq_routing_table(addr); +} Index: src/mainboard/lippert/roadrunner-lx/mainboard.c =================================================================== --- src/mainboard/lippert/roadrunner-lx/mainboard.c (revision 0) +++ src/mainboard/lippert/roadrunner-lx/mainboard.c (working copy) @@ -0,0 +1,74 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 LiPPERT Embedded Computers GmbH + * + * Based on mainboard.c from AMD's DB800 mainboard. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdlib.h> +#include <stdint.h> +#include <console/console.h> +#include <device/device.h> +#include <arch/io.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include "chip.h" + +static const u16 ec_init_table[] = { // hi=data, lo=index + 0x1900, // enable monitoring + 0x0351, // TMPIN1,2 diode mode, TMPIN3 off + 0x805C, // unlock zero adjust + 0x7056, 0x3C57, // zero adjust TMPIN1,2 + 0x005C, // lock zero adjust + 0xD014 // also set FAN_CTL polarity to Active High +}; + +static void init(struct device *dev) +{ + struct mainboard_lippert_roadrunner_lx_config *mb = dev->chip_info; + unsigned int gpio_base, i; + printk_debug("LiPPERT RoadRunner-LX ENTER %s\n", __FUNCTION__); + + /* Init CS5536 GPIOs */ + gpio_base = pci_read_config32(dev_find_device(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, 0), + PCI_BASE_ADDRESS_1) - 1; + outl(0x00000040, gpio_base + 0x00); // GPIO6 value 1 - LAN_PD# + outl(0x00000040, gpio_base + 0x04); // GPIO6 output 1 - LAN_PD# + outl(0x00000400, gpio_base + 0x34); // GPIO10 in aux1 1 - THRM_ALRM# + outl(0x00000400, gpio_base + 0x20); // GPIO10 input 1 - THRM_ALRM# + outl(0x08000000, gpio_base + 0x98); // GPIO27 pull up 0 - PM-LED + + /* Init Environment Controller */ + for (i=0; i<ARRAY_SIZE(ec_init_table); i++) { + u16 val = ec_init_table[i]; + outb((u8)val, 0x0295); outb(val>>8, 0x0296); + } + + outb(mb->sio_gp1x_config, 0x1220); // Simple-I/O GP17-10 + printk_debug("LiPPERT RoadRunner-LX EXIT %s\n", __FUNCTION__); +} + +static void enable_dev(struct device *dev) +{ + dev->ops->init = init; +} + +struct chip_operations mainboard_lippert_roadrunner_lx_ops = { + CHIP_NAME("LiPPERT RoadRunner-LX Mainboard") + .enable_dev = enable_dev, +}; Index: src/mainboard/lippert/roadrunner-lx/Options.lb =================================================================== --- src/mainboard/lippert/roadrunner-lx/Options.lb (revision 0) +++ src/mainboard/lippert/roadrunner-lx/Options.lb (working copy) @@ -0,0 +1,211 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2008 LiPPERT Embedded Computers GmbH +## +## Based on Options.lb from AMD's DB800 mainboard. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +uses HAVE_MP_TABLE +uses HAVE_PIRQ_TABLE +uses USE_FALLBACK_IMAGE +uses HAVE_FALLBACK_BOOT +uses HAVE_HARD_RESET +uses HAVE_OPTION_TABLE +uses USE_OPTION_TABLE +uses CONFIG_ROM_PAYLOAD +uses CONFIG_IDE +uses CONFIG_FS_PAYLOAD +uses CONFIG_FS_EXT2 +uses AUTOBOOT_DELAY +uses AUTOBOOT_CMDLINE +uses IRQ_SLOT_COUNT +uses MAINBOARD +uses MAINBOARD_VENDOR +uses MAINBOARD_PART_NUMBER +uses COREBOOT_EXTRA_VERSION +uses ARCH +uses FALLBACK_SIZE +uses STACK_SIZE +uses HEAP_SIZE +uses ROM_SIZE +uses ROM_SECTION_SIZE +uses ROM_IMAGE_SIZE +uses ROM_SECTION_SIZE +uses ROM_SECTION_OFFSET +uses CONFIG_ROM_PAYLOAD_START +uses CONFIG_COMPRESS +uses CONFIG_COMPRESSED_PAYLOAD_NRV2B +uses CONFIG_COMPRESSED_PAYLOAD_LZMA +uses CONFIG_PRECOMPRESSED_PAYLOAD +uses PAYLOAD_SIZE +uses _ROMBASE +uses _RAMBASE +uses XIP_ROM_SIZE +uses XIP_ROM_BASE +uses HAVE_MP_TABLE +uses CROSS_COMPILE +uses CC +uses HOSTCC +uses OBJCOPY +uses DEBUG +uses DEFAULT_CONSOLE_LOGLEVEL +uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_CONSOLE_SERIAL8250 +uses TTYS0_BAUD +uses TTYS0_BASE +uses TTYS0_LCS +uses CONFIG_UDELAY_TSC +uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 +uses CONFIG_CONSOLE_VGA +uses CONFIG_PCI_ROM_RUN +uses CONFIG_VIDEO_MB +uses USE_DCACHE_RAM +uses DCACHE_RAM_BASE +uses DCACHE_RAM_SIZE +uses PIRQ_ROUTE + +## ROM_SIZE is the size of boot ROM that this board will use. +default ROM_SIZE = 512*1024 + +### +### Build options +### +default CONFIG_CONSOLE_VGA=0 +default CONFIG_VIDEO_MB=8 +default CONFIG_PCI_ROM_RUN=0 + +## +## Build code for the fallback boot +## +default HAVE_FALLBACK_BOOT=1 + +## +## no MP table +## +default HAVE_MP_TABLE=0 + +## +## Build code to reset the motherboard from coreboot +## +default HAVE_HARD_RESET=0 + +## Delay timer options +## +default CONFIG_UDELAY_TSC=1 +default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1 + +## +## Build code to export a programmable irq routing table +## +default HAVE_PIRQ_TABLE=1 +default IRQ_SLOT_COUNT=7 +default PIRQ_ROUTE=1 + +## +## Build code to export a CMOS option table +## +default HAVE_OPTION_TABLE=0 + +### +### coreboot layout values +### + +## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default ROM_IMAGE_SIZE = 65536 +default FALLBACK_SIZE = 131072 + +## +## enable CACHE_AS_RAM specifics +## +default USE_DCACHE_RAM=1 +default DCACHE_RAM_BASE=0xc8000 +default DCACHE_RAM_SIZE=0x08000 + +## +## Use a small 8K stack +## +default STACK_SIZE=0x2000 + +## +## Use a small 16K heap +## +default HEAP_SIZE=0x4000 + +## +## Only use the option table in a normal image +## +#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE +default USE_OPTION_TABLE = 0 + +default _RAMBASE = 0x00004000 + +default CONFIG_ROM_PAYLOAD = 1 + +## +## The default compiler +## +default CROSS_COMPILE="" +default CC="$(CROSS_COMPILE)gcc -m32" +default HOSTCC="gcc" + +## +## The Serial Console +## + +# To Enable the Serial Console +default CONFIG_CONSOLE_SERIAL8250=1 + +## Select the serial console baud rate +default TTYS0_BAUD=115200 +#default TTYS0_BAUD=57600 +#default TTYS0_BAUD=38400 +#default TTYS0_BAUD=19200 +#default TTYS0_BAUD=9600 +#default TTYS0_BAUD=4800 +#default TTYS0_BAUD=2400 +#default TTYS0_BAUD=1200 + +# Select the serial console base port +default TTYS0_BASE=0x3f8 + +# Select the serial protocol +# This defaults to 8 data bits, 1 stop bit, and no parity +default TTYS0_LCS=0x3 + +# Compile extra debugging code +default DEBUG=1 + +## +### Select the coreboot loglevel +## +## EMERG 1 system is unusable +## ALERT 2 action must be taken immediately +## CRIT 3 critical conditions +## ERR 4 error conditions +## WARNING 5 warning conditions +## NOTICE 6 normal but significant condition +## INFO 7 informational +## DEBUG 8 debug-level messages +## SPEW 9 Way too many details + +## Request this level of debugging output +default DEFAULT_CONSOLE_LOGLEVEL=8 +## At a maximum only compile in this level of debugging +default MAXIMUM_CONSOLE_LOGLEVEL=8 + +end Index: targets/lippert/roadrunner-lx/Config.lb =================================================================== --- targets/lippert/roadrunner-lx/Config.lb (revision 0) +++ targets/lippert/roadrunner-lx/Config.lb (working copy) @@ -0,0 +1,62 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2008 LiPPERT Embedded Computers GmbH +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +# Config file for the LiPPERT Cool RoadRunner-LX, --JR 10/2008 +# based on Config.lb for the AMD Geode LX/5536 DB800 platform. + +target roadrunner-lx +mainboard lippert/roadrunner-lx + +# HACK to get the right TSC support. +option CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1 + +option CONFIG_COMPRESSED_PAYLOAD_NRV2B=0 +option CONFIG_COMPRESSED_PAYLOAD_LZMA=0 + +## Load payload (e.g. Linux) from IDE. +#option CONFIG_ROM_PAYLOAD=0 +#option CONFIG_IDE=1 +#option CONFIG_FS_PAYLOAD=1 +#option CONFIG_FS_EXT2=1 +#option AUTOBOOT_DELAY=0 +#option AUTOBOOT_CMDLINE="hda1:/payload.elf" + +# Leave 36k for VSA. Usually board is equipped with a 512 KB FWH (LPC) flash, +# however it can be replaced with a 1 MB chip. +option ROM_SIZE=512*1024-36*1024 +#option ROM_SIZE=1024*1024-36*1024 +option FALLBACK_SIZE=ROM_SIZE + +#option DEFAULT_CONSOLE_LOGLEVEL = 4 +#option MAXIMUM_CONSOLE_LOGLEVEL = 4 + +# Saves space on ROM_IMAGE_SIZE, but decompression costs a second on boot. +option CONFIG_COMPRESS = 1 + +romimage "image" + option USE_FALLBACK_IMAGE=1 + option ROM_IMAGE_SIZE=64*1024 + option COREBOOT_EXTRA_VERSION=".0" + payload ../payload.elf + # If getting payload from IDE + #payload /dev/null +end + +buildrom ./coreboot.rom ROM_SIZE "image"

1 0

Re: [coreboot] r1044 - in coreboot-v3: device include/device superio/fintek/f71805f superio/ite/it8712f superio/ite/it8716f superio/winbond/w83627hf superio/winbond/w83627thg
by Peter Stuge 19 Nov '08

19 Nov '08

svn(a)coreboot.org wrote: > Author: uwe > Date: 2008-11-18 23:32:05 +0100 (Tue, 18 Nov 2008) > New Revision: 1044 Nice! Thanks! //Peter

1 0

v3 amd8132 fixes
by Myles Watson 19 Nov '08

19 Nov '08

This patch fixes the 8132 so that it can use a 40-bit address space and so that it uses the correct functions. Using the device functions on the bridge was not so good for it. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Thanks, Myles

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coreboot November 2008