coreboot November 2008

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490 discussions

Re: [coreboot] HT chains fixup
by Marc Jones 21 Nov '08

21 Nov '08

On Wed, Nov 19, 2008 at 9:16 PM, Myles Watson <mylesgw(a)gmail.com> wrote: > > >> -----Original Message----- >> From: Marc Jones [mailto:marcj303@gmail.com] >> Sent: Wednesday, November 19, 2008 4:11 PM >> To: Myles Watson >> Subject: Re: [coreboot] HT chains fixup >> >> Myles, >> Hi, sorry to take so long to look at this. I have some possibly dumb >> questions. > > No problem. I appreciate the review. > >> What is gained by knowing the ht path? > When a HT chain is powered on, all the devices have the same UnitID (0) > The subordinate busses get assigned bus numbers in the order that they are > found by PCI scan, but they are found in the order of the chain. As you > assign each a device number, another device is visible at device 0 until the > end of the chain is found. > But I think that the unitid scan happens before and device/dts is used or called. This has to be done to set the HT link speed. See northbridge\amd\k8\incoherent_ht.c. By the time the device code starts they are setup and the bus can be scanned as normal pci. >> Every HT bridge/tunnel under a >> CPU acts like a PCI device. Linux doesn't know about HT and I am not >> sure that the dts needs to. > > That's why I made ht devices morph into pci devices at chain enumeration > time. Once they're assigned UnitIDs it doesn't matter where they are in the > chain. > Because it is a unitid bus number it is already numbered. I think that the device code should use any bus number already set. That would be equivalent to setting the bus number with pci_x@ in the dts. >> The exception being that coreboot needs to >> know the CPU that the bus comes off of. I feel like I am missing >> something obvious that you, Ron, and others understand. > > I'm getting just as much push back from everyone else. I'm not sure anyone > understands the code that well. I feel silly for having to rewrite so much > of it. It probably points to my lack of understanding. > >> What are you describing with and ht@? For example: >> + ht@0,a { >> + > /config/("southbridge/amd/amd8132/pcix.dts"); >> + }; >> + pci_a@0,1{ >> + > /config/("southbridge/amd/amd8132/apic.dts"); > > ht@0,a is ht chain 0, UnitID a. I wanted it to be explicit where the chains > end and what the numbers are. The way the code works is that it takes the > HT device and all the PCI devices that it implements off the list at once. > Without knowing which devices are HT, that's hard to tell. The code before > used a heuristic and a lot of #if statements. > How does the code treat an ht device differently at this point? > The reason I put pci_a here is that otherwise device 0,1 of the 8132 > collides with 0,1 of the 8111 (their dts names are the same.) > > The reason for specifying the chain number is that devices could be inserted > in a lot of places, and it is nice to be able to specify which one you mean. > Think of an 8-way box where you could replace any of the processors with a > co-processor. It gets ugly in a hurry. > So shouldn't you treat it like any bridge? ( I think this is how bridges should be treated.) pci@0,1{ /config/bridge dts pci@0,0{ /config/device dts }; }; Since ht bridges are getting special names should pci bridges? pcib@x,y >> Another nit I have is that pci_18_0 is the top device. Physically it >> is but logically it isn't. The dts doesn't make sense when you compare >> it with the lspci. I don't know if this is really better but maybe >> something like this: > > My next patches will move everything from being a child of 18.0 to being a > child of the domain. That's assuming I ever get agreement for what I'm > doing :) I plan to have it look like this: > > domain { > /k8/domain > ht@0,a > ht@0,6 > pci@18,0 > pci@18,1 > pci@18,2 > pci@18,3 > pci@19,0 > ... > }; > So a ht link off of another cpu will be a new domain? Do you know how the 8151 will be defined in the Serengeti dts? >> > domain_0_pci_18_0_ht_0_6(PCI: 00:06.0): enabled 1 have_resources 0 > > This will be domain_0_ht_0_6 if I get my way. great > >> What if this were a real PCI to PCI bridge? Would it be >> domain_0_pci_18_0_pci_0_6? > > Yes, but there's no such thing with an Opteron, right? It would have to be > another level down in the hierarchy like domain_0_ht_0_6_pci_6_0 (remember > that HT UnitID and PCI dev are the same, so ht_0_6 becomes pci_6_0.) > I meant if the ht bridge that acts like a pci bridge were a real pci bridge. I think then it is domain_0_pci_18_0_pci_0_6. >> > domain_0_pci_18_0_ht_0_6_pci_0_0(PCI: 01:00.0): enabled 1 >> have_resources >> > 0 >> >> Why isn't this domain_0_pci_18_0_ht_0_6_pci_1_0_0? > Bus numbers get assigned as they're discovered, so they aren't mentioned in > the dts. That's why the 8111 has to be at 0x6 and the 8132 has to be at > 0xa, otherwise the 8132's busses get numbered first, and the southbridge > ends up on bus 3. Actually the 8111 just has to have a lower number. 0x0 > and 0x2 also work. > This is what I noted above. Devices under a bridge need to be in the bridge brackets so you know where they are regardless of bus numbering. >> > domain_0_pci_18_0_ht_0_6_pci_0_1(PCI: 01:00.1): enabled 1 >> have_resources >> > 0 >> ... >> > domain_0_pci_18_0_pci_6_1_0(PCI: 00:07.0): enabled 1 have_resources 0 >> >> I really don't understand this one. It is a device on bus 0 so what >> does 6_1_0 mean? > > It's device 1 function 0 of the pci_6 ht device. Remember I had to add the > _6 so that it wouldn't have the same name as pci_a_1_0. I agree it's > confusing. I couldn't think of a really great way to do it. Maybe just > taking out the extra underscore would help: > > domain_0_pci6_0_1 > or naming it explicitly > domain_0_pciht6_0_1 > > I'm open to suggestions. This still doesn't make sense to me. It is on the silicon that happens to be a HT device but it is just a pci device on bus 0. Think of it in terms of any other motherboard device. The device is always at the same location in the system. This one happens to be set to unitid+1. I think that you still set it in the dts as pci@0,7. >> > Here are some of the next steps: >> > - Get video working. >> >> Do you know where the breakage is? > I think it's in resource allocation. It's really hard to follow, though. > In the end the 8132 claims the address space that should be for the video > buffer, and it never gets to the card. Is the Subtractive or VGA bits set in the 8132 bridge or is the BAR claiming the area? Marc

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r3765 build service
by coreboot information 21 Nov '08

21 Nov '08

Dear coreboot readers! This is the automated build check service of coreboot. The developer "uwe" checked in revision 3765 to the coreboot source repository and caused the following changes: Change Log: i810: Add support for multiple DIMMs, both single-sided and double-sided, as well as most (all?) combinations thereof. Drop some unused code, the unused row_offset variable, and obsolete comments. Also, fix a typo (thanks to Stefan Reinauer for noticing). This is tested on the MSI MS-6178 with a number of different DIMM combinations and so far all of them worked fine. Signed-off-by: Elia Yehuda <z4ziggy(a)gmail.com> Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Peter Stuge <peter(a)stuge.se> Build Log: Compilation of digitallogic:msm586seg has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3765&device=msm586seg&vend… If something broke during this checkin please be a pain in uwe's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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r3765 - trunk/coreboot-v2/src/northbridge/intel/i82810
by svn＠coreboot.org 21 Nov '08

21 Nov '08

Author: uwe Date: 2008-11-21 18:14:40 +0100 (Fri, 21 Nov 2008) New Revision: 3765 Modified: trunk/coreboot-v2/src/northbridge/intel/i82810/raminit.c Log: i810: Add support for multiple DIMMs, both single-sided and double-sided, as well as most (all?) combinations thereof. Drop some unused code, the unused row_offset variable, and obsolete comments. Also, fix a typo (thanks to Stefan Reinauer for noticing). This is tested on the MSI MS-6178 with a number of different DIMM combinations and so far all of them worked fine. Signed-off-by: Elia Yehuda <z4ziggy(a)gmail.com> Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/coreboot-v2/src/northbridge/intel/i82810/raminit.c =================================================================== --- trunk/coreboot-v2/src/northbridge/intel/i82810/raminit.c 2008-11-20 23:18:10 UTC (rev 3764) +++ trunk/coreboot-v2/src/northbridge/intel/i82810/raminit.c 2008-11-21 17:14:40 UTC (rev 3765) @@ -1,8 +1,9 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007 Uwe Hermann <uwe(a)hermann-uwe.de> + * Copyright (C) 2007-2008 Uwe Hermann <uwe(a)hermann-uwe.de> * Copyright (C) 2007 Corey Osgood <corey(a)slightlyhackish.com> + * Copyright (C) 2008 Elia Yehuda <z4ziggy(a)gmail.com> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -55,6 +56,22 @@ #define RAM_COMMAND_MRS 0x6 /* Mode register set */ #define RAM_COMMAND_CBR 0x7 /* CBR */ +/* + * Table which returns the RAM size in MB when fed the DRP[7:4] or [3:0] value. + * Note that 2 is a value which the DRP should never be programmed to. + * Some size values appear twice, due to single-sided vs dual-sided banks. + */ +static const u16 translate_i82810_to_mb[] = { +/* DRP 0 1 (2) 3 4 5 6 7 8 9 A B C D E F */ +/* MB */0, 8, 0, 16, 16, 24, 32, 32, 48, 64, 64, 96, 128, 128, 192, 256, +}; + +/* Size of bank#0 for dual-sided DIMMs */ +static const u8 translate_i82810_to_bank[] = { +/* DRP 0 1 (2) 3 4 5 6 7 8 9 A B C D E F */ +/* MB */0, 0, 0, 8, 0, 16, 16, 0, 32, 32, 0, 64, 64, 0, 128, 128, +}; + /*----------------------------------------------------------------------------- SDRAM configuration functions. -----------------------------------------------------------------------------*/ @@ -62,35 +79,87 @@ /** * Send the specified RAM command to all DIMMs. * - * @param TODO - * @param TODO + * @param The RAM command to send to the DIMM(s). */ -static void do_ram_command(uint32_t command, uint32_t addr_offset, - uint32_t row_offset) +static void do_ram_command(u8 command) { - uint8_t reg; + u32 addr, addr_offset; + u16 dimm_size, dimm_start, dimm_bank; + u8 reg8, drp; + int i, caslatency; - /* TODO: Support for multiple DIMMs. */ - /* Configure the RAM command. */ - reg = pci_read_config8(PCI_DEV(0, 0, 0), DRAMT); - reg &= 0x1f; /* Clear bits 7-5. */ - reg |= command << 5; - pci_write_config8(PCI_DEV(0, 0, 0), DRAMT, reg); + reg8 = pci_read_config8(PCI_DEV(0, 0, 0), DRAMT); + reg8 &= 0x1f; /* Clear bits 7-5. */ + reg8 |= command << 5; + pci_write_config8(PCI_DEV(0, 0, 0), DRAMT, reg8); - /* RAM_COMMAND_NORMAL affects only the memory controller and - doesn't need to be "sent" to the DIMMs. */ - /* if (command == RAM_COMMAND_NORMAL) return; */ + /* + * RAM_COMMAND_NORMAL affects only the memory controller and + * doesn't need to be "sent" to the DIMMs. + */ + if (command == RAM_COMMAND_NORMAL) + return; - PRINT_DEBUG(" Sending RAM command 0x"); - PRINT_DEBUG_HEX8(reg); - PRINT_DEBUG(" to 0x"); - PRINT_DEBUG_HEX32(0 + addr_offset); // FIXME - PRINT_DEBUG("\r\n"); + dimm_start = 0; + for (i = 0; i < DIMM_SOCKETS; i++) { + /* + * Calculate the address offset where we need to "send" the + * DIMM command to. For most commands the offset is 0, only + * RAM_COMMAND_MRS needs special values, see below. + * The final address offset bits depend on three things: + * + * (1) Some hardcoded values specified in the datasheet. + * (2) Which CAS latency we will use/set. This is the SMAA[4] + * bit, which is 1 for CL3, and 0 for CL2. The bitstring + * so far has the form '00000001X1010', X being SMAA[4]. + * (3) The DIMM to which we want to send the command. For + * DIMM0 no special handling is needed, but for DIMM1 we + * must invert the four bits SMAA[7:4] (see datasheet). + * + * Finally, the bitstring has to be shifted 3 bits to the left. + * See i810 datasheet pages 43, 85, and 86 for details. + */ + addr_offset = 0; + caslatency = 3; /* TODO: Dynamically get CAS latency later. */ + if (i == 0 && command == RAM_COMMAND_MRS && caslatency == 3) + addr_offset = 0x1d0; /* DIMM0, CL3, 0000111010000 */ + if (i == 1 && command == RAM_COMMAND_MRS && caslatency == 3) + addr_offset = 0x650; /* DIMM1, CL3, 0011001010000 */ + if (i == 0 && command == RAM_COMMAND_MRS && caslatency == 2) + addr_offset = 0x150; /* DIMM0, CL2, 0000101010000 */ + if (i == 1 && command == RAM_COMMAND_MRS && caslatency == 2) + addr_offset = 0x1a0; /* DIMM1, CL2, 0000110100000 */ - /* Read from (DIMM start address + addr_offset). */ - read32(0 + addr_offset); //first offset is always 0 - read32(row_offset + addr_offset); + drp = pci_read_config8(PCI_DEV(0, 0, 0), DRP); + drp = (drp >> (i * 4)) & 0x0f; + + dimm_size = translate_i82810_to_mb[drp]; + addr = (dimm_start * 1024 * 1024) + addr_offset; + if (dimm_size) { + PRINT_DEBUG(" Sending RAM command 0x"); + PRINT_DEBUG_HEX8(reg8); + PRINT_DEBUG(" to 0x"); + PRINT_DEBUG_HEX32(addr); + PRINT_DEBUG("\r\n"); + + read32(addr); + } + + dimm_bank = translate_i82810_to_bank[drp]; + addr = ((dimm_start + dimm_bank) * 1024 * 1024) + addr_offset; + if (dimm_bank) { + PRINT_DEBUG(" Sending RAM command 0x"); + PRINT_DEBUG_HEX8(reg8); + PRINT_DEBUG(" to 0x"); + PRINT_DEBUG_HEX32(addr); + PRINT_DEBUG("\r\n"); + + read32(addr); + } + + dimm_start += dimm_size; + } } /*----------------------------------------------------------------------------- @@ -100,7 +169,7 @@ /* * Set DRP - DRAM Row Population Register (Device 0). */ -static void spd_set_dram_size(uint32_t row_offset) +static void spd_set_dram_size(void) { /* The variables drp and dimm_size have to be ints since all the * SMBus-related functions return ints, and its just easier this way. @@ -137,36 +206,6 @@ dimm_size = 32; } - /* Set the row offset, in KBytes (should this be - * Kbits?). Note that this offset is the start of the - * next row. - */ - row_offset = (dimm_size * 4 * 1024); - - /* This is the way I was doing this, it's provided - * mainly as an alternative to the "new" way. - */ - -#if 0 - /* 8MB */ - if (dimm_size == 0x2) - dimm_size = 0x1; - /* 16MB */ - else if (dimm_size == 0x4) - dimm_size = 0x4; - /* 32MB */ - else if (dimm_size == 0x8) - dimm_size = 0x7; - /* 64 MB */ - else if (dimm_size == 0x10) - dimm_size = 0xa; - /* 128 MB */ - else if (dimm_size == 0x20) - dimm_size = 0xd; - else - print_debug("Ram Size not supported\r\n"); -#endif - /* This array is provided in raminit.h, because it got * extremely messy. The above way is cleaner, but * doesn't support any asymetrical/odd configurations. @@ -212,7 +251,7 @@ /* * TODO: BUFF_SC needs to be set according to the DRAM tech (x8, x16, - * or x32), but the datasheet doesn't list all the detaisl. Currently, it + * or x32), but the datasheet doesn't list all the details. Currently, it * needs to be pulled from the output of 'lspci -xxx Rx92'. * * Common results (tested on actual hardware) are: @@ -246,9 +285,6 @@ Public interface. -----------------------------------------------------------------------------*/ -/** - * TODO. - */ static void sdram_set_registers(void) { unsigned long val; @@ -292,16 +328,10 @@ //pci_write_config8(PCI_DEV(0, 0, 0), MISSC2, val); } -/** - * TODO. - */ static void sdram_set_spd_registers(void) { - /* spd_set_dram_size() moved into sdram_enable() to prevent having - * to pass a variable between here and there. - */ + spd_set_dram_size(); set_dram_buffer_strength(); - set_dram_timing(); } @@ -312,41 +342,31 @@ { int i; - /* Todo: this will currently work with either one dual sided or two - * single sided DIMMs. Needs to work with 2 dual sided DIMMs in the - * long run. - */ - uint32_t row_offset; - - spd_set_dram_size(row_offset); - /* 1. Apply NOP. */ PRINT_DEBUG("RAM Enable 1: Apply NOP\r\n"); - do_ram_command(RAM_COMMAND_NOP, 0, row_offset); + do_ram_command(RAM_COMMAND_NOP); udelay(200); /* 2. Precharge all. Wait tRP. */ PRINT_DEBUG("RAM Enable 2: Precharge all\r\n"); - do_ram_command(RAM_COMMAND_PRECHARGE, 0, row_offset); + do_ram_command(RAM_COMMAND_PRECHARGE); udelay(1); /* 3. Perform 8 refresh cycles. Wait tRC each time. */ PRINT_DEBUG("RAM Enable 3: CBR\r\n"); - do_ram_command(RAM_COMMAND_CBR, 0, row_offset); for (i = 0; i < 8; i++) { - read32(0); - read32(row_offset); + do_ram_command(RAM_COMMAND_CBR); udelay(1); } /* 4. Mode register set. Wait two memory cycles. */ PRINT_DEBUG("RAM Enable 4: Mode register set\r\n"); - do_ram_command(RAM_COMMAND_MRS, 0x1d0, row_offset); + do_ram_command(RAM_COMMAND_MRS); udelay(2); /* 5. Normal operation (enables refresh) */ PRINT_DEBUG("RAM Enable 5: Normal operation\r\n"); - do_ram_command(RAM_COMMAND_NORMAL, 0, row_offset); + do_ram_command(RAM_COMMAND_NORMAL); udelay(1); PRINT_DEBUG("Northbridge following SDRAM init:\r\n");

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How to find out "page size" of a flash chip?
by FENG Yu Ning 21 Nov '08

21 Nov '08

In flashchip.c, there is (just an example), /* Vendor Chip ... Page size (B) ... */ ... {"SST", "SST25VF040B", ... 256, ... }, How to find out the number 256? I have read through the datasheet of that chip, which mentioned 4K sector, 32K and 64K blocks, but no "page". There is neither an operation which needs an address with value 0 in the least significant 8 bits. Or, the number does not come out of a datasheet? Thanks, yu ning

3 8

Broken link for LinuxBios on AMD64 in Documentation page.
by Cedric RIVERA 21 Nov '08

21 Nov '08

Hello, An email just to reveal a broken link in the web documentation for the wonderful Coreboot project. Thank you. Regards, Cedric RIVERA.

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[PATCH] v2: Drop mem_controller indirection for Intel 810
by Uwe Hermann 20 Nov '08

20 Nov '08

As per Stefan's suggestions, drop the mem_controller indirection as there's only one memory controller on the 810. Patch attached. Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org

2 2

r3764 - in trunk/coreboot-v2/src: mainboard/asus/mew-am mainboard/asus/mew-vm mainboard/msi/ms6178 northbridge/intel/i82810
by svn＠coreboot.org 20 Nov '08

20 Nov '08

Author: uwe Date: 2008-11-21 00:18:10 +0100 (Fri, 21 Nov 2008) New Revision: 3764 Modified: trunk/coreboot-v2/src/mainboard/asus/mew-am/auto.c trunk/coreboot-v2/src/mainboard/asus/mew-vm/auto.c trunk/coreboot-v2/src/mainboard/msi/ms6178/auto.c trunk/coreboot-v2/src/northbridge/intel/i82810/debug.c trunk/coreboot-v2/src/northbridge/intel/i82810/raminit.c trunk/coreboot-v2/src/northbridge/intel/i82810/raminit.h Log: Get rid of the unnecessary indirection by 'struct mem_controller' for the Intel 810 chipset (and all boards using it). This isn't required for this chipset as there's only one memory controller. This also helps a lot with romcc register usage, you should see the dreaded "too few registers" less often. Build-tested with all three boards using the Intel 810 chipset. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Corey Osgood <corey.osgood(a)gmail.com> Modified: trunk/coreboot-v2/src/mainboard/asus/mew-am/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/mew-am/auto.c 2008-11-20 20:07:38 UTC (rev 3763) +++ trunk/coreboot-v2/src/mainboard/asus/mew-am/auto.c 2008-11-20 23:18:10 UTC (rev 3764) @@ -48,17 +48,9 @@ #include "northbridge/intel/i82810/raminit.c" /* #include "northbridge/intel/i82810/debug.c" */ -#include "sdram/generic_sdram.c" static void main(unsigned long bist) { - static const struct mem_controller memctrl[] = { - { - .d0 = PCI_DEV(0, 0, 0), - .channel0 = {0x50, 0x51}, - } - }; - if (bist == 0) early_mtrr_init(); @@ -67,7 +59,9 @@ console_init(); report_bist_failure(bist); enable_smbus(); - /* dump_spd_registers(&memctrl[0]); */ - sdram_initialize(ARRAY_SIZE(memctrl), memctrl); + /* dump_spd_registers(); */ + sdram_set_registers(); + sdram_set_spd_registers(); + sdram_enable(); /* ram_check(0, 640 * 1024); */ } Modified: trunk/coreboot-v2/src/mainboard/asus/mew-vm/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/mew-vm/auto.c 2008-11-20 20:07:38 UTC (rev 3763) +++ trunk/coreboot-v2/src/mainboard/asus/mew-vm/auto.c 2008-11-20 23:18:10 UTC (rev 3764) @@ -52,17 +52,9 @@ #include "northbridge/intel/i82810/raminit.c" #include "northbridge/intel/i82810/debug.c" -#include "sdram/generic_sdram.c" static void main(unsigned long bist) { - static const struct mem_controller memctrl[] = { - { - .d0 = PCI_DEV(0, 0, 0), - .channel0 = {0x50, 0x51}, - } - }; - if (bist == 0) early_mtrr_init(); @@ -75,15 +67,12 @@ /* Halt if there was a built in self test failure. */ report_bist_failure(bist); - /* dump_spd_registers(&memctrl[0]); */ + /* dump_spd_registers(); */ - /* sdram_initialize() runs out of registers. */ - /* sdram_initialize(ARRAY_SIZE(memctrl), memctrl); */ + sdram_set_registers(); + sdram_set_spd_registers(); + sdram_enable(); - sdram_set_registers(memctrl); - sdram_set_spd_registers(memctrl); - sdram_enable(0, memctrl); - /* Check RAM. */ /* ram_check(0, 640 * 1024); */ } Modified: trunk/coreboot-v2/src/mainboard/msi/ms6178/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms6178/auto.c 2008-11-20 20:07:38 UTC (rev 3763) +++ trunk/coreboot-v2/src/mainboard/msi/ms6178/auto.c 2008-11-20 23:18:10 UTC (rev 3764) @@ -37,19 +37,11 @@ #include "southbridge/intel/i82801xx/i82801xx_early_smbus.c" #include "pc80/udelay_io.c" #include "northbridge/intel/i82810/raminit.c" -#include "sdram/generic_sdram.c" #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) static void main(unsigned long bist) { - static const struct mem_controller memctrl[] = { - { - .d0 = PCI_DEV(0, 0, 0), - .channel0 = {0x50, 0x51}, - } - }; - if (bist == 0) early_mtrr_init(); @@ -66,7 +58,10 @@ enable_smbus(); report_bist_failure(bist); - /* dump_spd_registers(&memctrl[0]); */ - sdram_initialize(ARRAY_SIZE(memctrl), memctrl); + + /* dump_spd_registers(); */ + sdram_set_registers(); + sdram_set_spd_registers(); + sdram_enable(); /* ram_check(0, 640 * 1024); */ } Modified: trunk/coreboot-v2/src/northbridge/intel/i82810/debug.c =================================================================== --- trunk/coreboot-v2/src/northbridge/intel/i82810/debug.c 2008-11-20 20:07:38 UTC (rev 3763) +++ trunk/coreboot-v2/src/northbridge/intel/i82810/debug.c 2008-11-20 23:18:10 UTC (rev 3764) @@ -1,11 +1,11 @@ -static void dump_spd_registers(const struct mem_controller *ctrl) +static void dump_spd_registers(void) { int i; print_debug("\r\n"); - for(i = 0; i < 4; i++) { + for(i = 0; i < DIMM_SOCKETS; i++) { unsigned device; - device = ctrl->channel0[i]; + device = DIMM_SPD_BASE + i; if (device) { int j; print_debug("dimm: "); Modified: trunk/coreboot-v2/src/northbridge/intel/i82810/raminit.c =================================================================== --- trunk/coreboot-v2/src/northbridge/intel/i82810/raminit.c 2008-11-20 20:07:38 UTC (rev 3763) +++ trunk/coreboot-v2/src/northbridge/intel/i82810/raminit.c 2008-11-20 23:18:10 UTC (rev 3764) @@ -62,22 +62,21 @@ /** * Send the specified RAM command to all DIMMs. * - * @param Memory controller * @param TODO * @param TODO */ -static void do_ram_command(const struct mem_controller *ctrl, uint32_t command, - uint32_t addr_offset, uint32_t row_offset) +static void do_ram_command(uint32_t command, uint32_t addr_offset, + uint32_t row_offset) { uint8_t reg; /* TODO: Support for multiple DIMMs. */ /* Configure the RAM command. */ - reg = pci_read_config8(ctrl->d0, DRAMT); + reg = pci_read_config8(PCI_DEV(0, 0, 0), DRAMT); reg &= 0x1f; /* Clear bits 7-5. */ reg |= command << 5; - pci_write_config8(ctrl->d0, DRAMT, reg); + pci_write_config8(PCI_DEV(0, 0, 0), DRAMT, reg); /* RAM_COMMAND_NORMAL affects only the memory controller and doesn't need to be "sent" to the DIMMs. */ @@ -101,8 +100,7 @@ /* * Set DRP - DRAM Row Population Register (Device 0). */ -static void spd_set_dram_size(const struct mem_controller *ctrl, - uint32_t row_offset) +static void spd_set_dram_size(uint32_t row_offset) { /* The variables drp and dimm_size have to be ints since all the * SMBus-related functions return ints, and its just easier this way. @@ -113,12 +111,12 @@ for (i = 0; i < DIMM_SOCKETS; i++) { /* First check if a DIMM is actually present. */ - if (smbus_read_byte(ctrl->channel0[i], 2) == 4) { + if (smbus_read_byte(DIMM_SPD_BASE + i, 2) == 4) { print_debug("Found DIMM in slot "); print_debug_hex8(i); print_debug("\r\n"); - dimm_size = smbus_read_byte(ctrl->channel0[i], 31); + dimm_size = smbus_read_byte(DIMM_SPD_BASE + i, 31); /* WISHLIST: would be nice to display it as decimal? */ print_debug("DIMM is 0x"); @@ -181,7 +179,7 @@ /* If the DIMM is dual-sided, the DRP value is +2 */ /* TODO: Figure out asymetrical configurations. */ - if ((smbus_read_byte(ctrl->channel0[i], 127) | 0xf) == + if ((smbus_read_byte(DIMM_SPD_BASE + i, 127) | 0xf) == 0xff) { print_debug("DIMM is dual-sided\r\n"); dimm_size += 2; @@ -203,13 +201,13 @@ print_debug_hex8(drp); print_debug("\r\n"); - pci_write_config8(ctrl->d0, DRP, drp); + pci_write_config8(PCI_DEV(0, 0, 0), DRP, drp); } -static void set_dram_timing(const struct mem_controller *ctrl) +static void set_dram_timing(void) { /* TODO, for now using default, hopefully safe values. */ - // pci_write_config8(ctrl->d0, DRAMT, 0x00); + // pci_write_config8(PCI_DEV(0, 0, 0), DRAMT, 0x00); } /* @@ -239,9 +237,9 @@ * 0x4445 384MB 0xfd 128MB single-sided 256MB dual-sided * 0x0001 512MB 0xff 256MB dual-sided 256MB dual-sided */ -static void set_dram_buffer_strength(const struct mem_controller *ctrl) +static void set_dram_buffer_strength(void) { - pci_write_config16(ctrl->d0, BUFF_SC, 0x77da); + pci_write_config16(PCI_DEV(0, 0, 0), BUFF_SC, 0x77da); } /*----------------------------------------------------------------------------- @@ -250,15 +248,13 @@ /** * TODO. - * - * @param Memory controller */ -static void sdram_set_registers(const struct mem_controller *ctrl) +static void sdram_set_registers(void) { unsigned long val; /* TODO */ - pci_write_config8(ctrl->d0, GMCHCFG, 0x60); + pci_write_config8(PCI_DEV(0, 0, 0), GMCHCFG, 0x60); /* PAMR: Programmable Attributes Register * Every pair of bits controls an address range: @@ -275,49 +271,44 @@ */ /* Ideally, this should be R/W for as many ranges as possible. */ - pci_write_config8(ctrl->d0, PAM, 0xff); + pci_write_config8(PCI_DEV(0, 0, 0), PAM, 0xff); /* Enabling the VGA Framebuffer currently screws up the rest of the boot. * Disable for now */ /* Enable 1MB framebuffer. */ - //pci_write_config8(ctrl->d0, SMRAM, 0xC0); + //pci_write_config8(PCI_DEV(0, 0, 0), SMRAM, 0xC0); - //val = pci_read_config16(ctrl->d0, MISSC); + //val = pci_read_config16(PCI_DEV(0, 0, 0), MISSC); /* Preserve reserved bits. */ //val &= 0xff06; /* Set graphics cache window to 32MB, no power throttling. */ //val |= 0x0001; - //pci_write_config16(ctrl->d0, MISSC, val); + //pci_write_config16(PCI_DEV(0, 0, 0), MISSC, val); - //val = pci_read_config8(ctrl->d0, MISSC2); + //val = pci_read_config8(PCI_DEV(0, 0, 0), MISSC2); /* Enable graphics palettes and clock gating (not optional!) */ //val |= 0x06; - //pci_write_config8(ctrl->d0, MISSC2, val); + //pci_write_config8(PCI_DEV(0, 0, 0), MISSC2, val); } /** * TODO. - * - * @param Memory controller */ -static void sdram_set_spd_registers(const struct mem_controller *ctrl) +static void sdram_set_spd_registers(void) { /* spd_set_dram_size() moved into sdram_enable() to prevent having * to pass a variable between here and there. */ - set_dram_buffer_strength(ctrl); + set_dram_buffer_strength(); - set_dram_timing(ctrl); + set_dram_timing(); } /** * Enable SDRAM. - * - * @param Number of controllers - * @param Memory controller */ -static void sdram_enable(int controllers, const struct mem_controller *ctrl) +static void sdram_enable(void) { int i; @@ -327,21 +318,21 @@ */ uint32_t row_offset; - spd_set_dram_size(ctrl, row_offset); + spd_set_dram_size(row_offset); /* 1. Apply NOP. */ PRINT_DEBUG("RAM Enable 1: Apply NOP\r\n"); - do_ram_command(ctrl, RAM_COMMAND_NOP, 0, row_offset); + do_ram_command(RAM_COMMAND_NOP, 0, row_offset); udelay(200); /* 2. Precharge all. Wait tRP. */ PRINT_DEBUG("RAM Enable 2: Precharge all\r\n"); - do_ram_command(ctrl, RAM_COMMAND_PRECHARGE, 0, row_offset); + do_ram_command(RAM_COMMAND_PRECHARGE, 0, row_offset); udelay(1); /* 3. Perform 8 refresh cycles. Wait tRC each time. */ PRINT_DEBUG("RAM Enable 3: CBR\r\n"); - do_ram_command(ctrl, RAM_COMMAND_CBR, 0, row_offset); + do_ram_command(RAM_COMMAND_CBR, 0, row_offset); for (i = 0; i < 8; i++) { read32(0); read32(row_offset); @@ -350,12 +341,12 @@ /* 4. Mode register set. Wait two memory cycles. */ PRINT_DEBUG("RAM Enable 4: Mode register set\r\n"); - do_ram_command(ctrl, RAM_COMMAND_MRS, 0x1d0, row_offset); + do_ram_command(RAM_COMMAND_MRS, 0x1d0, row_offset); udelay(2); /* 5. Normal operation (enables refresh) */ PRINT_DEBUG("RAM Enable 5: Normal operation\r\n"); - do_ram_command(ctrl, RAM_COMMAND_NORMAL, 0, row_offset); + do_ram_command(RAM_COMMAND_NORMAL, 0, row_offset); udelay(1); PRINT_DEBUG("Northbridge following SDRAM init:\r\n"); Modified: trunk/coreboot-v2/src/northbridge/intel/i82810/raminit.h =================================================================== --- trunk/coreboot-v2/src/northbridge/intel/i82810/raminit.h 2008-11-20 20:07:38 UTC (rev 3763) +++ trunk/coreboot-v2/src/northbridge/intel/i82810/raminit.h 2008-11-20 23:18:10 UTC (rev 3764) @@ -24,10 +24,8 @@ /* The 82810 supports max. 2 dual-sided DIMMs. */ #define DIMM_SOCKETS 2 -struct mem_controller { - device_t d0; - uint16_t channel0[DIMM_SOCKETS]; -}; +/* DIMM0 is at 0x50, DIMM1 is at 0x51. */ +#define DIMM_SPD_BASE 0x50 /* The following table has been bumped over to this header to avoid clutter in * raminit.c. It's used to translate the value read from SPD Byte 31 to a value

1 0

lsmmap
by Robert Millan 20 Nov '08

20 Nov '08

Hi! I just added this command to GRUB. I thought it could be handy sometimes, specially on coreboot: grub> lsmmap base_addr = 0x0, length = 0x1000, type = 0x2 base_addr = 0xf0000, length = 0x1000, type = 0x2 base_addr = 0x1000, length = 0xef000, type = 0x1 base_addr = 0xf1000, length = 0x1ff0f000, type = 0x1 grub> -- Robert Millan The DRM opt-in fallacy: "Your data belongs to us. We will decide when (and how) you may access your data; but nobody's threatening your freedom: we still allow you to remove your data and not access it at all."

1 0

Re: [coreboot] r3762 - trunk/coreboot-v2/src/mainboard/tyan/s2895
by Myles Watson 20 Nov '08

20 Nov '08

> -----Original Message----- > From: coreboot-bounces(a)coreboot.org [mailto:coreboot-bounces@coreboot.org] > On Behalf Of svn(a)coreboot.org > Sent: Thursday, November 20, 2008 12:26 PM > To: coreboot(a)coreboot.org > Subject: [coreboot] r3762 - trunk/coreboot-v2/src/mainboard/tyan/s2895 > > Author: stepan > Date: 2008-11-20 20:26:16 +0100 (Thu, 20 Nov 2008) > New Revision: 3762 > > Modified: > trunk/coreboot-v2/src/mainboard/tyan/s2895/cache_as_ram_auto.c > Log: > OK, people, watch this. > > This is a school book example of why trivial indent patches just suck > big time. > > This error was introduced by a trivial self-acked indent patch and was > never detected (because of a missing Config-abuild.lb) > > So, indenting the code for no reason can make it a lot worse (read: > break it) instead of improving it. > > I ask everyone to keep this in mind when going on indent-frenzy again. Guilty. I apologize. Thanks, Myles

2 1

r3763 - in trunk/coreboot-v2/targets: amd/serengeti_cheetah asus/a8n_e gigabyte/m57sli iwill/dk8_htx msi/ms7135 nvidia/l1_2pvv tyan/s2895 tyan/s2912
by svn＠coreboot.org 20 Nov '08

20 Nov '08

Author: stepan Date: 2008-11-20 21:07:38 +0100 (Thu, 20 Nov 2008) New Revision: 3763 Added: trunk/coreboot-v2/targets/asus/a8n_e/Config-abuild.lb trunk/coreboot-v2/targets/msi/ms7135/Config-abuild.lb trunk/coreboot-v2/targets/tyan/s2895/Config-abuild.lb Modified: trunk/coreboot-v2/targets/amd/serengeti_cheetah/Config-abuild.lb trunk/coreboot-v2/targets/gigabyte/m57sli/Config-abuild.lb trunk/coreboot-v2/targets/iwill/dk8_htx/Config-abuild.lb trunk/coreboot-v2/targets/nvidia/l1_2pvv/Config-abuild.lb trunk/coreboot-v2/targets/tyan/s2912/Config-abuild.lb Log: fix Config-abuild.lb for all targets that need a failover image and don't have one (by fixing it for amd/serengeti_cheetah and copying the same file to all other broken targets) Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/coreboot-v2/targets/amd/serengeti_cheetah/Config-abuild.lb =================================================================== --- trunk/coreboot-v2/targets/amd/serengeti_cheetah/Config-abuild.lb 2008-11-20 19:26:16 UTC (rev 3762) +++ trunk/coreboot-v2/targets/amd/serengeti_cheetah/Config-abuild.lb 2008-11-20 20:07:38 UTC (rev 3763) @@ -9,19 +9,27 @@ __COMPRESSION__ -option ROM_SIZE=512*1024 - romimage "normal" + option USE_FAILOVER_IMAGE=0 option USE_FALLBACK_IMAGE=0 option ROM_IMAGE_SIZE=0x20000 option COREBOOT_EXTRA_VERSION=".0-normal" payload __PAYLOAD__ end -romimage "fallback" +romimage "fallback" + option USE_FAILOVER_IMAGE=0 option USE_FALLBACK_IMAGE=1 option ROM_IMAGE_SIZE=0x20000 option COREBOOT_EXTRA_VERSION=".0-fallback" payload __PAYLOAD__ end -buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" + +romimage "failover" + option USE_FAILOVER_IMAGE=1 + option USE_FALLBACK_IMAGE=0 + option ROM_IMAGE_SIZE=FAILOVER_SIZE + option XIP_ROM_SIZE=FAILOVER_SIZE +end + +buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" "failover" Added: trunk/coreboot-v2/targets/asus/a8n_e/Config-abuild.lb =================================================================== --- trunk/coreboot-v2/targets/asus/a8n_e/Config-abuild.lb (rev 0) +++ trunk/coreboot-v2/targets/asus/a8n_e/Config-abuild.lb 2008-11-20 20:07:38 UTC (rev 3763) @@ -0,0 +1,35 @@ +# This will make a target directory of ./VENDOR_MAINBOARD + +target VENDOR_MAINBOARD +mainboard VENDOR/MAINBOARD + +option CC="CROSSCC" +option CROSS_COMPILE="CROSS_PREFIX" +option HOSTCC="CROSS_HOSTCC" + +__COMPRESSION__ + +romimage "normal" + option USE_FAILOVER_IMAGE=0 + option USE_FALLBACK_IMAGE=0 + option ROM_IMAGE_SIZE=0x20000 + option COREBOOT_EXTRA_VERSION=".0-normal" + payload __PAYLOAD__ +end + +romimage "fallback" + option USE_FAILOVER_IMAGE=0 + option USE_FALLBACK_IMAGE=1 + option ROM_IMAGE_SIZE=0x20000 + option COREBOOT_EXTRA_VERSION=".0-fallback" + payload __PAYLOAD__ +end + +romimage "failover" + option USE_FAILOVER_IMAGE=1 + option USE_FALLBACK_IMAGE=0 + option ROM_IMAGE_SIZE=FAILOVER_SIZE + option XIP_ROM_SIZE=FAILOVER_SIZE +end + +buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" "failover" Modified: trunk/coreboot-v2/targets/gigabyte/m57sli/Config-abuild.lb =================================================================== --- trunk/coreboot-v2/targets/gigabyte/m57sli/Config-abuild.lb 2008-11-20 19:26:16 UTC (rev 3762) +++ trunk/coreboot-v2/targets/gigabyte/m57sli/Config-abuild.lb 2008-11-20 20:07:38 UTC (rev 3763) @@ -1,42 +1,35 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007 Uwe Hermann <uwe(a)hermann-uwe.de> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## +# This will make a target directory of ./VENDOR_MAINBOARD -target gigabyte_m57sli -mainboard gigabyte/m57sli +target VENDOR_MAINBOARD +mainboard VENDOR/MAINBOARD +option CC="CROSSCC" +option CROSS_COMPILE="CROSS_PREFIX" +option HOSTCC="CROSS_HOSTCC" + __COMPRESSION__ romimage "normal" + option USE_FAILOVER_IMAGE=0 option USE_FALLBACK_IMAGE=0 option ROM_IMAGE_SIZE=0x20000 - option XIP_ROM_SIZE=0x40000 - option COREBOOT_EXTRA_VERSION=".0-Normal" + option COREBOOT_EXTRA_VERSION=".0-normal" payload __PAYLOAD__ end -romimage "fallback" +romimage "fallback" + option USE_FAILOVER_IMAGE=0 option USE_FALLBACK_IMAGE=1 option ROM_IMAGE_SIZE=0x20000 - option XIP_ROM_SIZE=0x40000 - option COREBOOT_EXTRA_VERSION=".0-Fallback" + option COREBOOT_EXTRA_VERSION=".0-fallback" payload __PAYLOAD__ end -buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" +romimage "failover" + option USE_FAILOVER_IMAGE=1 + option USE_FALLBACK_IMAGE=0 + option ROM_IMAGE_SIZE=FAILOVER_SIZE + option XIP_ROM_SIZE=FAILOVER_SIZE +end + +buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" "failover" Modified: trunk/coreboot-v2/targets/iwill/dk8_htx/Config-abuild.lb =================================================================== --- trunk/coreboot-v2/targets/iwill/dk8_htx/Config-abuild.lb 2008-11-20 19:26:16 UTC (rev 3762) +++ trunk/coreboot-v2/targets/iwill/dk8_htx/Config-abuild.lb 2008-11-20 20:07:38 UTC (rev 3763) @@ -1,25 +1,35 @@ -# This will make a target directory of ./iwill_dk8_htx +# This will make a target directory of ./VENDOR_MAINBOARD -target iwill_dk8_htx -mainboard iwill/dk8_htx +target VENDOR_MAINBOARD +mainboard VENDOR/MAINBOARD -option CC="gcc -m32" -option CROSS_COMPILE="" -option HOSTCC="gcc" +option CC="CROSSCC" +option CROSS_COMPILE="CROSS_PREFIX" +option HOSTCC="CROSS_HOSTCC" -option CONFIG_COMPRESSED_PAYLOAD_LZMA=1 +__COMPRESSION__ romimage "normal" + option USE_FAILOVER_IMAGE=0 option USE_FALLBACK_IMAGE=0 - option ROM_IMAGE_SIZE=0x17000 + option ROM_IMAGE_SIZE=0x20000 option COREBOOT_EXTRA_VERSION=".0-normal" payload __PAYLOAD__ end -romimage "fallback" +romimage "fallback" + option USE_FAILOVER_IMAGE=0 option USE_FALLBACK_IMAGE=1 - option ROM_IMAGE_SIZE=0x17000 + option ROM_IMAGE_SIZE=0x20000 option COREBOOT_EXTRA_VERSION=".0-fallback" payload __PAYLOAD__ end -buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" + +romimage "failover" + option USE_FAILOVER_IMAGE=1 + option USE_FALLBACK_IMAGE=0 + option ROM_IMAGE_SIZE=FAILOVER_SIZE + option XIP_ROM_SIZE=FAILOVER_SIZE +end + +buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" "failover" Added: trunk/coreboot-v2/targets/msi/ms7135/Config-abuild.lb =================================================================== --- trunk/coreboot-v2/targets/msi/ms7135/Config-abuild.lb (rev 0) +++ trunk/coreboot-v2/targets/msi/ms7135/Config-abuild.lb 2008-11-20 20:07:38 UTC (rev 3763) @@ -0,0 +1,35 @@ +# This will make a target directory of ./VENDOR_MAINBOARD + +target VENDOR_MAINBOARD +mainboard VENDOR/MAINBOARD + +option CC="CROSSCC" +option CROSS_COMPILE="CROSS_PREFIX" +option HOSTCC="CROSS_HOSTCC" + +__COMPRESSION__ + +romimage "normal" + option USE_FAILOVER_IMAGE=0 + option USE_FALLBACK_IMAGE=0 + option ROM_IMAGE_SIZE=0x20000 + option COREBOOT_EXTRA_VERSION=".0-normal" + payload __PAYLOAD__ +end + +romimage "fallback" + option USE_FAILOVER_IMAGE=0 + option USE_FALLBACK_IMAGE=1 + option ROM_IMAGE_SIZE=0x20000 + option COREBOOT_EXTRA_VERSION=".0-fallback" + payload __PAYLOAD__ +end + +romimage "failover" + option USE_FAILOVER_IMAGE=1 + option USE_FALLBACK_IMAGE=0 + option ROM_IMAGE_SIZE=FAILOVER_SIZE + option XIP_ROM_SIZE=FAILOVER_SIZE +end + +buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" "failover" Modified: trunk/coreboot-v2/targets/nvidia/l1_2pvv/Config-abuild.lb =================================================================== --- trunk/coreboot-v2/targets/nvidia/l1_2pvv/Config-abuild.lb 2008-11-20 19:26:16 UTC (rev 3762) +++ trunk/coreboot-v2/targets/nvidia/l1_2pvv/Config-abuild.lb 2008-11-20 20:07:38 UTC (rev 3763) @@ -1,42 +1,35 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007 Uwe Hermann <uwe(a)hermann-uwe.de> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## +# This will make a target directory of ./VENDOR_MAINBOARD -target nvidia_l1_2pvv -mainboard nvidia/l1_2pvv +target VENDOR_MAINBOARD +mainboard VENDOR/MAINBOARD +option CC="CROSSCC" +option CROSS_COMPILE="CROSS_PREFIX" +option HOSTCC="CROSS_HOSTCC" + __COMPRESSION__ romimage "normal" + option USE_FAILOVER_IMAGE=0 option USE_FALLBACK_IMAGE=0 option ROM_IMAGE_SIZE=0x20000 - option XIP_ROM_SIZE=0x40000 - option COREBOOT_EXTRA_VERSION=".0-Normal" + option COREBOOT_EXTRA_VERSION=".0-normal" payload __PAYLOAD__ end -romimage "fallback" +romimage "fallback" + option USE_FAILOVER_IMAGE=0 option USE_FALLBACK_IMAGE=1 option ROM_IMAGE_SIZE=0x20000 - option XIP_ROM_SIZE=0x40000 - option COREBOOT_EXTRA_VERSION=".0-Fallback" + option COREBOOT_EXTRA_VERSION=".0-fallback" payload __PAYLOAD__ end -buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" +romimage "failover" + option USE_FAILOVER_IMAGE=1 + option USE_FALLBACK_IMAGE=0 + option ROM_IMAGE_SIZE=FAILOVER_SIZE + option XIP_ROM_SIZE=FAILOVER_SIZE +end + +buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" "failover" Added: trunk/coreboot-v2/targets/tyan/s2895/Config-abuild.lb =================================================================== --- trunk/coreboot-v2/targets/tyan/s2895/Config-abuild.lb (rev 0) +++ trunk/coreboot-v2/targets/tyan/s2895/Config-abuild.lb 2008-11-20 20:07:38 UTC (rev 3763) @@ -0,0 +1,35 @@ +# This will make a target directory of ./VENDOR_MAINBOARD + +target VENDOR_MAINBOARD +mainboard VENDOR/MAINBOARD + +option CC="CROSSCC" +option CROSS_COMPILE="CROSS_PREFIX" +option HOSTCC="CROSS_HOSTCC" + +__COMPRESSION__ + +romimage "normal" + option USE_FAILOVER_IMAGE=0 + option USE_FALLBACK_IMAGE=0 + option ROM_IMAGE_SIZE=0x20000 + option COREBOOT_EXTRA_VERSION=".0-normal" + payload __PAYLOAD__ +end + +romimage "fallback" + option USE_FAILOVER_IMAGE=0 + option USE_FALLBACK_IMAGE=1 + option ROM_IMAGE_SIZE=0x20000 + option COREBOOT_EXTRA_VERSION=".0-fallback" + payload __PAYLOAD__ +end + +romimage "failover" + option USE_FAILOVER_IMAGE=1 + option USE_FALLBACK_IMAGE=0 + option ROM_IMAGE_SIZE=FAILOVER_SIZE + option XIP_ROM_SIZE=FAILOVER_SIZE +end + +buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" "failover" Modified: trunk/coreboot-v2/targets/tyan/s2912/Config-abuild.lb =================================================================== --- trunk/coreboot-v2/targets/tyan/s2912/Config-abuild.lb 2008-11-20 19:26:16 UTC (rev 3762) +++ trunk/coreboot-v2/targets/tyan/s2912/Config-abuild.lb 2008-11-20 20:07:38 UTC (rev 3763) @@ -1,42 +1,35 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007 Uwe Hermann <uwe(a)hermann-uwe.de> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## +# This will make a target directory of ./VENDOR_MAINBOARD -target tyan_s2912 -mainboard tyan/s2912 +target VENDOR_MAINBOARD +mainboard VENDOR/MAINBOARD +option CC="CROSSCC" +option CROSS_COMPILE="CROSS_PREFIX" +option HOSTCC="CROSS_HOSTCC" + __COMPRESSION__ romimage "normal" + option USE_FAILOVER_IMAGE=0 option USE_FALLBACK_IMAGE=0 option ROM_IMAGE_SIZE=0x20000 - option XIP_ROM_SIZE=0x40000 - option COREBOOT_EXTRA_VERSION=".0-Normal" + option COREBOOT_EXTRA_VERSION=".0-normal" payload __PAYLOAD__ end -romimage "fallback" +romimage "fallback" + option USE_FAILOVER_IMAGE=0 option USE_FALLBACK_IMAGE=1 option ROM_IMAGE_SIZE=0x20000 - option XIP_ROM_SIZE=0x40000 - option COREBOOT_EXTRA_VERSION=".0-Fallback" + option COREBOOT_EXTRA_VERSION=".0-fallback" payload __PAYLOAD__ end -buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" +romimage "failover" + option USE_FAILOVER_IMAGE=1 + option USE_FALLBACK_IMAGE=0 + option ROM_IMAGE_SIZE=FAILOVER_SIZE + option XIP_ROM_SIZE=FAILOVER_SIZE +end + +buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" "failover"

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coreboot November 2008