coreboot November 2008

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msrtool: Add CS5536 probe and interrupt controller MSR definitions
by Peter Stuge 25 Nov '08

25 Nov '08

I hope we'll get more insight into the ALIX situation with these. //Peter

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r3770 build service
by coreboot information 25 Nov '08

25 Nov '08

Dear coreboot readers! This is the automated build check service of coreboot. The developer "stuge" checked in revision 3770 to the coreboot source repository and caused the following changes: Change Log: msrtool: Use libpci to let system and target probes find PCI devices. And some more notes in TODO. Signed-off-by: Peter Stuge <peter(a)stuge.se> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Build Log: Compilation of via:epia-cn has been fixed If something broke during this checkin please be a pain in stuge's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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r3770 - trunk/util/msrtool
by svn＠coreboot.org 25 Nov '08

25 Nov '08

Author: stuge Date: 2008-11-25 03:03:16 +0100 (Tue, 25 Nov 2008) New Revision: 3770 Modified: trunk/util/msrtool/TODO trunk/util/msrtool/configure trunk/util/msrtool/msrtool.c trunk/util/msrtool/msrtool.h trunk/util/msrtool/sys.c Log: msrtool: Use libpci to let system and target probes find PCI devices. And some more notes in TODO. Signed-off-by: Peter Stuge <peter(a)stuge.se> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/util/msrtool/TODO =================================================================== --- trunk/util/msrtool/TODO 2008-11-24 20:23:23 UTC (rev 3769) +++ trunk/util/msrtool/TODO 2008-11-25 02:03:16 UTC (rev 3770) @@ -1,8 +1,9 @@ Systems ------- FreeBSD #defines: see svn diff -r 3697:3698 util/ +i586: assembly instruction system driver, may have to ignore -c CPU # option Other ideas ----------- Move MSR definitions and probe instructions into an external text file? -Handle PCI registers as well? +Handle PCI and port IO registers as well? Modified: trunk/util/msrtool/configure =================================================================== --- trunk/util/msrtool/configure 2008-11-24 20:23:23 UTC (rev 3769) +++ trunk/util/msrtool/configure 2008-11-25 02:03:16 UTC (rev 3770) @@ -135,6 +135,25 @@ test -n "$DEBUG" && myCFLAGS="-O2 -g" || myCFLAGS="-Os" CFLAGS="${CFLAGS} ${myCFLAGS} -Wall -Werror" +cat > .config.c << EOF +#include <pci/pci.h> +struct pci_access *pacc; +int main(int argc, char *argv[]) +{ pacc = pci_alloc(); return 0; } +EOF + +pc_CFLAGS="$(pkg-config libpci --cflags 2>/dev/null)" +pc_LDFLAGS="$(pkg-config libpci --libs 2>/dev/null)" +CFLAGS=$(trycompile "libpci (from pciutils)" "${pc_CFLAGS}" "-I/usr/local/include") || { + rm -f .config.c + exit 1 +} +LDFLAGS=$(trylink "libpci (from pciutils)" "${pc_LDFLAGS}" "-lpci -lz" "-L/usr/local/lib -lpci -lz") || { + rm -f .config.c .config.o + exit 1 +} +rm -f .config.c .config.o .config + PREFIX="${PREFIX:-/usr/local}" OS_ARCH=$(uname) Modified: trunk/util/msrtool/msrtool.c =================================================================== --- trunk/util/msrtool/msrtool.c 2008-11-24 20:23:23 UTC (rev 3769) +++ trunk/util/msrtool/msrtool.c 2008-11-25 02:03:16 UTC (rev 3770) @@ -25,6 +25,7 @@ #include <sys/stat.h> #include <fcntl.h> #include <errno.h> +#include <pci/pci.h> #include "msrtool.h" @@ -36,6 +37,8 @@ const struct sysdef *sys = NULL; uint8_t reserved = 0, verbose = 0, quiet = 0; +struct pci_access *pacc = NULL; + static struct targetdef alltargets[] = { { "geodelx", "AMD Geode(tm) LX", geodelx_probe, geodelx_msrs }, { "cs5536", "AMD Geode(tm) CS5536", cs5536_probe, cs5536_msrs }, @@ -296,6 +299,14 @@ printf_quiet("msrtool %s\n", VERSION); + pacc = pci_alloc(); + if (NULL == pacc) { + fprintf(stderr, "Could not initialize PCI library! pci_alloc() failed.\n"); + return 1; + } + pci_init(pacc); + pci_scan_bus(pacc); + if (!sys && !input && !listknown) for (sys = allsystems; !SYSTEM_ISEOT(*sys); sys++) { printf_verbose("Probing for system %s: %s\n", sys->name, sys->prettyname); Modified: trunk/util/msrtool/msrtool.h =================================================================== --- trunk/util/msrtool/msrtool.h 2008-11-24 20:23:23 UTC (rev 3769) +++ trunk/util/msrtool/msrtool.h 2008-11-25 02:03:16 UTC (rev 3770) @@ -22,6 +22,7 @@ #include <stdio.h> #include <stdint.h> +#include <pci/pci.h> #define HEXCHARS "0123456789abcdefABCDEF" @@ -132,6 +133,8 @@ extern uint8_t reserved, verbose, quiet; +extern struct pci_access *pacc; + #define printf_quiet(x...) do { if (!quiet) fprintf(stderr,x); } while(0) #define printf_verbose(x...) do { if (verbose && !quiet) fprintf(stderr,x); } while(0) @@ -145,6 +148,7 @@ /* sys.c */ struct cpuid_t *cpuid(void); +struct pci_dev *pci_dev_find(uint16_t vendor, uint16_t device); /* msrutils.c */ void hexprint(FILE *f, const struct msr val, const uint8_t bits); Modified: trunk/util/msrtool/sys.c =================================================================== --- trunk/util/msrtool/sys.c 2008-11-24 20:23:23 UTC (rev 3769) +++ trunk/util/msrtool/sys.c 2008-11-25 02:03:16 UTC (rev 3770) @@ -17,6 +17,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <pci/pci.h> + #include "msrtool.h" static struct cpuid_t id; @@ -40,3 +42,18 @@ } return &id; } + +struct pci_dev *pci_dev_find(uint16_t vendor, uint16_t device) { + struct pci_dev *temp; + struct pci_filter filter; + + pci_filter_init(NULL, &filter); + filter.vendor = vendor; + filter.device = device; + + for (temp = pacc->devices; temp; temp = temp->next) + if (pci_filter_match(&filter, temp)) + return temp; + + return NULL; +}

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TCPA support
by Thomas Jourdan 24 Nov '08

24 Nov '08

Hi all I'm working on porting Coreboot v2 to the MSC-CXB-CD945 com express card (http://www.msc-ge.com/frame/en/produkte/com/com_express/cxb_cd945.html). The design is close to the Kontron 986LCD-M, so it won't be too hard. This board has an Infineon SLB 9635 TPM 1.2 chip, on the LPC bridge, for all the TCPA stuffs. I'd like to support this chip (I need it for applicaitons we developped on the board), and in a general way, try to add TCPA support in coreboot. The TCG ACPI Specification tells us : "A TCG platform MAY provide an ACPI device object representing the TPM in the ACPI namespace, if the bus where the TPM is located is not PNP capable or the bus is not exposed to the OS for PNP operations." I will not focus too much on the ACPI table at first but I'd like to add the device in the Config.lb. I'd like to have confirmation on the syntax I'll have to use in the Config.lb file. Here is the result of lspnp : 00:08 IFX0102 Infineon Trusted Platform Module state = active io 0x4e-0x4f io 0x1670-0x167f mem 0xfed40000-0xfed44fff irq 11 The device is a PNP device : if I don't add an entry for this device in the Config.lb file, will coreboot be able to read and allocate himself the resources ? If I add an entry, I was thinking about this : device pci 1f.0 on # LPC bridge chip drivers/tpm/slb9635 end end Then I define resources functions in my driver. Do I need to add an entry like this "device pnp ... on end" ? I don't really understand how this works. It only seems suitable for super i/o logical functions. By the way I (of course) don't have the datasheet of the component, just the TPM linux driver source code from trust.rub.de, and traces from acpidump, lspnp... Last question : when the board will be supported, I'll send patches to the mailing list. The original bios was developped by phoenix. For my personnal usage, I may re-use ACPI and SMBIOS tables extracted from this bios. But, for the patches I'll send, am I allowed to use them ? Regards, Thomas PS : this thread is not meant to become a fight between DRM / free software. I don't like DRM and stuffs like this but I must admit that the TPM chip is usefull for some kind of applications.

5 6

r1051 - in coreboot-v3: mainboard/kontron/986lcd-m northbridge/intel/i945 southbridge/intel/i82801gx
by svn＠coreboot.org 24 Nov '08

24 Nov '08

Author: rminnich Date: 2008-11-24 23:20:48 +0100 (Mon, 24 Nov 2008) New Revision: 1051 Modified: coreboot-v3/mainboard/kontron/986lcd-m/dts coreboot-v3/northbridge/intel/i945/bus.dts coreboot-v3/northbridge/intel/i945/northbridge.c coreboot-v3/southbridge/intel/i82801gx/smi.c Log: This board now builds. Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Modified: coreboot-v3/mainboard/kontron/986lcd-m/dts =================================================================== --- coreboot-v3/mainboard/kontron/986lcd-m/dts 2008-11-24 21:15:19 UTC (rev 1050) +++ coreboot-v3/mainboard/kontron/986lcd-m/dts 2008-11-24 22:20:48 UTC (rev 1051) @@ -147,7 +147,6 @@ /config/("northbridge/intel/i945/northbridge.dts"); /* guesses; we need a real lspci */ pci@0,0 { - /config/("northbridge/intel/i945/bus.dts"); pci@1b,0 { /config/("southbridge/intel/i82801gx/ac97audio.dts"); }; Modified: coreboot-v3/northbridge/intel/i945/bus.dts =================================================================== --- coreboot-v3/northbridge/intel/i945/bus.dts 2008-11-24 21:15:19 UTC (rev 1050) +++ coreboot-v3/northbridge/intel/i945/bus.dts 2008-11-24 22:20:48 UTC (rev 1051) @@ -18,5 +18,5 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ { - device_operations = "i945_bus_ops"; + device_operations = "i945_cpu_bus_ops"; }; Modified: coreboot-v3/northbridge/intel/i945/northbridge.c =================================================================== --- coreboot-v3/northbridge/intel/i945/northbridge.c 2008-11-24 21:15:19 UTC (rev 1050) +++ coreboot-v3/northbridge/intel/i945/northbridge.c 2008-11-24 22:20:48 UTC (rev 1051) @@ -164,7 +164,7 @@ i945_ram_resource(dev, 5, 4096 * 1024, tomk - 4 * 1024 * 1024); } - assign_resources(&dev->link[0]); + phase4_assign_resources(&dev->link[0]); } static unsigned int i945_pci_domain_scan_bus(struct device * dev, unsigned int max) @@ -189,6 +189,7 @@ .phase5_enable_resources = enable_childrens_resources, .phase6_init = NULL, .ops_pci = &pci_dev_ops_pci, + .ops_pci_bus = &pci_cf8_conf1, /* Do we want to use the memory mapped space here? */ }; static void mc_read_resources(struct device * dev) @@ -230,14 +231,14 @@ pci_set_resources(dev); } -static void intel_set_subsystem(struct device * dev, unsigned vendor, unsigned device) +static void i945_set_subsystem(struct device * dev, unsigned vendor, unsigned device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, ((device & 0xffff) << 16) | (vendor & 0xffff)); } static struct pci_operations intel_pci_ops = { - .set_subsystem = intel_set_subsystem, + .set_subsystem = i945_set_subsystem, }; struct device_operations i945_mc_ops = { @@ -265,7 +266,7 @@ } #warning get a number of the 945 mc -struct device_operations i945_cpu_ops = { +struct device_operations i945_cpu_bus_ops = { .id = {.type = DEVICE_ID_PCI, {.pci = {.vendor = PCI_VENDOR_ID_INTEL, .device = 0x1233}}}, Modified: coreboot-v3/southbridge/intel/i82801gx/smi.c =================================================================== --- coreboot-v3/southbridge/intel/i82801gx/smi.c 2008-11-24 21:15:19 UTC (rev 1050) +++ coreboot-v3/southbridge/intel/i82801gx/smi.c 2008-11-24 22:20:48 UTC (rev 1051) @@ -306,7 +306,7 @@ outb(0x00, 0xb2); } -void smm_install(void) +void smm_install(void *smm, unsigned int smm_len) { /* enable the SMM memory window */ pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), SMRAM, @@ -321,10 +321,10 @@ G_SMRAME | C_BASE_SEG); } -void smm_init(void) +void smm_init(void *smm, unsigned int smm_len) { smm_relocate(); - smm_install(); + smm_install(smm, smm_len); } void smm_lock(void)

1 0

r1050 - in coreboot-v3: mainboard/kontron/986lcd-m northbridge/intel/i945 southbridge/intel/i82801gx
by svn＠coreboot.org 24 Nov '08

24 Nov '08

Author: rminnich Date: 2008-11-24 22:15:19 +0100 (Mon, 24 Nov 2008) New Revision: 1050 Modified: coreboot-v3/mainboard/kontron/986lcd-m/irq_tables.h coreboot-v3/northbridge/intel/i945/raminit.c coreboot-v3/southbridge/intel/i82801gx/Makefile coreboot-v3/southbridge/intel/i82801gx/smmrelocate.S Log: Simple typos and fixups. This is almost building. Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Modified: coreboot-v3/mainboard/kontron/986lcd-m/irq_tables.h =================================================================== --- coreboot-v3/mainboard/kontron/986lcd-m/irq_tables.h 2008-11-24 17:28:26 UTC (rev 1049) +++ coreboot-v3/mainboard/kontron/986lcd-m/irq_tables.h 2008-11-24 21:15:19 UTC (rev 1050) @@ -19,8 +19,6 @@ * MA 02110-1301 USA */ -#include <arch/pirq_routing.h> - const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, /* u32 signature */ PIRQ_VERSION, /* u16 version */ Modified: coreboot-v3/northbridge/intel/i945/raminit.c =================================================================== --- coreboot-v3/northbridge/intel/i945/raminit.c 2008-11-24 17:28:26 UTC (rev 1049) +++ coreboot-v3/northbridge/intel/i945/raminit.c 2008-11-24 21:15:19 UTC (rev 1050) @@ -930,7 +930,7 @@ DQ2330, NC, CTL3215, NC, CLK2030, CLK2030, DQ2030, CMD3210 }; -static const u32 * map(u32 *table, unsigned int i){ +static const u32 * map(const u8 *table, unsigned int i){ const u32 *p = NULL; switch(table[i]) { case NC: p = nc; break; @@ -949,8 +949,6 @@ static void sdram_rcomp_buffer_strength_and_slew(struct sys_info *sysinfo) { - u32 *table; - #if 0 static const u32 const * const dual_channel_slew_group_lookup[] = { dq2030, cmd3210, ctl3215, ctl3215, clk2030, clk2030, dq2030, cmd3210, @@ -1072,7 +1070,7 @@ }; const u8 * strength_multiplier; - const u32* const * slew_group_lookup; + const u8* const * slew_group_lookup; int idx; /* Set Strength Multipliers */ @@ -1081,12 +1079,12 @@ if (sdram_capabilities_dual_channel()) { printk(BIOS_DEBUG, "Programming Dual Channel RCOMP\n"); strength_multiplier = dual_channel_strength_multiplier; - slew_group_lookup = dual_channel_slew_group_lookup; + slew_group_lookup = dual_channel_slew_group_lookup; idx = 5 * sysinfo->dimm[0] + sysinfo->dimm[2]; } else { printk(BIOS_DEBUG, "Programming Single Channel RCOMP\n"); strength_multiplier = single_channel_strength_multiplier; - slew_group_lookup = single_channel_slew_group_lookup; + slew_group_lookup = single_channel_slew_group_lookup; idx = 5 * sysinfo->dimm[0] + sysinfo->dimm[1]; } @@ -1105,8 +1103,6 @@ sdram_write_slew_rates(G1SRPUT, map(slew_group_lookup, idx * 8 + 0)); sdram_write_slew_rates(G2SRPUT, map(slew_group_lookup, idx * 8 + 1)); if ((map(slew_group_lookup, idx * 8 + 2) != nc) && (sysinfo->package == SYSINFO_PACKAGE_STACKED)) { - - sdram_write_slew_rates(G3SRPUT, ctl3220); } else { sdram_write_slew_rates(G3SRPUT, map(slew_group_lookup, idx * 8 + 2)); Modified: coreboot-v3/southbridge/intel/i82801gx/Makefile =================================================================== --- coreboot-v3/southbridge/intel/i82801gx/Makefile 2008-11-24 17:28:26 UTC (rev 1049) +++ coreboot-v3/southbridge/intel/i82801gx/Makefile 2008-11-24 21:15:19 UTC (rev 1050) @@ -39,8 +39,17 @@ $(src)/southbridge/intel/i82801gx/libsmbus.c \ $(obj)/southbridge/intel/i82801gx/smmrelocate.o \ +ifeq ($(CONFIG_PIRQ_TABLE),y) +STAGE2_CHIPSET_SRC += $(src)/southbridge/intel/i82801gx/irq_tables.c +endif + $(obj)/southbridge/intel/i82801gx/smmrelocate.o: $(src)/southbridge/intel/i82801gx/smmrelocate.S - as -o $@ $< + $(Q)mkdir -p $(dir $@) + $(Q)printf " CC $(subst $(shell pwd)/,,$(@))\n" + $(Q)$(CC) -E $(COREBOOTINCLUDE) -I$(src)/northbridge/intel/i945 $< \ + -o $(obj)/southbridge/intel/i82801gx/smmrelocate.s + $(Q)printf " AS $(subst $(shell pwd)/,,$(@))\n" + $(Q)$(AS) $(obj)/southbridge/intel/i82801gx/smmrelocate.s -o $@ STAGE0_CHIPSET_SRC += \ $(src)/southbridge/intel/i82801gx/stage1_smbus.c \ Modified: coreboot-v3/southbridge/intel/i82801gx/smmrelocate.S =================================================================== --- coreboot-v3/southbridge/intel/i82801gx/smmrelocate.S 2008-11-24 17:28:26 UTC (rev 1049) +++ coreboot-v3/southbridge/intel/i82801gx/smmrelocate.S 2008-11-24 21:15:19 UTC (rev 1050) @@ -19,8 +19,8 @@ * MA 02110-1301 USA */ -#include <arch/asm.h> -#include "../../../../src/northbridge/intel/i945/ich7.h" +#define ASSEMBLY +#include <ich7.h> #undef DEBUG_SMM_RELOCATION //#define DEBUG_SMM_RELOCATION

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r3769 build service
by coreboot information 24 Nov '08

24 Nov '08

Dear coreboot readers! This is the automated build check service of coreboot. The developer "stuge" checked in revision 3769 to the coreboot source repository and caused the following changes: Change Log: Add support for 32Mbit SPI flash SST25VF032B. Tested on gigabyte m57sli. File util/flashrom/flash.h already had correct ID for that part. Signed-off-by: Tero O Peippola <xeropp(a)gmail.com> Acked-by: Peter Stuge <peter(a)stuge.se> Build Log: Compilation of ibm:e326 has been fixed Compilation of via:epia-cn has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3769&device=epia-cn&vendor… If something broke during this checkin please be a pain in stuge's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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flashrom: add support for SST25VF032B
by Tero Peippola 24 Nov '08

24 Nov '08

Add support for 32Mbit SPI flash SST25VF032B. Tested on gigabyte m57sli. File util/flashrom/flash.h already had correct ID for that part. Signed-off-by: Tero O Peippola <xeropp(a)gmail.com> Index: util/flashrom/flashchips.c =================================================================== --- util/flashrom/flashchips.c (revision 3767) +++ util/flashrom/flashchips.c (working copy) @@ -108,6 +108,7 @@ {"Sharp", "LHF00L04", SHARP_ID, SHARP_LHF00L04, 1024, 64 * 1024, TEST_UNTESTED, probe_lhf00l04, erase_lhf00l04, write_lhf00l04}, {"Spansion", "S25FL016A", SPANSION_ID, SPANSION_S25FL016A, 2048, 256, TEST_OK_PREW, probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, {"SST", "SST25VF016B", SST_ID, SST_25VF016B, 2048, 256, TEST_OK_PREW, probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, + {"SST", "SST25VF032B", SST_ID, SST_25VF032B, 4096, 256, TEST_OK_PREW, probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, {"SST", "SST25VF040B", SST_ID, SST_25VF040B, 512, 256, TEST_UNTESTED, probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, {"SST", "SST28SF040A", SST_ID, SST_28SF040, 512, 256, TEST_UNTESTED, probe_28sf040, erase_28sf040, write_28sf040}, {"SST", "SST29EE010", SST_ID, SST_29EE010, 128, 128, TEST_OK_PREW, probe_jedec, erase_chip_jedec, write_jedec},

2 2

r3769 - trunk/util/flashrom
by svn＠coreboot.org 24 Nov '08

24 Nov '08

Author: stuge Date: 2008-11-24 21:23:23 +0100 (Mon, 24 Nov 2008) New Revision: 3769 Modified: trunk/util/flashrom/flashchips.c Log: Add support for 32Mbit SPI flash SST25VF032B. Tested on gigabyte m57sli. File util/flashrom/flash.h already had correct ID for that part. Signed-off-by: Tero O Peippola <xeropp(a)gmail.com> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/util/flashrom/flashchips.c =================================================================== --- trunk/util/flashrom/flashchips.c 2008-11-24 17:54:46 UTC (rev 3768) +++ trunk/util/flashrom/flashchips.c 2008-11-24 20:23:23 UTC (rev 3769) @@ -108,6 +108,7 @@ {"Sharp", "LHF00L04", SHARP_ID, SHARP_LHF00L04, 1024, 64 * 1024, TEST_UNTESTED, probe_lhf00l04, erase_lhf00l04, write_lhf00l04}, {"Spansion", "S25FL016A", SPANSION_ID, SPANSION_S25FL016A, 2048, 256, TEST_OK_PREW, probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, {"SST", "SST25VF016B", SST_ID, SST_25VF016B, 2048, 256, TEST_OK_PREW, probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, + {"SST", "SST25VF032B", SST_ID, SST_25VF032B, 4096, 256, TEST_OK_PREW, probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, {"SST", "SST25VF040B", SST_ID, SST_25VF040B, 512, 256, TEST_UNTESTED, probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, {"SST", "SST28SF040A", SST_ID, SST_28SF040, 512, 256, TEST_UNTESTED, probe_28sf040, erase_28sf040, write_28sf040}, {"SST", "SST29EE010", SST_ID, SST_29EE010, 128, 128, TEST_OK_PREW, probe_jedec, erase_chip_jedec, write_jedec},

1 0

r3768 build service
by coreboot information 24 Nov '08

24 Nov '08

Dear coreboot readers! This is the automated build check service of coreboot. The developer "jcrouse" checked in revision 3768 to the coreboot source repository and caused the following changes: Change Log: [PATCH] libpayload: rename config.h to libpayload-config.h Rename the generated config file to libpayload-config.h to differenciate it from other config.h files. Move the default location of the file to $(src)/include so that LIBPAYLOAD_PREFIX= users can access the file without staging it. Signed-off-by: Jordan Crouse <jordan(a)cosmicpenguin.net> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Build Log: Compilation of ibm:e326 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3768&device=e326&vendor=ibm If something broke during this checkin please be a pain in jcrouse's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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coreboot November 2008