coreboot November 2008

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r1057 - in coreboot-v3/arch/x86: . intel/core2
by svn＠coreboot.org 25 Nov '08

25 Nov '08

Author: hailfinger Date: 2008-11-26 00:39:31 +0100 (Wed, 26 Nov 2008) New Revision: 1057 Modified: coreboot-v3/arch/x86/intel/core2/stage0.S coreboot-v3/arch/x86/stage1.c Log: The Core2Duo CAR code did set up the stack incorrectly. In combination with a wrong calling convention of stage1_phase1() this caused stage1 to assume BIST had failed. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Modified: coreboot-v3/arch/x86/intel/core2/stage0.S =================================================================== --- coreboot-v3/arch/x86/intel/core2/stage0.S 2008-11-25 23:10:24 UTC (rev 1056) +++ coreboot-v3/arch/x86/intel/core2/stage0.S 2008-11-25 23:39:31 UTC (rev 1057) @@ -3,6 +3,7 @@ * * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich(a)gmail.com> * Copyright (C) 2007-2008 coresystems GmbH + * Copyright (C) 2008 Carl-Daniel Hailfinger * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -159,17 +160,26 @@ movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4), %eax movl %eax, %esp - /* Restore the BIST result */ + /* Store zero for the pointer to the global variables. */ + pushl $0 + + /* Restore the BIST result. */ movl %ebp, %eax + + /* We need to set ebp? No need. */ movl %esp, %ebp + + /* Second parameter: init_detected */ + /* Store zero for the unused init_detected parameter. */ + pushl $0 + + /* First parameter: bist */ pushl %eax -#if 0 - /* this will be interpreted as failed bist */ port80_post(0x23) -#endif call stage1_phase1 + /* We will not go back. */ port80_post(0x2f) error: Modified: coreboot-v3/arch/x86/stage1.c =================================================================== --- coreboot-v3/arch/x86/stage1.c 2008-11-25 23:10:24 UTC (rev 1056) +++ coreboot-v3/arch/x86/stage1.c 2008-11-25 23:39:31 UTC (rev 1057) @@ -187,7 +187,7 @@ * that we are restarting after some sort of reconfiguration. Note that we could use it on geode but * do not at present. */ -void __attribute__((stdcall)) stage1_phase1(u32 bist, u32 init_detected) +void __attribute__((stdcall,regparm(0))) stage1_phase1(u32 bist, u32 init_detected) { struct global_vars globvars; int ret;

1 0

r1056 - in coreboot-v3/arch/x86: . intel/core2
by svn＠coreboot.org 25 Nov '08

25 Nov '08

Author: stepan Date: 2008-11-26 00:10:24 +0100 (Wed, 26 Nov 2008) New Revision: 1056 Modified: coreboot-v3/arch/x86/Kconfig coreboot-v3/arch/x86/intel/core2/stage0.S Log: hack to make v3 rom access a lot faster. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: coreboot-v3/arch/x86/Kconfig =================================================================== --- coreboot-v3/arch/x86/Kconfig 2008-11-25 22:51:15 UTC (rev 1055) +++ coreboot-v3/arch/x86/Kconfig 2008-11-25 23:10:24 UTC (rev 1056) @@ -176,7 +176,7 @@ default 0x80000 if CPU_AMD_GEODELX default 0xc8000 if CPU_AMD_K8 default 0xffef0000 if CPU_VIA_C7 - default 0xffef0000 if CPU_INTEL_CORE2 + default 0xffdf8000 if CPU_INTEL_CORE2 help This option sets the base address of the area used for CAR. Modified: coreboot-v3/arch/x86/intel/core2/stage0.S =================================================================== --- coreboot-v3/arch/x86/intel/core2/stage0.S 2008-11-25 22:51:15 UTC (rev 1055) +++ coreboot-v3/arch/x86/intel/core2/stage0.S 2008-11-25 23:10:24 UTC (rev 1056) @@ -22,6 +22,9 @@ #define CACHE_AS_RAM_SIZE CONFIG_CARSIZE #define CACHE_AS_RAM_BASE CONFIG_CARBASE +#define XIP_ROM_BASE 0xfff00000 +#define XIP_ROM_SIZE 0x00100000 + #include <mtrr.h> #include <macros.h>

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r1055 - coreboot-v3/arch/x86/intel/core2
by svn＠coreboot.org 25 Nov '08

25 Nov '08

Author: stepan Date: 2008-11-25 23:51:15 +0100 (Tue, 25 Nov 2008) New Revision: 1055 Modified: coreboot-v3/arch/x86/intel/core2/stage0.S Log: get into ram init on kontron board. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: coreboot-v3/arch/x86/intel/core2/stage0.S =================================================================== --- coreboot-v3/arch/x86/intel/core2/stage0.S 2008-11-25 22:39:00 UTC (rev 1054) +++ coreboot-v3/arch/x86/intel/core2/stage0.S 2008-11-25 22:51:15 UTC (rev 1055) @@ -161,7 +161,10 @@ movl %esp, %ebp pushl %eax +#if 0 + /* this will be interpreted as failed bist */ port80_post(0x23) +#endif call stage1_phase1

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r1054 - coreboot-v3/mainboard/kontron/986lcd-m
by svn＠coreboot.org 25 Nov '08

25 Nov '08

Author: stepan Date: 2008-11-25 23:39:00 +0100 (Tue, 25 Nov 2008) New Revision: 1054 Modified: coreboot-v3/mainboard/kontron/986lcd-m/acpi_tables.c coreboot-v3/mainboard/kontron/986lcd-m/fadt.c coreboot-v3/mainboard/kontron/986lcd-m/mptable.c coreboot-v3/mainboard/kontron/986lcd-m/power_reset_check.c coreboot-v3/mainboard/kontron/986lcd-m/reset.c coreboot-v3/mainboard/kontron/986lcd-m/rtl8168.c coreboot-v3/mainboard/kontron/986lcd-m/stage1.c Log: get some serial output and post codes from the dongle (trivial changes) Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: coreboot-v3/mainboard/kontron/986lcd-m/acpi_tables.c =================================================================== --- coreboot-v3/mainboard/kontron/986lcd-m/acpi_tables.c 2008-11-25 20:45:32 UTC (rev 1053) +++ coreboot-v3/mainboard/kontron/986lcd-m/acpi_tables.c 2008-11-25 22:39:00 UTC (rev 1054) @@ -26,7 +26,6 @@ #include <msr.h> #include <legacy.h> #include <device/pci_ids.h> -#include <statictree.h> #include <config.h> #include "dmi.h" Modified: coreboot-v3/mainboard/kontron/986lcd-m/fadt.c =================================================================== --- coreboot-v3/mainboard/kontron/986lcd-m/fadt.c 2008-11-25 20:45:32 UTC (rev 1053) +++ coreboot-v3/mainboard/kontron/986lcd-m/fadt.c 2008-11-25 22:39:00 UTC (rev 1054) @@ -26,7 +26,6 @@ #include <msr.h> #include <legacy.h> #include <device/pci_ids.h> -#include <statictree.h> #include <config.h> #include <arch/acpi.h> Modified: coreboot-v3/mainboard/kontron/986lcd-m/mptable.c =================================================================== --- coreboot-v3/mainboard/kontron/986lcd-m/mptable.c 2008-11-25 20:45:32 UTC (rev 1053) +++ coreboot-v3/mainboard/kontron/986lcd-m/mptable.c 2008-11-25 22:39:00 UTC (rev 1054) @@ -27,7 +27,6 @@ #include <msr.h> #include <legacy.h> #include <device/pci_ids.h> -#include <statictree.h> #include <config.h> Modified: coreboot-v3/mainboard/kontron/986lcd-m/power_reset_check.c =================================================================== --- coreboot-v3/mainboard/kontron/986lcd-m/power_reset_check.c 2008-11-25 20:45:32 UTC (rev 1053) +++ coreboot-v3/mainboard/kontron/986lcd-m/power_reset_check.c 2008-11-25 22:39:00 UTC (rev 1054) @@ -25,7 +25,6 @@ #include <msr.h> #include <legacy.h> #include <device/pci_ids.h> -#include <statictree.h> #include <config.h> Modified: coreboot-v3/mainboard/kontron/986lcd-m/reset.c =================================================================== --- coreboot-v3/mainboard/kontron/986lcd-m/reset.c 2008-11-25 20:45:32 UTC (rev 1053) +++ coreboot-v3/mainboard/kontron/986lcd-m/reset.c 2008-11-25 22:39:00 UTC (rev 1054) @@ -26,7 +26,6 @@ #include <msr.h> #include <legacy.h> #include <device/pci_ids.h> -#include <statictree.h> #include <config.h> void soft_reset(void) Modified: coreboot-v3/mainboard/kontron/986lcd-m/rtl8168.c =================================================================== --- coreboot-v3/mainboard/kontron/986lcd-m/rtl8168.c 2008-11-25 20:45:32 UTC (rev 1053) +++ coreboot-v3/mainboard/kontron/986lcd-m/rtl8168.c 2008-11-25 22:39:00 UTC (rev 1054) @@ -27,7 +27,6 @@ #include <msr.h> #include <legacy.h> #include <device/pci_ids.h> -#include <statictree.h> #include <config.h> static void nic_init(struct device *dev) Modified: coreboot-v3/mainboard/kontron/986lcd-m/stage1.c =================================================================== --- coreboot-v3/mainboard/kontron/986lcd-m/stage1.c 2008-11-25 20:45:32 UTC (rev 1053) +++ coreboot-v3/mainboard/kontron/986lcd-m/stage1.c 2008-11-25 22:39:00 UTC (rev 1054) @@ -169,7 +169,7 @@ rawpnp_exit_ext_func_mode(port); - port = 0x2e; + port = 0x4e; ldn = W83627THG_SP1; rawpnp_enter_ext_func_mode(port); @@ -208,7 +208,7 @@ void early_superio_config_w83627thg(void); void ich7_enable_lpc(void); int boot_mode = 0; -#if 0 +#if 1 /* hack */ pci_conf1_write_config32(PCI_BDF(0, 0x1f, 0), RCBA, DEFAULT_RCBA | 1); /* Change port80 to LPC */ @@ -219,13 +219,10 @@ enable_lapic(); ich7_enable_lpc(); + early_superio_config_w83627thg(); - /* Set up the console */ -#warning need to know how to call uart8250_init -// uart8250_init(); - console_init(); - + post_code(0xcf); } void mainboard_pre_payload(void)

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r1053 - coreboot-v3/mainboard/kontron/986lcd-m
by svn＠coreboot.org 25 Nov '08

25 Nov '08

Author: rminnich Date: 2008-11-25 21:45:32 +0100 (Tue, 25 Nov 2008) New Revision: 1053 Modified: coreboot-v3/mainboard/kontron/986lcd-m/stage1.c Log: testing Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Modified: coreboot-v3/mainboard/kontron/986lcd-m/stage1.c =================================================================== --- coreboot-v3/mainboard/kontron/986lcd-m/stage1.c 2008-11-25 20:18:27 UTC (rev 1052) +++ coreboot-v3/mainboard/kontron/986lcd-m/stage1.c 2008-11-25 20:45:32 UTC (rev 1053) @@ -208,12 +208,14 @@ void early_superio_config_w83627thg(void); void ich7_enable_lpc(void); int boot_mode = 0; +#if 0 /* hack */ pci_conf1_write_config32(PCI_BDF(0, 0x1f, 0), RCBA, DEFAULT_RCBA | 1); /* Change port80 to LPC */ RCBA32(GCS) &= (~0x04); /* end hack */ - +#endif + post_code(0xcc); enable_lapic(); ich7_enable_lpc();

1 0

r1052 - in coreboot-v3: mainboard/kontron/986lcd-m southbridge/intel/i82801gx
by svn＠coreboot.org 25 Nov '08

25 Nov '08

Author: rminnich Date: 2008-11-25 21:18:27 +0100 (Tue, 25 Nov 2008) New Revision: 1052 Added: coreboot-v3/southbridge/intel/i82801gx/irq_tables.c Modified: coreboot-v3/mainboard/kontron/986lcd-m/stage1.c Log: For stefan Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Modified: coreboot-v3/mainboard/kontron/986lcd-m/stage1.c =================================================================== --- coreboot-v3/mainboard/kontron/986lcd-m/stage1.c 2008-11-24 22:20:48 UTC (rev 1051) +++ coreboot-v3/mainboard/kontron/986lcd-m/stage1.c 2008-11-25 20:18:27 UTC (rev 1052) @@ -208,6 +208,11 @@ void early_superio_config_w83627thg(void); void ich7_enable_lpc(void); int boot_mode = 0; + /* hack */ + pci_conf1_write_config32(PCI_BDF(0, 0x1f, 0), RCBA, DEFAULT_RCBA | 1); + /* Change port80 to LPC */ + RCBA32(GCS) &= (~0x04); + /* end hack */ enable_lapic(); Added: coreboot-v3/southbridge/intel/i82801gx/irq_tables.c =================================================================== --- coreboot-v3/southbridge/intel/i82801gx/irq_tables.c (rev 0) +++ coreboot-v3/southbridge/intel/i82801gx/irq_tables.c 2008-11-25 20:18:27 UTC (rev 1052) @@ -0,0 +1,42 @@ +/* +* This file is part of the coreboot project. +* +* Copyright (C) 2007 Advanced Micro Devices, Inc. +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +#include <types.h> +#include <lib.h> +#include <console.h> +#include <device/device.h> +#include <device/pci.h> +#include <string.h> +#include <msr.h> +#include <io.h> +#include <pirq_routing.h> +#include <irq_tables.h> +#include "i82801gx.h" + +/** + * Write_pirq_routing_table + * This is just a pass through for now, but it might have to change. + * All hooks for southbridge irq setup go here. + * See cs5536 for an example of how hooks can be put in. + */ +unsigned long write_pirq_routing_table(unsigned long addr) +{ + return copy_pirq_routing_table(addr); + +}

1 0

detecting errors from libpci
by Shadravan Fontanov 25 Nov '08

25 Nov '08

Hello, please, consider following code, reading the value in pci configuration register and using the libpci library: <start code> pacc = pci_alloc(); pci_init(pacc); pci_dev = pci_get_dev(pacc, PCI_DOMAIN, PCI_BUS, PCI_DEV, PCI_FUNC); current_value = pci_read_byte(pci_dev, PCI_OFFSET); pci_cleanup(pacc); if(current_value == 0xff) { printf(Error\n"); return -1; } <end code> It is impossible that the value in the register is 0xff. This is how I detect an error(for example: not sufficient read/write permissions). Question: is there another possibility to detect errors from reading/writing to pci registers(well, writing is not the problem, but reading...)? Regards Shadravan

1 0

dt compiler patch
by ron minnich 25 Nov '08

25 Nov '08

This has been tested and builds a working boot-to-linux coreboot on the dbe62 (old style dts) and builds a serengeti target (new dts, but that new dts not submitted yet). ron

2 12

[PATCH] libpayload: Fix immediate rebuild after a clean
by Mart Raudsepp 25 Nov '08

25 Nov '08

libpayload: Fix immediate rebuild after a clean After running make clean, most of build/ directory gets deleted. It is (re)created in the "prepare" make target, but that was libpayload.a dependency after the $OBJS, while OBJS building already needs to dump its created object files there. Simply rearrange the make target dependencies to get at least "make clean;make" working. Signed-off-by: Mart Raudsepp <mart.raudsepp(a)artecdesign.ee> --- libpayload/Makefile | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/libpayload/Makefile b/libpayload/Makefile index f2536e9..32c3957 100644 --- a/libpayload/Makefile +++ b/libpayload/Makefile @@ -111,7 +111,7 @@ copystuff: $(obj)/$(ARCHDIR-y)/head.S.o $(obj)/lib/libpayload.a $(Q)cp $(obj)/$(ARCHDIR-y)/head.S.o $(src)/lib/$(ARCHDIR-y)/head.o $(Q)cp $(obj)/lib/libpayload.a $(src)/lib -$(obj)/lib/libpayload.a: $(OBJS) prepare +$(obj)/lib/libpayload.a: prepare $(OBJS) $(Q)printf " AR $(subst $(shell pwd)/,,$(@))\n" $(Q)$(AR) rc $@ $(OBJS) -- 1.6.0.2

2 1

r3771 - trunk/payloads/libpayload
by svn＠coreboot.org 25 Nov '08

25 Nov '08

Author: jcrouse Date: 2008-11-25 17:41:21 +0100 (Tue, 25 Nov 2008) New Revision: 3771 Modified: trunk/payloads/libpayload/Makefile Log: libpayload: Fix immediate rebuild after a clean After running make clean, most of build/ directory gets deleted. It is (re)created in the "prepare" make target, but that was libpayload.a dependency after the $OBJS, while OBJS building already needs to dump its created object files there. Simply rearrange the make target dependencies to get at least "make clean;make" working. Signed-off-by: Mart Raudsepp <mart.raudsepp(a)artecdesign.ee> Acked-by: Jordan Crouse <jordan(a)cosmicpenguin.net> Modified: trunk/payloads/libpayload/Makefile =================================================================== --- trunk/payloads/libpayload/Makefile 2008-11-25 02:03:16 UTC (rev 3770) +++ trunk/payloads/libpayload/Makefile 2008-11-25 16:41:21 UTC (rev 3771) @@ -111,7 +111,7 @@ $(Q)cp $(obj)/$(ARCHDIR-y)/head.S.o $(src)/lib/$(ARCHDIR-y)/head.o $(Q)cp $(obj)/lib/libpayload.a $(src)/lib -$(obj)/lib/libpayload.a: $(OBJS) prepare +$(obj)/lib/libpayload.a: prepare $(OBJS) $(Q)printf " AR $(subst $(shell pwd)/,,$(@))\n" $(Q)$(AR) rc $@ $(OBJS)

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coreboot November 2008