coreboot November 2008

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76 participants
490 discussions

r1060 - coreboot-v3/include/arch/x86
by svn＠coreboot.org 26 Nov '08

26 Nov '08

Author: rminnich Date: 2008-11-26 19:25:42 +0100 (Wed, 26 Nov 2008) New Revision: 1060 Added: coreboot-v3/include/arch/x86/smm.h Log: smm support from v2 Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Added: coreboot-v3/include/arch/x86/smm.h =================================================================== --- coreboot-v3/include/arch/x86/smm.h (rev 0) +++ coreboot-v3/include/arch/x86/smm.h 2008-11-26 18:25:42 UTC (rev 1060) @@ -0,0 +1,250 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* AMD64 SMM State-Save Area + * starts @ 0x7e00 + */ +typedef struct { + u16 es_selector; + u16 es_attributes; + u32 es_limit; + u64 es_base; + + u16 cs_selector; + u16 cs_attributcs; + u32 cs_limit; + u64 cs_base; + + u16 ss_selector; + u16 ss_attributss; + u32 ss_limit; + u64 ss_base; + + u16 ds_selector; + u16 ds_attributds; + u32 ds_limit; + u64 ds_base; + + u16 fs_selector; + u16 fs_attributfs; + u32 fs_limit; + u64 fs_base; + + u16 gs_selector; + u16 gs_attributgs; + u32 gs_limit; + u64 gs_base; + + u8 reserved0[4]; + u16 gdtr_limit; + u8 reserved1[2]; + u64 gdtr_base; + + u16 ldtr_selector; + u16 ldtr_attributes; + u32 ldtr_limit; + u64 ldtr_base; + + u8 reserved2[4]; + u16 idtr_limit; + u8 reserved3[2]; + u64 idtr_base; + + u16 tr_selector; + u16 tr_attributes; + u32 tr_limit; + u64 tr_base; + + u8 reserved4[40]; + + u8 io_restart; + u8 autohalt_restart; + + u8 reserved5[6]; + + u64 efer; + + u8 reserved6[36]; + + u32 smm_revision; + u32 smbase; + + u8 reserved7[68]; + + u64 cr4; + u64 cr3; + u64 cr0; + u64 dr7; + u64 dr6; + + u64 rflags; + u64 rip; + u64 r15; + u64 r14; + u64 r13; + u64 r12; + u64 r11; + u64 r10; + u64 r9; + u64 r8; + + u64 rdi; + u64 rsi; + u64 rpb; + u64 rsp; + u64 rbx; + u64 rdx; + u64 rcx; + u64 rax; +} __attribute__((packed)) amd64_smm_state_save_area_t; + + +/* Intel Core 2 (EM64T) SMM State-Save Area + * starts @ 0x7d00 + */ +typedef struct { + u8 reserved0[208]; + + u32 gdtr_upper_base; + u32 ldtr_upper_base; + u32 idtr_upper_base; + + u8 reserved1[4]; + + u64 io_rdi; + u64 io_rip; + u64 io_rcx; + u64 io_rsi; + u64 cr4; + + u8 reserved2[68]; + + u64 gdtr_base; + u64 idtr_base; + u64 ldtr_base; + + u8 reserved3[84]; + + u32 smm_revision; + u32 smbase; + + u16 io_restart; + u16 autohalt_restart; + + u8 reserved4[24]; + + u64 r15; + u64 r14; + u64 r13; + u64 r12; + u64 r11; + u64 r10; + u64 r9; + u64 r8; + + u64 rax; + u64 rcx; + u64 rdx; + u64 rbx; + + u64 rsp; + u64 rbp; + u64 rsi; + u64 rdi; + + + u64 io_mem_addr; + u32 io_misc_info; + + u32 es_sel; + u32 cs_sel; + u32 ss_sel; + u32 ds_sel; + u32 fs_sel; + u32 gs_sel; + + u32 ldtr_sel; + u32 tr_sel; + + u64 dr7; + u64 dr6; + u64 rip; + u64 efer; + u64 rflags; + + u64 cr3; + u64 cr0; +} __attribute__((packed)) em64t_smm_state_save_area_t; + + +/* Legacy x86 SMM State-Save Area + * starts @ 0x7e00 + */ + +typedef struct { + u8 reserved0[248]; + u32 smbase; + u32 smm_revision; + u16 io_restart; + u16 autohalt_restart; + u8 reserved1[132]; + u32 gdtbase; + u8 reserved2[8]; + u32 idtbase; + u8 reserved3[16]; + u32 es; + u32 cs; + u32 ss; + u32 ds; + u32 fs; + u32 gs; + u32 ldtbase; + u32 tr; + u32 dr7; + u32 dr6; + u32 eax; + u32 ecx; + u32 edx; + u32 ebx; + u32 esp; + u32 ebp; + u32 esi; + u32 edi; + u32 eip; + u32 eflags; + u32 cr3; + u32 cr0; +} __attribute__((packed)) legacy_smm_state_save_area_t; + +typedef enum { + AMD64, + EM64T, + LEGACY +} save_state_type_t; + + +typedef struct { + save_state_type_t type; + union { + amd64_smm_state_save_area_t *amd64_state_save; + em64t_smm_state_save_area_t *em64t_state_save; + legacy_smm_state_save_area_t *legacy_state_save; + }; +} smm_state_save_area_t; +

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flashrom: Winbond W83627DHG SPI, RDID 90,
by hardik patel 26 Nov '08

26 Nov '08

Hi, I want to post a message in the forum: http://www.coreboot.org/pipermail/coreboot/2008-July/036446.html I am not sure how to post the message. I have written my response below to one of the messages in the forum. Can you help me in posting the message written below. Regards, Hardik Patel MY RESPONSE TO THE ENGINEER IN THE FORUM: Yes, just looking at overhead it does seem that the over head time for AAI is greater than Page Program time. However, overhead time is insignificant compared to overall program time. Let’s do a quick compare between the below two cases: Programming in AAI needs1(command)+3(dummyaddr)+2(data)+(1(command)+2(data))*127(aaiwrites) =387 cycles for 256 bytes Page ProgrammingProgramming in 256 byte chunks needs 1(command)+3(address)+256(data) =260 cycles for 256 bytes In AAI programming: Sending the bytes using the AAI protocol will depend on the clock frequency at which the memory accepts writes. For 50 Mhz clock, 387 cycles would take 387*(1/50Mhz)=7.74us Now the memory will take time to do internal programming. For AAI programming, it takes maximum 10us to program 1 word (or two bytes). Hence it would take 10us *127=1.27ms So the total time = 1.27ms + 7.74us=1.27774us. Thus the overhead time is insignificant portion of the total time. Now For Page Programming: Sending the Page data at 50Mhz clock frequency would take 260*(1/50Mhz) = 5.2us Now the memory will take time to do internal programming of the 256bytes which it just received. For example MX25L3235D macronix part would take 1.4ms (typical) to do page programming. So the total time = 1.4ms(typ) + 5.2us = 1.4052ms. THUS, clearly the above calculation suggests that overall time for AAI programming is faster than Page programming. Page programming time can take several milliseconds for many memories. I would prefer AAI. _________________________________________________________________

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ACPI S3
by Feng, Libo 26 Nov '08

26 Nov '08

Hi, all, I am trying to implement the ACPI S3 on coreboot. I have some questions: 1. Where is the proper place to check the sleep type in the power register? Now I check it just prior to disabling the cache as RAM, for not ruining the RAM. 2. How to jump into the wakeup_start in x86_64/kernel/acpi/wakeup.S? The code is in real mode, how does coreboot jump from the protected mode to the entry? In my case, the wakeup_start points to the physical address 0x2000, from there some real mode code reside. How to jump to the code. The below is the beginning part of wakeup_start: .text #include <linux/linkage.h> #include <asm/segment.h> #include <asm/page.h> #include <asm/msr.h> # Copyright 2003 Pavel Machek <pavel(a)suse.cz>, distribute under GPLv2 # # wakeup_code runs in real mode, and at unknown address (determined at run-time). # Therefore it must only use relative jumps/calls. # # Do we need to deal with A20? It is okay: ACPI specs says A20 must be enabled # # If physical address of wakeup_code is 0x12345, BIOS should call us with # cs = 0x1234, eip = 0x05 # ALIGN .align 16 ENTRY(wakeup_start) wakeup_code: wakeup_code_start = . .code16 # Running in *copy* of this code, somewhere in low 1MB. movb $0xa1, %al ; outb %al, $0x80 cli cld # setup data segment movw %cs, %ax movw %ax, %ds # Make ds:0 point to wakeup_start movw %ax, %ss mov $(wakeup_stack - wakeup_code), %sp # Private stack is needed for ASUS board pushl $0 # Kill any dangerous flags popfl ================================================================= Any comments are appreciated. Best Regards 丰立波 Feng Libo @ AMD Ext: 20906 Mobile Phone: 13683249071 Office Phone: 0086-010-62801406

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Re: [coreboot] r1059 - coreboot-v3/arch/x86/intel/core2
by Carl-Daniel Hailfinger 26 Nov '08

26 Nov '08

On 26.11.2008 10:17, svn(a)coreboot.org wrote: > Author: stepan > Date: 2008-11-26 10:17:29 +0100 (Wed, 26 Nov 2008) > New Revision: 1059 > > Modified: > coreboot-v3/arch/x86/intel/core2/stage0.S > Log: > back out until this issue is really fixed. > Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> > Acked-by: Stefan Reinauer <stepan(a)coresystems.de> > OK, and what failed this time? BIST? Last POST code? I want to fix this, but the information I have available is rather scarce. It is obvious that the existing code is broken and works only by accident for some platforms. AFAICS we can even scribble randomly over memory with the current Core2Duo CAR. I'll send a patch to re-add the comments. If the comments break anything, either the tests are flaky or your gcc/gas is totally broken. Regards, Carl-Daniel -- http://www.hailfinger.org/

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Re: [coreboot] r3770 - trunk/util/msrtool
by Jordan Crouse 26 Nov '08

26 Nov '08

svn(a)coreboot.org wrote: > Author: stuge > Date: 2008-11-25 03:03:16 +0100 (Tue, 25 Nov 2008) > New Revision: 3770 > > Modified: > trunk/util/msrtool/TODO > trunk/util/msrtool/configure > trunk/util/msrtool/msrtool.c > trunk/util/msrtool/msrtool.h > trunk/util/msrtool/sys.c > Log: > msrtool: Use libpci to let system and target probes find PCI devices. > > And some more notes in TODO. > > Signed-off-by: Peter Stuge <peter(a)stuge.se> > Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> > > > Modified: trunk/util/msrtool/TODO > =================================================================== > --- trunk/util/msrtool/TODO 2008-11-24 20:23:23 UTC (rev 3769) > +++ trunk/util/msrtool/TODO 2008-11-25 02:03:16 UTC (rev 3770) > @@ -1,8 +1,9 @@ > Systems > ------- > FreeBSD #defines: see svn diff -r 3697:3698 util/ > +i586: assembly instruction system driver, may have to ignore -c CPU # option > > Other ideas > ----------- > Move MSR definitions and probe instructions into an external text file? > -Handle PCI registers as well? > +Handle PCI and port IO registers as well? > > Modified: trunk/util/msrtool/configure > =================================================================== > --- trunk/util/msrtool/configure 2008-11-24 20:23:23 UTC (rev 3769) > +++ trunk/util/msrtool/configure 2008-11-25 02:03:16 UTC (rev 3770) > @@ -135,6 +135,25 @@ > test -n "$DEBUG" && myCFLAGS="-O2 -g" || myCFLAGS="-Os" > CFLAGS="${CFLAGS} ${myCFLAGS} -Wall -Werror" > > +cat > .config.c << EOF > +#include <pci/pci.h> > +struct pci_access *pacc; > +int main(int argc, char *argv[]) > +{ pacc = pci_alloc(); return 0; } > +EOF > + > +pc_CFLAGS="$(pkg-config libpci --cflags 2>/dev/null)" > +pc_LDFLAGS="$(pkg-config libpci --libs 2>/dev/null)" > +CFLAGS=$(trycompile "libpci (from pciutils)" "${pc_CFLAGS}" "-I/usr/local/include") || { > + rm -f .config.c > + exit 1 Any reason why we don't just drink all the koolaid and use the full autoconf/automake/pkgconfig system in all its glory? This seems to be fairly prone to porting issues - especially the -I/usr/local/include bit. Jordan

5 9

r1059 - coreboot-v3/arch/x86/intel/core2
by svn＠coreboot.org 26 Nov '08

26 Nov '08

Author: stepan Date: 2008-11-26 10:17:29 +0100 (Wed, 26 Nov 2008) New Revision: 1059 Modified: coreboot-v3/arch/x86/intel/core2/stage0.S Log: back out until this issue is really fixed. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: coreboot-v3/arch/x86/intel/core2/stage0.S =================================================================== --- coreboot-v3/arch/x86/intel/core2/stage0.S 2008-11-26 02:16:37 UTC (rev 1058) +++ coreboot-v3/arch/x86/intel/core2/stage0.S 2008-11-26 09:17:29 UTC (rev 1059) @@ -3,7 +3,6 @@ * * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich(a)gmail.com> * Copyright (C) 2007-2008 coresystems GmbH - * Copyright (C) 2008 Carl-Daniel Hailfinger * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -160,20 +159,9 @@ movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4), %eax movl %eax, %esp - /* Store zero for the pointer to the global variables. */ - pushl $0 - - /* Restore the BIST result. */ + /* Restore the BIST result */ movl %ebp, %eax - - /* We need to set ebp? No need. */ movl %esp, %ebp - - /* Second parameter: init_detected */ - /* Store zero for the unused init_detected parameter. */ - pushl $0 - - /* First parameter: bist */ pushl %eax #if 0 @@ -182,7 +170,6 @@ #endif call stage1_phase1 - /* We will not go back. */ port80_post(0x2f) error:

1 0

flashrom: simplify ich spi read/write operations
by FENG Yu Ning 26 Nov '08

26 Nov '08

This patch simplifies ich spi read/write operations, and changes naming from "page" to "block". The impact of modification have been made minimal, other parts of flashrom should not be affected. Not tested due to lack of facility. Very appreciated if anyone can help. Signed-off-by: FENG yu ning <fengyuning1984(a)gmail.com> Index: flashrom/ichspi.c =================================================================== --- flashrom/ichspi.c (revision 3767) +++ flashrom/ichspi.c (working copy) @@ -150,10 +150,10 @@ static int program_opcodes(OPCODES * op); static int run_opcode(OPCODE op, uint32_t offset, uint8_t datalength, uint8_t * data); -static int ich_spi_read_page(struct flashchip *flash, uint8_t * buf, - int offset, int maxdata); -static int ich_spi_write_page(struct flashchip *flash, uint8_t * bytes, - int offset, int maxdata); +static int ich_spi_read_block(struct flashchip *flash, uint8_t * buf, + int offset, int block_size, int maxdata); +static int ich_spi_write_block(struct flashchip *flash, uint8_t * bytes, + int offset, int block_size, int maxdata); OPCODES O_ST_M25P = { { @@ -478,28 +478,25 @@ return -1; } -static int ich_spi_read_page(struct flashchip *flash, uint8_t * buf, int offset, - int maxdata) +static int ich_spi_read_block(struct flashchip *flash, uint8_t * buf, + int offset, int block_size, int maxdata) { - int page_size = flash->page_size; - uint32_t remaining = flash->page_size; + uint32_t remaining = block_size; int a; - printf_debug("ich_spi_read_page: offset=%d, number=%d, buf=%p\n", - offset, page_size, buf); + printf_debug("ich_spi_read_block: offset=%d, block size=%d, buf=%p\n", + offset, block_size, buf); - for (a = 0; a < page_size; a += maxdata) { + for (a = 0; a < block_size; a += maxdata) { if (remaining < maxdata) { - if (spi_nbyte_read(offset + (page_size - remaining), - &buf[page_size - remaining], remaining)) { + if (spi_nbyte_read(offset + a, &buf[a], remaining)) { printf_debug("Error reading"); return 1; } remaining = 0; } else { - if (spi_nbyte_read(offset + (page_size - remaining), - &buf[page_size - remaining], maxdata)) { + if (spi_nbyte_read(offset + a, &buf[a], maxdata)) { printf_debug("Error reading"); return 1; } @@ -510,22 +507,21 @@ return 0; } -static int ich_spi_write_page(struct flashchip *flash, uint8_t * bytes, - int offset, int maxdata) +static int ich_spi_write_block(struct flashchip *flash, uint8_t * bytes, + int offset, int block_size, int maxdata) { - int page_size = flash->page_size; - uint32_t remaining = page_size; + uint32_t remaining = block_size; int a; - printf_debug("ich_spi_write_page: offset=%d, number=%d, buf=%p\n", - offset, page_size, bytes); + printf_debug("ich_spi_write_block: offset=%d, block size=%d, buf=%p\n", + offset, block_size, bytes); - for (a = 0; a < page_size; a += maxdata) { + for (a = 0; a < block_size; a += maxdata) { if (remaining < maxdata) { if (run_opcode (curopcodes->opcode[0], - offset + (page_size - remaining), remaining, - &bytes[page_size - remaining]) != 0) { + offset + a, remaining, + &bytes[a]) != 0) { printf_debug("Error writing"); return 1; } @@ -533,8 +529,8 @@ } else { if (run_opcode (curopcodes->opcode[0], - offset + (page_size - remaining), maxdata, - &bytes[page_size - remaining]) != 0) { + offset + a, maxdata, + &bytes[a]) != 0) { printf_debug("Error writing"); return 1; } @@ -547,34 +543,29 @@ int ich_spi_read(struct flashchip *flash, uint8_t * buf) { - int i, rc = 0; + int rc = 0; int total_size = flash->total_size * 1024; - int page_size = flash->page_size; int maxdata = 64; if (flashbus == BUS_TYPE_VIA_SPI) { maxdata = 16; } - for (i = 0; (i < total_size / page_size) && (rc == 0); i++) { - rc = ich_spi_read_page(flash, (void *)(buf + i * page_size), - i * page_size, maxdata); - } + rc = ich_spi_read_block(flash, buf, 0, total_size, maxdata); return rc; } int ich_spi_write(struct flashchip *flash, uint8_t * buf) { - int i, j, rc = 0; + int i, rc = 0; int total_size = flash->total_size * 1024; - int page_size = flash->page_size; int erase_size = 64 * 1024; int maxdata = 64; spi_disable_blockprotect(); - printf("Programming page: \n"); + printf("Programming flashchip: \n"); for (i = 0; i < total_size / erase_size; i++) { /* FIMXE: call the chip-specific spi_block_erase_XX instead. @@ -590,11 +581,12 @@ if (flashbus == BUS_TYPE_VIA_SPI) maxdata = 16; - for (j = 0; j < erase_size / page_size; j++) { - ich_spi_write_page(flash, - (void *)(buf + (i * erase_size) + (j * page_size)), - (i * erase_size) + (j * page_size), maxdata); - } + ich_spi_write_block(flash, + (void *)(buf + (i * erase_size)), + i * erase_size, + erase_size, + maxdata); + } printf("\n");

3 6

Re: [coreboot] r1057 - in coreboot-v3/arch/x86: . intel/core2
by Stefan Reinauer 26 Nov '08

26 Nov '08

svn(a)coreboot.org wrote: > Author: hailfinger > Date: 2008-11-26 00:39:31 +0100 (Wed, 26 Nov 2008) > New Revision: 1057 > > Modified: > coreboot-v3/arch/x86/intel/core2/stage0.S > coreboot-v3/arch/x86/stage1.c > Log: > The Core2Duo CAR code did set up the stack incorrectly. In combination > with a wrong calling convention of stage1_phase1() this caused stage1 to > assume BIST had failed. > > Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> > Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> > > Can you please back this out again? With this code nothing seems to work anymore. > Modified: coreboot-v3/arch/x86/intel/core2/stage0.S > =================================================================== > --- coreboot-v3/arch/x86/intel/core2/stage0.S 2008-11-25 23:10:24 UTC (rev 1056) > +++ coreboot-v3/arch/x86/intel/core2/stage0.S 2008-11-25 23:39:31 UTC (rev 1057) > @@ -3,6 +3,7 @@ > * > * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich(a)gmail.com> > * Copyright (C) 2007-2008 coresystems GmbH > + * Copyright (C) 2008 Carl-Daniel Hailfinger > * > * This program is free software; you can redistribute it and/or modify > * it under the terms of the GNU General Public License as published by > @@ -159,17 +160,26 @@ > movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4), %eax > movl %eax, %esp > > - /* Restore the BIST result */ > + /* Store zero for the pointer to the global variables. */ > + pushl $0 > + > + /* Restore the BIST result. */ > movl %ebp, %eax > + > + /* We need to set ebp? No need. */ > movl %esp, %ebp > + > + /* Second parameter: init_detected */ > + /* Store zero for the unused init_detected parameter. */ > + pushl $0 > + > + /* First parameter: bist */ > pushl %eax > > -#if 0 > - /* this will be interpreted as failed bist */ > port80_post(0x23) > -#endif > > call stage1_phase1 > + /* We will not go back. */ > > port80_post(0x2f) > error: > > Modified: coreboot-v3/arch/x86/stage1.c > =================================================================== > --- coreboot-v3/arch/x86/stage1.c 2008-11-25 23:10:24 UTC (rev 1056) > +++ coreboot-v3/arch/x86/stage1.c 2008-11-25 23:39:31 UTC (rev 1057) > @@ -187,7 +187,7 @@ > * that we are restarting after some sort of reconfiguration. Note that we could use it on geode but > * do not at present. > */ > -void __attribute__((stdcall)) stage1_phase1(u32 bist, u32 init_detected) > +void __attribute__((stdcall,regparm(0))) stage1_phase1(u32 bist, u32 init_detected) > { > struct global_vars globvars; > int ret; > > > -- > coreboot mailing list: coreboot(a)coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot > > -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: info(a)coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866

2 1

r1058 - in coreboot-v3/arch/x86: . intel/core2
by svn＠coreboot.org 26 Nov '08

26 Nov '08

Author: hailfinger Date: 2008-11-26 03:16:37 +0100 (Wed, 26 Nov 2008) New Revision: 1058 Modified: coreboot-v3/arch/x86/intel/core2/stage0.S coreboot-v3/arch/x86/stage1.c Log: Experimental backout of the critical code parts in r1057 as requested by Stefan. The only changes left from r1057 are: - Added comments - Two initial pushes of 0x00000000 (32 bits each) to the stack as safety Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: coreboot-v3/arch/x86/intel/core2/stage0.S =================================================================== --- coreboot-v3/arch/x86/intel/core2/stage0.S 2008-11-25 23:39:31 UTC (rev 1057) +++ coreboot-v3/arch/x86/intel/core2/stage0.S 2008-11-26 02:16:37 UTC (rev 1058) @@ -176,7 +176,10 @@ /* First parameter: bist */ pushl %eax +#if 0 + /* this will be interpreted as failed bist */ port80_post(0x23) +#endif call stage1_phase1 /* We will not go back. */ Modified: coreboot-v3/arch/x86/stage1.c =================================================================== --- coreboot-v3/arch/x86/stage1.c 2008-11-25 23:39:31 UTC (rev 1057) +++ coreboot-v3/arch/x86/stage1.c 2008-11-26 02:16:37 UTC (rev 1058) @@ -187,7 +187,7 @@ * that we are restarting after some sort of reconfiguration. Note that we could use it on geode but * do not at present. */ -void __attribute__((stdcall,regparm(0))) stage1_phase1(u32 bist, u32 init_detected) +void __attribute__((stdcall)) stage1_phase1(u32 bist, u32 init_detected) { struct global_vars globvars; int ret;

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[PATCH] v3: Fix BIST failure for Core2Duo, fix calling convention
by Carl-Daniel Hailfinger 26 Nov '08

26 Nov '08

The Core2Duo CAR code did set up the stack incorrectly. In combination with a wrong calling convention of stage1_phase1() this caused stage1 to assume BIST had failed. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: corebootv3-bistfail/arch/x86/stage1.c =================================================================== --- corebootv3-bistfail/arch/x86/stage1.c (Revision 1055) +++ corebootv3-bistfail/arch/x86/stage1.c (Arbeitskopie) @@ -187,7 +187,7 @@ * that we are restarting after some sort of reconfiguration. Note that we could use it on geode but * do not at present. */ -void __attribute__((stdcall)) stage1_phase1(u32 bist, u32 init_detected) +void __attribute__((stdcall,regparm(0))) stage1_phase1(u32 bist, u32 init_detected) { struct global_vars globvars; int ret; Index: corebootv3-bistfail/arch/x86/intel/core2/stage0.S =================================================================== --- corebootv3-bistfail/arch/x86/intel/core2/stage0.S (Revision 1055) +++ corebootv3-bistfail/arch/x86/intel/core2/stage0.S (Arbeitskopie) @@ -156,17 +156,26 @@ movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4), %eax movl %eax, %esp - /* Restore the BIST result */ + /* Store zero for the pointer to the global variables. */ + pushl $0 + + /* Restore the BIST result. */ movl %ebp, %eax + + /* We need to set ebp? No need. */ movl %esp, %ebp + + /* Second parameter: init_detected */ + /* Store zero for the unused init_detected parameter. */ + pushl $0 + + /* First parameter: bist */ pushl %eax -#if 0 - /* this will be interpreted as failed bist */ port80_post(0x23) -#endif call stage1_phase1 + /* We will not go back. */ port80_post(0x2f) error: -- http://www.hailfinger.org/ Index: corebootv3-bistfail/arch/x86/stage1.c =================================================================== --- corebootv3-bistfail/arch/x86/stage1.c (Revision 1055) +++ corebootv3-bistfail/arch/x86/stage1.c (Arbeitskopie) @@ -187,7 +187,7 @@ * that we are restarting after some sort of reconfiguration. Note that we could use it on geode but * do not at present. */ -void __attribute__((stdcall)) stage1_phase1(u32 bist, u32 init_detected) +void __attribute__((stdcall,regparm(0))) stage1_phase1(u32 bist, u32 init_detected) { struct global_vars globvars; int ret; Index: corebootv3-bistfail/arch/x86/intel/core2/stage0.S =================================================================== --- corebootv3-bistfail/arch/x86/intel/core2/stage0.S (Revision 1055) +++ corebootv3-bistfail/arch/x86/intel/core2/stage0.S (Arbeitskopie) @@ -156,17 +156,26 @@ movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4), %eax movl %eax, %esp - /* Restore the BIST result */ + /* Store zero for the pointer to the global variables. */ + pushl $0 + + /* Restore the BIST result. */ movl %ebp, %eax + + /* We need to set ebp? No need. */ movl %esp, %ebp + + /* Second parameter: init_detected */ + /* Store zero for the unused init_detected parameter. */ + pushl $0 + + /* First parameter: bist */ pushl %eax -#if 0 - /* this will be interpreted as failed bist */ port80_post(0x23) -#endif call stage1_phase1 + /* We will not go back. */ port80_post(0x2f) error:

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coreboot November 2008