In flashchip.c, there is (just an example),
/* Vendor Chip ... Page size (B) ... */ ... {"SST", "SST25VF040B", ... 256, ... },
How to find out the number 256? I have read through the datasheet of that chip, which mentioned 4K sector, 32K and 64K blocks, but no "page". There is neither an operation which needs an address with value 0 in the least significant 8 bits.
Or, the number does not come out of a datasheet?
Thanks, yu ning
I have dug into more documentation, and found partial answer.
I am only considering SST flash chips. From the SST Product Selection Guide, among various flash memories(Series 27,37,28,29,25), only SST29xE featured with page-by-page write operations, with a page size of 128 bytes.
Questions: 1. How do we decide the page-sizes of other SST(and other vendors) flash chips, which have no page mechanism? 2. Since we operate the flash chips (in case of ich) with ich_spi_read/write, which in turn call ich_spi_read/write_page, what happens to those chips without a page-read/write operation? I am going to investigate the source code and data sheets further, but it is appreciated if anyone familiar with this tell me directly (and it would guide me through the investigation).
Thanks, yu ning
Hello Yu Ning,
FENG Yu Ning wrote:
Questions:
- How do we decide the page-sizes of other SST(and other vendors)
flash chips, which have no page mechanism?
The page_size member is considered an eraseblock size by the code.
- Since we operate the flash chips (in case of ich) with
ich_spi_read/write, which in turn call ich_spi_read/write_page, what happens to those chips without a page-read/write operation? I am going to investigate the source code and data sheets further, but it is appreciated if anyone familiar with this tell me directly (and it would guide me through the investigation).
As you may have found, the code is pretty ugly overall. In the case of ichspi, read_page and write_page simply assume that it is possible to read or write all of page_size bytes in a loop.
Other SPI "bus" drivers work differently, but page_size is always assumed to describe an eraseblock size.
//Peter
On 11/19/08, Peter Stuge peter@stuge.se wrote:
The page_size member is considered an eraseblock size by the code.
Makes me clear. The naming is somewhat misleading, however.
As you may have found, the code is pretty ugly overall.
The code does not look good.
1.Here,
int ich_spi_write(struct flashchip *flash, uint8_t * buf) { int i, j, rc = 0; int total_size = flash->total_size * 1024; int page_size = flash->page_size; int erase_size = 64 * 1024;
the erase_size is "hard-wired" to 64k bytes.
2. Later in the same function, spi_block_erase_d8 is called to erase a block(If we are going to use block erase, I agree with the FIXME there). In fact, the erase-write loop covers the whole chip, I think doing chip-erase outside is better. page_size is not used as erase block size. It is used only as a write loop counter.
The ich spi read/write functions need to be written in the future.
In the case of ichspi, read_page and write_page simply assume that it is possible to read or write all of page_size bytes in a loop.
If there is no other design issues, its only function here is just confusing people.
Other SPI "bus" drivers work differently, but page_size is always assumed to describe an eraseblock size.
Thanks very much for the clear explanation.
yu ning
On 19.11.2008 09:31, FENG Yu Ning wrote:
On 11/19/08, Peter Stuge peter@stuge.se wrote:
The page_size member is considered an eraseblock size by the code.
Makes me clear. The naming is somewhat misleading, however.
Yes. We should have one eraseblock_size member and one write_size member.
As you may have found, the code is pretty ugly overall.
The code does not look good.
1.Here,
int ich_spi_write(struct flashchip *flash, uint8_t * buf) { int i, j, rc = 0; int total_size = flash->total_size * 1024; int page_size = flash->page_size; int erase_size = 64 * 1024;
the erase_size is "hard-wired" to 64k bytes.
- Later in the same function, spi_block_erase_d8 is called to erase a
block(If we are going to use block erase, I agree with the FIXME there). In fact, the erase-write loop covers the whole chip, I think doing chip-erase outside is better. page_size is not used as erase block size. It is used only as a write loop counter.
The ich spi read/write functions need to be written in the future.
In the case of ichspi, read_page and write_page simply assume that it is possible to read or write all of page_size bytes in a loop.
If there is no other design issues, its only function here is just confusing people.
You are right. I will repost my patch to fix this.
Regards, Carl-Daniel
On 19.11.2008 07:50, Peter Stuge wrote:
Hello Yu Ning,
FENG Yu Ning wrote:
Questions:
- How do we decide the page-sizes of other SST(and other vendors)
flash chips, which have no page mechanism?
The page_size member is considered an eraseblock size by the code.
Sorry, that is incorrect.
- Since we operate the flash chips (in case of ich) with
ich_spi_read/write, which in turn call ich_spi_read/write_page, what happens to those chips without a page-read/write operation? I am going to investigate the source code and data sheets further, but it is appreciated if anyone familiar with this tell me directly (and it would guide me through the investigation).
As you may have found, the code is pretty ugly overall. In the case of ichspi, read_page and write_page simply assume that it is possible to read or write all of page_size bytes in a loop.
Other SPI "bus" drivers work differently, but page_size is always assumed to describe an eraseblock size.
On ICH SPI, page_size is the maximum number of bytes you can write and read in one operation. ICH SPI hardcodes eraseblock size to 4k. ITE SPI is different.
I sent a patch to use explicit erase block sizes, but that patch does not have any Ack yet.
Regards, Carl-Daniel
On 19.11.2008 13:34, Carl-Daniel Hailfinger wrote:
On 19.11.2008 07:50, Peter Stuge wrote:
Hello Yu Ning,
FENG Yu Ning wrote:
Questions:
- How do we decide the page-sizes of other SST(and other vendors)
flash chips, which have no page mechanism?
The page_size member is considered an eraseblock size by the code.
Sorry, that is incorrect.
- Since we operate the flash chips (in case of ich) with
ich_spi_read/write, which in turn call ich_spi_read/write_page, what happens to those chips without a page-read/write operation? I am going to investigate the source code and data sheets further, but it is appreciated if anyone familiar with this tell me directly (and it would guide me through the investigation).
As you may have found, the code is pretty ugly overall. In the case of ichspi, read_page and write_page simply assume that it is possible to read or write all of page_size bytes in a loop.
Other SPI "bus" drivers work differently, but page_size is always assumed to describe an eraseblock size.
On ICH SPI, page_size is the maximum number of bytes you can write and read in one operation. ICH SPI hardcodes eraseblock size to 4k. ITE SPI
Typo. That should have been 64k.
is different.
I sent a patch to use explicit erase block sizes, but that patch does not have any Ack yet.
Regards, Carl-Daniel
On 11/19/08, Carl-Daniel Hailfinger c-d.hailfinger.devel.2006@gmx.net wrote:
On ICH SPI, page_size is the maximum number of bytes you can write and read in one operation. ICH SPI hardcodes eraseblock size to 4k. ITE SPI is different.
Point me to the exact place of documentation if convenient? I have been reading(quick browsing) the ICH7 spec., but have not found this limitation yet(or just forgotten immediately). I have been reading various docs these days.
I sent a patch to use explicit erase block sizes, but that patch does not have any Ack yet.
About when? Maybe I can help search for it.
BTW, I have not finished reading ichspi.c, but ask previously, are we able to write a part of the chip in ichspi.c(to support ROM layout)?
yu ning
On 11/19/08, Carl-Daniel Hailfinger c-d.hailfinger.devel.2006@gmx.net wrote:
On 19.11.2008 07:50, Peter Stuge wrote:
The page_size member is considered an eraseblock size by the code.
Sorry, that is incorrect.
On ICH SPI, page_size is the maximum number of bytes you can write and read in one operation.
I have just read related part of ichspi.c carefully. The conclusion is, in the ich7 part of ichspi.c(I have not investigated others), page_size is neither erase-block size, nor the maximum number of data bytes per operaion. It is simply meaningless.
Carl-Daniel, I think the variable fitting your explanation would be maxdata.
ICH SPI hardcodes eraseblock size to 64k.
If we can use block erase, things should look better. I have a motherboard here - intel D945PLRN, which has i945PL,ich7, and SST25LF040A(it explains why I keep asking questions about intel chipsets and SST). That SST spi flash chip uses 52h as block erasing instruction instead of d6h, and the block size is 32k.
Carl-Daniel, are you working on that? If not, I would like to have a try, only I seldom do coding and don't know whether I am capable.
yu ning
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Carl-Daniel Hailfinger -
FENG Yu Ning -
Peter Stuge