coreboot November 2008

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[PATCH] v3: Fix VIA VT1211 LDNs (repost)
by Uwe Hermann 16 Nov '08

16 Nov '08

See patch. Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org

2 2

r1033 - coreboot-v3/superio/via/vt1211
by svn＠coreboot.org 16 Nov '08

16 Nov '08

Author: uwe Date: 2008-11-16 14:41:15 +0100 (Sun, 16 Nov 2008) New Revision: 1033 Modified: coreboot-v3/superio/via/vt1211/vt1211.h Log: Fix the incorrect VIA VT1211 LDNs, add a comment for each of them. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: coreboot-v3/superio/via/vt1211/vt1211.h =================================================================== --- coreboot-v3/superio/via/vt1211/vt1211.h 2008-11-16 01:52:08 UTC (rev 1032) +++ coreboot-v3/superio/via/vt1211/vt1211.h 2008-11-16 13:41:15 UTC (rev 1033) @@ -21,16 +21,17 @@ #ifndef SUPERIO_VIA_VT1211_VT122_H #define SUPERIO_VIA_VT1211_VT122_H -#define VT1211_FDC 0 /* Floppy */ -#define VT1211_PP 1 /* Parallel Port */ -#define VT1211_SP1 2 /* Com1 */ -#define VT1211_SP2 3 /* Com2 */ -#define VT1211_KBC 5 /* Keyboard & Mouse */ -#define VT1211_CIR 6 -#define VT1211_GAME_MIDI_GPIO1 7 -#define VT1211_GPIO2 8 -#define VT1211_GPIO3 9 -#define VT1211_ACPI 10 -#define VT1211_HWM 11 /* Hardware Monitor */ +#define VT1211_FDC 0 /* Floppy */ +#define VT1211_PP 1 /* Parallel port */ +#define VT1211_SP1 2 /* COM1 */ +#define VT1211_SP2 3 /* COM2 */ +#define VT1211_MIDI 6 /* MIDI */ +#define VT1211_GAME 7 /* Game port */ +#define VT1211_GPIO 8 /* GPIO pins */ +#define VT1211_WATCHDOG 9 /* Watchdog timer */ +#define VT1211_WAKEUP 10 /* Wakeup control */ +#define VT1211_HWM 11 /* Hardware monitor */ +#define VT1211_FIR 12 /* IRDA */ +#define VT1211_ROM 13 /* ROM control */ #endif /* SUPERIO_VIA_VT1211_VT122_H */

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Re: [coreboot] r1026 - in coreboot-v3: mainboard/kontron/986lcd-m southbridge/intel/i82801gx
by Carl-Daniel Hailfinger 16 Nov '08

16 Nov '08

On 14.11.2008 18:14, svn(a)coreboot.org wrote: > Author: rminnich > New Revision: 1026 > > /home/rminnich/coreboot-v3/build/coreboot.initram_partiallylinked.o: section .data.rel.ro.local: dual_channel_slew_group_lookup.3242 single_channel_slew_group_lookup.3243 > Basic rule: If you want to have arrays of pointers in initram, you lose. Pointers are not relocatable by definition. const is not going to help you there. > and > /home/rminnich/coreboot-v3/southbridge/intel/i82801gx/smbus.c:34: error: conflicting types for ?\226?\128?\152smbus_read_byte?\226?\128?\153 > include/device/smbus.h:56: error: previous declaration of ?\226?\128?\152smbus_read_byte?\226?\128?\153 was here > > we are working these. The second is much harder than it seems. > It concerns whether we put i2c devices (i.e. DRAM spd SEEPROMS) in the dts. > I have a 8 month old patch to fix this, but the patch was vetoed back then. I could repost. Regards, Carl-Daniel -- http://www.hailfinger.org/

5 28

Problem with the RTC
by Chris Lingard 16 Nov '08

16 Nov '08

coreboot-v2 has been giving the following error: PCI: 00:01.0 init set power on after power fail RTC Init Invalid CMOS LB checksum PNP: 002e.1 init I have put some debugging in rtc_checksum_valid of mc146818rtc.c to output the variables, and got PU model AMD Athlon(tm) 64 X2 Dual Core Processor 6000+ Setting up local apic... apic_id: 0x01 done. CPU #1 Initialized All AP CPUs stopped PCI: 00:18.0 init PCI: 00:01.0 init set power on after power fail RTC Init Sum f31c Old Sum f31c Sum cfe1 Old Sum 2225 Invalid CMOS LB checksum PNP: 002e.1 init This persists on reboot, and on cold start. I have no idea why the second call to this procedure results in this, but think it is a timing problem. This procedure is called twice from rtc_init, and I think that the second call is wrong; so I changed the second one: /* See if there is a LB CMOS checksum error */ /* checksum_invalid = !rtc_checksum_valid(LB_CKS_RANGE_START, LB_CKS_RANGE_END,LB_CKS_LOC); */ if(checksum_invalid) printk_debug("Invalid CMOS LB checksum\n"); { /* Make certain we have a valid checksum */ rtc_set_checksum(PC_CKS_RANGE_START, PC_CKS_RANGE_END,PC_CKS_LOC); } checksum_invalid is already set, so the second call to rtc_checksum_valid is commented out The check sum was being written back every time, right or wrong, so I have put rtc_set_checksum within the failure bit. Chris Lingard

3 3

latest cumulative kontron patch
by ron minnich 16 Nov '08

16 Nov '08

The thing almost builds now. Fixed the 'array of pointers' in a way that will work for now. Many other fixes. superio updated. Not that this is a threat, I am going to walk the dog, I hope to see at least a review when I get back :-) ron

5 10

r1032 - coreboot-v3/superio/winbond/w83627thg
by svn＠coreboot.org 15 Nov '08

15 Nov '08

Author: hailfinger Date: 2008-11-16 02:52:08 +0100 (Sun, 16 Nov 2008) New Revision: 1032 Modified: coreboot-v3/superio/winbond/w83627thg/stage1.c coreboot-v3/superio/winbond/w83627thg/superio.c Log: Drop duplicated functions from W83627THG SuperI/O stage1 code and fix up a function prototype. Fix up #include statements for W83627THG SuperI/O stage2 code. Use anonymous instead of named unions in struct device. Point pnp_dev_info members to w83627thg_ops. Disable UART and keyboard initialization for now. Add new code in phase3_chip_setup_dev to fill in configuration values from the dts (code is partially disabled). Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: coreboot-v3/superio/winbond/w83627thg/stage1.c =================================================================== --- coreboot-v3/superio/winbond/w83627thg/stage1.c 2008-11-16 01:22:18 UTC (rev 1031) +++ coreboot-v3/superio/winbond/w83627thg/stage1.c 2008-11-16 01:52:08 UTC (rev 1032) @@ -21,25 +21,12 @@ #include <device/pnp.h> #include "w83627thg.h" -static inline void pnp_enter_ext_func_mode(device_t dev) +static void w83627thg_enable_serial(u8 dev, u8 serial, u16 iobase) { - unsigned int port = dev >> 8; - outb(0x87, port); - outb(0x87, port); + rawpnp_enter_ext_func_mode(dev); + rawpnp_set_logical_device(dev, serial); + rawpnp_set_enable(dev, 0); + rawpnp_set_iobase(dev, PNP_IDX_IO0, iobase); + rawpnp_set_enable(dev, 1); + rawpnp_exit_ext_func_mode(dev); } - -static void pnp_exit_ext_func_mode(device_t dev) -{ - unsigned int port = dev >> 8; - outb(0xaa, port); -} - -static void w83627thg_enable_serial(device_t dev, unsigned int iobase) -{ - pnp_enter_ext_func_mode(dev); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, iobase); - pnp_set_enable(dev, 1); - pnp_exit_ext_func_mode(dev); -} Modified: coreboot-v3/superio/winbond/w83627thg/superio.c =================================================================== --- coreboot-v3/superio/winbond/w83627thg/superio.c 2008-11-16 01:22:18 UTC (rev 1031) +++ coreboot-v3/superio/winbond/w83627thg/superio.c 2008-11-16 01:52:08 UTC (rev 1032) @@ -30,16 +30,16 @@ #include <keyboard.h> // #include <pc80/mc146818rtc.h> #include <statictree.h> -#include "w83627hf.h" +#include "w83627thg.h" static void w83627thg_enter_ext_func_mode(struct device * dev) { - outb(0x87, dev->path.u.pnp.port); - outb(0x87, dev->path.u.pnp.port); + outb(0x87, dev->path.pnp.port); + outb(0x87, dev->path.pnp.port); } static void w83627thg_exit_ext_func_mode(struct device * dev) { - outb(0xaa, dev->path.u.pnp.port); + outb(0xaa, dev->path.pnp.port); } static void w83627thg_init(struct device * dev) @@ -53,19 +53,19 @@ return; } conf = dev->device_configuration; - switch(dev->path.u.pnp.device) { + switch(dev->path.pnp.device) { case W83627THG_SP1: res0 = find_resource(dev, PNP_IDX_IO0); - init_uart8250(res0->base, &conf->com1); +// init_uart8250(res0->base, &conf->com1); break; case W83627THG_SP2: res0 = find_resource(dev, PNP_IDX_IO0); - init_uart8250(res0->base, &conf->com2); +// init_uart8250(res0->base, &conf->com2); break; case W83627THG_KBC: res0 = find_resource(dev, PNP_IDX_IO0); res1 = find_resource(dev, PNP_IDX_IO1); - init_pc_keyboard(res0->base, res1->base, &conf->keyboard); +// init_pc_keyboard(res0->base, res1->base, &conf->keyboard); break; } } @@ -92,31 +92,98 @@ } static void phase3_chip_setup_dev(struct device *dev); -static struct device_operations w83627thg_ops = { +struct device_operations w83627thg_ops = { .phase3_chip_setup_dev = phase3_chip_setup_dev, .phase3_enable = w83627thg_enable, .phase4_read_resources = pnp_read_resources, .phase4_set_resources = w83627thg_set_resources, .phase5_enable_resources = w83627thg_enable_resources, - .enable = , - .init = w83627thg_init, + .phase6_init = w83627thg_init, }; +/* TODO: this device is not at all filled out. Just copied from v2. */ static struct pnp_info pnp_dev_info[] = { - { &ops, W83627THG_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, }, - { &ops, W83627THG_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, }, - { &ops, W83627THG_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, - { &ops, W83627THG_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, + { &w83627thg_ops, W83627THG_FDC, 0, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, }, + { &w83627thg_ops, W83627THG_PP, 0, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, }, + { &w83627thg_ops, W83627THG_SP1, 0, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, + { &w83627thg_ops, W83627THG_SP2, 0, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, // No 4 { 0,}, - { &ops, W83627THG_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, { 0x7ff, 0x4}, }, - { &ops, W83627THG_GAME_MIDI_GPIO1, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x7ff, 0 }, {0x7fe, 4} }, - { &ops, W83627THG_GPIO2,}, - { &ops, W83627THG_GPIO3,}, - { &ops, W83627THG_ACPI, PNP_IRQ0, }, - { &ops, W83627THG_HWM, PNP_IO0 | PNP_IRQ0, { 0xff8, 0 } }, + { &w83627thg_ops, W83627THG_KBC, 0, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, { 0x7ff, 0x4}, }, + { &w83627thg_ops, W83627THG_GAME_MIDI_GPIO1, 0, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x7ff, 0 }, {0x7fe, 4} }, + { &w83627thg_ops, W83627THG_GPIO2,}, + { &w83627thg_ops, W83627THG_GPIO3,}, + { &w83627thg_ops, W83627THG_ACPI, 0, PNP_IRQ0, }, + { &w83627thg_ops, W83627THG_HWM, 0, PNP_IO0 | PNP_IRQ0, { 0xff8, 0 } }, }; static void phase3_chip_setup_dev(struct device *dev) { + /* Get dts values and populate pnp_dev_info. */ + const struct superio_winbond_w83627thg_dts_config * const conf = dev->device_configuration; + +#if 0 +These are not set up at all v2. Ignore for now. */ + /* Floppy */ + pnp_dev_info[W83627THG_FDC].enable = conf->floppyenable; + pnp_dev_info[W83627THG_FDC].io0.val = conf->floppyio; + pnp_dev_info[W83627THG_FDC].irq0.val = conf->floppyirq; + pnp_dev_info[W83627THG_FDC].drq0.val = conf->floppydrq; + + /* Parallel port */ + pnp_dev_info[W83627THG_PP].enable = conf->ppenable; + pnp_dev_info[W83627THG_PP].io0.val = conf->ppio; + pnp_dev_info[W83627THG_PP].irq0.val = conf->ppirq; + + /* Consumer IR */ + pnp_dev_info[W83627THG_CIR].enable = conf->cirenable; + + /* Game port */ + pnp_dev_info[W83627THG_GAME_MIDI_GPIO1].enable = conf->gameenable; + pnp_dev_info[W83627THG_GAME_MIDI_GPIO1].io0.val = conf->gameio; + pnp_dev_info[W83627THG_GAME_MIDI_GPIO1].io1.val = conf->gameio2; + pnp_dev_info[W83627THG_GAME_MIDI_GPIO1].irq0.val = conf->gameirq; + + /* GPIO2 */ + pnp_dev_info[W83627THG_GPIO2].enable = conf->gpio2enable; + + /* GPIO3 */ + pnp_dev_info[W83627THG_GPIO3].enable = conf->gpio3enable; + + /* ACPI */ + pnp_dev_info[W83627THG_ACPI].enable = conf->acpienable; + + /* Hardware Monitor */ + pnp_dev_info[W83627THG_HWM].enable = conf->hwmenable; + pnp_dev_info[W83627THG_HWM].io0.val = conf->hwmio; + pnp_dev_info[W83627THG_HWM].irq0.val = conf->hwmirq; + +#endif + + /* COM1 */ + pnp_dev_info[W83627THG_SP1].enable = conf->com1enable; + pnp_dev_info[W83627THG_SP1].io0.val = conf->com1io; + pnp_dev_info[W83627THG_SP1].irq0.val = conf->com1irq; + + /* COM2 */ + pnp_dev_info[W83627THG_SP2].enable = conf->com2enable; + pnp_dev_info[W83627THG_SP2].io0.val = conf->com2io; + pnp_dev_info[W83627THG_SP2].irq0.val = conf->com2irq; + + /* Keyboard */ + pnp_dev_info[W83627THG_KBC].enable = conf->kbenable; + pnp_dev_info[W83627THG_KBC].io0.val = conf->kbio; + pnp_dev_info[W83627THG_KBC].io1.val = conf->kbio2; + pnp_dev_info[W83627THG_KBC].irq0.val = conf->kbirq; + pnp_dev_info[W83627THG_KBC].irq1.val = conf->kbirq2; + + /* Initialize SuperIO for PNP children. */ + if (!dev->links) { + dev->links = 1; + dev->link[0].dev = dev; + dev->link[0].children = NULL; + dev->link[0].link = 0; + } + + /* Call init with updated tables to create children. */ pnp_enable_devices(dev, &w83627thg_ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); }

1 0

LPCflasher Project
by Joseph Smith 15 Nov '08

15 Nov '08

Hello, I think I am going to name this project the "LPCflasher". So I added up all the stuff I ordered to build it and it only came to $17.87. Yah, that's what I am talking about, a exellent bios development tool for under $20 dollars :-) -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org

6 22

r1031 - in coreboot-v3: mainboard/kontron/986lcd-m northbridge/intel/i945 southbridge/intel/i82801gx
by svn＠coreboot.org 15 Nov '08

15 Nov '08

Author: hailfinger Date: 2008-11-16 02:22:18 +0100 (Sun, 16 Nov 2008) New Revision: 1031 Modified: coreboot-v3/mainboard/kontron/986lcd-m/rtl8168.c coreboot-v3/northbridge/intel/i945/stage1.c coreboot-v3/southbridge/intel/i82801gx/smi.c coreboot-v3/southbridge/intel/i82801gx/smihandler.c Log: Move v2 printk_foo(...) syntax to v3 printk(BIOS_FOO, ...) syntax. Parts of this patch (southbridge/intel/i82801gx/smi.c) were Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> The rest is Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: coreboot-v3/mainboard/kontron/986lcd-m/rtl8168.c =================================================================== --- coreboot-v3/mainboard/kontron/986lcd-m/rtl8168.c 2008-11-15 16:17:12 UTC (rev 1030) +++ coreboot-v3/mainboard/kontron/986lcd-m/rtl8168.c 2008-11-16 01:22:18 UTC (rev 1031) @@ -32,7 +32,7 @@ static void nic_init(struct device *dev) { - printk_debug("Initializing RTL8168 Gigabit Ethernet\n"); + printk(BIOS_DEBUG, "Initializing RTL8168 Gigabit Ethernet\n"); // Nothing to do yet, but this has to be here to keep // coreboot from trying to execute an option ROM. } Modified: coreboot-v3/northbridge/intel/i945/stage1.c =================================================================== --- coreboot-v3/northbridge/intel/i945/stage1.c 2008-11-15 16:17:12 UTC (rev 1030) +++ coreboot-v3/northbridge/intel/i945/stage1.c 2008-11-16 01:22:18 UTC (rev 1031) @@ -101,8 +101,8 @@ /* As of now, we don't have all the A0 workarounds implemented */ if (i945_silicon_revision() == 0) - printk_info - ("Warning: i945 silicon revision A0 might not work correctly.\n"); + printk(BIOS_INFO, + "Warning: i945 silicon revision A0 might not work correctly.\n"); /* Setting up Southbridge. In the northbridge code. */ printk(BIOS_DEBUG, "Setting up static southbridge registers..."); @@ -432,8 +432,8 @@ if (i945_silicon_revision() == 1 && ((MCHBAR8(0xe08) & (1 << 5)) == 1)) { if ((MCHBAR32(0x214) & 0xf) != 0x3) { - printk_info - ("DMI link requires A1 stepping workaround. Rebooting.\n"); + printk(BIOS_INFO, + "DMI link requires A1 stepping workaround. Rebooting.\n"); reg32 = MCHBAR32(MMARB1); reg32 &= 0xfffffff8; reg32 |= 3; Modified: coreboot-v3/southbridge/intel/i82801gx/smi.c =================================================================== --- coreboot-v3/southbridge/intel/i82801gx/smi.c 2008-11-15 16:17:12 UTC (rev 1030) +++ coreboot-v3/southbridge/intel/i82801gx/smi.c 2008-11-16 01:22:18 UTC (rev 1031) @@ -100,16 +100,16 @@ static void dump_pm1_status(u16 pm1_sts) { - printk_debug("PM1_STS: "); - if (pm1_sts & (1 << 15)) printk_debug("WAK "); - if (pm1_sts & (1 << 14)) printk_debug("PCIEXPWAK "); - if (pm1_sts & (1 << 11)) printk_debug("PRBTNOR "); - if (pm1_sts & (1 << 10)) printk_debug("RTC "); - if (pm1_sts & (1 << 8)) printk_debug("PWRBTN "); - if (pm1_sts & (1 << 5)) printk_debug("GBL "); - if (pm1_sts & (1 << 4)) printk_debug("BM "); - if (pm1_sts & (1 << 0)) printk_debug("TMROF "); - printk_debug("\n"); + printk(BIOS_DEBUG, "PM1_STS: "); + if (pm1_sts & (1 << 15)) printk(BIOS_DEBUG, "WAK "); + if (pm1_sts & (1 << 14)) printk(BIOS_DEBUG, "PCIEXPWAK "); + if (pm1_sts & (1 << 11)) printk(BIOS_DEBUG, "PRBTNOR "); + if (pm1_sts & (1 << 10)) printk(BIOS_DEBUG, "RTC "); + if (pm1_sts & (1 << 8)) printk(BIOS_DEBUG, "PWRBTN "); + if (pm1_sts & (1 << 5)) printk(BIOS_DEBUG, "GBL "); + if (pm1_sts & (1 << 4)) printk(BIOS_DEBUG, "BM "); + if (pm1_sts & (1 << 0)) printk(BIOS_DEBUG, "TMROF "); + printk(BIOS_DEBUG, "\n"); } /** @@ -129,28 +129,28 @@ static void dump_smi_status(u32 smi_sts) { - printk_debug("SMI_STS: "); - if (smi_sts & (1 << 26)) printk_debug("SPI "); - if (smi_sts & (1 << 25)) printk_debug("EL_SMI "); - if (smi_sts & (1 << 21)) printk_debug("MONITOR "); - if (smi_sts & (1 << 20)) printk_debug("PCI_EXP_SMI "); - if (smi_sts & (1 << 18)) printk_debug("INTEL_USB2 "); - if (smi_sts & (1 << 17)) printk_debug("LEGACY_USB2 "); - if (smi_sts & (1 << 16)) printk_debug("SMBUS_SMI "); - if (smi_sts & (1 << 15)) printk_debug("SERIRQ_SMI "); - if (smi_sts & (1 << 14)) printk_debug("PERIODIC "); - if (smi_sts & (1 << 13)) printk_debug("TCO "); - if (smi_sts & (1 << 12)) printk_debug("DEVMON "); - if (smi_sts & (1 << 11)) printk_debug("MCSMI "); - if (smi_sts & (1 << 10)) printk_debug("GPI "); - if (smi_sts & (1 << 9)) printk_debug("GPE0 "); - if (smi_sts & (1 << 8)) printk_debug("PM1 "); - if (smi_sts & (1 << 6)) printk_debug("SWSMI_TMR "); - if (smi_sts & (1 << 5)) printk_debug("APM "); - if (smi_sts & (1 << 4)) printk_debug("SLP_SMI "); - if (smi_sts & (1 << 3)) printk_debug("LEGACY_USB "); - if (smi_sts & (1 << 2)) printk_debug("BIOS "); - printk_debug("\n"); + printk(BIOS_DEBUG, "SMI_STS: "); + if (smi_sts & (1 << 26)) printk(BIOS_DEBUG, "SPI "); + if (smi_sts & (1 << 25)) printk(BIOS_DEBUG, "EL_SMI "); + if (smi_sts & (1 << 21)) printk(BIOS_DEBUG, "MONITOR "); + if (smi_sts & (1 << 20)) printk(BIOS_DEBUG, "PCI_EXP_SMI "); + if (smi_sts & (1 << 18)) printk(BIOS_DEBUG, "INTEL_USB2 "); + if (smi_sts & (1 << 17)) printk(BIOS_DEBUG, "LEGACY_USB2 "); + if (smi_sts & (1 << 16)) printk(BIOS_DEBUG, "SMBUS_SMI "); + if (smi_sts & (1 << 15)) printk(BIOS_DEBUG, "SERIRQ_SMI "); + if (smi_sts & (1 << 14)) printk(BIOS_DEBUG, "PERIODIC "); + if (smi_sts & (1 << 13)) printk(BIOS_DEBUG, "TCO "); + if (smi_sts & (1 << 12)) printk(BIOS_DEBUG, "DEVMON "); + if (smi_sts & (1 << 11)) printk(BIOS_DEBUG, "MCSMI "); + if (smi_sts & (1 << 10)) printk(BIOS_DEBUG, "GPI "); + if (smi_sts & (1 << 9)) printk(BIOS_DEBUG, "GPE0 "); + if (smi_sts & (1 << 8)) printk(BIOS_DEBUG, "PM1 "); + if (smi_sts & (1 << 6)) printk(BIOS_DEBUG, "SWSMI_TMR "); + if (smi_sts & (1 << 5)) printk(BIOS_DEBUG, "APM "); + if (smi_sts & (1 << 4)) printk(BIOS_DEBUG, "SLP_SMI "); + if (smi_sts & (1 << 3)) printk(BIOS_DEBUG, "LEGACY_USB "); + if (smi_sts & (1 << 2)) printk(BIOS_DEBUG, "BIOS "); + printk(BIOS_DEBUG, "\n"); } @@ -172,25 +172,25 @@ static void dump_gpe0_status(u32 gpe0_sts) { int i; - printk_debug("GPE0_STS: "); + printk(BIOS_DEBUG, "GPE0_STS: "); for (i=31; i<= 16; i--) { - if (gpe0_sts & (1 << i)) printk_debug("GPIO%d ", (i-16)); + if (gpe0_sts & (1 << i)) printk(BIOS_DEBUG, "GPIO%d ", (i-16)); } - if (gpe0_sts & (1 << 14)) printk_debug("USB4 "); - if (gpe0_sts & (1 << 13)) printk_debug("PME_B0 "); - if (gpe0_sts & (1 << 12)) printk_debug("USB3 "); - if (gpe0_sts & (1 << 11)) printk_debug("PME "); - if (gpe0_sts & (1 << 10)) printk_debug("EL_SCI/BATLOW "); - if (gpe0_sts & (1 << 9)) printk_debug("PCI_EXP "); - if (gpe0_sts & (1 << 8)) printk_debug("RI "); - if (gpe0_sts & (1 << 7)) printk_debug("SMB_WAK "); - if (gpe0_sts & (1 << 6)) printk_debug("TCO_SCI "); - if (gpe0_sts & (1 << 5)) printk_debug("AC97 "); - if (gpe0_sts & (1 << 4)) printk_debug("USB2 "); - if (gpe0_sts & (1 << 3)) printk_debug("USB1 "); - if (gpe0_sts & (1 << 2)) printk_debug("HOT_PLUG "); - if (gpe0_sts & (1 << 0)) printk_debug("THRM "); - printk_debug("\n"); + if (gpe0_sts & (1 << 14)) printk(BIOS_DEBUG, "USB4 "); + if (gpe0_sts & (1 << 13)) printk(BIOS_DEBUG, "PME_B0 "); + if (gpe0_sts & (1 << 12)) printk(BIOS_DEBUG, "USB3 "); + if (gpe0_sts & (1 << 11)) printk(BIOS_DEBUG, "PME "); + if (gpe0_sts & (1 << 10)) printk(BIOS_DEBUG, "EL_SCI/BATLOW "); + if (gpe0_sts & (1 << 9)) printk(BIOS_DEBUG, "PCI_EXP "); + if (gpe0_sts & (1 << 8)) printk(BIOS_DEBUG, "RI "); + if (gpe0_sts & (1 << 7)) printk(BIOS_DEBUG, "SMB_WAK "); + if (gpe0_sts & (1 << 6)) printk(BIOS_DEBUG, "TCO_SCI "); + if (gpe0_sts & (1 << 5)) printk(BIOS_DEBUG, "AC97 "); + if (gpe0_sts & (1 << 4)) printk(BIOS_DEBUG, "USB2 "); + if (gpe0_sts & (1 << 3)) printk(BIOS_DEBUG, "USB1 "); + if (gpe0_sts & (1 << 2)) printk(BIOS_DEBUG, "HOT_PLUG "); + if (gpe0_sts & (1 << 0)) printk(BIOS_DEBUG, "THRM "); + printk(BIOS_DEBUG, "\n"); } /** @@ -214,21 +214,21 @@ static void dump_tco_status(u32 tco_sts) { - printk_debug("TCO_STS: "); - if (tco_sts & (1 << 20)) printk_debug("SMLINK_SLV "); - if (tco_sts & (1 << 18)) printk_debug("BOOT "); - if (tco_sts & (1 << 17)) printk_debug("SECOND_TO "); - if (tco_sts & (1 << 16)) printk_debug("INTRD_DET "); - if (tco_sts & (1 << 12)) printk_debug("DMISERR "); - if (tco_sts & (1 << 10)) printk_debug("DMISMI "); - if (tco_sts & (1 << 9)) printk_debug("DMISCI "); - if (tco_sts & (1 << 8)) printk_debug("BIOSWR "); - if (tco_sts & (1 << 7)) printk_debug("NEWCENTURY "); - if (tco_sts & (1 << 3)) printk_debug("TIMEOUT "); - if (tco_sts & (1 << 2)) printk_debug("TCO_INT "); - if (tco_sts & (1 << 1)) printk_debug("SW_TCO "); - if (tco_sts & (1 << 0)) printk_debug("NMI2SMI "); - printk_debug("\n"); + printk(BIOS_DEBUG, "TCO_STS: "); + if (tco_sts & (1 << 20)) printk(BIOS_DEBUG, "SMLINK_SLV "); + if (tco_sts & (1 << 18)) printk(BIOS_DEBUG, "BOOT "); + if (tco_sts & (1 << 17)) printk(BIOS_DEBUG, "SECOND_TO "); + if (tco_sts & (1 << 16)) printk(BIOS_DEBUG, "INTRD_DET "); + if (tco_sts & (1 << 12)) printk(BIOS_DEBUG, "DMISERR "); + if (tco_sts & (1 << 10)) printk(BIOS_DEBUG, "DMISMI "); + if (tco_sts & (1 << 9)) printk(BIOS_DEBUG, "DMISCI "); + if (tco_sts & (1 << 8)) printk(BIOS_DEBUG, "BIOSWR "); + if (tco_sts & (1 << 7)) printk(BIOS_DEBUG, "NEWCENTURY "); + if (tco_sts & (1 << 3)) printk(BIOS_DEBUG, "TIMEOUT "); + if (tco_sts & (1 << 2)) printk(BIOS_DEBUG, "TCO_INT "); + if (tco_sts & (1 << 1)) printk(BIOS_DEBUG, "SW_TCO "); + if (tco_sts & (1 << 0)) printk(BIOS_DEBUG, "NMI2SMI "); + printk(BIOS_DEBUG, "\n"); } @@ -251,14 +251,14 @@ { u32 smi_en; - printk_debug("Initializing SMM handler..."); + printk(BIOS_DEBUG, "Initializing SMM handler..."); pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f, 0)), 0x40) & 0xfffc; - printk_spew(" ... pmbase = 0x%04x\n", pmbase); + printk(BIOS_SPEW, " ... pmbase = 0x%04x\n", pmbase); smi_en = inl(pmbase + SMI_EN); if (smi_en & APMC_EN) { - printk_info("SMI# handler already enabled?\n"); + printk(BIOS_INFO, "SMI# handler already enabled?\n"); return; } @@ -266,7 +266,7 @@ memcpy((void *)0x38000, &smm_relocation_start, &smm_relocation_end - &smm_relocation_start); - printk_debug("\n"); + printk(BIOS_DEBUG, "\n"); dump_smi_status(reset_smi_status()); dump_pm1_status(reset_pm1_status()); dump_gpe0_status(reset_gpe0_status()); @@ -297,7 +297,7 @@ */ /* raise an SMI interrupt */ - printk_spew(" ... raise SMI#\n"); + printk(BIOS_SPEW, " ... raise SMI#\n"); outb(0x00, 0xb2); } @@ -328,7 +328,7 @@ * After running this function, only a full reset can * make the SMM registers writable again. */ - printk_debug("Locking SMM.\n"); + printk(BIOS_DEBUG, "Locking SMM.\n"); pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), SMRAM, D_LCK | G_SMRAME | C_BASE_SEG); } Modified: coreboot-v3/southbridge/intel/i82801gx/smihandler.c =================================================================== --- coreboot-v3/southbridge/intel/i82801gx/smihandler.c 2008-11-15 16:17:12 UTC (rev 1030) +++ coreboot-v3/southbridge/intel/i82801gx/smihandler.c 2008-11-16 01:22:18 UTC (rev 1031) @@ -140,16 +140,16 @@ static void dump_pm1_status(u16 pm1_sts) { - printk_debug("PM1_STS: "); - if (pm1_sts & (1 << 15)) printk_debug("WAK "); - if (pm1_sts & (1 << 14)) printk_debug("PCIEXPWAK "); - if (pm1_sts & (1 << 11)) printk_debug("PRBTNOR "); - if (pm1_sts & (1 << 10)) printk_debug("RTC "); - if (pm1_sts & (1 << 8)) printk_debug("PWRBTN "); - if (pm1_sts & (1 << 5)) printk_debug("GBL "); - if (pm1_sts & (1 << 4)) printk_debug("BM "); - if (pm1_sts & (1 << 0)) printk_debug("TMROF "); - printk_debug("\n"); + printk(BIOS_DEBUG, "PM1_STS: "); + if (pm1_sts & (1 << 15)) printk(BIOS_DEBUG, "WAK "); + if (pm1_sts & (1 << 14)) printk(BIOS_DEBUG, "PCIEXPWAK "); + if (pm1_sts & (1 << 11)) printk(BIOS_DEBUG, "PRBTNOR "); + if (pm1_sts & (1 << 10)) printk(BIOS_DEBUG, "RTC "); + if (pm1_sts & (1 << 8)) printk(BIOS_DEBUG, "PWRBTN "); + if (pm1_sts & (1 << 5)) printk(BIOS_DEBUG, "GBL "); + if (pm1_sts & (1 << 4)) printk(BIOS_DEBUG, "BM "); + if (pm1_sts & (1 << 0)) printk(BIOS_DEBUG, "TMROF "); + printk(BIOS_DEBUG, "\n"); } /** @@ -169,28 +169,28 @@ static void dump_smi_status(u32 smi_sts) { - printk_debug("SMI_STS: "); - if (smi_sts & (1 << 26)) printk_debug("SPI "); - if (smi_sts & (1 << 25)) printk_debug("EL_SMI "); - if (smi_sts & (1 << 21)) printk_debug("MONITOR "); - if (smi_sts & (1 << 20)) printk_debug("PCI_EXP_SMI "); - if (smi_sts & (1 << 18)) printk_debug("INTEL_USB2 "); - if (smi_sts & (1 << 17)) printk_debug("LEGACY_USB2 "); - if (smi_sts & (1 << 16)) printk_debug("SMBUS_SMI "); - if (smi_sts & (1 << 15)) printk_debug("SERIRQ_SMI "); - if (smi_sts & (1 << 14)) printk_debug("PERIODIC "); - if (smi_sts & (1 << 13)) printk_debug("TCO "); - if (smi_sts & (1 << 12)) printk_debug("DEVMON "); - if (smi_sts & (1 << 11)) printk_debug("MCSMI "); - if (smi_sts & (1 << 10)) printk_debug("GPI "); - if (smi_sts & (1 << 9)) printk_debug("GPE0 "); - if (smi_sts & (1 << 8)) printk_debug("PM1 "); - if (smi_sts & (1 << 6)) printk_debug("SWSMI_TMR "); - if (smi_sts & (1 << 5)) printk_debug("APM "); - if (smi_sts & (1 << 4)) printk_debug("SLP_SMI "); - if (smi_sts & (1 << 3)) printk_debug("LEGACY_USB "); - if (smi_sts & (1 << 2)) printk_debug("BIOS "); - printk_debug("\n"); + printk(BIOS_DEBUG, "SMI_STS: "); + if (smi_sts & (1 << 26)) printk(BIOS_DEBUG, "SPI "); + if (smi_sts & (1 << 25)) printk(BIOS_DEBUG, "EL_SMI "); + if (smi_sts & (1 << 21)) printk(BIOS_DEBUG, "MONITOR "); + if (smi_sts & (1 << 20)) printk(BIOS_DEBUG, "PCI_EXP_SMI "); + if (smi_sts & (1 << 18)) printk(BIOS_DEBUG, "INTEL_USB2 "); + if (smi_sts & (1 << 17)) printk(BIOS_DEBUG, "LEGACY_USB2 "); + if (smi_sts & (1 << 16)) printk(BIOS_DEBUG, "SMBUS_SMI "); + if (smi_sts & (1 << 15)) printk(BIOS_DEBUG, "SERIRQ_SMI "); + if (smi_sts & (1 << 14)) printk(BIOS_DEBUG, "PERIODIC "); + if (smi_sts & (1 << 13)) printk(BIOS_DEBUG, "TCO "); + if (smi_sts & (1 << 12)) printk(BIOS_DEBUG, "DEVMON "); + if (smi_sts & (1 << 11)) printk(BIOS_DEBUG, "MCSMI "); + if (smi_sts & (1 << 10)) printk(BIOS_DEBUG, "GPI "); + if (smi_sts & (1 << 9)) printk(BIOS_DEBUG, "GPE0 "); + if (smi_sts & (1 << 8)) printk(BIOS_DEBUG, "PM1 "); + if (smi_sts & (1 << 6)) printk(BIOS_DEBUG, "SWSMI_TMR "); + if (smi_sts & (1 << 5)) printk(BIOS_DEBUG, "APM "); + if (smi_sts & (1 << 4)) printk(BIOS_DEBUG, "SLP_SMI "); + if (smi_sts & (1 << 3)) printk(BIOS_DEBUG, "LEGACY_USB "); + if (smi_sts & (1 << 2)) printk(BIOS_DEBUG, "BIOS "); + printk(BIOS_DEBUG, "\n"); } @@ -212,25 +212,25 @@ static void dump_gpe0_status(u32 gpe0_sts) { int i; - printk_debug("GPE0_STS: "); + printk(BIOS_DEBUG, "GPE0_STS: "); for (i=31; i<= 16; i--) { - if (gpe0_sts & (1 << i)) printk_debug("GPIO%d ", (i-16)); + if (gpe0_sts & (1 << i)) printk(BIOS_DEBUG, "GPIO%d ", (i-16)); } - if (gpe0_sts & (1 << 14)) printk_debug("USB4 "); - if (gpe0_sts & (1 << 13)) printk_debug("PME_B0 "); - if (gpe0_sts & (1 << 12)) printk_debug("USB3 "); - if (gpe0_sts & (1 << 11)) printk_debug("PME "); - if (gpe0_sts & (1 << 10)) printk_debug("EL_SCI/BATLOW "); - if (gpe0_sts & (1 << 9)) printk_debug("PCI_EXP "); - if (gpe0_sts & (1 << 8)) printk_debug("RI "); - if (gpe0_sts & (1 << 7)) printk_debug("SMB_WAK "); - if (gpe0_sts & (1 << 6)) printk_debug("TCO_SCI "); - if (gpe0_sts & (1 << 5)) printk_debug("AC97 "); - if (gpe0_sts & (1 << 4)) printk_debug("USB2 "); - if (gpe0_sts & (1 << 3)) printk_debug("USB1 "); - if (gpe0_sts & (1 << 2)) printk_debug("HOT_PLUG "); - if (gpe0_sts & (1 << 0)) printk_debug("THRM "); - printk_debug("\n"); + if (gpe0_sts & (1 << 14)) printk(BIOS_DEBUG, "USB4 "); + if (gpe0_sts & (1 << 13)) printk(BIOS_DEBUG, "PME_B0 "); + if (gpe0_sts & (1 << 12)) printk(BIOS_DEBUG, "USB3 "); + if (gpe0_sts & (1 << 11)) printk(BIOS_DEBUG, "PME "); + if (gpe0_sts & (1 << 10)) printk(BIOS_DEBUG, "EL_SCI/BATLOW "); + if (gpe0_sts & (1 << 9)) printk(BIOS_DEBUG, "PCI_EXP "); + if (gpe0_sts & (1 << 8)) printk(BIOS_DEBUG, "RI "); + if (gpe0_sts & (1 << 7)) printk(BIOS_DEBUG, "SMB_WAK "); + if (gpe0_sts & (1 << 6)) printk(BIOS_DEBUG, "TCO_SCI "); + if (gpe0_sts & (1 << 5)) printk(BIOS_DEBUG, "AC97 "); + if (gpe0_sts & (1 << 4)) printk(BIOS_DEBUG, "USB2 "); + if (gpe0_sts & (1 << 3)) printk(BIOS_DEBUG, "USB1 "); + if (gpe0_sts & (1 << 2)) printk(BIOS_DEBUG, "HOT_PLUG "); + if (gpe0_sts & (1 << 0)) printk(BIOS_DEBUG, "THRM "); + printk(BIOS_DEBUG, "\n"); } @@ -255,21 +255,21 @@ static void dump_tco_status(u32 tco_sts) { - printk_debug("TCO_STS: "); - if (tco_sts & (1 << 20)) printk_debug("SMLINK_SLV "); - if (tco_sts & (1 << 18)) printk_debug("BOOT "); - if (tco_sts & (1 << 17)) printk_debug("SECOND_TO "); - if (tco_sts & (1 << 16)) printk_debug("INTRD_DET "); - if (tco_sts & (1 << 12)) printk_debug("DMISERR "); - if (tco_sts & (1 << 10)) printk_debug("DMISMI "); - if (tco_sts & (1 << 9)) printk_debug("DMISCI "); - if (tco_sts & (1 << 8)) printk_debug("BIOSWR "); - if (tco_sts & (1 << 7)) printk_debug("NEWCENTURY "); - if (tco_sts & (1 << 3)) printk_debug("TIMEOUT "); - if (tco_sts & (1 << 2)) printk_debug("TCO_INT "); - if (tco_sts & (1 << 1)) printk_debug("SW_TCO "); - if (tco_sts & (1 << 0)) printk_debug("NMI2SMI "); - printk_debug("\n"); + printk(BIOS_DEBUG, "TCO_STS: "); + if (tco_sts & (1 << 20)) printk(BIOS_DEBUG, "SMLINK_SLV "); + if (tco_sts & (1 << 18)) printk(BIOS_DEBUG, "BOOT "); + if (tco_sts & (1 << 17)) printk(BIOS_DEBUG, "SECOND_TO "); + if (tco_sts & (1 << 16)) printk(BIOS_DEBUG, "INTRD_DET "); + if (tco_sts & (1 << 12)) printk(BIOS_DEBUG, "DMISERR "); + if (tco_sts & (1 << 10)) printk(BIOS_DEBUG, "DMISMI "); + if (tco_sts & (1 << 9)) printk(BIOS_DEBUG, "DMISCI "); + if (tco_sts & (1 << 8)) printk(BIOS_DEBUG, "BIOSWR "); + if (tco_sts & (1 << 7)) printk(BIOS_DEBUG, "NEWCENTURY "); + if (tco_sts & (1 << 3)) printk(BIOS_DEBUG, "TIMEOUT "); + if (tco_sts & (1 << 2)) printk(BIOS_DEBUG, "TCO_INT "); + if (tco_sts & (1 << 1)) printk(BIOS_DEBUG, "SW_TCO "); + if (tco_sts & (1 << 0)) printk(BIOS_DEBUG, "NMI2SMI "); + printk(BIOS_DEBUG, "\n"); } @@ -344,21 +344,21 @@ u8 reg8; global_nvs_t *gnvs = (global_nvs_t *)0xc00; - printk_debug("SMI function trap 0x%x: ", smif); + printk(BIOS_DEBUG, "SMI function trap 0x%x: ", smif); switch (smif) { case 0x32: - printk_debug("OS Init\n"); + printk(BIOS_DEBUG, "OS Init\n"); break; case 0xd6: - printk_debug("Get Brightness\n"); + printk(BIOS_DEBUG, "Get Brightness\n"); outb(0x17, 0x66); reg8 = inb(0x62); gnvs->brtl = reg8; break; default: - printk_debug("Unknown function\n"); + printk(BIOS_DEBUG, "Unknown function\n"); break; } @@ -410,7 +410,7 @@ console_loglevel = 1; #endif - printk_debug("\nSMI# #%d\n", node); + printk(BIOS_DEBUG, "\nSMI# #%d\n", node); switch (smm_revision) { case 0x00030007: @@ -424,8 +424,8 @@ (0xa8000 + 0x7d00 - (node * 0x400)); break; default: - printk_debug("smm_revision: 0x%08x\n", smm_revision); - printk_debug("SMI# not supported on your CPU\n"); + printk(BIOS_DEBUG, "smm_revision: 0x%08x\n", smm_revision); + printk(BIOS_DEBUG, "SMI# not supported on your CPU\n"); /* Don't release lock, so no further SMI will happen, * if we don't handle it anyways. */ @@ -433,7 +433,7 @@ } pmbase = pcie_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc; - printk_spew("SMI#: pmbase = 0x%04x\n", pmbase); + printk(BIOS_SPEW, "SMI#: pmbase = 0x%04x\n", pmbase); /* We need to clear the SMI status registers, or we won't see what's * happening in the following calls. @@ -451,7 +451,7 @@ /* Comment in for some useful debug */ for (i=0; i<4; i++) { if (reg32 & (1 << i)) { - printk_debug(" io trap #%d\n", i); + printk(BIOS_DEBUG, " io trap #%d\n", i); } } #endif @@ -460,16 +460,16 @@ reg32 = RCBA32(0x1e10); if ((reg32 & 0xfffc) != 0x808) { - printk_debug(" trapped io address = 0x%x\n", reg32 & 0xfffc); - printk_debug(" AHBE = %x\n", (reg32 >> 16) & 0xf); - printk_debug(" read/write: %s\n", (reg32 & (1 << 24)) ? "read" : + printk(BIOS_DEBUG, " trapped io address = 0x%x\n", reg32 & 0xfffc); + printk(BIOS_DEBUG, " AHBE = %x\n", (reg32 >> 16) & 0xf); + printk(BIOS_DEBUG, " read/write: %s\n", (reg32 & (1 << 24)) ? "read" : "write"); } if (!(reg32 & (1 << 24))) { /* Write Cycle */ reg32 = RCBA32(0x1e18); - printk_debug(" iotrap written data = 0x%08x\n", reg32); + printk(BIOS_DEBUG, " iotrap written data = 0x%08x\n", reg32); } @@ -497,7 +497,7 @@ * resolute answer would be to power down the * box. */ - printk_debug("Switching back to RO\n"); + printk(BIOS_DEBUG, "Switching back to RO\n"); pcie_write_config32(PCI_DEV(0, 0x1f, 0), 0xdc, (bios_cntl & ~1)); } /* No else for now? */ } @@ -522,13 +522,13 @@ pmctrl = inw(pmbase + 0x04); pmctrl |= (1 << 0); outw(pmctrl, pmbase + 0x04); - printk_debug("SMI#: ACPI disabled.\n"); + printk(BIOS_DEBUG, "SMI#: ACPI disabled.\n"); break; case ACPI_ENABLE: pmctrl = inw(pmbase + 0x04); pmctrl &= ~(1 << 0); outw(pmctrl, pmbase + 0x04); - printk_debug("SMI#: ACPI enabled.\n"); + printk(BIOS_DEBUG, "SMI#: ACPI enabled.\n"); break; } } @@ -536,11 +536,11 @@ if (smi_sts & (1 << 4)) { // SLP_SMI u32 reg32; reg32 = inl(pmbase + 0x04); - printk_debug("SMI#: SLP = 0x%08x\n"); - printk_debug("SMI#: Powering off.\n"); + printk(BIOS_DEBUG, "SMI#: SLP = 0x%08x\n"); + printk(BIOS_DEBUG, "SMI#: Powering off.\n"); outl((6 << 10), pmbase + 0x04); outl((1 << 13) | (6 << 10), pmbase + 0x04); - printk_debug("....\n"); + printk(BIOS_DEBUG, "....\n"); }

1 0

Re: [coreboot] LPCflasher Project
by steve＠fl-eng.com 15 Nov '08

15 Nov '08

Hi You could diode isolate the vin to a buck boost to isolate it's input and you can diode isolate its output to create a pseduo isolated regulator that would prevent reverse bias from being a big problem. Typically, the output stage of a buck/buck-boost regulator is an inductor- capacitor. The voltage on the cap is the regulated rippled/filtered output. Then there usually is a resistor feedback network right at the capacitor to feedback the cap voltage to the regulator IC and close the loop; so you can actually regulate the output. You can usually put a diode after the inductor and before the capacitor to pseudo isolate the output. The feedback network should still be located at the capacitor though. This way, the regulator will achieve your desired output voltage (that you set through the resistor divider network) regardless of the diode drops. Steve Spano > > From: Joseph Smith <joe(a)settoplinux.org> > Date: 2008/11/15 Sat PM 04:33:24 EST > To: steve(a)fl-eng.com > CC: Peter Stuge <peter(a)stuge.se>, coreboot <coreboot(a)coreboot.org> > Subject: Re: [coreboot] LPCflasher Project > > > > > On Sat, 15 Nov 2008 16:09:58 -0500, <steve(a)fl-eng.com> wrote: > > Host USB ports are supposed to use a MosFET with internal current sense > for > > power protection. The FET signals the O/S when its current threshold is > > being > > exceeded and then the O/S suspends the port and removes power. > > > > If you apply +5v INTO the host port, you can create current spikes across > > the > > FET which would damage the FET, trip the O/S into thinking a power fault > > has > > occured and shut down the port. Even in this state, the reverse bias > diode > > in > > the FET will continue to allow the external voltage to be fed into the > the > > motherboard. > > > > The FET/Motherboard external voltage will keep fighting each other as the > > ripple in the motherboard +5v and your external +5v criss-cross each > > other. > > > > This would probably be bad.... > > > That's what I was thinking, thanks. > > > > You can diode OR all of your mother board/external supplies together and > > then run them into a buck/boost regulator. THat way the buck/boost will > > maintain a local +5v supply at your board "regadless" of external > > voltages. > > > > Thoughts? > > > Ah, so I can use a Buck-Boost regulator to compensate for the diode voltage > drop. That makes sense. In that case I could just cut out the simple LED > circut, use the Buck-Boost regulator to boost the 5V to 8V and put a LED > inline as my diode and the output should be a solid one way 5V power line > right? > > -- > Thanks, > Joseph Smith > Set-Top-Linux > www.settoplinux.org >

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Re: [coreboot] LPCflasher Project
by steve＠fl-eng.com 15 Nov '08

15 Nov '08

Host USB ports are supposed to use a MosFET with internal current sense for power protection. The FET signals the O/S when its current threshold is being exceeded and then the O/S suspends the port and removes power. If you apply +5v INTO the host port, you can create current spikes across the FET which would damage the FET, trip the O/S into thinking a power fault has occured and shut down the port. Even in this state, the reverse bias diode in the FET will continue to allow the external voltage to be fed into the the motherboard. The FET/Motherboard external voltage will keep fighting each other as the ripple in the motherboard +5v and your external +5v criss-cross each other. This would probably be bad.... You can diode OR all of your mother board/external supplies together and then run them into a buck/boost regulator. THat way the buck/boost will maintain a local +5v supply at your board "regadless" of external voltages. Thoughts? Steve Spano FLE > > From: Joseph Smith <joe(a)settoplinux.org> > Date: 2008/11/15 Sat PM 03:53:43 EST > To: Peter Stuge <peter(a)stuge.se> > CC: coreboot <coreboot(a)coreboot.org> > Subject: Re: [coreboot] LPCflasher Project > > > > On Sat, 15 Nov 2008 21:26:05 +0100, Peter Stuge <peter(a)stuge.se> wrote: > > Joseph Smith wrote: > >> Anyone know if USB ports have power feedback protection. > > > > All the details are in the USB spec. IIRC electrical is a separate > > chapter. > > > > > >> What I mean by that is if I use the LPCflasher as a inline flasher > >> with a PLCC32 socket plug, > > > > I don't understand this. Do you mean a socket or a plug? > > > Both, a socket on top of a plug that is also connected to the LPCflasher. > If I power on the motherboard it is going to supply voltage back to the > LPCflasher, right? > > > >> flash the chip > > > > Flash which chip? > > > Any LPC or FWH. > > > >> and then power up the motherboard, I don't want the VCC's from the > >> motherboard to short out the flasher and or the USB port from the > >> host PC. > > > > Make sure GND is connected across and you should be OK. > > > Yup. > > > >> The 3.3V regulator I am using has a internal diode so I am not so > >> worried about that. I am just worried about the power source 5V > >> USB. I could always use a Schottky diode that will only drop the > >> voltage by .6V, but I don't know if 4.4V will suffice??? > > > > Suffice for what? Look at the documentation for the regulator you're > > using to see what input voltage it needs. > > > > > I wasn't really ready to release this yet, because the power part is still > a work in progress but it will be the easiest way to explain this. See the > diode I have above the regulator? I put that there so power is not flowing > back to the USB port of the PC doing the flashing when you power on the > motherboard that just got flashed. My question is if I take out that diode > and you power on the motherboard that just got flashed is power going to > flow back into the USB port and damage it? And if I leave the diode it is > going to drop the 5V by approx. half a volt. Will I still be able to flash > 5V chips at 4.5V? Does that make sense? > > -- > Thanks, > Joseph Smith > Set-Top-Linux > www.settoplinux.org > -- coreboot mailing list: coreboot(a)coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

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coreboot November 2008