coreboot October 2008

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608 discussions

superiotool winbond identification issue (W83627HF vs W83977EF)
by Andriy Gapon 28 Oct '08

28 Oct '08

I see the following code in winbond.c: ... {0x52f, "W83977EF/EG", { ... /* ID only */ {0x52, "W83627HF/F/HG/G", { {NOLDN, NULL, ... if (devid == 0x52 || devid == 0x68 || devid == 0x88) id = devid; /* ID only */ ... According to my understanding this means that W83627HF chip entry claims ID 0x52 regardless of revision. But, on the other hand, I have W83977EF-AW in my system and according to its specification it has ID 0x52 and revision 0xFx. My particular chip has 0x52 and 0xF4 for instance. And with current code its entry (0x52f) is not reachable. Looking at specification of W83627HF that I found I see that it actually has ID of 0x52 and revision 0x1x. So while W83627 family of chips may cover a range of revisions for ID 0x52, it doesn't cover them all. And there are some significant differences in registers. For example W83977EF doesn't have logical devices 6, 9 and 0xb. References: 1. http://www.datasheet4u.com/html/W/8/3/W83977EF-AW_Winbond.pdf.html Section 10.0 2. http://www.datasheet4u.com/html/W/8/3/W83627HF_Winbond.pdf.html Section 13.1 -- Andriy Gapon

2 4

r3697 build service
by coreboot information 28 Oct '08

28 Oct '08

Dear coreboot readers! This is the automated build check service of coreboot. The developer "uwe" checked in revision 3697 to the coreboot source repository and caused the following changes: Change Log: Mark Winbond W39V040FA" (512 KB) as fully supported, tested by Martin Stecklum <stecky(a)gmx.net> (both write and erase). The tests were done on an MSI MS-7065 board, so that's supported now too (wiki page will be updated). Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Build Log: Compilation of amd:serengeti_cheetah_fam10 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3697&device=serengeti_chee… Compilation of msi:ms9185 has been fixed If something broke during this checkin please be a pain in uwe's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

1 0

r3696 build service
by coreboot information 28 Oct '08

28 Oct '08

Dear coreboot readers! This is the automated build check service of coreboot. The developer "uwe" checked in revision 3696 to the coreboot source repository and caused the following changes: Change Log: Add support for the Intel 82371MX (MPIIX) southbridge (trivial). Untested, but should work just as well as the other *PIIX* southbridges according to the datasheets. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Build Log: Compilation of msi:ms9185 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3696&device=ms9185&vendor=… If something broke during this checkin please be a pain in uwe's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

1 0

r3697 - trunk/util/flashrom
by svn＠coreboot.org 28 Oct '08

28 Oct '08

Author: uwe Date: 2008-10-28 13:00:59 +0100 (Tue, 28 Oct 2008) New Revision: 3697 Modified: trunk/util/flashrom/flashchips.c Log: Mark Winbond W39V040FA" (512 KB) as fully supported, tested by Martin Stecklum <stecky(a)gmx.net> (both write and erase). The tests were done on an MSI MS-7065 board, so that's supported now too (wiki page will be updated). Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/util/flashrom/flashchips.c =================================================================== --- trunk/util/flashrom/flashchips.c 2008-10-28 11:50:05 UTC (rev 3696) +++ trunk/util/flashrom/flashchips.c 2008-10-28 12:00:59 UTC (rev 3697) @@ -135,7 +135,7 @@ {"Winbond", "W39V040A", WINBOND_ID, W_39V040A, 512, 64*1024, TEST_UNTESTED, probe_jedec, erase_chip_jedec, write_39sf020}, {"Winbond", "W39V040B", WINBOND_ID, W_39V040B, 512, 64*1024, TEST_OK_PREW, probe_jedec, erase_chip_jedec, write_39sf020}, {"Winbond", "W39V040C", 0xda, 0x50, 512, 64*1024, TEST_OK_PREW, probe_w39v040c, erase_w39v040c, write_w39v040c}, - {"Winbond", "W39V040FA", WINBOND_ID, W_39V040FA, 512, 64*1024, TEST_OK_PR, probe_jedec, erase_chip_jedec, write_39sf020}, + {"Winbond", "W39V040FA", WINBOND_ID, W_39V040FA, 512, 64*1024, TEST_OK_PREW, probe_jedec, erase_chip_jedec, write_39sf020}, {"Winbond", "W39V080A", WINBOND_ID, W_39V080A, 1024, 64*1024, TEST_OK_PREW, probe_jedec, erase_chip_jedec, write_39sf020}, {"Winbond", "W49F002U", WINBOND_ID, W_49F002U, 256, 128, TEST_OK_PREW, probe_jedec, erase_chip_jedec, write_49f002}, {"Winbond", "W49V002A", WINBOND_ID, W_49V002A, 256, 128, TEST_OK_PREW, probe_jedec, erase_chip_jedec, write_49f002},

1 0

r3696 - trunk/util/flashrom
by svn＠coreboot.org 28 Oct '08

28 Oct '08

Author: uwe Date: 2008-10-28 12:50:05 +0100 (Tue, 28 Oct 2008) New Revision: 3696 Modified: trunk/util/flashrom/chipset_enable.c Log: Add support for the Intel 82371MX (MPIIX) southbridge (trivial). Untested, but should work just as well as the other *PIIX* southbridges according to the datasheets. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/util/flashrom/chipset_enable.c =================================================================== --- trunk/util/flashrom/chipset_enable.c 2008-10-27 13:44:07 UTC (rev 3695) +++ trunk/util/flashrom/chipset_enable.c 2008-10-28 11:50:05 UTC (rev 3696) @@ -125,7 +125,7 @@ /* Set bit 9: 1-Meg Extended BIOS Enable (PCI master accesses to * FFF00000-FFF7FFFF are forwarded to ISA). - * Note: This bit is reserved on PIIX/PIIX3. + * Note: This bit is reserved on PIIX/PIIX3/MPIIX. * Set bit 7: Extended BIOS Enable (PCI master accesses to * FFF80000-FFFDFFFF are forwarded to ISA). * Set bit 6: Lower BIOS Enable (PCI master, or ISA master accesses to @@ -135,8 +135,9 @@ * Note: Accesses to FFFF0000-FFFFFFFF are always forwarded to ISA. * Set bit 2: BIOSCS# Write Enable (1=enable, 0=disable). */ - if (dev->device_id == 0x122e || dev->device_id == 0x7000) - new = old | 0x00c4; /* Bit 9 is reserved on PIIX/PIIX3. */ + if (dev->device_id == 0x122e || dev->device_id == 0x7000 + || dev->device_id == 0x1234) + new = old | 0x00c4; /* PIIX/PIIX3/MPIIX: Bit 9 is reserved. */ else new = old | 0x02c4; @@ -750,6 +751,7 @@ static const FLASH_ENABLE enables[] = { {0x1039, 0x0630, "SiS630", enable_flash_sis630}, {0x8086, 0x122e, "Intel PIIX", enable_flash_piix4}, + {0x8086, 0x1234, "Intel MPIIX", enable_flash_piix4}, {0x8086, 0x7000, "Intel PIIX3", enable_flash_piix4}, {0x8086, 0x7110, "Intel PIIX4/4E/4M", enable_flash_piix4}, {0x8086, 0x7198, "Intel 440MX", enable_flash_piix4},

1 0

v3 HT
by Myles Watson 28 Oct '08

28 Oct '08

I've been looking at v2 and v3 HT code. It seems like the biggest problem is that we changed the representation of the device tree and didn't change the code. I think it would be best to have the dts match an lspci as closely as possible. That means the code has to be a little smarter so that it can fill in the missing information. If we start with a dts which describes the Serengeti machine, we have: /{ device_operations="serengeti"; mainboard_vendor = "AMD"; mainboard_name = "Serengeti"; cpus { }; apic@0 { }; domain@0 { /config/("northbridge/amd/k8/domain"); pci0@18,0 { /config/("northbridge/amd/k8/pci"); pci@0,0 { /config/("southbridge/amd/amd8111/pci.dts"); pci@1,0{ /config/("southbridge/amd/amd8111/nic.dts"); }; }; pci@1,0 { /config/("southbridge/amd/amd8111/lpc.dts"); }; pci@1,1 { /config/("southbridge/amd/amd8111/ide.dts"); }; pci@1,0{ /config/("southbridge/amd/amd8132/pcix.dts"); }; }; pci1@18,0 { /config/("northbridge/amd/k8/pci"); }; pci2@18,0 { /config/("northbridge/amd/k8/pci"); }; pci@18,1 {}; pci@18,2 {}; pci@18,3 {}; ioport@2e { /config/("superio/winbond/w83627hf/dts"); com1enable = "1"; }; }; }; It doesn't exactly match an lspci, because lspci doesn't care what link the devices are on. I think we have to keep that difference. Then when the hypertransport enumeration code runs, the bridges appear to be siblings of their children. With v2 there was another layer of hierarchy so that the children of link 0 would just be the 8132 and the 8111. So the new code should: 1. Scan the list of children for bridges 2. Assign the devices bus numbers and attach them correctly Does that mean that we need to create dynamic bus devices or structures to hold that information? Probably not. We can just change pointer assignments. I don't think we need to expand the dts to fix this, we just need to make the code match the structure. Thanks, Myles

4 27

K8 HT architecture
by Carl-Daniel Hailfinger 28 Oct '08

28 Oct '08

Hi, I'm trying to understand how HT is modeled into PCI space so that I can propose the "right" way to handle it in the dts. Depending on whether I run lspci -t under coreboot or factory BIOS, different topologies will be displayed. That means looking at lspci is not going to tell me how the hardware really works. Given a standard setup with three HT links from the CPU, where do I find which device? Is PCI device 18.0 sort of a PCI bridge which has multiple PCI buses (HT links) behind itself? +--18.0----(first HT link)--+--0.0 | |\ \--0.1 | | | | | \--(second HT link)---(may be empty) | | | \----(third HT link)--+--0.0 | +--1.0 | \--1.1 +--18.1 +--18.2 +--18.3 Will a MP setup look like this: +--18.0----(first HT link)--+--19.0---(2nd HT link) | |\ | \--(3rd HT link) | | | +--19.1 | | | +--19.2 | | | +--19.3 | | | | | \--(second HT link)---(may be empty) | | | \----(third HT link)--+--0.0 | +--1.0 | \--1.1 +--18.1 +--18.2 +--18.3 Or is the hardware organized in a completely different way? I'm especially curious about the MP scenario as depicted above. Where do the PCI functions of 18.[0123] reside? Regards, Carl-Daniel -- http://www.hailfinger.org/

5 16

r956 - in coreboot-v3: . device mainboard/amd mainboard/amd/serengeti southbridge/amd/amd8111 southbridge/amd/amd8132
by svn＠coreboot.org 28 Oct '08

28 Oct '08

Author: myles Date: 2008-10-28 03:06:15 +0100 (Tue, 28 Oct 2008) New Revision: 956 Modified: coreboot-v3/Kconfig coreboot-v3/device/Makefile coreboot-v3/device/pcix_device.c coreboot-v3/mainboard/amd/Kconfig coreboot-v3/mainboard/amd/serengeti/defconfig coreboot-v3/mainboard/amd/serengeti/dts coreboot-v3/southbridge/amd/amd8111/amd8111.c coreboot-v3/southbridge/amd/amd8132/amd8132_bridge.c Log: This fixes the 8132 so that it can be included in the build for serengeti. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Modified: coreboot-v3/Kconfig =================================================================== --- coreboot-v3/Kconfig 2008-10-27 23:16:17 UTC (rev 955) +++ coreboot-v3/Kconfig 2008-10-28 02:06:15 UTC (rev 956) @@ -102,6 +102,8 @@ boolean config SOUTHBRIDGE_NVIDIA_MCP55 boolean +config SOUTHBRIDGE_AMD_AMD8132 + boolean config SOUTHBRIDGE_AMD_AMD8111 boolean config SOUTHBRIDGE_AMD_SB600 Modified: coreboot-v3/device/Makefile =================================================================== --- coreboot-v3/device/Makefile 2008-10-27 23:16:17 UTC (rev 955) +++ coreboot-v3/device/Makefile 2008-10-28 02:06:15 UTC (rev 956) @@ -33,5 +33,9 @@ STAGE2_DEVICE_SRC += hypertransport.c endif +# this is only needed for pcix devices +ifeq ($(CONFIG_SOUTHBRIDGE_AMD_AMD8132),y) +STAGE2_DEVICE_SRC += pcix_device.c +endif $(obj)/device/pci_device.o: $(src)/device/pci_device.c $(obj)/statictree.h Modified: coreboot-v3/device/pcix_device.c =================================================================== --- coreboot-v3/device/pcix_device.c 2008-10-27 23:16:17 UTC (rev 955) +++ coreboot-v3/device/pcix_device.c 2008-10-28 02:06:15 UTC (rev 956) @@ -120,9 +120,9 @@ /* Find the PCI-X capability. */ pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); - sstatus = pci_read_config16(dev, pos + PCI_X_SEC_STATUS); + status = pci_read_config16(dev, pos + PCI_X_SEC_STATUS); - if (PCI_X_SSTATUS_MFREQ(sstatus) == PCI_X_SSTATUS_CONVENTIONAL_PCI) { + if (PCI_X_SSTATUS_MFREQ(status) == PCI_X_SSTATUS_CONVENTIONAL_PCI) { max = do_pci_scan_bridge(dev, max, pci_scan_bus); } else { max = do_pci_scan_bridge(dev, max, pcix_scan_bus); @@ -130,23 +130,23 @@ /* Print the PCI-X bus speed. */ printk(BIOS_DEBUG, "PCI-X: %02x: %s\n", dev->link[0].secondary, - pcix_speed(sstatus)); + pcix_speed(status)); return max; } /** Default device operations for PCI-X bridges. */ -static const struct pci_operations pcix_bus_ops_pci = { +struct pci_operations pcix_bus_ops_pci = { .set_subsystem = 0, }; -const struct device_operations default_pcix_ops_bus = { - .read_resources = pci_bus_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_bus_enable_resources, - .init = 0, - .scan_bus = pcix_scan_bridge, - .enable = 0, - .reset_bus = pci_bus_reset, - .ops_pci = &pcix_bus_ops_pci, +struct device_operations default_pcix_ops_bus = { + .phase4_read_resources = pci_bus_read_resources, + .phase4_set_resources = pci_dev_set_resources, + .phase5_enable_resources = pci_bus_enable_resources, + .phase6_init = 0, + .phase3_scan = pcix_scan_bridge, + .phase3_chip_setup_dev = 0, + .reset_bus = pci_bus_reset, + .ops_pci = &pcix_bus_ops_pci, }; Modified: coreboot-v3/mainboard/amd/Kconfig =================================================================== --- coreboot-v3/mainboard/amd/Kconfig 2008-10-27 23:16:17 UTC (rev 955) +++ coreboot-v3/mainboard/amd/Kconfig 2008-10-28 02:06:15 UTC (rev 956) @@ -66,6 +66,7 @@ select CPU_AMD_K8 select NORTHBRIDGE_AMD_K8 select SOUTHBRIDGE_AMD_AMD8111 + select SOUTHBRIDGE_AMD_AMD8132 select SUPERIO_WINBOND_W83627HF select IOAPIC help Modified: coreboot-v3/mainboard/amd/serengeti/defconfig =================================================================== --- coreboot-v3/mainboard/amd/serengeti/defconfig 2008-10-27 23:16:17 UTC (rev 955) +++ coreboot-v3/mainboard/amd/serengeti/defconfig 2008-10-28 02:06:15 UTC (rev 956) @@ -24,6 +24,7 @@ # CONFIG_VENDOR_PCENGINES is not set CONFIG_MAINBOARD_DIR="amd/serengeti" # CONFIG_BOARD_AMD_DB800 is not set +# CONFIG_BOARD_AMD_DBM690T is not set # CONFIG_BOARD_AMD_NORWICH is not set CONFIG_BOARD_AMD_SERENGETI=y # CONFIG_COREBOOT_ROMSIZE_KB_128 is not set @@ -71,6 +72,7 @@ # Console # CONFIG_CONSOLE=y +# CONFIG_CONSOLE_PREPEND_LOG_LEVEL is not set CONFIG_CONSOLE_LOGLEVEL_8=y # CONFIG_CONSOLE_LOGLEVEL_7 is not set # CONFIG_CONSOLE_LOGLEVEL_6 is not set @@ -94,7 +96,7 @@ # Cosmetic console options # # CONFIG_CONSOLE_PREFIX is not set -CONFIG_CONSOLE_BUFFER=y +# CONFIG_CONSOLE_BUFFER is not set # # Devices @@ -110,6 +112,7 @@ CONFIG_HW_MEM_HOLE_SIZEK=0x1000 CONFIG_NORTHBRIDGE_AMD_K8=y CONFIG_SOUTHBRIDGE_AMD_AMD8111=y +CONFIG_SOUTHBRIDGE_AMD_AMD8132=y CONFIG_SUPERIO_WINBOND_W83627HF=y # Modified: coreboot-v3/mainboard/amd/serengeti/dts =================================================================== --- coreboot-v3/mainboard/amd/serengeti/dts 2008-10-27 23:16:17 UTC (rev 955) +++ coreboot-v3/mainboard/amd/serengeti/dts 2008-10-28 02:06:15 UTC (rev 956) @@ -27,15 +27,10 @@ }; domain@0 { /config/("northbridge/amd/k8/domain"); - pci@1,0{ - }; pci0@18,0 { /config/("northbridge/amd/k8/pci"); pci@0,0 { /config/("southbridge/amd/amd8111/pci.dts"); - pci@1,0{ - /config/("southbridge/amd/amd8111/nic.dts"); - }; pci@0,0{ /config/("southbridge/amd/amd8111/usb.dts"); }; @@ -44,28 +39,34 @@ }; pci@0,2{ /config/("southbridge/amd/amd8111/usb2.dts"); + disable; }; - pci@4,0{ + pci@1,0{ + /config/("southbridge/amd/amd8111/nic.dts"); + disable; }; }; - pci@7,0 { + pci@1,0 { /config/("southbridge/amd/amd8111/lpc.dts"); }; - pci@7,1 { + pci@1,1 { /config/("southbridge/amd/amd8111/ide.dts"); }; - pci@7,2 { + pci@1,2 { /config/("southbridge/amd/amd8111/smbus.dts"); }; - pci@7,3 { + pci@1,3 { /config/("southbridge/amd/amd8111/acpi.dts"); }; - pci@7,5 { + pci@1,5 { /config/("southbridge/amd/amd8111/ac97audio.dts"); }; - pci@7,6 { + pci@1,6 { /config/("southbridge/amd/amd8111/ac97modem.dts"); }; + pci@2,0 { + /config/("southbridge/amd/amd8132/pcix.dts"); + }; }; pci1@18,0 { /config/("northbridge/amd/k8/pci"); Modified: coreboot-v3/southbridge/amd/amd8111/amd8111.c =================================================================== --- coreboot-v3/southbridge/amd/amd8111/amd8111.c 2008-10-27 23:16:17 UTC (rev 955) +++ coreboot-v3/southbridge/amd/amd8111/amd8111.c 2008-10-28 02:06:15 UTC (rev 956) @@ -34,19 +34,19 @@ void amd8111_enable(struct device * dev) { - struct device * lpc_dev; + struct device * sub_dev; struct device * bus_dev; unsigned index; unsigned reg_old, reg; /* See if we are behind the amd8111 pci bridge */ bus_dev = dev->bus->dev; - if ((bus_dev->id.pci.vendor == PCI_VENDOR_ID_AMD) && - (bus_dev->id.pci.device == PCI_DEVICE_ID_AMD_8111_PCI)) + if ((bus_dev->id.pci.vendor == PCI_VENDOR_ID_AMD) && + (bus_dev->id.pci.device == PCI_DEVICE_ID_AMD_8111_PCI)) { unsigned devfn; devfn = bus_dev->path.pci.devfn + (1 << 3); - lpc_dev = dev_find_slot(bus_dev->bus->secondary, devfn); + sub_dev = dev_find_slot(bus_dev->bus->secondary, devfn); index = ((dev->path.pci.devfn & ~7) >> 3) + 8; if (dev->path.pci.devfn == 2) { /* EHCI */ index = 16; @@ -54,40 +54,40 @@ } else { unsigned devfn; devfn = (dev->path.pci.devfn) & ~7; - lpc_dev = dev_find_slot(dev->bus->secondary, devfn); + sub_dev = dev_find_slot(dev->bus->secondary, devfn); index = dev->path.pci.devfn & 7; } - if ((!lpc_dev) || (index >= 17)) { + if ((!sub_dev) || (index >= 17)) { return; } - if ((lpc_dev->id.pci.vendor != PCI_VENDOR_ID_AMD) || - (lpc_dev->id.pci.device != PCI_DEVICE_ID_AMD_8111_ISA)) + if ((sub_dev->id.pci.vendor != PCI_VENDOR_ID_AMD) || + (sub_dev->id.pci.device != PCI_DEVICE_ID_AMD_8111_ISA)) { u32 id; - id = pci_read_config32(lpc_dev, PCI_VENDOR_ID); + id = pci_read_config32(sub_dev, PCI_VENDOR_ID); if (id != (PCI_VENDOR_ID_AMD | (PCI_DEVICE_ID_AMD_8111_ISA << 16))) { return; } } if (index < 16) { - reg = reg_old = pci_read_config16(lpc_dev, 0x48); + reg = reg_old = pci_read_config16(sub_dev, 0x48); reg &= ~(1 << index); if (dev->enabled) { reg |= (1 << index); } if (reg != reg_old) { - pci_write_config16(lpc_dev, 0x48, reg); + pci_write_config16(sub_dev, 0x48, reg); } } else if (index == 16) { - reg = reg_old = pci_read_config8(lpc_dev, 0x47); + reg = reg_old = pci_read_config8(sub_dev, 0x47); reg &= ~(1 << 7); if (!dev->enabled) { reg |= (1 << 7); } if (reg != reg_old) { - pci_write_config8(lpc_dev, 0x47, reg); + pci_write_config8(sub_dev, 0x47, reg); } } } Modified: coreboot-v3/southbridge/amd/amd8132/amd8132_bridge.c =================================================================== --- coreboot-v3/southbridge/amd/amd8132/amd8132_bridge.c 2008-10-27 23:16:17 UTC (rev 955) +++ coreboot-v3/southbridge/amd/amd8132/amd8132_bridge.c 2008-10-28 02:06:15 UTC (rev 956) @@ -22,6 +22,7 @@ #include <lib.h> #include <console.h> #include <device/pci.h> +#include <device/pcix.h> #include <msr.h> #include <legacy.h> #include <device/pci_ids.h> @@ -425,9 +426,9 @@ .device = PCI_DEVICE_ID_AMD_8132_IOAPIC}}}, .constructor = default_device_constructor, .phase3_scan = 0, - .phase4_enable_disable = ioapic_enable, + .phase3_chip_setup_dev = ioapic_enable, .phase4_read_resources = pci_dev_read_resources, .phase4_set_resources = pci_dev_set_resources, .phase6_init = amd8132_ioapic_init, - .ops_pci = &pci_dev_ops_pci, + .ops_pci = &pci_ops_pci_dev, };

1 0

r955 - in coreboot-v3/southbridge/amd: amd8111 amd8132 amd8151 cs5536 rs690 sb600
by svn＠coreboot.org 28 Oct '08

28 Oct '08

Author: mjones Date: 2008-10-28 00:16:17 +0100 (Tue, 28 Oct 2008) New Revision: 955 Modified: coreboot-v3/southbridge/amd/amd8111/ac97.c coreboot-v3/southbridge/amd/amd8111/acpi.c coreboot-v3/southbridge/amd/amd8111/ide.c coreboot-v3/southbridge/amd/amd8111/lpc.c coreboot-v3/southbridge/amd/amd8111/nic.c coreboot-v3/southbridge/amd/amd8111/pci.c coreboot-v3/southbridge/amd/amd8111/smbus.c coreboot-v3/southbridge/amd/amd8111/usb.c coreboot-v3/southbridge/amd/amd8111/usb2.c coreboot-v3/southbridge/amd/amd8132/amd8132_bridge.c coreboot-v3/southbridge/amd/amd8151/amd8151_agp3.c coreboot-v3/southbridge/amd/cs5536/cs5536.c coreboot-v3/southbridge/amd/rs690/gfx.c coreboot-v3/southbridge/amd/rs690/ht.c coreboot-v3/southbridge/amd/rs690/pcie.c coreboot-v3/southbridge/amd/sb600/ac97.c coreboot-v3/southbridge/amd/sb600/hda.c coreboot-v3/southbridge/amd/sb600/ide.c coreboot-v3/southbridge/amd/sb600/lpc.c coreboot-v3/southbridge/amd/sb600/pci.c coreboot-v3/southbridge/amd/sb600/sata.c coreboot-v3/southbridge/amd/sb600/sm.c coreboot-v3/southbridge/amd/sb600/usb.c Log: Whitespace cleanup on AMD southbridge device_operations structs. (trivial) Signed-off-by: Marc Jones <marc.jones(a)amd.com> Acked-by: Marc Jones <marc.jones(a)amd.com> Modified: coreboot-v3/southbridge/amd/amd8111/ac97.c =================================================================== --- coreboot-v3/southbridge/amd/amd8111/ac97.c 2008-10-27 20:05:38 UTC (rev 954) +++ coreboot-v3/southbridge/amd/amd8111/ac97.c 2008-10-27 23:16:17 UTC (rev 955) @@ -41,10 +41,10 @@ struct device_operations ac97audio = { .id = {.type = DEVICE_ID_PCI, {.pci = {.vendor = PCI_VENDOR_ID_AMD, - .device = 0x746D}}}, + .device = 0x746D}}}, .constructor = default_device_constructor, .phase3_scan = 0, - .phase3_chip_setup_dev = amd8111_enable, + .phase3_chip_setup_dev = amd8111_enable, .phase4_read_resources = pci_dev_read_resources, .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = pci_dev_enable_resources, @@ -55,10 +55,10 @@ struct device_operations ac97modem = { .id = {.type = DEVICE_ID_PCI, {.pci = {.vendor = PCI_VENDOR_ID_AMD, - .device = 0x746E}}}, + .device = 0x746E}}}, .constructor = default_device_constructor, .phase3_scan = 0, - .phase3_chip_setup_dev = amd8111_enable, + .phase3_chip_setup_dev = amd8111_enable, .phase4_read_resources = pci_dev_read_resources, .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = pci_dev_enable_resources, Modified: coreboot-v3/southbridge/amd/amd8111/acpi.c =================================================================== --- coreboot-v3/southbridge/amd/amd8111/acpi.c 2008-10-27 20:05:38 UTC (rev 954) +++ coreboot-v3/southbridge/amd/amd8111/acpi.c 2008-10-27 23:16:17 UTC (rev 955) @@ -228,14 +228,14 @@ struct device_operations acpi = { .id = {.type = DEVICE_ID_PCI, {.pci = {.vendor = PCI_VENDOR_ID_AMD, - .device = PCI_DEVICE_ID_AMD_8111_ACPI}}}, + .device = PCI_DEVICE_ID_AMD_8111_ACPI}}}, .constructor = default_device_constructor, .phase3_scan = scan_static_bus, - .phase3_chip_setup_dev = amd8111_enable, + .phase3_chip_setup_dev = amd8111_enable, .phase4_read_resources = acpi_read_resources, .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = acpi_enable_resources, .phase6_init = acpi_init, .ops_pci = &lops_pci, - .ops_smbus_bus = &lops_smbus_bus, + .ops_smbus_bus = &lops_smbus_bus, }; Modified: coreboot-v3/southbridge/amd/amd8111/ide.c =================================================================== --- coreboot-v3/southbridge/amd/amd8111/ide.c 2008-10-27 20:05:38 UTC (rev 954) +++ coreboot-v3/southbridge/amd/amd8111/ide.c 2008-10-27 23:16:17 UTC (rev 955) @@ -75,13 +75,13 @@ struct device_operations amd8111_ide = { .id = {.type = DEVICE_ID_PCI, {.pci = {.vendor = PCI_VENDOR_ID_AMD, - .device = PCI_DEVICE_ID_AMD_8111_IDE}}}, + .device = PCI_DEVICE_ID_AMD_8111_IDE}}}, .constructor = default_device_constructor, .phase3_scan = 0, - .phase3_chip_setup_dev = amd8111_enable, + .phase3_chip_setup_dev = amd8111_enable, .phase4_read_resources = pci_dev_read_resources, .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = pci_dev_enable_resources, .phase6_init = ide_init, - .ops_pci = &lops_pci + .ops_pci = &lops_pci }; Modified: coreboot-v3/southbridge/amd/amd8111/lpc.c =================================================================== --- coreboot-v3/southbridge/amd/amd8111/lpc.c 2008-10-27 20:05:38 UTC (rev 954) +++ coreboot-v3/southbridge/amd/amd8111/lpc.c 2008-10-27 23:16:17 UTC (rev 955) @@ -210,10 +210,10 @@ struct device_operations amd8111_lpc = { .id = {.type = DEVICE_ID_PCI, {.pci = {.vendor = PCI_VENDOR_ID_AMD, - .device = PCI_DEVICE_ID_AMD_8111_ISA}}}, + .device = PCI_DEVICE_ID_AMD_8111_ISA}}}, .constructor = default_device_constructor, .phase3_scan = scan_static_bus, - .phase3_chip_setup_dev = amd8111_enable, + .phase3_chip_setup_dev = amd8111_enable, .phase4_read_resources = amd8111_lpc_read_resources, .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = amd8111_lpc_enable_resources, Modified: coreboot-v3/southbridge/amd/amd8111/nic.c =================================================================== --- coreboot-v3/southbridge/amd/amd8111/nic.c 2008-10-27 20:05:38 UTC (rev 954) +++ coreboot-v3/southbridge/amd/amd8111/nic.c 2008-10-27 23:16:17 UTC (rev 955) @@ -96,10 +96,10 @@ struct device_operations amd8111_nic = { .id = {.type = DEVICE_ID_PCI, {.pci = {.vendor = PCI_VENDOR_ID_AMD, - .device = PCI_DEVICE_ID_AMD_8111_NIC}}}, + .device = PCI_DEVICE_ID_AMD_8111_NIC}}}, .constructor = default_device_constructor, .phase3_scan = 0, - .phase3_chip_setup_dev = amd8111_enable, + .phase3_chip_setup_dev = amd8111_enable, .phase4_read_resources = pci_dev_read_resources, .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = pci_dev_enable_resources, Modified: coreboot-v3/southbridge/amd/amd8111/pci.c =================================================================== --- coreboot-v3/southbridge/amd/amd8111/pci.c 2008-10-27 20:05:38 UTC (rev 954) +++ coreboot-v3/southbridge/amd/amd8111/pci.c 2008-10-27 23:16:17 UTC (rev 955) @@ -72,10 +72,10 @@ struct device_operations amd8111_pci = { .id = {.type = DEVICE_ID_PCI, {.pci = {.vendor = PCI_VENDOR_ID_AMD, - .device = PCI_DEVICE_ID_AMD_8111_PCI}}}, + .device = PCI_DEVICE_ID_AMD_8111_PCI}}}, .constructor = default_device_constructor, .phase3_scan = pci_scan_bridge, - .phase3_chip_setup_dev = amd8111_enable, + .phase3_chip_setup_dev = amd8111_enable, .phase4_read_resources = pci_bus_read_resources, .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = pci_bus_enable_resources, Modified: coreboot-v3/southbridge/amd/amd8111/smbus.c =================================================================== --- coreboot-v3/southbridge/amd/amd8111/smbus.c 2008-10-27 20:05:38 UTC (rev 954) +++ coreboot-v3/southbridge/amd/amd8111/smbus.c 2008-10-27 23:16:17 UTC (rev 955) @@ -50,14 +50,14 @@ struct device_operations amd8111_smbus = { .id = {.type = DEVICE_ID_PCI, {.pci = {.vendor = PCI_VENDOR_ID_AMD, - .device = PCI_DEVICE_ID_AMD_8111_SMB}}}, + .device = PCI_DEVICE_ID_AMD_8111_SMB}}}, .constructor = default_device_constructor, .phase3_scan = scan_static_bus, - .phase3_chip_setup_dev = amd8111_enable, + .phase3_chip_setup_dev = amd8111_enable, .phase4_read_resources = pci_dev_read_resources, .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = pci_dev_enable_resources, .phase6_init = NULL, - .ops_pci = &lops_pci, - .ops_smbus_bus = &lops_smbus_bus, + .ops_pci = &lops_pci, + .ops_smbus_bus = &lops_smbus_bus, }; Modified: coreboot-v3/southbridge/amd/amd8111/usb.c =================================================================== --- coreboot-v3/southbridge/amd/amd8111/usb.c 2008-10-27 20:05:38 UTC (rev 954) +++ coreboot-v3/southbridge/amd/amd8111/usb.c 2008-10-27 23:16:17 UTC (rev 955) @@ -47,13 +47,13 @@ struct device_operations amd8111_usb = { .id = {.type = DEVICE_ID_PCI, {.pci = {.vendor = PCI_VENDOR_ID_AMD, - .device = PCI_DEVICE_ID_AMD_8111_USB}}}, + .device = PCI_DEVICE_ID_AMD_8111_USB}}}, .constructor = default_device_constructor, .phase3_scan = scan_static_bus, - .phase3_chip_setup_dev = amd8111_enable, + .phase3_chip_setup_dev = amd8111_enable, .phase4_read_resources = pci_dev_read_resources, .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = pci_dev_enable_resources, .phase6_init = NULL, - .ops_pci = &lops_pci + .ops_pci = &lops_pci }; Modified: coreboot-v3/southbridge/amd/amd8111/usb2.c =================================================================== --- coreboot-v3/southbridge/amd/amd8111/usb2.c 2008-10-27 20:05:38 UTC (rev 954) +++ coreboot-v3/southbridge/amd/amd8111/usb2.c 2008-10-27 23:16:17 UTC (rev 955) @@ -46,10 +46,10 @@ struct device_operations amd8111_usb2 = { .id = {.type = DEVICE_ID_PCI, {.pci = {.vendor = PCI_VENDOR_ID_AMD, - .device = PCI_DEVICE_ID_AMD_8111_USB}}}, + .device = PCI_DEVICE_ID_AMD_8111_USB}}}, .constructor = default_device_constructor, .phase3_scan = scan_static_bus, - .phase3_chip_setup_dev = amd8111_usb2_enable, + .phase3_chip_setup_dev = amd8111_usb2_enable, .phase4_read_resources = pci_dev_read_resources, .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = pci_dev_enable_resources, Modified: coreboot-v3/southbridge/amd/amd8132/amd8132_bridge.c =================================================================== --- coreboot-v3/southbridge/amd/amd8132/amd8132_bridge.c 2008-10-27 20:05:38 UTC (rev 954) +++ coreboot-v3/southbridge/amd/amd8132/amd8132_bridge.c 2008-10-27 23:16:17 UTC (rev 955) @@ -348,16 +348,16 @@ struct device_operations amd8132_pcix = { .id = {.type = DEVICE_ID_PCI, {.pci = {.vendor = PCI_VENDOR_ID_AMD, - .device = PCI_DEVICE_ID_AMD_8132_PCIX}}}, + .device = PCI_DEVICE_ID_AMD_8132_PCIX}}}, .constructor = default_device_constructor, - .reset_bus = pci_bus_reset, + .reset_bus = pci_bus_reset, .phase3_scan = amd8132_scan_bridge, #if BRIDGE_40_BIT_SUPPORT - .phase4_read_resources = bridge_read_resources, - .phase4_set_resources = bridge_set_resources, + .phase4_read_resources = bridge_read_resources, + .phase4_set_resources = bridge_set_resources, #else - .phase4_read_resources = pci_bus_read_resources, - .phase4_set_resources = pci_dev_set_resources, + .phase4_read_resources = pci_bus_read_resources, + .phase4_set_resources = pci_dev_set_resources, #endif .phase5_enable_resources = pci_dev_enable_resources, .phase6_init = amd8132_pcix_init, @@ -422,10 +422,10 @@ struct device_operations amd8132_apic = { .id = {.type = DEVICE_ID_PCI, {.pci = {.vendor = PCI_VENDOR_ID_AMD, - .device = PCI_DEVICE_ID_AMD_8132_IOAPIC}}}, + .device = PCI_DEVICE_ID_AMD_8132_IOAPIC}}}, .constructor = default_device_constructor, .phase3_scan = 0, - .phase4_enable_disable = ioapic_enable, + .phase4_enable_disable = ioapic_enable, .phase4_read_resources = pci_dev_read_resources, .phase4_set_resources = pci_dev_set_resources, .phase6_init = amd8132_ioapic_init, Modified: coreboot-v3/southbridge/amd/amd8151/amd8151_agp3.c =================================================================== --- coreboot-v3/southbridge/amd/amd8151/amd8151_agp3.c 2008-10-27 20:05:38 UTC (rev 954) +++ coreboot-v3/southbridge/amd/amd8151/amd8151_agp3.c 2008-10-27 23:16:17 UTC (rev 955) @@ -43,11 +43,11 @@ struct device_operations amd8151_agp3bridge = { .id = {.type = DEVICE_ID_PCI, {.pci = {.vendor = PCI_VENDOR_ID_AMD, - .device = PCI_DEVICE_ID_AMD_8151_AGP}}}, + .device = PCI_DEVICE_ID_AMD_8151_AGP}}}, .constructor = default_device_constructor, .phase3_scan = pci_scan_bridge - .phase4_read_resources = pci_bus_read_resources, - .phase4_set_resources = pci_dev_set_resources, + .phase4_read_resources = pci_bus_read_resources, + .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = pci_bus_enable_resources, .phase6_init = agp3bridge_init, }; @@ -78,11 +78,11 @@ struct device_operations amd8151_agp3dev = { .id = {.type = DEVICE_ID_PCI, {.pci = {.vendor = PCI_VENDOR_ID_AMD, - .device = PCI_DEVICE_ID_AMD_8151_SYSCTRL}}}, + .device = PCI_DEVICE_ID_AMD_8151_SYSCTRL}}}, .constructor = default_device_constructor, - .phase4_enable_disable = agp3dev_enable, - .phase4_read_resources = pci_dev_read_resources, - .phase4_set_resources = pci_dev_set_resources, + .phase4_enable_disable = agp3dev_enable, + .phase4_read_resources = pci_dev_read_resources, + .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = pci_dev_enable_resources, .phase6_init = NULL, .ops_pci = &pci_dev_ops_pci, Modified: coreboot-v3/southbridge/amd/cs5536/cs5536.c =================================================================== --- coreboot-v3/southbridge/amd/cs5536/cs5536.c 2008-10-27 20:05:38 UTC (rev 954) +++ coreboot-v3/southbridge/amd/cs5536/cs5536.c 2008-10-27 23:16:17 UTC (rev 955) @@ -712,19 +712,19 @@ struct device_operations cs5536_ops = { .id = {.type = DEVICE_ID_PCI, {.pci = {.vendor = PCI_VENDOR_ID_AMD, - .device = PCI_DEVICE_ID_AMD_CS5536_ISA}}}, - .constructor = default_device_constructor, - .phase3_scan = scan_static_bus, - .phase4_read_resources = pci_dev_read_resources, - .phase4_set_resources = pci_dev_set_resources, - .phase5_enable_resources = cs5536_pci_dev_enable_resources, - .phase6_init = southbridge_init, + .device = PCI_DEVICE_ID_AMD_CS5536_ISA}}}, + .constructor = default_device_constructor, + .phase3_scan = scan_static_bus, + .phase4_read_resources = pci_dev_read_resources, + .phase4_set_resources = pci_dev_set_resources, + .phase5_enable_resources = cs5536_pci_dev_enable_resources, + .phase6_init = southbridge_init, }; struct device_operations cs5536_ide = { .id = {.type = DEVICE_ID_PCI, {.pci = {.vendor = PCI_VENDOR_ID_AMD, - .device = PCI_DEVICE_ID_AMD_CS5536_B0_IDE}}}, + .device = PCI_DEVICE_ID_AMD_CS5536_B0_IDE}}}, .constructor = default_device_constructor, #warning FIXME: what has to go in phase3_scan? .phase3_scan = 0, Modified: coreboot-v3/southbridge/amd/rs690/gfx.c =================================================================== --- coreboot-v3/southbridge/amd/rs690/gfx.c 2008-10-27 20:05:38 UTC (rev 954) +++ coreboot-v3/southbridge/amd/rs690/gfx.c 2008-10-27 23:16:17 UTC (rev 955) @@ -563,10 +563,10 @@ struct device_operations rs690_gfx = { .id = {.type = DEVICE_ID_PCI, {.pci = {.vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_ATI_RS690MT_INT_GFX}}}, + .device = PCI_DEVICE_ID_ATI_RS690MT_INT_GFX}}}, .constructor = default_device_constructor, - .phase3_chip_setup_dev = rs690_enable, - .phase3_enable = rs690_internal_gfx_enable, + .phase3_chip_setup_dev = rs690_enable, + .phase3_enable = rs690_internal_gfx_enable, .phase3_scan = 0, .phase4_read_resources = rs690_gfx_read_resources, .phase4_set_resources = rs690_gfx_set_resources, Modified: coreboot-v3/southbridge/amd/rs690/ht.c =================================================================== --- coreboot-v3/southbridge/amd/rs690/ht.c 2008-10-27 20:05:38 UTC (rev 954) +++ coreboot-v3/southbridge/amd/rs690/ht.c 2008-10-27 23:16:17 UTC (rev 955) @@ -83,10 +83,10 @@ struct device_operations rs690_ht = { .id = {.type = DEVICE_ID_PCI, {.pci = {.vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_ATI_RS690_HT}}}, + .device = PCI_DEVICE_ID_ATI_RS690_HT}}}, .constructor = default_device_constructor, .phase3_scan = 0, - .phase3_chip_setup_dev = rs690_enable, + .phase3_chip_setup_dev = rs690_enable, .phase4_read_resources = pci_dev_read_resources, .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = pci_dev_enable_resources, Modified: coreboot-v3/southbridge/amd/rs690/pcie.c =================================================================== --- coreboot-v3/southbridge/amd/rs690/pcie.c 2008-10-27 20:05:38 UTC (rev 954) +++ coreboot-v3/southbridge/amd/rs690/pcie.c 2008-10-27 23:16:17 UTC (rev 955) @@ -397,10 +397,10 @@ struct device_operations rs690_pcie = { .id = {.type = DEVICE_ID_PCI, {.pci = {.vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_ATI_RS690_PCIE}}}, + .device = PCI_DEVICE_ID_ATI_RS690_PCIE}}}, .constructor = default_device_constructor, .phase3_scan = pci_scan_bridge, - .phase3_chip_setup_dev = rs690_enable, + .phase3_chip_setup_dev = rs690_enable, .phase4_read_resources = pci_bus_read_resources, .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = pci_bus_enable_resources, @@ -412,7 +412,7 @@ struct device_operations rs690_pcie2 = { .id = {.type = DEVICE_ID_PCI, {.pci = {.vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_ATI_RS690_PCIE_DEV2}}}, + .device = PCI_DEVICE_ID_ATI_RS690_PCIE_DEV2}}}, .constructor = default_device_constructor, .phase3_scan = pci_scan_bridge, .phase4_read_resources = pci_bus_read_resources, @@ -425,7 +425,7 @@ struct device_operations rs690_pcie3 = { .id = {.type = DEVICE_ID_PCI, {.pci = {.vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_ATI_RS690_PCIE_DEV3}}}, + .device = PCI_DEVICE_ID_ATI_RS690_PCIE_DEV3}}}, .constructor = default_device_constructor, .phase3_scan = pci_scan_bridge, .phase4_read_resources = pci_bus_read_resources, @@ -438,7 +438,7 @@ struct device_operations rs690_pcie4 = { .id = {.type = DEVICE_ID_PCI, {.pci = {.vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_ATI_RS690_PCIE_DEV4}}}, + .device = PCI_DEVICE_ID_ATI_RS690_PCIE_DEV4}}}, .constructor = default_device_constructor, .phase3_scan = pci_scan_bridge, .phase4_read_resources = pci_bus_read_resources, @@ -451,7 +451,7 @@ struct device_operations rs690_pcie5 = { .id = {.type = DEVICE_ID_PCI, {.pci = {.vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_ATI_RS690_PCIE_DEV5}}}, + .device = PCI_DEVICE_ID_ATI_RS690_PCIE_DEV5}}}, .constructor = default_device_constructor, .phase3_scan = pci_scan_bridge, .phase4_read_resources = pci_bus_read_resources, @@ -464,7 +464,7 @@ struct device_operations rs690_pcie6 = { .id = {.type = DEVICE_ID_PCI, {.pci = {.vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_ATI_RS690_PCIE_DEV6}}}, + .device = PCI_DEVICE_ID_ATI_RS690_PCIE_DEV6}}}, .constructor = default_device_constructor, .phase3_scan = pci_scan_bridge, .phase4_read_resources = pci_bus_read_resources, @@ -477,7 +477,7 @@ struct device_operations rs690_pcie7 = { .id = {.type = DEVICE_ID_PCI, {.pci = {.vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_ATI_RS690_PCIE_DEV7}}}, + .device = PCI_DEVICE_ID_ATI_RS690_PCIE_DEV7}}}, .constructor = default_device_constructor, .phase3_scan = pci_scan_bridge, .phase4_read_resources = pci_bus_read_resources, @@ -490,7 +490,7 @@ struct device_operations rs690_pcie8 = { .id = {.type = DEVICE_ID_PCI, {.pci = {.vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_ATI_RS690_PCIE_DEV8}}}, + .device = PCI_DEVICE_ID_ATI_RS690_PCIE_DEV8}}}, .constructor = default_device_constructor, .phase3_scan = pci_scan_bridge, .phase4_read_resources = pci_bus_read_resources, Modified: coreboot-v3/southbridge/amd/sb600/ac97.c =================================================================== --- coreboot-v3/southbridge/amd/sb600/ac97.c 2008-10-27 20:05:38 UTC (rev 954) +++ coreboot-v3/southbridge/amd/sb600/ac97.c 2008-10-27 23:16:17 UTC (rev 955) @@ -35,10 +35,10 @@ struct device_operations ac97audio = { .id = {.type = DEVICE_ID_PCI, {.pci = {.vendor = PCI_VENDOR_ID_AMD, - .device = PCI_DEVICE_ID_ATI_SB600_ACI}}}, + .device = PCI_DEVICE_ID_ATI_SB600_ACI}}}, .constructor = default_device_constructor, .phase3_scan = 0, - .phase3_chip_setup_dev = sb600_enable, + .phase3_chip_setup_dev = sb600_enable, .phase4_read_resources = pci_dev_read_resources, .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = pci_dev_enable_resources, @@ -49,10 +49,10 @@ struct device_operations ac97modem = { .id = {.type = DEVICE_ID_PCI, {.pci = {.vendor = PCI_VENDOR_ID_AMD, - .device = PCI_DEVICE_ID_ATI_SB600_MCI}}}, + .device = PCI_DEVICE_ID_ATI_SB600_MCI}}}, .constructor = default_device_constructor, .phase3_scan = 0, - .phase3_chip_setup_dev = sb600_enable, + .phase3_chip_setup_dev = sb600_enable, .phase4_read_resources = pci_dev_read_resources, .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = pci_dev_enable_resources, Modified: coreboot-v3/southbridge/amd/sb600/hda.c =================================================================== --- coreboot-v3/southbridge/amd/sb600/hda.c 2008-10-27 20:05:38 UTC (rev 954) +++ coreboot-v3/southbridge/amd/sb600/hda.c 2008-10-27 23:16:17 UTC (rev 955) @@ -277,12 +277,12 @@ struct device_operations sb600_hda = { .id = {.type = DEVICE_ID_PCI, {.pci = {.vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_ATI_SB600_HDA}}}, + .device = PCI_DEVICE_ID_ATI_SB600_HDA}}}, .constructor = default_device_constructor, - .phase3_chip_setup_dev = sb600_enable, + .phase3_chip_setup_dev = sb600_enable, .phase4_read_resources = pci_dev_read_resources, .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = pci_dev_enable_resources, .phase6_init = hda_init, - .ops_pci = &lops_pci + .ops_pci = &lops_pci }; Modified: coreboot-v3/southbridge/amd/sb600/ide.c =================================================================== --- coreboot-v3/southbridge/amd/sb600/ide.c 2008-10-27 20:05:38 UTC (rev 954) +++ coreboot-v3/southbridge/amd/sb600/ide.c 2008-10-27 23:16:17 UTC (rev 955) @@ -68,12 +68,12 @@ struct device_operations sb600_ide = { .id = {.type = DEVICE_ID_PCI, {.pci = {.vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_ATI_SB600_IDE}}}, + .device = PCI_DEVICE_ID_ATI_SB600_IDE}}}, .constructor = default_device_constructor, - .phase3_chip_setup_dev = sb600_enable, + .phase3_chip_setup_dev = sb600_enable, .phase4_read_resources = pci_dev_read_resources, .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = pci_dev_enable_resources, .phase6_init = ide_init, - .ops_pci = &lops_pci + .ops_pci = &lops_pci }; Modified: coreboot-v3/southbridge/amd/sb600/lpc.c =================================================================== --- coreboot-v3/southbridge/amd/sb600/lpc.c 2008-10-27 20:05:38 UTC (rev 954) +++ coreboot-v3/southbridge/amd/sb600/lpc.c 2008-10-27 23:16:17 UTC (rev 955) @@ -210,13 +210,13 @@ struct device_operations sb600_lpc = { .id = {.type = DEVICE_ID_PCI, {.pci = {.vendor = PCI_VENDOR_ID_AMD, - .device = PCI_DEVICE_ID_ATI_SB600_LPC}}}, + .device = PCI_DEVICE_ID_ATI_SB600_LPC}}}, .constructor = default_device_constructor, - .phase3_scan = scan_static_bus, - .phase3_chip_setup_dev = sb600_enable, + .phase3_scan = scan_static_bus, + .phase3_chip_setup_dev = sb600_enable, .phase4_read_resources = sb600_lpc_read_resources, .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = sb600_lpc_enable_resources, .phase6_init = lpc_init, - .ops_pci = &lops_pci + .ops_pci = &lops_pci }; Modified: coreboot-v3/southbridge/amd/sb600/pci.c =================================================================== --- coreboot-v3/southbridge/amd/sb600/pci.c 2008-10-27 20:05:38 UTC (rev 954) +++ coreboot-v3/southbridge/amd/sb600/pci.c 2008-10-27 23:16:17 UTC (rev 955) @@ -127,13 +127,13 @@ struct device_operations sb600_pci = { .id = {.type = DEVICE_ID_PCI, {.pci = {.vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_ATI_SB600_PCI}}}, + .device = PCI_DEVICE_ID_ATI_SB600_PCI}}}, .constructor = default_device_constructor, .phase3_scan = pci_scan_bridge, - .phase3_chip_setup_dev = sb600_enable, + .phase3_chip_setup_dev = sb600_enable, .phase4_read_resources = pci_bus_read_resources, .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = pci_bus_enable_resources, .phase6_init = pci_init, - .reset_bus = pci_bus_reset, + .reset_bus = pci_bus_reset, }; Modified: coreboot-v3/southbridge/amd/sb600/sata.c =================================================================== --- coreboot-v3/southbridge/amd/sb600/sata.c 2008-10-27 20:05:38 UTC (rev 954) +++ coreboot-v3/southbridge/amd/sb600/sata.c 2008-10-27 23:16:17 UTC (rev 955) @@ -190,12 +190,12 @@ struct device_operations sb600_sata = { .id = {.type = DEVICE_ID_PCI, {.pci = {.vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_ATI_SB600_SATA}}}, + .device = PCI_DEVICE_ID_ATI_SB600_SATA}}}, .constructor = default_device_constructor, - .phase3_chip_setup_dev = sb600_enable, + .phase3_chip_setup_dev = sb600_enable, .phase4_read_resources = pci_dev_read_resources, .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = pci_dev_enable_resources, .phase6_init = sata_init, - .ops_pci = &lops_pci + .ops_pci = &lops_pci }; Modified: coreboot-v3/southbridge/amd/sb600/sm.c =================================================================== --- coreboot-v3/southbridge/amd/sb600/sm.c 2008-10-27 20:05:38 UTC (rev 954) +++ coreboot-v3/southbridge/amd/sb600/sm.c 2008-10-27 23:16:17 UTC (rev 955) @@ -392,14 +392,14 @@ struct device_operations sb600_sm = { .id = {.type = DEVICE_ID_PCI, {.pci = {.vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_ATI_SB600_SM}}}, + .device = PCI_DEVICE_ID_ATI_SB600_SM}}}, .constructor = default_device_constructor, .phase3_scan = 0, - .phase3_chip_setup_dev = sb600_enable, + .phase3_chip_setup_dev = sb600_enable, .phase4_read_resources = sb600_sm_read_resources, .phase4_set_resources = sb600_sm_set_resources, .phase5_enable_resources = pci_dev_enable_resources, .phase6_init = sm_init, - .ops_pci = &lops_pci, - .ops_smbus_bus = &lops_smbus_bus, + .ops_pci = &lops_pci, + .ops_smbus_bus = &lops_smbus_bus, }; Modified: coreboot-v3/southbridge/amd/sb600/usb.c =================================================================== --- coreboot-v3/southbridge/amd/sb600/usb.c 2008-10-27 20:05:38 UTC (rev 954) +++ coreboot-v3/southbridge/amd/sb600/usb.c 2008-10-27 23:16:17 UTC (rev 955) @@ -166,14 +166,14 @@ struct device_operations sb600_usb = { .id = {.type = DEVICE_ID_PCI, {.pci = {.vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_ATI_SB600_USB_0}}}, + .device = PCI_DEVICE_ID_ATI_SB600_USB_0}}}, .constructor = default_device_constructor, .phase3_scan = scan_static_bus, .phase4_read_resources = pci_dev_read_resources, .phase4_set_resources = usb_set_resources, .phase5_enable_resources = pci_dev_enable_resources, .phase6_init = usb_init, - .ops_pci = &lops_pci + .ops_pci = &lops_pci }; #if 0 @@ -202,13 +202,13 @@ struct device_operations sb600_usb2 = { .id = {.type = DEVICE_ID_PCI, {.pci = {.vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_ATI_SB600_USB2}}}, + .device = PCI_DEVICE_ID_ATI_SB600_USB2}}}, .constructor = default_device_constructor, .phase3_scan = scan_static_bus, - .phase3_chip_setup_dev = sb600_enable, + .phase3_chip_setup_dev = sb600_enable, .phase4_read_resources = pci_dev_read_resources, .phase4_set_resources = usb_set_resources, .phase5_enable_resources = pci_dev_enable_resources, .phase6_init = usb_init, - .ops_pci = &lops_pci + .ops_pci = &lops_pci };

1 0

Coreboot bios for a Thinkpad 600x, 2645-4eu ???
by Parts & Repair 27 Oct '08

27 Oct '08

Hello, Please find the following info below to see if Coreboot has bios for my Tp 600x, 2645-4eu; I have included a lspci running Slackware 12.1 and below that I have a TEXT Dump from CPU-z 1.48 running XP from the same laptop, yes it's a dual boot box. root@darkstar:/# lspci 00:00.0 Host bridge: Intel Corporation 440BX/ZX/DX - 82443BX/ZX/DX Host bridge (rev 03) 00:01.0 PCI bridge: Intel Corporation 440BX/ZX/DX - 82443BX/ZX/DX AGP bridge (rev 03) 00:02.0 CardBus bridge: Texas Instruments PCI1450 (rev 03) 00:02.1 CardBus bridge: Texas Instruments PCI1450 (rev 03) 00:03.0 Communication controller: Agere Systems WinModem 56k (rev 01) 00:06.0 Multimedia audio controller: Cirrus Logic CS 4614/22/24/30 [CrystalClear SoundFusion Audio Accelerator] (rev 01) 00:07.0 Bridge: Intel Corporation 82371AB/EB/MB PIIX4 ISA (rev 02) 00:07.1 IDE interface: Intel Corporation 82371AB/EB/MB PIIX4 IDE (rev 01) 00:07.2 USB Controller: Intel Corporation 82371AB/EB/MB PIIX4 USB (rev 01) 00:07.3 Bridge: Intel Corporation 82371AB/EB/MB PIIX4 ACPI (rev 03) 01:00.0 VGA compatible controller: Neomagic Corporation NM2360 [MagicMedia 256ZX] 06:00.0 Ethernet controller: Atheros Communications Inc. AR2413 802.11bg NIC (rev 01) --------------------------------------------------------------------------- ------------------------- CPU-Z version 1.48 ------------------------- Processors Map ------------------------------------------------------------------------------------ Number of processors 1 Number of threads 1 Processor 0 -- Core 0 -- Thread 0 Processors Information ------------------------------------------------------------------------------------ Processor 1 (ID = 0) Number of cores 1 (max 1) Number of threads 1 (max 1) Name Intel Pentium III E Codename Coppermine Specification Package MMC (platform ID = 3h) CPUID 6.8.1 Extended CPUID 6.8 Brand ID 2 Core Stepping cA2 Technology 0.18 um Core Speed 498.3 MHz (5.0 x 99.7 MHz) Stock frequency 500 MHz Instructions sets MMX, SSE L1 Data cache 16 KBytes, 4-way set associative, 32-byte line size L1 Instruction cache 16 KBytes, 4-way set associative, 32-byte line size L2 cache 256 KBytes, 8-way set associative, 32-byte line size FID/VID Control no Features Thread dumps ------------------------------------------------------------------------------------ CPU Thread 0 APIC ID 0 Topology Processor ID 0, Core ID 0, Thread ID 0 Type 01000806h Max CPUID level 00000002h Function eax ebx ecx edx 0x00000000 0x00000002 0x756E6547 0x6C65746E 0x49656E69 0x00000001 0x00000681 0x00000002 0x00000000 0x0383F9FF 0x00000002 0x03020101 0x00000000 0x00000000 0x0C040882 Cache descriptor Level 1 D 16 KB 1 thread(s) Cache descriptor Level 1 I 16 KB 1 thread(s) Cache descriptor Level 2 U 256 KB 1 thread(s) MSR 0x00000017 edx = 0x804C0000 eax = 0x00000000 MSR 0x0000002A edx = 0x00000000 eax = 0x4C080020 Chipset ------------------------------------------------------------------------------ Northbridge Intel i440BX/ZX rev. C1 Memory Type SDRAM Memory Size 576 MBytes Memory Frequency 99.7 MHz (1:1) CAS# 3.0 RAS# to CAS# 2 RAS# Precharge 2 DRAM Idle Timer 0 Memory SPD ------------------------------------------------------------------------------ No SPD information available Monitoring ------------------------------------------------------------------------------ Mainboard Model 26454EU (0x19F - 0x44C0F5) PCI Device List ------------------------------------------------------------------------------ Host Bridge bus 0 (0x00), device 0 (0x00), function 0 (0x00) Common header Vendor ID 0x8086 Model ID 0x7190 Revision ID 0x03 PI 0x00 SubClass 0x00 BaseClass 0x06 Cache Line 0x00 Latency 0x40 Header 0x00 PCI header Address 0 (memory) 0x40000000 Subvendor ID 0x0000 Subsystem ID 0x0000 Int. Line 0x00 Int. Pin 0x00 Capabilities AGP Capability Offset A0h Version 1.0 Status disabled Max transfer 2x Queue lenght 1 (max 32) Dump 0 1 2 3 4 5 6 7 8 9 A B C D E F 00 86 80 90 71 06 00 10 A2 03 00 00 06 00 40 00 00 10 08 00 00 40 00 00 00 00 00 00 00 00 00 00 00 00 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30 00 00 00 00 A0 00 00 00 00 00 00 00 00 00 00 00 40 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50 04 08 02 00 00 00 00 09 03 10 11 01 00 00 00 00 60 08 18 28 28 38 48 48 48 00 2A E8 AD 08 AF 00 00 70 20 1F 0A 78 29 0A 03 01 00 37 DC 38 00 00 00 00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90 E0 00 08 00 04 61 00 00 00 05 00 00 00 00 00 00 A0 02 00 10 00 03 02 00 1F 00 00 00 00 00 00 00 00 B0 80 00 00 00 30 00 00 00 00 00 00 00 20 10 00 00 C0 00 00 00 00 00 00 00 00 18 0C E7 7B 79 00 00 00 D0 00 00 00 00 00 00 00 00 0C 00 00 00 00 00 00 00 E0 4C AD FF BB 8A 3E 00 00 2C D3 F7 CF 9D 3E 00 00 F0 00 00 00 00 00 F8 00 60 20 0F 00 00 00 00 00 00 PCI to PCI Bridge bus 0 (0x00), device 1 (0x01), function 0 (0x00) Common header Vendor ID 0x8086 Model ID 0x7191 Revision ID 0x03 PI 0x00 SubClass 0x04 BaseClass 0x06 Cache Line 0x00 Latency 0xA8 Header 0x01 PCI header Primary bus 0x00 Secondary bus 0x01 Int. Line 0x00 Int. Pin 0x00 Dump 0 1 2 3 4 5 6 7 8 9 A B C D E F 00 86 80 91 71 07 00 20 02 03 00 04 06 00 A8 01 00 10 00 00 00 00 00 00 00 00 00 01 01 B0 D0 D0 A0 A2 20 00 70 F0 DF 00 E0 F0 F7 00 00 00 00 00 00 00 00 30 00 00 00 00 00 00 00 00 00 00 00 00 00 00 88 00 40 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 A0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 B0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 C0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 D0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 E0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 F0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 PCI to CardBus Bridge bus 0 (0x00), device 2 (0x02), function 0 (0x00) Common header Vendor ID 0x104C Model ID 0xAC1B Revision ID 0x03 PI 0x00 SubClass 0x07 BaseClass 0x06 Cache Line 0x08 Latency 0xA8 Header 0x82 PCI header Capabilities Power Management Capability Offset A0h Version 1.0 Dump 0 1 2 3 4 5 6 7 8 9 A B C D E F 00 4C 10 1B AC 07 00 10 02 03 00 07 06 08 A8 82 00 10 00 30 10 50 A0 00 00 02 00 02 04 B0 00 F0 DF FF 20 00 F0 DF FF 00 F0 DF FB 00 E0 DF FF 00 FE 00 00 30 FC FE 00 00 00 FD 00 00 FC FD 00 00 0B 01 C0 00 40 14 10 30 01 01 00 00 00 00 00 00 00 00 00 00 00 50 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80 69 90 44 00 00 00 00 00 80 80 81 80 00 10 00 00 90 C0 22 66 41 00 00 00 00 00 00 00 00 00 00 00 00 A0 01 00 11 7E 00 00 C0 00 00 00 00 00 00 00 00 00 B0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 C0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 D0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 E0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 F0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 PCI to CardBus Bridge bus 0 (0x00), device 2 (0x02), function 1 (0x01) Common header Vendor ID 0x104C Model ID 0xAC1B Revision ID 0x03 PI 0x00 SubClass 0x07 BaseClass 0x06 Cache Line 0x08 Latency 0xA8 Header 0x82 PCI header Capabilities Power Management Capability Offset A0h Version 1.0 Dump 0 1 2 3 4 5 6 7 8 9 A B C D E F 00 4C 10 1B AC 07 00 10 02 03 00 07 06 08 A8 82 00 10 00 20 10 50 A0 00 00 22 00 05 07 B0 00 E0 DF FB 20 00 E0 DF FB 00 00 00 6C 00 F0 FF 6F 00 FA 00 00 30 FC FA 00 00 00 F9 00 00 FC F9 00 00 0B 02 00 04 40 14 10 30 01 01 00 00 00 00 00 00 00 00 00 00 00 50 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80 69 B0 44 00 00 00 00 00 80 80 81 80 00 10 00 00 90 C0 23 66 41 00 00 00 00 00 00 00 00 00 00 00 00 A0 01 00 11 7E 00 00 C0 00 00 00 00 00 00 00 00 00 B0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 C0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 D0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 E0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 F0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Communication Device bus 0 (0x00), device 3 (0x03), function 0 (0x00) Common header Vendor ID 0x11C1 Model ID 0x0449 Revision ID 0x01 PI 0x00 SubClass 0x80 BaseClass 0x07 Cache Line 0x00 Latency 0x00 Header 0x00 PCI header Address 0 (memory) 0x50101000 Address 1 (port) 0x00004500 Address 2 (port) 0x00004400 Subvendor ID 0x1014 Subsystem ID 0x018C Int. Line 0x0B Int. Pin 0x01 Capabilities Power Management Capability Offset F8h Version 1.1 Dump 0 1 2 3 4 5 6 7 8 9 A B C D E F 00 C1 11 49 04 07 01 90 82 01 00 80 07 00 00 00 00 10 00 10 10 50 01 45 00 00 01 44 00 00 00 00 00 00 20 00 00 00 00 00 00 00 00 40 00 00 00 14 10 8C 01 30 00 00 00 00 F8 00 00 00 00 00 00 00 0B 01 FC 0E 40 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 50 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 60 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 70 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 80 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 90 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF A0 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF B0 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF C0 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF D0 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF E0 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF F0 FF FF FF FF FF FF FF FF 01 00 22 E4 00 00 00 00 Audio device bus 0 (0x00), device 6 (0x06), function 0 (0x00) Common header Vendor ID 0x1013 Model ID 0x6003 Revision ID 0x01 PI 0x00 SubClass 0x01 BaseClass 0x04 Cache Line 0x00 Latency 0x40 Header 0x00 PCI header Address 0 (memory) 0x50100000 Address 1 (memory) 0x50000000 Subvendor ID 0x1014 Subsystem ID 0x0153 Int. Line 0x0B Int. Pin 0x01 Capabilities Power Management Capability Offset 40h Version 1.1 Dump 0 1 2 3 4 5 6 7 8 9 A B C D E F 00 13 10 03 60 06 01 10 04 01 00 01 04 00 40 00 00 10 00 00 10 50 00 00 00 50 00 00 00 00 00 00 00 00 20 00 00 00 00 00 00 00 00 00 00 00 00 14 10 53 01 30 00 00 00 00 40 00 00 00 00 00 00 00 0B 01 04 18 40 01 00 22 06 00 00 00 00 00 00 00 00 00 00 00 00 50 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 A0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 B0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 C0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 D0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 E0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 F0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Bridge device bus 0 (0x00), device 7 (0x07), function 0 (0x00) Common header Vendor ID 0x8086 Model ID 0x7110 Revision ID 0x02 PI 0x00 SubClass 0x80 BaseClass 0x06 Cache Line 0x00 Latency 0x00 Header 0x80 PCI header Subvendor ID 0x0000 Subsystem ID 0x0000 Int. Line 0x00 Int. Pin 0x00 Dump 0 1 2 3 4 5 6 7 8 9 A B C D E F 00 86 80 10 71 0F 00 80 02 02 00 80 06 00 00 80 00 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40 00 00 00 00 00 00 00 00 00 00 00 00 09 00 27 04 50 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60 0B 0B 0B 0B 90 00 00 00 00 FE 80 00 00 00 00 00 70 00 00 00 00 00 00 0C 0C 00 00 00 00 00 00 00 00 80 00 00 07 00 00 00 00 00 00 00 00 00 00 00 00 00 90 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 A0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 B0 07 81 11 10 00 00 00 00 00 00 00 00 00 00 00 00 C0 00 00 00 00 00 00 00 00 00 00 00 25 00 00 00 00 D0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 E0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 F0 00 00 00 00 00 00 00 00 30 0F 00 00 00 00 00 00 IDE Controller bus 0 (0x00), device 7 (0x07), function 1 (0x01) Common header Vendor ID 0x8086 Model ID 0x7111 Revision ID 0x01 PI 0x80 SubClass 0x01 BaseClass 0x01 Cache Line 0x00 Latency 0x30 Header 0x00 PCI header Address 4 (port) 0x0000FCF0 Subvendor ID 0x0000 Subsystem ID 0x0000 Int. Line 0x00 Int. Pin 0x00 Dump 0 1 2 3 4 5 6 7 8 9 A B C D E F 00 86 80 11 71 05 00 80 02 01 80 01 01 00 30 00 00 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20 F1 FC 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40 07 A3 03 A3 00 00 00 00 05 00 02 02 00 00 00 00 50 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 A0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 B0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 C0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 D0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 E0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 F0 00 00 00 00 00 00 00 00 30 0F 00 00 00 00 00 00 USB Controller (UHCI) bus 0 (0x00), device 7 (0x07), function 2 (0x02) Common header Vendor ID 0x8086 Model ID 0x7112 Revision ID 0x01 PI 0x00 SubClass 0x03 BaseClass 0x0C Cache Line 0x00 Latency 0x30 Header 0x00 PCI header Address 4 (port) 0x00004000 Subvendor ID 0x0000 Subsystem ID 0x0000 Int. Line 0x0B Int. Pin 0x04 Dump 0 1 2 3 4 5 6 7 8 9 A B C D E F 00 86 80 12 71 05 00 80 02 01 00 03 0C 00 30 00 00 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20 01 40 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30 00 00 00 00 00 00 00 00 00 00 00 00 0B 04 00 00 40 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 A0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 B0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 C0 00 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00 D0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 E0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 F0 00 00 00 00 00 00 00 00 30 0F 00 00 00 00 00 01 Bridge device bus 0 (0x00), device 7 (0x07), function 3 (0x03) Common header Vendor ID 0x8086 Model ID 0x7113 Revision ID 0x03 PI 0x00 SubClass 0x80 BaseClass 0x06 Cache Line 0x00 Latency 0x00 Header 0x00 PCI header Subvendor ID 0x0000 Subsystem ID 0x0000 Int. Line 0x00 Int. Pin 0x00 Dump 0 1 2 3 4 5 6 7 8 9 A B C D E F 00 86 80 13 71 03 00 80 02 03 00 80 06 00 00 00 00 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40 01 EF 00 00 80 00 40 10 E1 00 00 00 80 00 10 00 50 00 18 00 00 00 00 00 00 23 00 00 02 00 00 00 90 60 00 00 00 60 E8 15 67 90 00 00 00 00 00 00 00 00 70 00 00 00 00 00 00 00 00 2E 00 11 00 00 00 00 00 80 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90 A1 EF 00 00 00 00 00 00 00 00 00 00 00 00 00 00 A0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 B0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 C0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 D0 00 00 01 00 00 00 00 00 00 00 00 00 00 00 00 00 E0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 F0 00 00 00 00 00 00 00 00 30 0F 00 00 00 00 00 00 VGA Controller bus 1 (0x01), device 0 (0x00), function 0 (0x00) Common header Vendor ID 0x10C8 Model ID 0x0006 Revision ID 0x00 PI 0x00 SubClass 0x00 BaseClass 0x03 Cache Line 0x00 Latency 0x80 Header 0x00 PCI header Address 0 (memory) 0xE0000000 Address 1 (memory) 0x70000000 Address 2 (memory) 0x70400000 Subvendor ID 0x1014 Subsystem ID 0x0152 Int. Line 0x0B Int. Pin 0x01 Capabilities Power Management Capability Offset DCh Version 1.0 Dump 0 1 2 3 4 5 6 7 8 9 A B C D E F 00 C8 10 06 00 07 00 90 02 00 00 00 03 00 80 00 00 10 08 00 00 E0 00 00 00 70 00 00 40 70 00 00 00 00 20 00 00 00 00 00 00 00 00 00 00 00 00 14 10 52 01 30 00 00 00 00 DC 00 00 00 00 00 00 00 0B 01 10 FF 40 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 A0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 B0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 C0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 D0 00 00 00 00 00 00 00 00 00 00 00 00 01 00 21 06 E0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 F0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Ethernet Controller bus 5 (0x05), device 0 (0x00), function 0 (0x00) Common header Vendor ID 0x168C Model ID 0x001A Revision ID 0x01 PI 0x00 SubClass 0x00 BaseClass 0x02 Cache Line 0x08 Latency 0x80 Header 0x00 PCI header Address 0 (memory) 0x6FFF0000 Subvendor ID 0x1799 Subsystem ID 0x701D Int. Line 0x0B Int. Pin 0x01 Capabilities Power Management Capability Offset 44h Version 1.1 Dump 0 1 2 3 4 5 6 7 8 9 A B C D E F 00 8C 16 1A 00 46 03 90 02 01 00 00 02 08 80 00 00 10 00 00 FF 6F 00 00 00 00 00 00 00 00 00 00 00 00 20 00 00 00 00 00 00 00 00 01 50 00 00 99 17 1D 70 30 00 00 00 00 44 00 00 00 00 00 00 00 0B 01 0A 1C 40 80 00 00 00 01 00 C2 01 00 40 00 C6 00 00 00 00 50 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 A0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 B0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 C0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 D0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 E0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 F0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 DMI ------------------------------------------------------------------------------ DMI BIOS -------- vendor IBM version ITET55WW date 11/30/1999 DMI System Information ---------------------- manufacturer IBM product 26454EU version Not Available serial 78HGXB0 UUID F3FCD601-43EB11CB-97ADD94A-C6588F82 DMI Baseboard ------------- vendor IBM model 26454EU revision Not Available serial J1BX1G09427 DMI System Enclosure -------------------- manufacturer IBM chassis type Notebook chassis serial Not Available DMI Processor ------------- manufacturer GenuineIntel model Pentium III FSB speed 100.0 MHz DMI Memory Controller --------------------- correction unknown Max module size 256 MBytes DMI Memory Module ----------------- designation Base Memory size 64 MBytes (single bank) DMI Memory Module ----------------- designation DIMM Slot 1 size 256 MBytes (double bank) DMI Memory Module ----------------- designation DIMM Slot 2 size 256 MBytes (double bank) DMI Port Connector ------------------ designation Not Available (internal) designation Serial (external) port type Serial Port 16550A connector DB-9 male DMI Port Connector ------------------ designation Not Available (internal) designation Parallel (external) port type Parallel Port ECP/EPP connector DB-25 female DMI Port Connector ------------------ designation Not Available (internal) designation PS/2 Mouse (external) port type Mouse Port connector PS/2 DMI Port Connector ------------------ designation Not Available (internal) designation Telephone Jack (external) port type Modem Port connector RJ-11 DMI Port Connector ------------------ designation Not Available (internal) designation Headphone Jack (external) port type Audio Port connector Mini Jack (headphones) DMI Port Connector ------------------ designation Not Available (internal) designation Microphone/Line-In (external) port type Audio Port connector Mini Jack (headphones) DMI Port Connector ------------------ designation Not Available (internal) designation USB (external) port type USB connector Access Bus (USB) DMI Extension Slot ------------------ designation CardBus Slot 1 type PCMCIA width 32 bits populated no DMI Extension Slot ------------------ designation CardBus Slot 2 type PCMCIA width 32 bits populated no DMI Physical Memory Array ------------------------- location Motherboard usage System Memory correction None max capacity 512 MBytes max# of devices 3 DMI Memory Device ----------------- designation DIMM 0 format DIMM type unknown total width 64 bits data width 64 bits size 64 MBytes DMI Memory Device ----------------- designation DIMM 1 format DIMM type unknown total width 64 bits data width 64 bits size 256 MBytes DMI Memory Device ----------------- designation DIMM 2 format DIMM type unknown total width 64 bits data width 64 bits size 256 MBytes Display I2C ------------------------------------------------------------------------------ Software ------------------------------------------------------------------------------ Windows Version Microsoft Windows XP Professional Service Pack 1 (Build 2600) DirectX Version 8.1b Resources ------------------------------------------------------------------------------ Memory I/O Space, BA=0x0000000040000000 Memory I/O Space, BA=0x0000000050103000 Memory I/O Space, BA=0x0000000050102000 Memory I/O Space, BA=0x0000000050101000 Port I/O Space, BA=0x4500 Port I/O Space, BA=0x4400 Memory I/O Space, BA=0x0000000050100000 Memory I/O Space, BA=0x0000000050000000 Port I/O Space, BA=0xFCF0 Port I/O Space, BA=0x4000 Memory I/O Space, BA=0x00000000E0000000 Memory I/O Space, BA=0x0000000070000000 Memory I/O Space, BA=0x0000000070400000 Memory I/O Space, BA=0x000000006FFF0000 Port I/O Space, BA=0xEF08, size=0x4 Port I/O Space, BA=0xEFA0 ------------------------------------------------------------------------------ CPU-Z 1.48 report file Processor(s) Number of processors 1 Number of cores 1 per processor Number of threads 1 per processor Name Intel Pentium III E Code Name Coppermine Specification Package MMC Family/Model/Stepping 6.8.1 Extended Family/Model 6.8 Brand ID 2 Core Stepping cA2 Technology 0.18 um Core Speed 498.3 MHz Multiplier x Bus speed 5.0 x 99.7 MHz Stock frequency 500 MHz Instruction sets MMX, SSE L1 Data cache (per processor) 16 KBytes, 4-way set associative, 32-byte line size L1 Instruction cache (per processor) 16 KBytes, 4-way set associative, 32-byte line size L2 cache (per processor) 256 KBytes, 8-way set associative, 32-byte line size Chipset & Memory Northbridge Intel i440BX/ZX rev. C1 Memory Type SDRAM Memory Size 576 MBytes Memory Frequency 99.7 MHz (1:1) CAS# Latency (tCL) 3.0 clocks RAS# to CAS# (tRCD) 2 clocks RAS# Precharge (tRP) 2 clocks DRAM Idle Timer 0 clocks System System Manufacturer IBM System Name 26454EU System S/N 78HGXB0 Mainboard Vendor IBM Mainboard Model 26454EU BIOS Vendor IBM BIOS Version ITET55WW BIOS Date 11/30/1999 Memory SPD Software Windows Version Microsoft Windows XP Professional Service Pack 1 (Build 2600) DirectX Version 8.1b

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coreboot October 2008