coreboot October 2008

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Re: [coreboot] r954 - in coreboot-v3: device include/device mainboard/amd/dbm690t mainboard/amd/serengeti mainboard/emulation/qemu-x86 northbridge/amd/geodelx southbridge/amd/amd8111 southbridge/amd/rs690 southbridge/amd/sb600 southbridge/intel/i82371eb superio/ite/it8712f superio/winbond/w83627hf
by Uwe Hermann 27 Oct '08

27 Oct '08

On Mon, Oct 27, 2008 at 09:05:38PM +0100, svn(a)coreboot.org wrote: > Modified: coreboot-v3/superio/ite/it8712f/superio.c > =================================================================== > --- coreboot-v3/superio/ite/it8712f/superio.c 2008-10-24 19:26:34 UTC (rev 953) > +++ coreboot-v3/superio/ite/it8712f/superio.c 2008-10-27 20:05:38 UTC (rev 954) > @@ -105,10 +105,10 @@ > static void it8712f_setup_scan_bus(struct device *dev); > > struct device_operations it8712f_ops = { > - .phase2_setup_scan_bus = it8712f_setup_scan_bus, > + .phase3_chip_setup_dev = it8712f_setup_scan_bus, > + .phase3_enable = it8712f_pnp_enable_resources, > .phase4_read_resources = pnp_read_resources, > .phase4_set_resources = it8712f_pnp_set_resources, > - .phase4_enable_disable = it8712f_pnp_enable_resources, > .phase5_enable_resources = it8712f_pnp_enable, > .phase6_init = it8712f_init, > }; > > Modified: coreboot-v3/superio/winbond/w83627hf/superio.c > =================================================================== > --- coreboot-v3/superio/winbond/w83627hf/superio.c 2008-10-24 19:26:34 UTC (rev 953) > +++ coreboot-v3/superio/winbond/w83627hf/superio.c 2008-10-27 20:05:38 UTC (rev 954) > @@ -189,12 +189,12 @@ > pnp_exit_ext_func_mode(dev); > } > } > -static void phase2_setup_scan_bus(struct device *dev); > +static void phase3_chip_setup_dev(struct device *dev); > struct device_operations w83627hf_ops = { > - .phase2_setup_scan_bus = phase2_setup_scan_bus, > + .phase3_chip_setup_dev = phase3_chip_setup_dev, > + .phase3_enable = w83627hf_pnp_enable_resources, > .phase4_read_resources = pnp_read_resources, > .phase4_set_resources = w83627hf_pnp_set_resources, > - .phase4_enable_disable = w83627hf_pnp_enable_resources, > .phase5_enable_resources = w83627hf_pnp_enable, > .phase6_init = w83627hf_init, > }; > @@ -215,7 +215,7 @@ > }; > > > -static void phase2_setup_scan_bus(struct device *dev) > +static void phase3_chip_setup_dev(struct device *dev) > { > pnp_enable_devices(dev, &w83627hf_ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); > } Isn't the same fix required for the other Super I/Os in v3? superio/fintek/f71805f/superio.c superio/ite/it8716f/superio.c Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org

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r954 - in coreboot-v3: device include/device mainboard/amd/dbm690t mainboard/amd/serengeti mainboard/emulation/qemu-x86 northbridge/amd/geodelx southbridge/amd/amd8111 southbridge/amd/rs690 southbridge/amd/sb600 southbridge/intel/i82371eb superio/ite/it8712f superio/winbond/w83627hf
by svn＠coreboot.org 27 Oct '08

27 Oct '08

Author: rminnich Date: 2008-10-27 21:05:38 +0100 (Mon, 27 Oct 2008) New Revision: 954 Modified: coreboot-v3/device/device.c coreboot-v3/device/pci_device.c coreboot-v3/device/pci_rom.c coreboot-v3/device/root_device.c coreboot-v3/include/device/device.h coreboot-v3/mainboard/amd/dbm690t/mainboard.c coreboot-v3/mainboard/amd/serengeti/dts coreboot-v3/mainboard/emulation/qemu-x86/vga.c coreboot-v3/northbridge/amd/geodelx/geodelx.c coreboot-v3/southbridge/amd/amd8111/ac97.c coreboot-v3/southbridge/amd/amd8111/acpi.c coreboot-v3/southbridge/amd/amd8111/ide.c coreboot-v3/southbridge/amd/amd8111/lpc.c coreboot-v3/southbridge/amd/amd8111/nic.c coreboot-v3/southbridge/amd/amd8111/pci.c coreboot-v3/southbridge/amd/amd8111/smbus.c coreboot-v3/southbridge/amd/amd8111/usb.c coreboot-v3/southbridge/amd/amd8111/usb2.c coreboot-v3/southbridge/amd/rs690/gfx.c coreboot-v3/southbridge/amd/rs690/gfx.dts coreboot-v3/southbridge/amd/rs690/ht.c coreboot-v3/southbridge/amd/rs690/pcie.c coreboot-v3/southbridge/amd/sb600/ac97.c coreboot-v3/southbridge/amd/sb600/hda.c coreboot-v3/southbridge/amd/sb600/ide.c coreboot-v3/southbridge/amd/sb600/lpc.c coreboot-v3/southbridge/amd/sb600/pci.c coreboot-v3/southbridge/amd/sb600/sata.c coreboot-v3/southbridge/amd/sb600/sm.c coreboot-v3/southbridge/amd/sb600/usb.c coreboot-v3/southbridge/intel/i82371eb/i82371eb.c coreboot-v3/superio/ite/it8712f/superio.c coreboot-v3/superio/winbond/w83627hf/superio.c Log: Marc reviewed the v3 device tree code and we developed the set of cleanups/fixes. Fixup device tree code. Add/change methods as needed. This should help serengeti. Signed-off-by: Ronald G. Minnich<rminnich(a)gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Corey Osgood <corey.osgood(a)gmail.com> Acked-by: Marc Jones <marc.jones(a)amd.com> Modified: coreboot-v3/device/device.c =================================================================== --- coreboot-v3/device/device.c 2008-10-24 19:26:34 UTC (rev 953) +++ coreboot-v3/device/device.c 2008-10-27 20:05:38 UTC (rev 954) @@ -754,14 +754,14 @@ printk(BIOS_DEBUG, "Phase 2: Early setup...\n"); for (dev = all_devices; dev; dev = dev->next) { printk(BIOS_SPEW, - "%s: dev %s: ops %p ops->phase2_setup_scan_bus %p\n", + "%s: dev %s: ops %p ops->phase2_fixup %p\n", __FUNCTION__, dev->dtsname, dev->ops, - dev->ops? dev->ops->phase2_setup_scan_bus : NULL); - if (dev->ops && dev->ops->phase2_setup_scan_bus) { + dev->ops? dev->ops->phase2_fixup : NULL); + if (dev->ops && dev->ops->phase2_fixup) { printk(BIOS_SPEW, - "Calling phase2 phase2_setup_scan_bus...\n"); - dev->ops->phase2_setup_scan_bus(dev); - printk(BIOS_SPEW, "phase2_setup_scan_bus done\n"); + "Calling phase2 phase2_fixup...\n"); + dev->ops->phase2_fixup(dev); + printk(BIOS_SPEW, "phase2_fixup done\n"); } } @@ -797,14 +797,12 @@ return max; } - if (busdevice->ops->phase3_enable_scan) - busdevice->ops->phase3_enable_scan(busdevice); - do_phase3 = 1; while (do_phase3) { int link; printk(BIOS_INFO, "%s: scanning %s(%s)\n", __FUNCTION__, busdevice->dtsname, dev_path(busdevice)); +#warning do we call phase3_enable here. new_max = busdevice->ops->phase3_scan(busdevice, max); do_phase3 = 0; for (link = 0; link < busdevice->links; link++) { @@ -853,8 +851,8 @@ printk(BIOS_INFO, "Phase 3: Enumerating buses...\n"); root = &dev_root; - if (root->ops && root->ops->phase3_enable_scan) { - root->ops->phase3_enable_scan(root); + if (root->ops && root->ops->phase3_chip_setup_dev) { + root->ops->phase3_chip_setup_dev(root); } post_code(POST_STAGE2_PHASE3_MIDDLE); if (!root->ops) { Modified: coreboot-v3/device/pci_device.c =================================================================== --- coreboot-v3/device/pci_device.c 2008-10-24 19:26:34 UTC (rev 953) +++ coreboot-v3/device/pci_device.c 2008-10-27 20:05:38 UTC (rev 954) @@ -739,7 +739,6 @@ .phase5_enable_resources = pci_dev_enable_resources, .phase6_init = pci_dev_init, .phase3_scan = 0, - .phase4_enable_disable = 0, .ops_pci = &pci_dev_ops_pci, }; @@ -749,12 +748,11 @@ }; struct device_operations default_pci_ops_bus = { + .phase3_scan = pci_scan_bridge, .phase4_read_resources = pci_bus_read_resources, .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = pci_bus_enable_resources, .phase6_init = 0, - .phase3_scan = pci_scan_bridge, - .phase4_enable_disable = 0, .reset_bus = pci_bus_reset, .ops_pci = &pci_bus_ops_pci, }; @@ -1006,8 +1004,8 @@ * it may be absent and enable_dev() must cope. */ /* Run the magic enable sequence for the device. */ - if (dev->ops && dev->ops->phase3_enable_scan) { - dev->ops->phase3_enable_scan(dev); + if (dev->ops && dev->ops->phase3_chip_setup_dev) { + dev->ops->phase3_chip_setup_dev(dev); } /* Now read the vendor and device ID. */ id = pci_read_config32(dev, PCI_VENDOR_ID); @@ -1062,8 +1060,8 @@ set_pci_ops(dev); /* Now run the magic enable/disable sequence for the device. */ - if (dev->ops && dev->ops->phase4_enable_disable) { - dev->ops->phase4_enable_disable(dev); + if (dev->ops && dev->ops->phase3_enable) { + dev->ops->phase3_enable(dev); } /* Display the device and error if we don't have some PCI operations Modified: coreboot-v3/device/pci_rom.c =================================================================== --- coreboot-v3/device/pci_rom.c 2008-10-24 19:26:34 UTC (rev 953) +++ coreboot-v3/device/pci_rom.c 2008-10-27 20:05:38 UTC (rev 954) @@ -108,7 +108,8 @@ rom_data = (struct pci_data *)((unsigned char *)rom_header + le32_to_cpu(rom_header->data)); - printk(BIOS_SPEW, "PCI ROM Image, Vendor %04x, Device %04x,\n", + printk(BIOS_SPEW, "PCI ROM Image, @%p, Vendor %04x, Device %04x,\n", + &rom_data->vendor, rom_data->vendor, rom_data->device); if (dev->id.pci.vendor != rom_data->vendor || dev->id.pci.device != rom_data->device) { printk(BIOS_ERR, Modified: coreboot-v3/device/root_device.c =================================================================== --- coreboot-v3/device/root_device.c 2008-10-24 19:26:34 UTC (rev 953) +++ coreboot-v3/device/root_device.c 2008-10-27 20:05:38 UTC (rev 954) @@ -119,12 +119,12 @@ } for (child = busdevice->link[link].children; child; child = child->sibling) { - if (child->ops && child->ops->phase3_enable_scan) { - child->ops->phase3_enable_scan(child); + if (child->ops && child->ops->phase3_chip_setup_dev) { + child->ops->phase3_chip_setup_dev(child); } /* Sigh. Have to enable to scan... */ - if (child->ops && child->ops->phase5_enable_resources) { - child->ops->phase5_enable_resources(child); + if (child->ops && child->ops->phase3_enable) { + child->ops->phase3_enable(child); } if (child->path.type == DEVICE_PATH_I2C) { printk(BIOS_DEBUG, "smbus: %s(%s)[%d]->", @@ -217,11 +217,11 @@ * mainboard directory. */ struct device_operations default_dev_ops_root = { + .phase3_scan = root_dev_scan_bus, .phase4_read_resources = root_dev_read_resources, .phase4_set_resources = root_dev_set_resources, .phase5_enable_resources = root_dev_enable_resources, .phase6_init = root_dev_init, - .phase3_scan = root_dev_scan_bus, .reset_bus = root_dev_reset, }; Modified: coreboot-v3/include/device/device.h =================================================================== --- coreboot-v3/include/device/device.h 2008-10-24 19:26:34 UTC (rev 953) +++ coreboot-v3/include/device/device.h 2008-10-27 20:05:38 UTC (rev 954) @@ -143,19 +143,19 @@ void (*phase1_set_device_operations)(struct device *dev); /* phase 2 is for any magic you have to do before the busses are scanned */ - void (*phase2_setup_scan_bus)(struct device * dev); + void (*phase2_fixup)(struct device * dev); /* phase 3 is for scanning the bus, if needed. */ - void (*phase3_enable_scan)(struct device *dev); + void (*phase3_chip_setup_dev)(struct device *dev); + /* some devices need to be enabled to scan. */ + /* this function enables/disables according the value of 'enabled' in the device*/ + void (*phase3_enable)(struct device * dev); unsigned int (*phase3_scan)(struct device * bus, unsigned int max); /* typically used by phase4 */ /* again, if we never use this anywhere else, we may change the names */ void (*phase4_read_resources)(struct device * dev); void (*phase4_set_resources)(struct device * dev); - /* some devices need to be enabled to scan, then disabled again. */ - /* this function enables/disables according the value of 'enabled' in the device*/ - void (*phase4_enable_disable)(struct device * dev); /* phase 5: enable devices */ void (*phase5_enable_resources)(struct device * dev); Modified: coreboot-v3/mainboard/amd/dbm690t/mainboard.c =================================================================== --- coreboot-v3/mainboard/amd/dbm690t/mainboard.c 2008-10-24 19:26:34 UTC (rev 953) +++ coreboot-v3/mainboard/amd/dbm690t/mainboard.c 2008-10-27 20:05:38 UTC (rev 954) @@ -129,5 +129,5 @@ {.pci = {.vendor = PCI_VENDOR_ID_AMD, .device = 1}}}, .constructor = default_device_constructor, - .phase3_enable_scan = dbm690t_enable, + .phase3_chip_setup_dev = dbm690t_enable, }; Modified: coreboot-v3/mainboard/amd/serengeti/dts =================================================================== --- coreboot-v3/mainboard/amd/serengeti/dts 2008-10-24 19:26:34 UTC (rev 953) +++ coreboot-v3/mainboard/amd/serengeti/dts 2008-10-27 20:05:38 UTC (rev 954) @@ -46,7 +46,6 @@ /config/("southbridge/amd/amd8111/usb2.dts"); }; pci@4,0{ - rom_address = "0xfc000000"; }; }; pci@7,0 { Modified: coreboot-v3/mainboard/emulation/qemu-x86/vga.c =================================================================== --- coreboot-v3/mainboard/emulation/qemu-x86/vga.c 2008-10-24 19:26:34 UTC (rev 953) +++ coreboot-v3/mainboard/emulation/qemu-x86/vga.c 2008-10-27 20:05:38 UTC (rev 954) @@ -40,6 +40,8 @@ * but since QEMU has no Super I/O... */ init_pc_keyboard(0x60, 0x64, &conf); + /* now run the rom */ + pci_dev_init(dev); } struct device_operations qemuvga_pci_ops_dev = { @@ -50,9 +52,8 @@ .phase3_scan = 0, .phase4_read_resources = pci_dev_read_resources, .phase4_set_resources = pci_dev_set_resources, - .phase4_enable_disable = setup_onboard, .phase5_enable_resources = pci_dev_enable_resources, - .phase6_init = pci_dev_init, + .phase6_init = setup_onboard, .ops_pci = &pci_dev_ops_pci, }; Modified: coreboot-v3/northbridge/amd/geodelx/geodelx.c =================================================================== --- coreboot-v3/northbridge/amd/geodelx/geodelx.c 2008-10-24 19:26:34 UTC (rev 953) +++ coreboot-v3/northbridge/amd/geodelx/geodelx.c 2008-10-27 20:05:38 UTC (rev 954) @@ -227,7 +227,7 @@ {.pci_domain = {.vendor = PCI_VENDOR_ID_AMD, .device = PCI_DEVICE_ID_AMD_LXBRIDGE}}}, .constructor = default_device_constructor, - .phase2_setup_scan_bus = geodelx_pci_domain_phase2, + .phase2_fixup = geodelx_pci_domain_phase2, .phase3_scan = pci_domain_scan_bus, .phase4_read_resources = pci_domain_read_resources, .phase4_set_resources = geodelx_pci_domain_set_resources, Modified: coreboot-v3/southbridge/amd/amd8111/ac97.c =================================================================== --- coreboot-v3/southbridge/amd/amd8111/ac97.c 2008-10-24 19:26:34 UTC (rev 953) +++ coreboot-v3/southbridge/amd/amd8111/ac97.c 2008-10-27 20:05:38 UTC (rev 954) @@ -44,7 +44,7 @@ .device = 0x746D}}}, .constructor = default_device_constructor, .phase3_scan = 0, - .phase4_enable_disable = amd8111_enable, + .phase3_chip_setup_dev = amd8111_enable, .phase4_read_resources = pci_dev_read_resources, .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = pci_dev_enable_resources, @@ -58,7 +58,7 @@ .device = 0x746E}}}, .constructor = default_device_constructor, .phase3_scan = 0, - .phase4_enable_disable = amd8111_enable, + .phase3_chip_setup_dev = amd8111_enable, .phase4_read_resources = pci_dev_read_resources, .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = pci_dev_enable_resources, Modified: coreboot-v3/southbridge/amd/amd8111/acpi.c =================================================================== --- coreboot-v3/southbridge/amd/amd8111/acpi.c 2008-10-24 19:26:34 UTC (rev 953) +++ coreboot-v3/southbridge/amd/amd8111/acpi.c 2008-10-27 20:05:38 UTC (rev 954) @@ -231,7 +231,7 @@ .device = PCI_DEVICE_ID_AMD_8111_ACPI}}}, .constructor = default_device_constructor, .phase3_scan = scan_static_bus, - .phase4_enable_disable = amd8111_enable, + .phase3_chip_setup_dev = amd8111_enable, .phase4_read_resources = acpi_read_resources, .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = acpi_enable_resources, Modified: coreboot-v3/southbridge/amd/amd8111/ide.c =================================================================== --- coreboot-v3/southbridge/amd/amd8111/ide.c 2008-10-24 19:26:34 UTC (rev 953) +++ coreboot-v3/southbridge/amd/amd8111/ide.c 2008-10-27 20:05:38 UTC (rev 954) @@ -78,7 +78,7 @@ .device = PCI_DEVICE_ID_AMD_8111_IDE}}}, .constructor = default_device_constructor, .phase3_scan = 0, - .phase4_enable_disable = amd8111_enable, + .phase3_chip_setup_dev = amd8111_enable, .phase4_read_resources = pci_dev_read_resources, .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = pci_dev_enable_resources, Modified: coreboot-v3/southbridge/amd/amd8111/lpc.c =================================================================== --- coreboot-v3/southbridge/amd/amd8111/lpc.c 2008-10-24 19:26:34 UTC (rev 953) +++ coreboot-v3/southbridge/amd/amd8111/lpc.c 2008-10-27 20:05:38 UTC (rev 954) @@ -213,7 +213,7 @@ .device = PCI_DEVICE_ID_AMD_8111_ISA}}}, .constructor = default_device_constructor, .phase3_scan = scan_static_bus, - .phase4_enable_disable = amd8111_enable, + .phase3_chip_setup_dev = amd8111_enable, .phase4_read_resources = amd8111_lpc_read_resources, .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = amd8111_lpc_enable_resources, Modified: coreboot-v3/southbridge/amd/amd8111/nic.c =================================================================== --- coreboot-v3/southbridge/amd/amd8111/nic.c 2008-10-24 19:26:34 UTC (rev 953) +++ coreboot-v3/southbridge/amd/amd8111/nic.c 2008-10-27 20:05:38 UTC (rev 954) @@ -99,7 +99,7 @@ .device = PCI_DEVICE_ID_AMD_8111_NIC}}}, .constructor = default_device_constructor, .phase3_scan = 0, - .phase4_enable_disable = amd8111_enable, + .phase3_chip_setup_dev = amd8111_enable, .phase4_read_resources = pci_dev_read_resources, .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = pci_dev_enable_resources, Modified: coreboot-v3/southbridge/amd/amd8111/pci.c =================================================================== --- coreboot-v3/southbridge/amd/amd8111/pci.c 2008-10-24 19:26:34 UTC (rev 953) +++ coreboot-v3/southbridge/amd/amd8111/pci.c 2008-10-27 20:05:38 UTC (rev 954) @@ -75,7 +75,7 @@ .device = PCI_DEVICE_ID_AMD_8111_PCI}}}, .constructor = default_device_constructor, .phase3_scan = pci_scan_bridge, - .phase4_enable_disable = amd8111_enable, + .phase3_chip_setup_dev = amd8111_enable, .phase4_read_resources = pci_bus_read_resources, .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = pci_bus_enable_resources, Modified: coreboot-v3/southbridge/amd/amd8111/smbus.c =================================================================== --- coreboot-v3/southbridge/amd/amd8111/smbus.c 2008-10-24 19:26:34 UTC (rev 953) +++ coreboot-v3/southbridge/amd/amd8111/smbus.c 2008-10-27 20:05:38 UTC (rev 954) @@ -53,7 +53,7 @@ .device = PCI_DEVICE_ID_AMD_8111_SMB}}}, .constructor = default_device_constructor, .phase3_scan = scan_static_bus, - .phase4_enable_disable = amd8111_enable, + .phase3_chip_setup_dev = amd8111_enable, .phase4_read_resources = pci_dev_read_resources, .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = pci_dev_enable_resources, Modified: coreboot-v3/southbridge/amd/amd8111/usb.c =================================================================== --- coreboot-v3/southbridge/amd/amd8111/usb.c 2008-10-24 19:26:34 UTC (rev 953) +++ coreboot-v3/southbridge/amd/amd8111/usb.c 2008-10-27 20:05:38 UTC (rev 954) @@ -50,7 +50,7 @@ .device = PCI_DEVICE_ID_AMD_8111_USB}}}, .constructor = default_device_constructor, .phase3_scan = scan_static_bus, - .phase4_enable_disable = amd8111_enable, + .phase3_chip_setup_dev = amd8111_enable, .phase4_read_resources = pci_dev_read_resources, .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = pci_dev_enable_resources, Modified: coreboot-v3/southbridge/amd/amd8111/usb2.c =================================================================== --- coreboot-v3/southbridge/amd/amd8111/usb2.c 2008-10-24 19:26:34 UTC (rev 953) +++ coreboot-v3/southbridge/amd/amd8111/usb2.c 2008-10-27 20:05:38 UTC (rev 954) @@ -49,7 +49,7 @@ .device = PCI_DEVICE_ID_AMD_8111_USB}}}, .constructor = default_device_constructor, .phase3_scan = scan_static_bus, - .phase4_enable_disable = amd8111_usb2_enable, + .phase3_chip_setup_dev = amd8111_usb2_enable, .phase4_read_resources = pci_dev_read_resources, .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = pci_dev_enable_resources, Modified: coreboot-v3/southbridge/amd/rs690/gfx.c =================================================================== --- coreboot-v3/southbridge/amd/rs690/gfx.c 2008-10-24 19:26:34 UTC (rev 953) +++ coreboot-v3/southbridge/amd/rs690/gfx.c 2008-10-27 20:05:38 UTC (rev 954) @@ -79,13 +79,9 @@ struct southbridge_amd_rs690_gfx_config *cfg = dev->device_configuration; deviceid = pci_read_config16(dev, PCI_DEVICE_ID); vendorid = pci_read_config16(dev, PCI_VENDOR_ID); - printk(BIOS_INFO, "internal_gfx_pci_dev_init device=%x, vendor=%x, vga_rom_address=0x%x.\n", + printk(BIOS_INFO, "internal_gfx_pci_dev_init device=%x, vendor=%x, vga_rom_address=0x%lx.\n", deviceid, vendorid, cfg->vga_rom_address); -#if 0 /* I think these should be done in Config.lb. Please check it. */ - dev->on_mainboard = 1; - dev->rom_address = cfg->vga_rom_address; /* 0xfff00000; */ -#endif pci_dev_init(dev); /* clk ind */ @@ -569,9 +565,9 @@ {.pci = {.vendor = PCI_VENDOR_ID_ATI, .device = PCI_DEVICE_ID_ATI_RS690MT_INT_GFX}}}, .constructor = default_device_constructor, - .phase2_setup_scan_bus = rs690_internal_gfx_enable, + .phase3_chip_setup_dev = rs690_enable, + .phase3_enable = rs690_internal_gfx_enable, .phase3_scan = 0, - .phase4_enable_disable = rs690_enable, .phase4_read_resources = rs690_gfx_read_resources, .phase4_set_resources = rs690_gfx_set_resources, .phase5_enable_resources = pci_dev_enable_resources, Modified: coreboot-v3/southbridge/amd/rs690/gfx.dts =================================================================== --- coreboot-v3/southbridge/amd/rs690/gfx.dts 2008-10-24 19:26:34 UTC (rev 953) +++ coreboot-v3/southbridge/amd/rs690/gfx.dts 2008-10-27 20:05:38 UTC (rev 954) @@ -33,7 +33,7 @@ */ { device_operations = "rs690_gfx"; - vga_rom_address = "0xfff00000"; /* The location that the VGA rom has been appened. */ + vga_rom_address = "0xfff0000"; gfx_dev2_dev3 = "1"; /* for GFX Core initialization REFCLK_SEL */ gfx_dual_slot = "0"; /* Is it dual graphics slots */ gfx_lane_reversal = "0"; /* Single/Dual slot lan reversal */ Modified: coreboot-v3/southbridge/amd/rs690/ht.c =================================================================== --- coreboot-v3/southbridge/amd/rs690/ht.c 2008-10-24 19:26:34 UTC (rev 953) +++ coreboot-v3/southbridge/amd/rs690/ht.c 2008-10-27 20:05:38 UTC (rev 954) @@ -85,9 +85,8 @@ {.pci = {.vendor = PCI_VENDOR_ID_ATI, .device = PCI_DEVICE_ID_ATI_RS690_HT}}}, .constructor = default_device_constructor, - .phase2_setup_scan_bus = rs690_enable, .phase3_scan = 0, - .phase4_enable_disable = rs690_enable, + .phase3_chip_setup_dev = rs690_enable, .phase4_read_resources = pci_dev_read_resources, .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = pci_dev_enable_resources, Modified: coreboot-v3/southbridge/amd/rs690/pcie.c =================================================================== --- coreboot-v3/southbridge/amd/rs690/pcie.c 2008-10-24 19:26:34 UTC (rev 953) +++ coreboot-v3/southbridge/amd/rs690/pcie.c 2008-10-27 20:05:38 UTC (rev 954) @@ -400,7 +400,7 @@ .device = PCI_DEVICE_ID_ATI_RS690_PCIE}}}, .constructor = default_device_constructor, .phase3_scan = pci_scan_bridge, - .phase4_enable_disable = rs690_enable, + .phase3_chip_setup_dev = rs690_enable, .phase4_read_resources = pci_bus_read_resources, .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = pci_bus_enable_resources, Modified: coreboot-v3/southbridge/amd/sb600/ac97.c =================================================================== --- coreboot-v3/southbridge/amd/sb600/ac97.c 2008-10-24 19:26:34 UTC (rev 953) +++ coreboot-v3/southbridge/amd/sb600/ac97.c 2008-10-27 20:05:38 UTC (rev 954) @@ -38,7 +38,7 @@ .device = PCI_DEVICE_ID_ATI_SB600_ACI}}}, .constructor = default_device_constructor, .phase3_scan = 0, - .phase4_enable_disable = sb600_enable, + .phase3_chip_setup_dev = sb600_enable, .phase4_read_resources = pci_dev_read_resources, .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = pci_dev_enable_resources, @@ -52,7 +52,7 @@ .device = PCI_DEVICE_ID_ATI_SB600_MCI}}}, .constructor = default_device_constructor, .phase3_scan = 0, - .phase4_enable_disable = sb600_enable, + .phase3_chip_setup_dev = sb600_enable, .phase4_read_resources = pci_dev_read_resources, .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = pci_dev_enable_resources, Modified: coreboot-v3/southbridge/amd/sb600/hda.c =================================================================== --- coreboot-v3/southbridge/amd/sb600/hda.c 2008-10-24 19:26:34 UTC (rev 953) +++ coreboot-v3/southbridge/amd/sb600/hda.c 2008-10-27 20:05:38 UTC (rev 954) @@ -279,7 +279,7 @@ {.pci = {.vendor = PCI_VENDOR_ID_ATI, .device = PCI_DEVICE_ID_ATI_SB600_HDA}}}, .constructor = default_device_constructor, - .phase4_enable_disable = sb600_enable, + .phase3_chip_setup_dev = sb600_enable, .phase4_read_resources = pci_dev_read_resources, .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = pci_dev_enable_resources, Modified: coreboot-v3/southbridge/amd/sb600/ide.c =================================================================== --- coreboot-v3/southbridge/amd/sb600/ide.c 2008-10-24 19:26:34 UTC (rev 953) +++ coreboot-v3/southbridge/amd/sb600/ide.c 2008-10-27 20:05:38 UTC (rev 954) @@ -70,7 +70,7 @@ {.pci = {.vendor = PCI_VENDOR_ID_ATI, .device = PCI_DEVICE_ID_ATI_SB600_IDE}}}, .constructor = default_device_constructor, - .phase4_enable_disable = sb600_enable, + .phase3_chip_setup_dev = sb600_enable, .phase4_read_resources = pci_dev_read_resources, .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = pci_dev_enable_resources, Modified: coreboot-v3/southbridge/amd/sb600/lpc.c =================================================================== --- coreboot-v3/southbridge/amd/sb600/lpc.c 2008-10-24 19:26:34 UTC (rev 953) +++ coreboot-v3/southbridge/amd/sb600/lpc.c 2008-10-27 20:05:38 UTC (rev 954) @@ -213,7 +213,7 @@ .device = PCI_DEVICE_ID_ATI_SB600_LPC}}}, .constructor = default_device_constructor, .phase3_scan = scan_static_bus, - .phase4_enable_disable = sb600_enable, + .phase3_chip_setup_dev = sb600_enable, .phase4_read_resources = sb600_lpc_read_resources, .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = sb600_lpc_enable_resources, Modified: coreboot-v3/southbridge/amd/sb600/pci.c =================================================================== --- coreboot-v3/southbridge/amd/sb600/pci.c 2008-10-24 19:26:34 UTC (rev 953) +++ coreboot-v3/southbridge/amd/sb600/pci.c 2008-10-27 20:05:38 UTC (rev 954) @@ -130,7 +130,7 @@ .device = PCI_DEVICE_ID_ATI_SB600_PCI}}}, .constructor = default_device_constructor, .phase3_scan = pci_scan_bridge, - .phase4_enable_disable = sb600_enable, + .phase3_chip_setup_dev = sb600_enable, .phase4_read_resources = pci_bus_read_resources, .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = pci_bus_enable_resources, Modified: coreboot-v3/southbridge/amd/sb600/sata.c =================================================================== --- coreboot-v3/southbridge/amd/sb600/sata.c 2008-10-24 19:26:34 UTC (rev 953) +++ coreboot-v3/southbridge/amd/sb600/sata.c 2008-10-27 20:05:38 UTC (rev 954) @@ -192,7 +192,7 @@ {.pci = {.vendor = PCI_VENDOR_ID_ATI, .device = PCI_DEVICE_ID_ATI_SB600_SATA}}}, .constructor = default_device_constructor, - .phase4_enable_disable = sb600_enable, + .phase3_chip_setup_dev = sb600_enable, .phase4_read_resources = pci_dev_read_resources, .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = pci_dev_enable_resources, Modified: coreboot-v3/southbridge/amd/sb600/sm.c =================================================================== --- coreboot-v3/southbridge/amd/sb600/sm.c 2008-10-24 19:26:34 UTC (rev 953) +++ coreboot-v3/southbridge/amd/sb600/sm.c 2008-10-27 20:05:38 UTC (rev 954) @@ -395,7 +395,7 @@ .device = PCI_DEVICE_ID_ATI_SB600_SM}}}, .constructor = default_device_constructor, .phase3_scan = 0, - .phase4_enable_disable = sb600_enable, + .phase3_chip_setup_dev = sb600_enable, .phase4_read_resources = sb600_sm_read_resources, .phase4_set_resources = sb600_sm_set_resources, .phase5_enable_resources = pci_dev_enable_resources, Modified: coreboot-v3/southbridge/amd/sb600/usb.c =================================================================== --- coreboot-v3/southbridge/amd/sb600/usb.c 2008-10-24 19:26:34 UTC (rev 953) +++ coreboot-v3/southbridge/amd/sb600/usb.c 2008-10-27 20:05:38 UTC (rev 954) @@ -205,7 +205,7 @@ .device = PCI_DEVICE_ID_ATI_SB600_USB2}}}, .constructor = default_device_constructor, .phase3_scan = scan_static_bus, - .phase4_enable_disable = sb600_enable, + .phase3_chip_setup_dev = sb600_enable, .phase4_read_resources = pci_dev_read_resources, .phase4_set_resources = usb_set_resources, .phase5_enable_resources = pci_dev_enable_resources, Modified: coreboot-v3/southbridge/intel/i82371eb/i82371eb.c =================================================================== --- coreboot-v3/southbridge/intel/i82371eb/i82371eb.c 2008-10-24 19:26:34 UTC (rev 953) +++ coreboot-v3/southbridge/intel/i82371eb/i82371eb.c 2008-10-27 20:05:38 UTC (rev 954) @@ -90,7 +90,6 @@ .phase3_scan = 0, .phase4_read_resources = pci_dev_read_resources, .phase4_set_resources = pci_dev_set_resources, - .phase4_enable_disable = 0, .phase5_enable_resources = pci_dev_enable_resources, .phase6_init = i82371eb_isa_init, .ops_pci = &pci_dev_ops_pci, @@ -103,7 +102,6 @@ .phase3_scan = 0, .phase4_read_resources = pci_dev_read_resources, .phase4_set_resources = pci_dev_set_resources, - .phase4_enable_disable = 0, .phase5_enable_resources = pci_dev_enable_resources, .phase6_init = i82371eb_ide_init, .ops_pci = &pci_dev_ops_pci, @@ -116,7 +114,6 @@ .phase3_scan = 0, .phase4_read_resources = pci_dev_read_resources, .phase4_set_resources = pci_dev_set_resources, - .phase4_enable_disable = 0, .phase5_enable_resources = pci_dev_enable_resources, .phase6_init = i82371eb_acpi_init, .ops_pci = &pci_dev_ops_pci, Modified: coreboot-v3/superio/ite/it8712f/superio.c =================================================================== --- coreboot-v3/superio/ite/it8712f/superio.c 2008-10-24 19:26:34 UTC (rev 953) +++ coreboot-v3/superio/ite/it8712f/superio.c 2008-10-27 20:05:38 UTC (rev 954) @@ -105,10 +105,10 @@ static void it8712f_setup_scan_bus(struct device *dev); struct device_operations it8712f_ops = { - .phase2_setup_scan_bus = it8712f_setup_scan_bus, + .phase3_chip_setup_dev = it8712f_setup_scan_bus, + .phase3_enable = it8712f_pnp_enable_resources, .phase4_read_resources = pnp_read_resources, .phase4_set_resources = it8712f_pnp_set_resources, - .phase4_enable_disable = it8712f_pnp_enable_resources, .phase5_enable_resources = it8712f_pnp_enable, .phase6_init = it8712f_init, }; Modified: coreboot-v3/superio/winbond/w83627hf/superio.c =================================================================== --- coreboot-v3/superio/winbond/w83627hf/superio.c 2008-10-24 19:26:34 UTC (rev 953) +++ coreboot-v3/superio/winbond/w83627hf/superio.c 2008-10-27 20:05:38 UTC (rev 954) @@ -189,12 +189,12 @@ pnp_exit_ext_func_mode(dev); } } -static void phase2_setup_scan_bus(struct device *dev); +static void phase3_chip_setup_dev(struct device *dev); struct device_operations w83627hf_ops = { - .phase2_setup_scan_bus = phase2_setup_scan_bus, + .phase3_chip_setup_dev = phase3_chip_setup_dev, + .phase3_enable = w83627hf_pnp_enable_resources, .phase4_read_resources = pnp_read_resources, .phase4_set_resources = w83627hf_pnp_set_resources, - .phase4_enable_disable = w83627hf_pnp_enable_resources, .phase5_enable_resources = w83627hf_pnp_enable, .phase6_init = w83627hf_init, }; @@ -215,7 +215,7 @@ }; -static void phase2_setup_scan_bus(struct device *dev) +static void phase3_chip_setup_dev(struct device *dev) { pnp_enable_devices(dev, &w83627hf_ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); }

1 0

nvramtool in Debian unstable
by Uwe Hermann 27 Oct '08

27 Oct '08

Hi, just FYI, I've uploaded an nvramtool package to Debian unstable, so you can now get it via $ apt-get install nvramtool on Debian (and soon other derivates such as Ubuntu). http://packages.qa.debian.org/n/nvramtool.html Cheers, Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org

1 0

[PATCH] v2: Original import for mainboard msi/ms6147
by Mats Erik Andersson 27 Oct '08

27 Oct '08

Action: First import of code basis for mainboard msi/ms6147. Most files are taken unchange for chipset i440bx/i371eb, but decisive changes have gone into raminit.c and debug.c, which are thus positioned in the mainboard directory. Mainboard is booting with dynamic memory detection. Signed-by: Mats Erik Andersson <mats.andersson(a)gisladisker.org> --- My main contribution is to implement a functional detection of populated RAM slots. The code has proven its ability to detect, configure, and successfully initialize memory ranging from 16MB+16MB in one slot, up to 64MB+64MB+64MB+64MB in two slots. The mainboard has only two SDRAM slots, but the code is able to work with one to four slots. Best regards Mats Erik Andersson

4 4

r3695 - in trunk/coreboot-v2: src/mainboard/msi src/mainboard/msi/ms6147 targets/msi targets/msi/ms6147
by svn＠coreboot.org 27 Oct '08

27 Oct '08

Author: uwe Date: 2008-10-27 14:44:07 +0100 (Mon, 27 Oct 2008) New Revision: 3695 Added: trunk/coreboot-v2/src/mainboard/msi/ms6147/ trunk/coreboot-v2/src/mainboard/msi/ms6147/Config.lb trunk/coreboot-v2/src/mainboard/msi/ms6147/Options.lb trunk/coreboot-v2/src/mainboard/msi/ms6147/auto.c trunk/coreboot-v2/src/mainboard/msi/ms6147/chip.h trunk/coreboot-v2/src/mainboard/msi/ms6147/irq_tables.c trunk/coreboot-v2/src/mainboard/msi/ms6147/mainboard.c trunk/coreboot-v2/targets/msi/ms6147/ trunk/coreboot-v2/targets/msi/ms6147/Config.lb Log: Add initial support for the MSI MS-6147 mainboard. Signed-off-by: Mats Erik Andersson <mats.andersson(a)gisladisker.org> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Added: trunk/coreboot-v2/src/mainboard/msi/ms6147/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms6147/Config.lb (rev 0) +++ trunk/coreboot-v2/src/mainboard/msi/ms6147/Config.lb 2008-10-27 13:44:07 UTC (rev 3695) @@ -0,0 +1,153 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2008 Mats Erik Andersson <mats.andersson(a)gisladisker.org> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +if USE_FALLBACK_IMAGE + default ROM_SECTION_SIZE = FALLBACK_SIZE + default ROM_SECTION_OFFSET = (ROM_SIZE - FALLBACK_SIZE) +else + default ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE) + default ROM_SECTION_OFFSET = 0 +end + +default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) +default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE) + +default _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE) + +default XIP_ROM_SIZE = 64 * 1024 +default XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE) + +arch i386 end +driver mainboard.o + +if HAVE_PIRQ_TABLE + object irq_tables.o +end + +makerule ./failover.E + depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" +end +makerule ./failover.inc + depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" +end +makerule ./auto.E + # depends "$(MAINBOARD)/auto.c option_table.h ../romcc" + depends "$(MAINBOARD)/auto.c ../romcc" + action "../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" +end +makerule ./auto.inc + # depends "$(MAINBOARD)/auto.c option_table.h ../romcc" + depends "$(MAINBOARD)/auto.c ../romcc" + action "../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" +end + +mainboardinit cpu/x86/16bit/entry16.inc +mainboardinit cpu/x86/32bit/entry32.inc +ldscript /cpu/x86/16bit/entry16.lds +ldscript /cpu/x86/32bit/entry32.lds + +if USE_FALLBACK_IMAGE + mainboardinit cpu/x86/16bit/reset16.inc + ldscript /cpu/x86/16bit/reset16.lds +else + mainboardinit cpu/x86/32bit/reset32.inc + ldscript /cpu/x86/32bit/reset32.lds +end + +mainboardinit arch/i386/lib/cpu_reset.inc + +mainboardinit arch/i386/lib/id.inc +ldscript /arch/i386/lib/id.lds + +if USE_FALLBACK_IMAGE + ldscript /arch/i386/lib/failover.lds + mainboardinit ./failover.inc +end + +mainboardinit cpu/x86/fpu/enable_fpu.inc +mainboardinit cpu/x86/mmx/enable_mmx.inc +mainboardinit ./auto.inc +mainboardinit cpu/x86/mmx/disable_mmx.inc + +dir /pc80 +config chip.h + +chip northbridge/intel/i440bx # Northbridge + device apic_cluster 0 on # APIC cluster + chip cpu/intel/slot_2 # CPU (FIXME: It's slot 1, actually) + device apic 0 on end # APIC + end + end + device pci_domain 0 on # PCI domain + device pci 0.0 on end # Host bridge + device pci 1.0 on end # PCI/AGP bridge + chip southbridge/intel/i82371eb # Southbridge + device pci 7.0 on # ISA bridge + chip superio/winbond/w83977tf # Super I/O + device pnp 3f0.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 3f0.1 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + drq 0x74 = 3 + end + device pnp 3f0.2 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 3f0.3 on # COM2 / IR + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 3f0.5 on # PS/2 keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 # PS/2 keyboard interrupt + irq 0x72 = 12 # PS/2 mouse interrupt + end + device pnp 3f0.7 on # GPIO 1 + end + device pnp 3f0.8 on # GPIO 2 + end + device pnp 3f0.9 off # GPIO 3 + end + device pnp 3f0.a on # ACPI + end + end + end + device pci 7.1 on end # IDE + device pci 7.2 on end # USB + device pci 7.3 on end # ACPI + register "ide0_enable" = "1" + register "ide1_enable" = "1" + register "ide_legacy_enable" = "1" + # Enable UDMA/33 for higher speed if your IDE device(s) support it. + register "ide0_drive0_udma33_enable" = "1" + register "ide0_drive1_udma33_enable" = "1" + register "ide1_drive0_udma33_enable" = "1" + register "ide1_drive1_udma33_enable" = "1" + end + end +end Added: trunk/coreboot-v2/src/mainboard/msi/ms6147/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms6147/Options.lb (rev 0) +++ trunk/coreboot-v2/src/mainboard/msi/ms6147/Options.lb 2008-10-27 13:44:07 UTC (rev 3695) @@ -0,0 +1,99 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2008 Mats Erik Andersson <mats.andersson(a)gisladisker.org> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +uses HAVE_MP_TABLE +uses HAVE_PIRQ_TABLE +uses USE_FALLBACK_IMAGE +uses HAVE_FALLBACK_BOOT +uses HAVE_HARD_RESET +uses HAVE_OPTION_TABLE +uses USE_OPTION_TABLE +uses CONFIG_ROM_PAYLOAD +uses IRQ_SLOT_COUNT +uses MAINBOARD +uses MAINBOARD_VENDOR +uses MAINBOARD_PART_NUMBER +uses COREBOOT_EXTRA_VERSION +uses ARCH +uses FALLBACK_SIZE +uses STACK_SIZE +uses HEAP_SIZE +uses ROM_SIZE +uses ROM_SECTION_SIZE +uses ROM_IMAGE_SIZE +uses ROM_SECTION_SIZE +uses ROM_SECTION_OFFSET +uses CONFIG_ROM_PAYLOAD_START +uses CONFIG_COMPRESSED_PAYLOAD_LZMA +uses PAYLOAD_SIZE +uses _ROMBASE +uses _RAMBASE +uses XIP_ROM_SIZE +uses XIP_ROM_BASE +uses HAVE_MP_TABLE +uses CROSS_COMPILE +uses CC +uses HOSTCC +uses OBJCOPY +uses DEFAULT_CONSOLE_LOGLEVEL +uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_CONSOLE_SERIAL8250 +uses TTYS0_BAUD +uses TTYS0_BASE +uses TTYS0_LCS +uses CONFIG_UDELAY_TSC +uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 +uses MAINBOARD_VENDOR +uses MAINBOARD_PART_NUMBER +uses CONFIG_CONSOLE_VGA +uses CONFIG_PCI_ROM_RUN + +default ROM_SIZE = 256 * 1024 +default HAVE_FALLBACK_BOOT = 1 +default HAVE_MP_TABLE = 0 +default HAVE_HARD_RESET = 0 +default CONFIG_UDELAY_TSC = 1 +default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 +default HAVE_PIRQ_TABLE = 1 +default IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb. +default MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. +default MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. +default ROM_IMAGE_SIZE = 64 * 1024 +default FALLBACK_SIZE = 128 * 1024 +default STACK_SIZE = 8 * 1024 +default HEAP_SIZE = 16 * 1024 +default HAVE_OPTION_TABLE = 0 +#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE +default USE_OPTION_TABLE = 0 +default _RAMBASE = 0x00004000 +default CONFIG_ROM_PAYLOAD = 1 +default CROSS_COMPILE = "" +default CC = "$(CROSS_COMPILE)gcc -m32" +default HOSTCC = "gcc" +default CONFIG_CONSOLE_SERIAL8250 = 1 +default TTYS0_BAUD = 115200 +default TTYS0_BASE = 0x3f8 +default TTYS0_LCS = 0x3 # 8n1 +default DEFAULT_CONSOLE_LOGLEVEL = 9 +default MAXIMUM_CONSOLE_LOGLEVEL = 9 +default CONFIG_CONSOLE_VGA = 1 +default CONFIG_PCI_ROM_RUN = 1 + +end Added: trunk/coreboot-v2/src/mainboard/msi/ms6147/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms6147/auto.c (rev 0) +++ trunk/coreboot-v2/src/mainboard/msi/ms6147/auto.c 2008-10-27 13:44:07 UTC (rev 3695) @@ -0,0 +1,80 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Mats Erik Andersson <mats.andersson(a)gisladisker.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define ASSEMBLY 1 + +#include <stdint.h> +#include <stdlib.h> +#include <device/pci_def.h> +#include <arch/io.h> +#include <device/pnp_def.h> +#include <arch/romcc_io.h> +#include <arch/hlt.h> +#include "pc80/serial.c" +#include "arch/i386/lib/console.c" +#include "ram/ramtest.c" +#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" +#include "northbridge/intel/i440bx/raminit.h" +#include "lib/debug.c" +#include "pc80/udelay_io.c" +#include "lib/delay.c" +#include "cpu/x86/mtrr/earlymtrr.c" +#include <cpu/x86/bist.h> +#include "superio/winbond/w83977tf/w83977tf_early_serial.c" + +#define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1) + +static inline int spd_read_byte(unsigned int device, unsigned int address) +{ + return smbus_read_byte(device, address); +} + +#include "northbridge/intel/i440bx/raminit.c" +/* #include "northbridge/intel/i440bx/debug.c" */ +#include "sdram/generic_sdram.c" + +static void main(unsigned long bist) +{ + static const struct mem_controller memctrl[] = { + { + .d0 = PCI_DEV(0, 0, 0), + .channel0 = {0x50, 0x51, 0x52, 0x53}, + } + }; + + if (bist == 0) + early_mtrr_init(); + + w83977tf_enable_serial(SERIAL_DEV, TTYS0_BASE); + uart_init(); + console_init(); + report_bist_failure(bist); + enable_smbus(); + /* dump_spd_registers(&memctrl[0]); */ + sdram_initialize(ARRAY_SIZE(memctrl), memctrl); +#if 0 + ram_check(0, 640 * 1024); /* DOS-area */ + ram_check(0x00100000, 0x00400000); /* 1MB to 4MB */ + ram_check(0x00100000, 0x03ffffff); /* 1MB to 64MB- */ + ram_check(0x03fff000, 0x04000010); /* Across 64MB boundary */ + ram_check(0x07ffff00, 0x07fffff0); /* Just below 128MB */ + ram_check(0x00100000, 0x07ffffff); /* 1MB to 128MB- */ +#endif +} Added: trunk/coreboot-v2/src/mainboard/msi/ms6147/chip.h =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms6147/chip.h (rev 0) +++ trunk/coreboot-v2/src/mainboard/msi/ms6147/chip.h 2008-10-27 13:44:07 UTC (rev 3695) @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Mats Erik Andersson <mats.andersson(a)gisladisker.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_msi_ms6147_ops; +struct mainboard_msi_ms6147_config {}; Added: trunk/coreboot-v2/src/mainboard/msi/ms6147/irq_tables.c =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms6147/irq_tables.c (rev 0) +++ trunk/coreboot-v2/src/mainboard/msi/ms6147/irq_tables.c 2008-10-27 13:44:07 UTC (rev 3695) @@ -0,0 +1,51 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Mats Erik Andersson <mats.andersson(a)gisladisker.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/pirq_routing.h> + +const struct irq_routing_table intel_irq_routing_table = { + PIRQ_SIGNATURE, + PIRQ_VERSION, + 32 + 16 * IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ + 0x00, /* Interrupt router bus */ + (0x07 << 3) | 0x0, /* Interrupt router device */ + 0x1c00, /* IRQs devoted exclusively to PCI usage */ + 0x8086, /* Vendor */ + 0x7000, /* Device */ + 0, /* Crap (miniport) */ + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ + 0x20, /* Checksum */ + { + /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + {0x00,(0x0e<<3)|0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x1, 0x0}, + {0x00,(0x10<<3)|0x0, {{0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0x0deb8}}, 0x2, 0x0}, + {0x00,(0x12<<3)|0x0, {{0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0x0deb8}}, 0x3, 0x0}, + {0x00,(0x14<<3)|0x0, {{0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0x0deb8}}, 0x4, 0x0}, + {0x00,(0x00<<3)|0x0, {{0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0x0deb8}}, 0x0, 0x0}, /* North bridge */ + {0x00,(0x07<<3)|0x1, {{0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0x0deb8}}, 0x0, 0x0}, /* IDE */ + {0x00,(0x07<<3)|0x2, {{0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x63, 0x0deb8}}, 0x0, 0x0}, /* UHCI */ + {0x00,(0x01<<3)|0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x0, 0x0}, /* AGP bridge */ + } +}; + +unsigned long write_pirq_routing_table(unsigned long addr) +{ + return copy_pirq_routing_table(addr); +} Added: trunk/coreboot-v2/src/mainboard/msi/ms6147/mainboard.c =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms6147/mainboard.c (rev 0) +++ trunk/coreboot-v2/src/mainboard/msi/ms6147/mainboard.c 2008-10-27 13:44:07 UTC (rev 3695) @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Mats Erik Andersson <mats.andersson(a)gisladisker.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <device/device.h> +#include "chip.h" + +struct chip_operations mainboard_msi_ms6147_ops = { + CHIP_NAME("MSI MS-6147 Mainboard") +}; Added: trunk/coreboot-v2/targets/msi/ms6147/Config.lb =================================================================== --- trunk/coreboot-v2/targets/msi/ms6147/Config.lb (rev 0) +++ trunk/coreboot-v2/targets/msi/ms6147/Config.lb 2008-10-27 13:44:07 UTC (rev 3695) @@ -0,0 +1,49 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2008 Mats Erik Andersson <mats.andersson(a)gisladisker.org> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +target ms6147 +mainboard msi/ms6147 + +option ROM_SIZE = 256 * 1024 + +option MAINBOARD_VENDOR = "MSI" +option MAINBOARD_PART_NUMBER = "MS-6147" + +option IRQ_SLOT_COUNT = 8 + +option DEFAULT_CONSOLE_LOGLEVEL = 9 +option MAXIMUM_CONSOLE_LOGLEVEL = 9 + +option CONFIG_CONSOLE_VGA = 1 +option CONFIG_PCI_ROM_RUN = 1 + +romimage "normal" + option USE_FALLBACK_IMAGE = 0 + option COREBOOT_EXTRA_VERSION = ".Normal" + payload ../payload.elf +end + +romimage "fallback" + option USE_FALLBACK_IMAGE = 1 + option COREBOOT_EXTRA_VERSION = ".Fallback" + payload ../payload.elf +end + +buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"

1 0

[Patch]inteltool GM965 and ICH8 Regs dump, GM965 IGP temperature report
by lu zhihe 27 Oct '08

27 Oct '08

It bases on inteltool trunk r3692. This patch include GM965 and ICH8(except mpbase, it makes my Laptop halt) regs dump. It also support GM965 IGP temperature report. The support for GM945 mem. temperature report need test! Hope you like it. Signed-off-by: Lu Zhihe <tombowfly(a)gmail.com> diff --new-file -u -r inteltool.orig/Makefile inteltool/Makefile --- inteltool.orig/Makefile 2008-08-20 13:41:24.000000000 +0000 +++ inteltool/Makefile 2008-10-27 20:18:33.000000000 +0000 @@ -27,7 +27,7 @@ CFLAGS = -O2 -g -Wall -W LDFLAGS = -lpci -lz -OBJS = inteltool.o cpu.o gpio.o rootcmplx.o powermgt.o memory.o pcie.o +OBJS = inteltool.o cpu.o gpio.o rootcmplx.o powermgt.o memory.o pcie.o temp.o all: pciutils dep $(PROGRAM) diff --new-file -u -r inteltool.orig/gpio.c inteltool/gpio.c --- inteltool.orig/gpio.c 2008-08-20 13:41:24.000000000 +0000 +++ inteltool/gpio.c 2008-10-26 19:07:49.000000000 +0000 @@ -78,6 +78,26 @@ { 0x3C, 4, "RESERVED" } }; +static const io_register_t ich8_gpio_registers[] = { + { 0x00, 4, "GPIO_USE_SEL" }, + { 0x04, 4, "GP_IO_SEL" }, + { 0x08, 4, "RESERVED" }, + { 0x0c, 4, "GP_LVL" }, + { 0x10, 4, "GPIO_USE_SEL_Override_LOW" }, + { 0x14, 4, "RESERVED" }, + { 0x18, 4, "GPO_BLINK" }, + { 0x1c, 4, "GP_SER_BLINK" }, + { 0x20, 4, "GP_SB_CMDSTS" }, + { 0x24, 4, "GP_SB_DATA" }, + { 0x28, 4, "RESERVED" }, + { 0x2c, 4, "GPI_INV" }, + { 0x30, 4, "GPIO_USE_SEL2" }, + { 0x34, 4, "GP_IO_SEL2" }, + { 0x38, 4, "GP_LVL2" }, + { 0x3C, 4, "GPIO_USE_SEL_Override_HIGH" } +}; + + int print_gpios(struct pci_dev *sb) { int i, size; @@ -87,6 +107,11 @@ printf("\n============= GPIOS =============\n\n"); switch (sb->device_id) { + case PCI_DEVICE_ID_INTEL_ICH8: + gpiobase = pci_read_word(sb, 0x48) & 0xfffc; + gpio_registers = ich8_gpio_registers; + size = ARRAY_SIZE(ich8_gpio_registers); + break; case PCI_DEVICE_ID_INTEL_ICH7: case PCI_DEVICE_ID_INTEL_ICH7M: case PCI_DEVICE_ID_INTEL_ICH7DH: diff --new-file -u -r inteltool.orig/inteltool.c inteltool/inteltool.c --- inteltool.orig/inteltool.c 2008-08-20 13:41:24.000000000 +0000 +++ inteltool/inteltool.c 2008-10-27 20:11:33.000000000 +0000 @@ -32,6 +32,8 @@ } supported_chips_list[] = { { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845, "i845" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82945GM, "i945GM" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82965GM, "i965GM" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8, "ICH8" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7MDH, "ICH7-M DH" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7M, "ICH7-M" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7, "ICH7" }, @@ -92,12 +94,14 @@ int dump_gpios = 0, dump_mchbar = 0, dump_rcba = 0; int dump_pmbase = 0, dump_epbar = 0, dump_dmibar = 0; int dump_pciexbar = 0, dump_coremsrs = 0; + int detect_temp = 0; static struct option long_options[] = { {"version", 0, 0, 'v'}, {"help", 0, 0, 'h'}, {"gpios", 0, 0, 'g'}, {"mchbar", 0, 0, 'm'}, + {"temp", 0, 0, 't'}, {"rcba", 0, 0, 'r'}, {"pmbase", 0, 0, 'p'}, {"epbar", 0, 0, 'e'}, @@ -108,7 +112,7 @@ {0, 0, 0, 0} }; - while ((opt = getopt_long(argc, argv, "vh?grpmedPMa", + while ((opt = getopt_long(argc, argv, "vh?grpmtedPMa", long_options, &option_index)) != EOF) { switch (opt) { case 'v': @@ -121,6 +125,9 @@ case 'm': dump_mchbar = 1; break; + case 't': + detect_temp = 1; + break; case 'r': dump_rcba = 1; break; @@ -142,6 +149,7 @@ case 'a': dump_gpios = 1; dump_mchbar = 1; + detect_temp = 1; dump_rcba = 1; dump_pmbase = 1; dump_epbar = 1; @@ -174,7 +182,7 @@ /* Find the required devices */ - sb = pci_get_dev(pacc, 0, 0, 0x1f, 0); + sb = pci_get_dev(pacc, 0, 0, 0x1f, 0); /*Device 30, Func 0*/ if (!sb) { printf("No southbridge found.\n"); exit(1); @@ -187,7 +195,7 @@ exit(1); } - nb = pci_get_dev(pacc, 0, 0, 0x00, 0); + nb = pci_get_dev(pacc, 0, 0, 0x00, 0); /*Device 0, Func 0*/ if (!nb) { printf("No northbridge found.\n"); exit(1); @@ -239,6 +247,11 @@ print_mchbar(nb); printf("\n\n"); } + + if (detect_temp) { + print_temp(nb); + printf("\n\n"); + } if (dump_epbar) { print_epbar(nb); diff --new-file -u -r inteltool.orig/inteltool.h inteltool/inteltool.h --- inteltool.orig/inteltool.h 2008-08-20 13:41:24.000000000 +0000 +++ inteltool/inteltool.h 2008-10-27 20:44:00.000000000 +0000 @@ -33,9 +33,45 @@ #define PCI_DEVICE_ID_INTEL_ICH7 0x27b8 #define PCI_DEVICE_ID_INTEL_ICH7M 0x27b9 #define PCI_DEVICE_ID_INTEL_ICH7MDH 0x27bd +#define PCI_DEVICE_ID_INTEL_ICH8 0x2815 #define PCI_DEVICE_ID_INTEL_82845 0x1a30 #define PCI_DEVICE_ID_INTEL_82945GM 0x27a0 +#define PCI_DEVICE_ID_INTEL_82965GM 0x2a00 + + +/*GM965 Regs*/ +#define GM965_TSC1 (0x1001) //16bits +#define GM965_TSS1 (0x1004) //16bits +#define GM965_TR1 (0x1006) //8bits + +#define GM965_TSE 0x8000 +#define GM965_TMOV (0x01 << 10) + +/*GM965 doc say TSC2 control memory thermal sensor */ +#define GM965_TSC2 (0x1041) //16bits +#define GM965_TSS2 (0x1044) //16bits +#define GM965_TR2 (0x1046) //8bits + + +/*GM945 Regs*/ +/*GM945 doc say TSC1 just control memory thermal sensor + * no as GM965 control IGP's + * */ +#define GM945_TSC1 (0xC88) //8bits + +#define GM945_TSS1 (0xC8A) //8bits +#define GM945_TR1 (0xC8B) //8bits + +#define GM945_TSE 0x80 +#define GM945_TMOV 0x10 + +/*GM945 doc say TSC0-1 control memory thermal sensor*/ +#define GM945_TSC0_1 (0xCD8) //8bits +#define GM945_TSS0 (0xCDA) //8bits +#define GM945_TR0 (0xCDB) //8bits + + #define ARRAY_SIZE(a) ((int)(sizeof(a) / sizeof((a)[0]))) @@ -53,4 +89,5 @@ int print_epbar(struct pci_dev *nb); int print_dmibar(struct pci_dev *nb); int print_pciexbar(struct pci_dev *nb); +int print_temp(struct pci_dev *nb); diff --new-file -u -r inteltool.orig/memory.c inteltool/memory.c --- inteltool.orig/memory.c 2008-08-20 13:41:24.000000000 +0000 +++ inteltool/memory.c 2008-10-25 20:04:02.000000000 +0000 @@ -36,6 +36,9 @@ printf("\n============= MCHBAR ============\n\n"); switch (nb->device_id) { + case PCI_DEVICE_ID_INTEL_82965GM: + mchbar_phys = pci_read_long(nb, 0x48) & 0xfffffffe; + break; case PCI_DEVICE_ID_INTEL_82945GM: mchbar_phys = pci_read_long(nb, 0x44) & 0xfffffffe; break; diff --new-file -u -r inteltool.orig/pcie.c inteltool/pcie.c --- inteltool.orig/pcie.c 2008-08-20 13:41:24.000000000 +0000 +++ inteltool/pcie.c 2008-10-25 20:11:06.000000000 +0000 @@ -35,6 +35,7 @@ printf("\n============= EPBAR =============\n\n"); switch (nb->device_id) { + case PCI_DEVICE_ID_INTEL_82965GM: case PCI_DEVICE_ID_INTEL_82945GM: epbar_phys = pci_read_long(nb, 0x40) & 0xfffffffe; break; @@ -76,6 +77,9 @@ printf("\n============= DMIBAR ============\n\n"); switch (nb->device_id) { + case PCI_DEVICE_ID_INTEL_82965GM: + dmibar_phys = pci_read_long(nb, 0x68) & 0xfffffffe; + break; case PCI_DEVICE_ID_INTEL_82945GM: dmibar_phys = pci_read_long(nb, 0x4c) & 0xfffffffe; break; @@ -119,6 +123,9 @@ printf("========= PCIEXBAR ========\n\n"); switch (nb->device_id) { + case PCI_DEVICE_ID_INTEL_82965GM: + pciexbar_reg = pci_read_long(nb, 0x60); + break; case PCI_DEVICE_ID_INTEL_82945GM: pciexbar_reg = pci_read_long(nb, 0x48); break; diff --new-file -u -r inteltool.orig/powermgt.c inteltool/powermgt.c --- inteltool.orig/powermgt.c 2008-08-20 13:41:24.000000000 +0000 +++ inteltool/powermgt.c 2008-10-26 19:24:28.000000000 +0000 @@ -31,6 +31,7 @@ printf("\n============= PMBASE ============\n\n"); switch (sb->device_id) { + /*case PCI_DEVICE_ID_INTEL_ICH8: //F31G will hang when dump pmbase Lu Zhihe*/ case PCI_DEVICE_ID_INTEL_ICH7: case PCI_DEVICE_ID_INTEL_ICH7M: case PCI_DEVICE_ID_INTEL_ICH7DH: diff --new-file -u -r inteltool.orig/rootcmplx.c inteltool/rootcmplx.c --- inteltool.orig/rootcmplx.c 2008-08-20 13:41:24.000000000 +0000 +++ inteltool/rootcmplx.c 2008-10-26 19:13:23.000000000 +0000 @@ -41,6 +41,7 @@ printf("\n============= RCBA ==============\n\n"); switch (sb->device_id) { + case PCI_DEVICE_ID_INTEL_ICH8: case PCI_DEVICE_ID_INTEL_ICH7: case PCI_DEVICE_ID_INTEL_ICH7M: case PCI_DEVICE_ID_INTEL_ICH7DH: diff --new-file -u -r inteltool.orig/temp.c inteltool/temp.c --- inteltool.orig/temp.c 1970-01-01 00:00:00.000000000 +0000 +++ inteltool/temp.c 2008-10-27 20:43:07.000000000 +0000 @@ -0,0 +1,154 @@ +/* + * Written by Lu Zhihe <tombowfly at gmail.com > + * + * Now only support GM965 IGP temperature detect. + * The support for GM945 mem. temperature detect need more test. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + + +#include <stdio.h> +#include <stdlib.h> +#include <sys/mman.h> +#include <unistd.h> + +#include "inteltool.h" + +int do_temp_detect(volatile uint8_t *mchbar, int reg_group) +{ + uint16_t tsc1 = 0, tss1 = 0, tr1 = 0; + uint16_t tse = 0, tmov = 0; + uint16_t tsc1_val = 0; + uint8_t tr1_val = 0; + float temp = 0; + + switch (reg_group) + { + case PCI_DEVICE_ID_INTEL_82965GM: + { +#if 1 + tsc1 = GM965_TSC1; + tss1 = GM965_TSS1; + tr1 = GM965_TR1; +#else + tsc1 = GM965_TSC2; + tss1 = GM965_TSS2; + tr1 = GM965_TR2; +#endif + tse = GM965_TSE; + tmov = GM965_TMOV; + } + break; + + /*FIXME*/ + case PCI_DEVICE_ID_INTEL_82945GM: + { +#if 1 + tsc1 = GM945_TSC1; + tss1 = GM945_TSS1; + tr1 = GM945_TR1; +#else + tsc1 = GM945_TSC0_1; + tss1 = GM945_TSS0; + tr1 = GM945_TR0; +#endif + tse = GM945_TSE; + tmov = GM945_TMOV; + } + break; + + default: + break; + } + + tsc1_val = *(uint16_t *)(mchbar+tsc1); + + if(!(tsc1_val&tse)) + { + *(uint16_t *)(mchbar+tsc1) |= tse; + tsc1_val = *(uint16_t *)(mchbar+tsc1); + } + + while(1) + { + if(tsc1_val&tse) + { + do{ + tr1_val = *(uint8_t *)(mchbar + tr1); +#ifdef EXPERIENT + /*Default Regs vaule = 0xFF, GM865 doc say: under 40 degrees Centigrade, + * the temperature report may unavailable*/ + if(tr1_val != 0xFF) + { + /*Magic Num by experiential data*/ + printf("GPU Thermal = %d degrees Centigrade\n", (170 - tr1_val)); + } + else + { + printf("Your GPU temperature is under 40 degrees Centigrade\n"); + } +#else + /*Base on Intel GM9965 doc, July 2006 rel. ver. Lu Zhihe*/ + temp = 0.0016*tr1_val*tr1_val-1.10707*tr1_val + 161.05; + printf("GPU Thermal = %.2f degC\n", temp); + +#endif + sleep(1); + }while(*(uint16_t *)(mchbar + tss1)& tmov ); + } + } + return 0; +} + + +int print_temp(struct pci_dev *nb) +{ + int size = (16 * 1024); + volatile uint8_t *mchbar; + uint32_t mchbar_phys; + int reg_group; + + switch (nb->device_id) { + case PCI_DEVICE_ID_INTEL_82965GM: + mchbar_phys = pci_read_long(nb, 0x48) & 0xfffffffe; + reg_group = PCI_DEVICE_ID_INTEL_82965GM; + break; + case PCI_DEVICE_ID_INTEL_82945GM: + mchbar_phys = pci_read_long(nb, 0x44) & 0xfffffffe; + reg_group = PCI_DEVICE_ID_INTEL_82945GM; + break; + case 0x1234: // Dummy for non-existent functionality + printf("This northbrigde does not have MCHBAR.\n"); + return 1; + default: + printf("Error: Dumping MCHBAR on this northbridge is not (yet) supported.\n"); + return 1; + } + + mchbar = mmap(0, size, PROT_WRITE | PROT_READ, MAP_SHARED, + fd_mem, (off_t) mchbar_phys); + + if (mchbar == MAP_FAILED) { + perror("Error mapping MCHBAR"); + exit(1); + } + + do_temp_detect(mchbar, reg_group); + + munmap((void *)mchbar, size); + return 0; +} + + -- Thx Lu Zhihe

1 0

DFI Infinity NF570-M2/G motherboard
by Tiago Marques 27 Oct '08

27 Oct '08

1MB = 1 million bytes 1Mb = 1Mbit = 1 million bits 1MiB (mebibyte) = 1.048.576 bytes, which is what most people call mega byte(MB), but isn't. 1Mibit = 1 Mib = 1.048.576 bits Usually when a chip is said to have 1MB it really has 1MiB, not less, and 8Mib, not 8Mb. http://en.wikipedia.org/wiki/Mebibit Best regards, Tiago Marques On Sun, Oct 26, 2008 at 3:37 PM, Chris Lingard <chris(a)stockwith.co.uk>wrote: > Carl-Daniel Hailfinger wrote: > >> On 26.10.2008 15:39, Chris Lingard wrote: >> >>> Corey Osgood wrote: >>> >>>> On Sat, Oct 25, 2008 at 11:13 AM, Chris Lingard <chris(a)stockwith.co.uk >>>> <mailto:chris@stockwith.co.uk>> wrote: >>>> The board comes with a ITE IT8716F 4MB chip; but that is compatible >>>> with SST49LF040A chips. I already have these and some SST49LF080A >>>> chips; just wish there were 160 or 320MB >>>> >>>> >>>> I'm hoping that's a typo, SST49LF080 is 8Mb (that's 8 megabits, or 1 >>>> megabyte), larger chips would be 16 or 32Mb (2 or 4MB). >>>> >>> Well if 040 is 4MB and 080 is 8MB, I would hope there is a 160 at 16MB >>> and so on; or do engineers use a secret numbering system :-) >>> >> >> Secret numbering system. >> 040 is 4 Mbit = 512 kByte >> 080 is 8 Mbit = 1 MByte >> 160 is 16 Mbit = 2 MByte >> >> I used to do boot CDs pretending to be 2.8Mb floppies, and would be >>> happy with a 4Mb chip to get a Linux kernel into. >>> >> >> No, these were 2.88 MByte floppies, not 2.88 Mbit floppies. Even the >> SST49LF160 chip is smaller than that floppy. >> >> Regards, >> Carl-Daniel >> >> > LOL > > We use different terms > > To me a Mb is one million bytes > And a MB is one million bits > > But we all agree in the end > > Chris Lingard > > > > -- > coreboot mailing list: coreboot(a)coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot >

1 0

brainstorm: new LPC dongle from Artec Group
by Martin-Éric Racine 27 Oct '08

27 Oct '08

Greetings, Noticing that the main community of users for Artec Group's LPC dongle has been at Coreboot, I have two announcements to make: 1) The current LPC dongle model is EOL. Some components no longer exist on the market so, after the batch we're producing this month, it's gone. 2) We're already working on a new LPC dongle to replace the current one. In conjunction with item #2 above, we are hereby giving the Coreboot community an opportunity to influence the design of this new product. While we cannot guarantee that every idea submitted will be used, we will definitely be reading all the feedback we receive. The end result will be an even better LPC dongle that serves the growing needs of the embedded hardware developer community. To compare with the current dongle design, see: http://artecgroup.myshopify.com/products/programmable-lpc-dongle Looking forward to receiving your ideas for this new LPC dongle product. Best Regards, -- Martin-Éric Racine Business Development Manager Artec Group OÜ

9 16

V3 Parallel port console
by Gregg C Levine 26 Oct '08

26 Oct '08

Hello! My Google Mail account for the list tells me that while I was away on vacation, the list discussed an interesting thing to add to the V3 branch. That of a Parallel port based console. Has anything actually come out of this one idea? I for one like it. I know I suggested something of a sort early on that is shortly after the list moved to its present site, but before the name change. I've been reading the posts, and as it happens they all make sense. -- Gregg C Levine hansolofalcon(a)worldnet.att.net "The Force will be with you always." Obi-Wan Kenobi

1 0

[PATCH] flashrom: Add support for PIIX/PIIX3 southbridges
by Uwe Hermann 26 Oct '08

26 Oct '08

See patch. Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org

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coreboot October 2008