coreboot October 2008

coreboot@coreboot.org

84 participants
608 discussions

r953 - coreboot-v3/northbridge/amd/k8
by svn＠coreboot.org 24 Oct '08

24 Oct '08

Author: myles Date: 2008-10-24 21:26:34 +0200 (Fri, 24 Oct 2008) New Revision: 953 Modified: coreboot-v3/northbridge/amd/k8/pci.c Log: This patch fixes whitespace so that a future patch is easier to read. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Myles Watson <mylesgw(a)gmail.com> Thanks, Myles Modified: coreboot-v3/northbridge/amd/k8/pci.c =================================================================== --- coreboot-v3/northbridge/amd/k8/pci.c 2008-10-24 17:53:03 UTC (rev 952) +++ coreboot-v3/northbridge/amd/k8/pci.c 2008-10-24 19:26:34 UTC (rev 953) @@ -1,5 +1,5 @@ /* - * K8 northbridge + * K8 northbridge * This file is part of the coreboot project. * Copyright (C) 2004-2005 Linux Networx * (Written by Eric Biederman <ebiederman(a)lnxi.com> and Jason Schildt for Linux Networx) @@ -54,14 +54,14 @@ static unsigned int amdk8_scan_chain(struct device * dev, unsigned nodeid, unsigned link, unsigned sblink, unsigned int max, unsigned offset_unitid) { - + u32 link_type; int i; u32 busses, config_busses; unsigned free_reg, config_reg; unsigned ht_unitid_base[4]; // here assume only 4 HT device on chain - unsigned max_bus; - unsigned min_bus; + unsigned max_bus; + unsigned min_bus; unsigned max_devfn; printk(BIOS_SPEW, "amdk8_scan_chain\n"); dev->link[link].cap = 0x80 + (link *0x20); @@ -79,7 +79,7 @@ return max; } /* See if there is an available configuration space mapping - * register in function 1. + * register in function 1. */ free_reg = 0; for(config_reg = 0xe0; config_reg <= 0xec; config_reg += 4) { @@ -89,7 +89,7 @@ free_reg = config_reg; continue; } - if (((config & 3) == 3) && + if (((config & 3) == 3) && (((config >> 4) & 7) == nodeid) && (((config >> 8) & 3) == link)) { break; @@ -99,7 +99,7 @@ config_reg = free_reg; } /* If we can't find an available configuration space mapping - * register skip this bus + * register skip this bus */ if (config_reg > 0xec) { return max; @@ -110,36 +110,36 @@ * so we set the subordinate bus number to 0xff for the moment. */ #if SB_HT_CHAIN_ON_BUS0 > 0 - // first chain will on bus 0 + // first chain will on bus 0 if((nodeid == 0) && (sblink==link)) { // actually max is 0 here - min_bus = max; - } + min_bus = max; + } #if SB_HT_CHAIN_ON_BUS0 > 1 // second chain will be on 0x40, third 0x80, forth 0xc0 - else { - min_bus = ((max>>6) + 1) * 0x40; - } - max = min_bus; - #else - //other ... - else { - min_bus = ++max; - } - #endif + else { + min_bus = ((max>>6) + 1) * 0x40; + } + max = min_bus; + #else + //other ... + else { + min_bus = ++max; + } + #endif #else - min_bus = ++max; + min_bus = ++max; #endif - max_bus = 0xff; + max_bus = 0xff; - dev->link[link].secondary = min_bus; - dev->link[link].subordinate = max_bus; + dev->link[link].secondary = min_bus; + dev->link[link].subordinate = max_bus; /* Read the existing primary/secondary/subordinate bus * number configuration. */ busses = pci_read_config32(dev, dev->link[link].cap + 0x14); config_busses = f1_read_config32(config_reg); - + /* Configure the bus numbers for this bridge: the configuration * transactions will not be propagates by the bridge if it is * not correctly configured @@ -151,22 +151,22 @@ pci_write_config32(dev, dev->link[link].cap + 0x14, busses); config_busses &= 0x000fc88; - config_busses |= + config_busses |= (3 << 0) | /* rw enable, no device compare */ - (( nodeid & 7) << 4) | - (( link & 3 ) << 8) | + (( nodeid & 7) << 4) | + (( link & 3 ) << 8) | ((dev->link[link].secondary) << 16) | ((dev->link[link].subordinate) << 24); f1_write_config32(config_reg, config_busses); /* Now we can scan all of the subordinate busses i.e. the - * chain on the hypertranport link + * chain on the hypertranport link */ for(i=0;i<4;i++) { ht_unitid_base[i] = 0x20; } - if (min_bus == 0) + if (min_bus == 0) max_devfn = (0x17<<3) | 7; else max_devfn = (0x1f<<3) | 7; @@ -204,53 +204,53 @@ static unsigned int amdk8_scan_chains(struct device * dev, unsigned int max) { - unsigned nodeid; - unsigned link; - unsigned sblink = 0; + unsigned nodeid; + unsigned link; + unsigned sblink = 0; unsigned offset_unitid = 0; - nodeid = amdk8_nodeid(dev); - + nodeid = amdk8_nodeid(dev); + printk(BIOS_DEBUG, "amdk8_scan_chains\n"); - if(nodeid==0) { - sblink = (pci_read_config32(dev, 0x64)>>8) & 3; + if(nodeid==0) { + sblink = (pci_read_config32(dev, 0x64)>>8) & 3; #if SB_HT_CHAIN_ON_BUS0 > 0 #if ((HT_CHAIN_UNITID_BASE != 1) || (HT_CHAIN_END_UNITID_BASE != 0x20)) - offset_unitid = 1; - #endif - // do southbridge ht chain first, in case s2885 put southbridge chain (8131/8111) on link2, + offset_unitid = 1; + #endif + // do southbridge ht chain first, in case s2885 put southbridge chain (8131/8111) on link2, // but put 8151 on link0 - max = amdk8_scan_chain(dev, nodeid, sblink, sblink, max, offset_unitid ); + max = amdk8_scan_chain(dev, nodeid, sblink, sblink, max, offset_unitid ); #endif - } + } - for(link = 0; link < dev->links; link++) { + for(link = 0; link < dev->links; link++) { #if SB_HT_CHAIN_ON_BUS0 > 0 if( (nodeid == 0) && (sblink == link) ) continue; //already done #endif offset_unitid = 0; #if ((HT_CHAIN_UNITID_BASE != 1) || (HT_CHAIN_END_UNITID_BASE != 0x20)) - #if SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1 + #if SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1 if((nodeid == 0) && (sblink == link)) #endif offset_unitid = 1; #endif max = amdk8_scan_chain(dev, nodeid, link, sblink, max, offset_unitid); - } + } - return max; + return max; } #warning document this unreadable function reg_useable -static int reg_useable(unsigned reg, +static int reg_useable(unsigned reg, struct device * goal_dev, unsigned goal_nodeid, unsigned goal_link) { struct resource *res; unsigned nodeid, link; int result; res = 0; -#warning fix hard-coded 8 in for loop. +#warning fix hard-coded 8 in for loop. for(nodeid = 0; !res && (nodeid < 8); nodeid++) { struct device * dev; dev = __f0_dev[nodeid]; @@ -263,7 +263,7 @@ result = 2; if (res) { result = 0; - if ( (goal_link == (link - 1)) && + if ( (goal_link == (link - 1)) && (goal_nodeid == (nodeid - 1)) && (res->flags <= 1)) { result = 1; @@ -330,7 +330,7 @@ static void amdk8_link_read_bases(struct device * dev, unsigned nodeid, unsigned link) { struct resource *resource; - + /* Initialize the io space constraints on the current bus */ resource = amdk8_find_iopair(dev, nodeid, link); if (resource) { @@ -340,7 +340,7 @@ resource->gran = log2c(HT_IO_HOST_ALIGN); resource->limit = 0xffffUL; resource->flags = IORESOURCE_IO; - compute_allocate_resource(&dev->link[link], resource, + compute_allocate_resource(&dev->link[link], resource, IORESOURCE_IO, IORESOURCE_IO); } @@ -353,8 +353,8 @@ resource->gran = log2c(HT_MEM_HOST_ALIGN); resource->limit = 0xffffffffffULL; resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; - compute_allocate_resource(&dev->link[link], resource, - IORESOURCE_MEM | IORESOURCE_PREFETCH, + compute_allocate_resource(&dev->link[link], resource, + IORESOURCE_MEM | IORESOURCE_PREFETCH, IORESOURCE_MEM | IORESOURCE_PREFETCH); } @@ -367,8 +367,8 @@ resource->gran = log2c(HT_MEM_HOST_ALIGN); resource->limit = 0xffffffffffULL; resource->flags = IORESOURCE_MEM; - compute_allocate_resource(&dev->link[link], resource, - IORESOURCE_MEM | IORESOURCE_PREFETCH, + compute_allocate_resource(&dev->link[link], resource, + IORESOURCE_MEM | IORESOURCE_PREFETCH, IORESOURCE_MEM); } } @@ -402,7 +402,7 @@ if (resource->flags & IORESOURCE_STORED) { return; } - + /* Only handle PCI memory and IO resources */ if (!(resource->flags & (IORESOURCE_MEM | IORESOURCE_IO))) return; @@ -413,7 +413,7 @@ } /* Get the base address */ rbase = resource->base; - + /* Get the limit (rounded up) */ rend = resource_end(resource); @@ -436,14 +436,14 @@ limit |= (nodeid & 7); if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) { - printk(BIOS_SPEW, "%s, enabling legacy VGA IO forwarding for %s link %x\n", - __func__, dev_path(dev), link); + printk(BIOS_SPEW, "%s, enabling legacy VGA IO forwarding for %s link %x\n", + __func__, dev_path(dev), link); base |= PCI_IO_BASE_VGA_EN; } if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_NO_ISA) { base |= PCI_IO_BASE_NO_ISA; } - + f1_write_config32(reg + 0x4, limit); f1_write_config32(reg, base); } @@ -476,7 +476,7 @@ * but it is too diffcult to deal with the resource allocation magic. */ #ifdef CONFIG_MULTIPLE_VGA_INIT -extern struct device * vga_pri; // the primary vga device, defined in device.c +extern struct device * vga_pri; // the primary vga device, defined in device.c #endif static void amdk8_create_vga_resource(struct device * dev, unsigned nodeid) @@ -491,7 +491,7 @@ for (link = 0; link < dev->links; link++) { if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) { #ifdef CONFIG_MULTIPLE_VGA_INIT - printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d dev->link[link] bus range [%d,%d]\n", vga_pri->bus->secondary, + printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d dev->link[link] bus range [%d,%d]\n", vga_pri->bus->secondary, dev->link[link].secondary,dev->link[link].subordinate); /* We need to make sure the vga_pri is under the link */ if((vga_pri->bus->secondary >= dev->link[link].secondary ) && @@ -501,7 +501,7 @@ break; } } - + /* no VGA card installed */ if (link == dev->links) return; @@ -545,7 +545,7 @@ printk(BIOS_DEBUG, "amdk8_set_resources: nodeid %d\n", nodeid); amdk8_create_vga_resource(dev, nodeid); - + /* Set each resource we have found */ for(i = 0; i < dev->resources; i++) { amdk8_set_resource(dev, &dev->resource[i], nodeid);

1 0

v3 constructor on new devices
by Myles Watson 24 Oct '08

24 Oct '08

Why do we call the constructor function of a new device? I can't see where we ever set it. Thanks, Myles >From device/device.c: memset(dev, 0, sizeof(*dev)); dev->path = *path; dev->id = *devid; /* Initialize the back pointers in the link fields. */ for (link = 0; link < MAX_LINKS; link++) { dev->link[link].dev = dev; dev->link[link].link = link; } /* By default devices are enabled. */ dev->enabled = 1; /* Add the new device to the list of children of the bus. */ dev->bus = parent; if (child) { child->sibling = dev; } else { parent->children = dev; } /* Append a new device to the global device list. * The list is used to find devices once everything is set up. */ *last_dev_p = dev; last_dev_p = &dev->next; /* Give the device a name. */ sprintf(dev->dtsname, "dynamic %s", dev_path(dev)); /* Run the device specific constructor as last part of the chain * so it gets the chance to overwrite the "inherited" values above */ constructor(dev);

1 0

r952 - coreboot-v3/northbridge/amd/k8
by svn＠coreboot.org 24 Oct '08

24 Oct '08

Author: myles Date: 2008-10-24 19:53:03 +0200 (Fri, 24 Oct 2008) New Revision: 952 Modified: coreboot-v3/northbridge/amd/k8/common.c coreboot-v3/northbridge/amd/k8/domain.c Log: This patch fixes whitespace so that my next patch is easier to read. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Myles Watson <mylesgw(a)gmail.com> Thanks, Myles Modified: coreboot-v3/northbridge/amd/k8/common.c =================================================================== --- coreboot-v3/northbridge/amd/k8/common.c 2008-10-23 18:55:01 UTC (rev 951) +++ coreboot-v3/northbridge/amd/k8/common.c 2008-10-24 17:53:03 UTC (rev 952) @@ -76,6 +76,7 @@ } } #endif + void get_fx_devs(void) { int i; @@ -123,48 +124,48 @@ struct hw_mem_hole_info mem_hole; int i; - mem_hole.hole_startk = CONFIG_HW_MEM_HOLE_SIZEK; + mem_hole.hole_startk = CONFIG_HW_MEM_HOLE_SIZEK; mem_hole.node_id = -1; - for (i = 0; i < 8; i++) { - u32 base; - u32 hole; - base = f1_read_config32(0x40 + (i << 3)); - if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) { - continue; - } + for (i = 0; i < 8; i++) { + u32 base; + u32 hole; + base = f1_read_config32(0x40 + (i << 3)); + if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) { + continue; + } - hole = pci_read_config32(__f1_dev[i], 0xf0); - if(hole & 1) { // we find the hole - mem_hole.hole_startk = (hole & (0xff<<24)) >> 10; - mem_hole.node_id = i; // record the node No with hole - break; // only one hole + hole = pci_read_config32(__f1_dev[i], 0xf0); + if(hole & 1) { // we find the hole + mem_hole.hole_startk = (hole & (0xff<<24)) >> 10; + mem_hole.node_id = i; // record the node No with hole + break; // only one hole } - } + } - //We need to double check if there is speical set on base reg and limit reg are not continous instead of hole, it will find out it's hole_startk - if(mem_hole.node_id==-1) { - u32 limitk_pri = 0; - for(i=0; i<8; i++) { - u32 base, limit; - unsigned base_k, limit_k; - base = f1_read_config32(0x40 + (i << 3)); - if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) { - continue; - } + //We need to double check if there is speical set on base reg and limit reg are not continous instead of hole, it will find out it's hole_startk + if(mem_hole.node_id==-1) { + u32 limitk_pri = 0; + for(i=0; i<8; i++) { + u32 base, limit; + unsigned base_k, limit_k; + base = f1_read_config32(0x40 + (i << 3)); + if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) { + continue; + } - base_k = (base & 0xffff0000) >> 2; - if(limitk_pri != base_k) { // we find the hole - mem_hole.hole_startk = limitk_pri; - mem_hole.node_id = i; - break; //only one hole + base_k = (base & 0xffff0000) >> 2; + if(limitk_pri != base_k) { // we find the hole + mem_hole.hole_startk = limitk_pri; + mem_hole.node_id = i; + break; //only one hole } - limit = f1_read_config32(0x44 + (i << 3)); - limit_k = ((limit + 0x00010000) & 0xffff0000) >> 2; - limitk_pri = limit_k; - } - } + limit = f1_read_config32(0x44 + (i << 3)); + limit_k = ((limit + 0x00010000) & 0xffff0000) >> 2; + limitk_pri = limit_k; + } + } return mem_hole; @@ -172,35 +173,35 @@ void disable_hoist_memory(unsigned long hole_startk, int i) { - int ii; - struct device * dev; - u32 base, limit; - u32 hoist; + int ii; + struct device * dev; + u32 base, limit; + u32 hoist; u32 hole_sizek; - //1. find which node has hole - //2. change limit in that node. - //3. change base and limit in later node - //4. clear that node f0 + //1. find which node has hole + //2. change limit in that node. + //3. change base and limit in later node + //4. clear that node f0 //if there is not mem hole enabled, we need to change it's base instead hole_sizek = (4*1024*1024) - hole_startk; - for(ii=7;ii>i;ii--) { + for(ii=7;ii>i;ii--) { - base = f1_read_config32(0x40 + (ii << 3)); - if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) { - continue; - } + base = f1_read_config32(0x40 + (ii << 3)); + if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) { + continue; + } limit = f1_read_config32(0x44 + (ii << 3)); - f1_write_config32(0x44 + (ii << 3),limit - (hole_sizek << 2)); - f1_write_config32(0x40 + (ii << 3),base - (hole_sizek << 2)); - } - limit = f1_read_config32(0x44 + (i << 3)); - f1_write_config32(0x44 + (i << 3),limit - (hole_sizek << 2)); - dev = __f1_dev[i]; + f1_write_config32(0x44 + (ii << 3),limit - (hole_sizek << 2)); + f1_write_config32(0x40 + (ii << 3),base - (hole_sizek << 2)); + } + limit = f1_read_config32(0x44 + (i << 3)); + f1_write_config32(0x44 + (i << 3),limit - (hole_sizek << 2)); + dev = __f1_dev[i]; hoist = pci_read_config32(dev, 0xf0); if(hoist & 1) { pci_write_config32(dev, 0xf0, 0); @@ -214,30 +215,30 @@ u32 hoist_memory(unsigned long hole_startk, int i) { - int ii; - u32 carry_over; - struct device * dev; - u32 base, limit; - u32 basek; - u32 hoist; + int ii; + u32 carry_over; + struct device * dev; + u32 base, limit; + u32 basek; + u32 hoist; - carry_over = (4*1024*1024) - hole_startk; + carry_over = (4*1024*1024) - hole_startk; - for(ii=7;ii>i;ii--) { + for(ii=7;ii>i;ii--) { - base = f1_read_config32(0x40 + (ii << 3)); - if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) { - continue; - } + base = f1_read_config32(0x40 + (ii << 3)); + if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) { + continue; + } limit = f1_read_config32(0x44 + (ii << 3)); - f1_write_config32(0x44 + (ii << 3),limit + (carry_over << 2)); - f1_write_config32(0x40 + (ii << 3),base + (carry_over << 2)); - } - limit = f1_read_config32(0x44 + (i << 3)); - f1_write_config32(0x44 + (i << 3),limit + (carry_over << 2)); - dev = __f1_dev[i]; - base = pci_read_config32(dev, 0x40 + (i << 3)); - basek = (base & 0xffff0000) >> 2; + f1_write_config32(0x44 + (ii << 3),limit + (carry_over << 2)); + f1_write_config32(0x40 + (ii << 3),base + (carry_over << 2)); + } + limit = f1_read_config32(0x44 + (i << 3)); + f1_write_config32(0x44 + (i << 3),limit + (carry_over << 2)); + dev = __f1_dev[i]; + base = pci_read_config32(dev, 0x40 + (i << 3)); + basek = (base & 0xffff0000) >> 2; if(basek == hole_startk) { //don't need set memhole here, because hole off set will be 0, overflow //so need to change base reg instead, new basek will be 4*1024*1024 @@ -247,17 +248,17 @@ } else { - hoist = /* hole start address */ - ((hole_startk << 10) & 0xff000000) + - /* hole address to memory controller address */ - (((basek + carry_over) >> 6) & 0x0000ff00) + - /* enable */ - 1; + hoist = /* hole start address */ + ((hole_startk << 10) & 0xff000000) + + /* hole address to memory controller address */ + (((basek + carry_over) >> 6) & 0x0000ff00) + + /* enable */ + 1; - pci_write_config32(dev, 0xf0, hoist); + pci_write_config32(dev, 0xf0, hoist); } - return carry_over; + return carry_over; } #endif Modified: coreboot-v3/northbridge/amd/k8/domain.c =================================================================== --- coreboot-v3/northbridge/amd/k8/domain.c 2008-10-23 18:55:01 UTC (rev 951) +++ coreboot-v3/northbridge/amd/k8/domain.c 2008-10-24 17:53:03 UTC (rev 952) @@ -126,18 +126,18 @@ } } #ifndef CONFIG_PCI_64BIT_PREF_MEM - /* Initialize the system wide io space constraints */ + /* Initialize the system-wide io space constraints */ resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); resource->base = 0x400; resource->limit = 0xffffUL; resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; - /* Initialize the system wide memory resources constraints */ + /* Initialize the system-wide memory resource constraints */ resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); resource->limit = 0xfcffffffffULL; resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; #else - /* Initialize the system wide io space constraints */ + /* Initialize the system-wide io space constraints */ resource = new_resource(dev, 0); resource->base = 0x400; resource->limit = 0xffffUL; @@ -145,7 +145,7 @@ compute_allocate_resource(&dev->link[0], resource, IORESOURCE_IO, IORESOURCE_IO); - /* Initialize the system wide prefetchable memory resources constraints */ + /* Initialize the system-wide prefetchable memory resource constraints */ resource = new_resource(dev, 1); resource->limit = 0xfcffffffffULL; resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; @@ -153,7 +153,7 @@ IORESOURCE_MEM | IORESOURCE_PREFETCH, IORESOURCE_MEM | IORESOURCE_PREFETCH); - /* Initialize the system wide memory resources constraints */ + /* Initialize the system-wide memory resource constraints */ resource = new_resource(dev, 2); resource->limit = 0xfcffffffffULL; resource->flags = IORESOURCE_MEM; @@ -197,10 +197,10 @@ mem2 = find_resource(dev, 2); #if 1 - printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n", - mem1->base, mem1->limit, mem1->size, mem1->align); - printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n", - mem2->base, mem2->limit, mem2->size, mem2->align); + printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n", + mem1->base, mem1->limit, mem1->size, mem1->align); + printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n", + mem2->base, mem2->limit, mem2->size, mem2->align); #endif /* See if both resources have roughly the same limits */ @@ -227,10 +227,10 @@ } #if 1 - printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n", - mem1->base, mem1->limit, mem1->size, mem1->align); - printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n", - mem2->base, mem2->limit, mem2->size, mem2->align); + printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n", + mem1->base, mem1->limit, mem1->size, mem1->align); + printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n", + mem2->base, mem2->limit, mem2->size, mem2->align); #endif last = &dev->resource[dev->resources]; @@ -264,10 +264,11 @@ #endif #if CONFIG_HW_MEM_HOLE_SIZEK != 0 - /* if the hw mem hole is already set in raminit stage, here we will compare mmio_basek and hole_basek - * if mmio_basek is bigger that hole_basek and will use hole_basek as mmio_basek and we don't need to reset hole. - * otherwise We reset the hole to the mmio_basek - */ + /* If the hw mem hole is already set in raminit stage, here we will + * compare mmio_basek and hole_basek. If mmio_basek is bigger than + * hole_basek, we use hole_basek as mmio_basek and we don't need + * to reset hole. Otherwise, we reset the hole to the mmio_basek. + */ mem_hole = get_hw_mem_hole_info();

1 0

HT devices in v3
by Myles Watson 24 Oct '08

24 Oct '08

I'm getting stuck in Hypertransport enumeration. Is there supposed to be a pci_domain that is the child of a HT link? If so, what device ID would it have. I'm thinking specifically about the 8132 and 8111 on the Serengeti board. The dts currently looks like this (simplified): domain@0 { /config/("northbridge/amd/k8/domain"); pci@1,0{ }; pci0@18,0 { /config/("northbridge/amd/k8/pci"); pci@0,0 { /config/("southbridge/amd/amd8111/pci.dts"); pci@1,0{ /config/("southbridge/amd/amd8111/nic.dts"); }; pci@0,0{ /config/("southbridge/amd/amd8111/usb.dts"); }; }; pci@7,0 { /config/("southbridge/amd/amd8111/lpc.dts"); }; }; I think it should look like this: domain@0 { /config/("northbridge/amd/k8/domain"); pci0@18,0 { /config/("northbridge/amd/k8/pci"); pci@0,0 { //Really at 00:6.0 /config/("southbridge/amd/amd8111/pci.dts"); pci@1,0{ /config/("southbridge/amd/amd8111/nic.dts"); }; pci@0,0{ /config/("southbridge/amd/amd8111/usb.dts"); }; }; pci@1,0 { //Really at 00:7.0 /config/("southbridge/amd/amd8111/lpc.dts"); }; pci@2,0{ //Really at 00:a.0 and 00:b.0 /config/("southbridge/amd/amd8132/pcix.dts"); }; }; My reasoning is that the 8132 and the 81111 should be at the same level. This doesn't work for me in hypertransport enumeration for various reasons. Before I do a big rewrite, I'd like a little sanity check. By the way, "dynamic" in the dtsname is bad when you had the device in the dts. It means it didn't find your device where you said it was. Thanks, Myles

5 12

HT_CHAIN.*_UNITID_BASE
by Myles Watson 24 Oct '08

24 Oct '08

Is this defined because of broken hardware? I'm surprised that we need this. Thanks, Myles

1 1

Re: [coreboot] r3688 - in trunk/coreboot-v2/src: arch/i386/init cpu/amd/model_lx
by Jens Rottmann 24 Oct '08

24 Oct '08

>> + movb %cl, %al >> + shrl $2, %ecx >> + andb $3, %al >> + rep movsl >> + movb %al, %cl >> rep movsb > >I guess we don't care that this movs 256 bytes extra when al & 3 = 0. No, it doesn't. "rep movs" doesn't do anything if (e)cx = 0. Regards, Jens

2 1

Re: [coreboot] r947 - coreboot-v3/northbridge/intel/i440bxemulation
by Carl-Daniel Hailfinger 24 Oct '08

24 Oct '08

On 23.10.2008 14:56, svn(a)coreboot.org wrote: > Author: oxygene > Date: 2008-10-23 14:56:34 +0200 (Thu, 23 Oct 2008) > New Revision: 947 > > Modified: > coreboot-v3/northbridge/intel/i440bxemulation/domain > coreboot-v3/northbridge/intel/i440bxemulation/i440bx.c > Log: > Read actual memory size in qemu-i386 > > Signed-Off-By: Patrick Georgi <patrick(a)georgi-clan.de> > Acked-by: Stefan Reinauer <stepan(a)coresystems.de> > Thanks for the patch. IIRC various qemu versions have different bugs in that area, so I'd appreciate to know on which version the code was tested. Please fix up the leftover warning message as indicated below. The qemu mainboard dts needs to be fixed as well. Regards, Carl-Daniel > Modified: coreboot-v3/northbridge/intel/i440bxemulation/domain > =================================================================== > --- coreboot-v3/northbridge/intel/i440bxemulation/domain 2008-10-23 01:18:30 UTC (rev 946) > +++ coreboot-v3/northbridge/intel/i440bxemulation/domain 2008-10-23 12:56:34 UTC (rev 947) > @@ -19,6 +19,5 @@ > */ > > { > - ramsize = "128"; > device_operations = "i440bx_domain"; > }; > > Modified: coreboot-v3/northbridge/intel/i440bxemulation/i440bx.c > =================================================================== > --- coreboot-v3/northbridge/intel/i440bxemulation/i440bx.c 2008-10-23 01:18:30 UTC (rev 946) > +++ coreboot-v3/northbridge/intel/i440bxemulation/i440bx.c 2008-10-23 12:56:34 UTC (rev 947) > @@ -3,6 +3,7 @@ > * > * Copyright (C) 2000 Ron Minnich, Advanced Computing Lab, LANL > * Copyright (C) 2007 Ronald G. Minnich <rminnich(a)gmail.com> > + * Copyright (C) 2008 Patrick Georgi <patrick(a)georgi-clan.de> > * > * This program is free software; you can redistribute it and/or modify > * it under the terms of the GNU General Public License as published by > @@ -43,19 +44,30 @@ > #include <device/device.h> > #include <device/pci.h> > #include <string.h> > +#include <io.h> > #include "i440bx.h" > #include <statictree.h> > > /* Here are the ops for 440BX as a PCI domain. */ > > +static int inb_cmos(int port) > +{ > + outb(port, 0x70); > + return inb(0x71); > +} > + > static void pci_domain_set_resources(struct device *dev) > { > struct device *mc_dev; > u32 tolmk; /* Top of low mem, Kbytes. */ > int idx; > - struct northbridge_intel_i440bxemulation_domain_config *device_configuration = > - dev->device_configuration; > - tolmk = device_configuration->ramsize * 1024; > + /* read large mem memory descriptor > + for <16 MB read the more detailed small mem descriptor > + all values in kbytes */ > + tolmk = ((inb_cmos(0x35)<<8) |inb_cmos(0x34)) * 64; > + if (tolmk <= 16 * 1024) { > + tolmk = (inb_cmos(0x31)<<8) |inb_cmos(0x30); > + } > printk(BIOS_WARNING, "Ignoring chipset specified RAM size. Using dts " > "settings of %d kB instead.\n", tolmk); > This printk referred to the old code and it now is wrong. > mc_dev = dev->link[0].children; > > > -- > coreboot mailing list: coreboot(a)coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot > > -- http://www.hailfinger.org/

2 1

Re: [coreboot] r3690 - trunk/coreboot-v2/src/pc80/ide
by Peter Stuge 24 Oct '08

24 Oct '08

svn(a)coreboot.org wrote: > Made await_ide(), which polls for an ide status change, check the > status reg much more often. Nice. Thanks Jens! //Peter

1 0

Re: [coreboot] r3688 - in trunk/coreboot-v2/src: arch/i386/init cpu/amd/model_lx
by Peter Stuge 24 Oct '08

24 Oct '08

svn(a)coreboot.org wrote: > + movb %cl, %al > + shrl $2, %ecx > + andb $3, %al > + rep movsl > + movb %al, %cl > rep movsb I guess we don't care that this movs 256 bytes extra when al & 3 = 0. //Peter

1 0

Re: [coreboot] r946 - in coreboot-v3/mainboard: . via via/epia-cn
by Peter Stuge 24 Oct '08

24 Oct '08

svn(a)coreboot.org wrote: > First parts of VIA EPIA-CN support. Could we make it depend on CONFIG_EXPERIMENTAL ? //Peter

2 2

← Newer
1
...
16
17
18
19
20
21
22
...
61
Older →

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

2009

2008

2007

2006

2005

2004

2003

2002

coreboot October 2008