#95: Run coreboot in VirtualBox
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Reporter: uwe | Owner: somebody
Type: defect | Status: new
Priority: minor | Milestone:
Component: misc | Version:
Keywords: | Dependencies:
Patchstatus: there is no patch |
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It would be nice if we could test coreboot images in VirtualBox, see
http://virtualbox.org/.
VirtualBox does not (yet) provide a simple mechanism to use a different
BIOS in their emulated machines (something like "-L" in qemu). Instead the
BIOS image (a custom bochs BIOS + LGPL'g VGABIOS) is converted to C code
(an array of bytes, or the like) and merged into the VirtualBox
executable.
The relevant files are
{{{
src/VBox/Devices/PC/DevPcBios.cpp
bldprogs/bin2c.c
}}}
if someone want to hack VirtualBox to easily support using coreboot images
instead of their usual BIOS.
--
Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/95>
coreboot <http://www.coreboot.org/>
I wanted to know which physical port of my multiple USB controllers have
the debug capability. There was no way to find that easily, so I created
a tool which will do most of the work for the user.
Example output:
The following PCI devices support a USB debug port (says lspci):
0000:00:1d.7
The following PCI devices support a USB debug port (says the kernel):
0000:00:1d.7
PCI device 0000:00:1d.7, USB bus 3, USB physical port 1
Currently connected high-speed devices:
/: Bus 03.Port 1: Dev 1, Class=root_hub, Driver=ehci_hcd/6p, 480M
|__ Port 2: Dev 20, If 0, Class=stor., Driver=usb-storage, 480M
The output can be improved, but it's a good start.
Regards,
Carl-Daniel
--
http://www.hailfinger.org/
#110: Allow for per-device subsystem IDs
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Reporter: uwe | Owner: somebody
Type: enhancement | Status: new
Priority: minor | Milestone:
Component: coreboot | Version: v3
Keywords: | Dependencies:
Patchstatus: there is no patch |
---------------------------------+------------------------------------------
Currently both v2 and v3 only allow us to use one global set of PCI
subsystem IDs, which is too simplistic. In theory (and often in practice)
each PCI device has (or can have) its own subsystem ID.
We should fix this, at least in v3, possibly also in v2.
See also http://www.coreboot.org/pipermail/coreboot/2008-July/036514.html
--
Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/110>
coreboot <http://www.coreboot.org/>
Hello all,
This patch adds support for the Abit AB-BM6 mainboard to flashrom.
The biggest part is a generic function to lower a GPIO line on the PIIX4E
southbridge, copied and adapted from its ich_gpio_raise() counterpart
(mostly lower instead of raise, followed names from the PIIX4E datasheet).
The board specific function then uses this to lower GPO 26.
Signed-off-by: Tim ter Laak <timl(a)scintilla.utwente.nl>
---
The patch was made from the flashrom subdir, because svn diff from the
top-level coreboot dir (as per the directions in the Development
Guidelines on the wiki) didn't seem to work for me. Probably because
flashrom is fetched externally when checking out coreboot? Anyway, I hope
this is okay. If you really prefer a diff from the top-level dir just let
me know, and I'll regenerate it with gnu diff.
Kind regards,
Tim.
Index: board_enable.c
===================================================================
--- board_enable.c (revision 3559)
+++ board_enable.c (working copy)
@@ -349,6 +349,58 @@
}
/**
+ * Set the specified GPIO on the specified PIIX4 southbridge to low.
+ *
+ * @param name The name of this board.
+ * @param piix_vendor PCI vendor ID of the specified PIIX4 southbridge. (0x8086)
+ * @param piix_device PCI device ID of the specified PIIX4 southbridge, function Power Management (0x7113 for PIIX4E)
+ * @param pmbase_reg PMBASE register offset in the bridge. (0x40 for PIIX4E)
+ * @param pmbase_mask PMBASE bitmask (0xFFC0)
+ * @param gporeg Offset of GPOREG register in I/O space, relative to GPIOBASE. (0x34)
+ * @param gpio_bit The bit (GPIO) which shall be set to low.
+ * @return If the write-enable was successful return 0, otherwise return -1.
+ */
+static int piix4_gpio_lower(const char *name, uint16_t piix_vendor,
+ uint16_t piix_device, uint8_t pmbase_reg,
+ uint8_t gporeg, uint32_t pmbase_mask,
+ unsigned int gpio_bit)
+{
+ struct pci_dev *dev;
+ uint16_t pmbar;
+ uint32_t reg32;
+
+ dev = pci_dev_find(piix_vendor, piix_device); /* Intel PIIX4 ACPI function */
+ if (!dev) {
+ fprintf(stderr, "\nERROR: PIIX4 dev %4x:%4x not found.\n",
+ piix_vendor, piix_device);
+ return -1;
+ }
+
+ /* Use PMBASE register to find the I/O space for GPIO. */
+ pmbar = pci_read_word(dev, pmbase_reg) & pmbase_mask;
+
+ /* Set specified GPIO to high. */
+ reg32 = INL(pmbar + gporeg);
+ OUTB(0x00, 0xEB); /* dummy write to unused port as delay */
+
+ reg32 &= ~(1 << gpio_bit);
+ OUTL(reg32, pmbar + gporeg);
+ OUTB(0x00, 0xEB); /* another delay */
+
+ return 0;
+}
+
+/**
+ * Suited for Abit AB-BM6.
+ */
+static int piix4_gpio26_lower(const char *name)
+{
+ return piix4_gpio_lower(name, 0x8086, 0x7113, 0x40, 0x34, 0xffc0, 26);
+}
+
+
+
+/**
* Suited for Acorp 6A815EPD.
*/
static int board_acorp_6a815epd(const char *name)
@@ -672,6 +724,8 @@
NULL, NULL, "GIGABYTE GA-7VT600", board_biostar_p4m80_m4},
{0x1106, 0x3149, 0x1462, 0x7094, 0x10ec, 0x8167, 0x1462, 0x094c,
NULL, NULL, "MSI K8T Neo2", w83627thf_gpio4_4_raise_2e},
+ {0x8086, 0x7190, 0x0000, 0x0000, 0x8086, 0x7110, 0x0000, 0x0000,
+ "abit", "ab-bm6", "Abit AB-BM6", piix4_gpio26_lower},
{0, 0, 0, 0, 0, 0, 0, 0, NULL, NULL} /* Keep this */
};
Hi,
Why is it problem to boot from an usb port when we are using linuxbios and
filo. as I can see all usb code are there, what is missing?
Thanks,
/Masoud
#108: Add int 10 VESA video driver to libpayload
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Reporter: stuge | Owner: somebody
Type: enhancement | Status: new
Priority: major | Milestone:
Component: libpayload | Version:
Keywords: video | Dependencies:
Patchstatus: there is no patch |
---------------------------------+------------------------------------------
--
Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/108>
coreboot <http://www.coreboot.org/>
#104: flashrom: Change flash drivers to never erase data before writing
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Reporter: stuge | Owner: somebody
Type: defect | Status: new
Priority: major | Milestone: flashrom v1.0
Component: flashrom | Version:
Keywords: erase write | Dependencies: #103
Patchstatus: there is no patch |
---------------------------------+------------------------------------------
The user should be responsible for ensuring that the flash chip has been
erased where new data should be written.
At the moment, flashrom will erase at least one full page and then rewrite
it, when the user asks to only write a few bytes using -l/-i/-s/-e.
--
Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/104>
coreboot <http://www.coreboot.org/>
