coreboot October 2008

coreboot@coreboot.org

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608 discussions

#101: flashrom: Remove pciutils check from Makefile
by coreboot 16 Jan '10

16 Jan '10

#101: flashrom: Remove pciutils check from Makefile ---------------------------------------------+------------------------------ Reporter: stuge | Owner: somebody Type: defect | Status: new Priority: major | Milestone: flashrom v1.0 Component: flashrom | Version: Keywords: pciutils libpci build ldflags | Dependencies: Patchstatus: patch needs review | ---------------------------------------------+------------------------------ The check belongs in a configure script or similar, the check also claims that packages can not be found for any build error, which is not good enough. Has confused more than one user already. -- Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/101> coreboot <http://www.coreboot.org/>

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#113: problem
by coreboot 16 Jan '10

16 Jan '10

#113: problem ---------------------------------+------------------------------------------ Reporter: anonymous | Owner: somebody Type: defect | Status: new Priority: major | Milestone: Component: adlo | Version: v2 Keywords: | Dependencies: Patchstatus: there is no patch | ---------------------------------+------------------------------------------ there is a bug -- Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/113> coreboot <http://www.coreboot.org/>

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#106: flashrom: Add -T to automatically test all flash chip operations
by coreboot 16 Jan '10

16 Jan '10

#106: flashrom: Add -T to automatically test all flash chip operations ---------------------------------+------------------------------------------ Reporter: stuge | Owner: somebody Type: enhancement | Status: new Priority: major | Milestone: flashrom v1.0 Component: flashrom | Version: Keywords: testing | Dependencies: Patchstatus: there is no patch | ---------------------------------+------------------------------------------ Maybe require -f to actually perform the test, since it will potentially fail to restore the flash chip to it's original state. -- Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/106> coreboot <http://www.coreboot.org/>

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sony vaio pcg sr1k
by misi e 21 Jul '09

21 Jul '09

Hello, as I posted on the blog of Uwe, I have a sony vaio pcg sr1k laptop, and wonder if I could flash it with coreboot. The box has Intel Corporation 440BX/ZX/DX - 82443BX/ZX/DX Host bridge chipset. hovewer the results of the following commands are not encouriging, please tell me if there is any chance to get coreboot working. Please find attached the outpoot of the commands. sudo superiotool -dV > siot.out lspci -tvnn > lspci.out sudo flashrom -V

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#100: flashrom: Change start/end -s and -e to -S and -E, and change erase -E to -e.
by coreboot 19 Jun '09

19 Jun '09

#100: flashrom: Change start/end -s and -e to -S and -E, and change erase -E to -e. -------------------------------------+-------------------------------------- Reporter: stuge | Owner: somebody Type: enhancement | Status: new Priority: major | Milestone: flashrom v1.0 Component: flashrom | Version: Keywords: usability cli options | Dependencies: Patchstatus: patch needs review | -------------------------------------+-------------------------------------- -- Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/100> coreboot <http://www.coreboot.org/>

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Re: [coreboot] Tyan Product Listings
by joelr＠tyan.com 07 May '09

07 May '09

Stefan, Here is a list of products we have tested thus far and have found will work just fine with FlashROM Motherboard Flash Utility Support Spreadsheet Bios Chip Vendor Bios Chip Part # Motherboard Linux Flash Utility FlashROM (v3332) FlashROM (v3332) OS Support 32-bit Distributions 64-bit Distributions S5377 Yes SST 49LF008A S5376G2NR Yes Yes SST 49LF008A S5376WAG2NR Yes Yes SST 49LF008A S5375 Yes SST 49LF008A S5375-1U Yes SST 49LF008A S5220 Yes SST 49LF008A S5211 Yes Yes SST 49LF008A S5211-1U Yes Yes SST 49LF008A S5197 Yes SST 49LF008A S5191 Yes SST 49LF008A S5180 Yes SST 49LF008A S3095 Yes SST 49LF008A S2882 Yes Yes PMC 49LF004T S2882-D Yes Yes PMC 49LF004T S2881 Yes Yes PMC 49LF004T Our process is still ongoing so we will have new updates periodically to help include new FlashROM versions as well as new Tyan motherboards to this listing. Our plans are to go through our current product listings and see if we can get FlashROM to work on them. We want to be able to add something other than AMI, Award or Phoenix as a flash utility for our customers. We have been pleased with what the FlashROM utility does and we are working on further validation with this particular utility. Thanks again for your reply and we will continue to stay in touch as new updates are made available. Joel Robertson Tech Support Manager Customer Service Manager Vendor Relations Manager joelr(a)tyan.com (510) 651-8868 ext. 5196 ________________________________ From: coreboot-bounces(a)coreboot.org [mailto:coreboot-bounces@coreboot.org] On Behalf Of Stefan Reinauer Sent: Tuesday, August 26, 2008 5:39 PM To: joelr (joelr - TYANUS) Cc: coreboot(a)coreboot.org Subject: Re: [coreboot] Tyan Product Listings Dear Joel Robertson, thank you very much for your interest in coreboot and flashrom! If a specific mainboard was tested and is working, please send a mail containing the mainboard and the flash chip you used, and what you tested on that mainboard+flash combination (verify, read, erase, write) to either coreboot(a)coreboot.rom or flashrom(a)coreboot.rom. Then we can update the web pages accordingly. In case you wish to have new, currently unsupported mainboards supported by flashrom, let us know here, too. I think we can help. Best regards, Stefan Reinauer joelr(a)tyan.com wrote: To Whomever it may concern: We would like to update the motherboard listings that support the FlashROM software. We have additional motherboards that we would like to have listed but we need clarification on the process of how to go about this. We have verified that the FlashROM does work in a 32-bit and 64-bit linux environment. We have also made sure that it will verify, read, erase and write a bios chip successfully. Please let us know what we need to update the current support listings on the coreboot.org site. Thanks, Joel Robertson Tech Support Manager Customer Service Manager Vendor Relations Manager joelr(a)tyan.com (510) 651-8868 ext. 5196 -- coreboot mailing list coreboot(a)coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot -- coresystems GmbH * Brahmsstr. 16 * D-79104 Freiburg i. Br. Tel.: +49 761 7668825 * Fax: +49 761 7664613 Email: info(a)coresystems.de * http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg * HRB 7656 Geschäftsführer: Stefan Reinauer * Ust-IdNr.: DE245674866

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[PATCH]es 7 assorted fixes
by Jens Rottmann 19 Mar '09

19 Mar '09

route_irq15.diff (changes pirq_routing.c): Fixes a off-by-one error when routing the IRQs. This led to IRQ15 not getting assigned. autoboot_delay.diff (changes filo.c): Fixes compile error when AUTOBOOT_DELAY=0. dword_copy.diff (changes crt0.S.lb, cache_as_ram.inc (Geode LX)): Speed up copying coreboot to ram by using "movsl" instead of "movsb". Also use different console messages for copying and uncompressing, like it's already done in similar code in other places. speed_calc.diff (changes raminit.c (Geode LX)): Changed RAM speed calculation to fix RAM modules getting rejected only due to integer rounding errors. Previously, the formula was: speed = 2 * (10000/spd_value) For spd_value=60 this means speed = 2 * 166 = 332, which is less than 333 and coreboot died saying RAM was incompatible. The new formula is: speed = 20000 / spd_value For spd_value=60, speed=333, which is fine. await_ide.diff (changes ide.c): Made await_ide(), which polls for an ide status change, check the status reg much more often. In my case this reduced the time spent in coreboot by 1.5 sec! The timeout values of course aren't changed, only the granularity. Also, I didn't see any udelay() implementation that looked like it couldn't cope with 10 us delays. (Most are written as for (...) inb(0x80) loops.) fs_arch.diff (changes ext2fs.c, fat.c): #if ARCH == 'i386' results in a compile error: character constant too long (or something alike). Changed it to #ifdef __i386 I'm unsure if this is correct, though! Why didn't anyone hit this problem before? Is this some ROMCC-special? it8712_gpio.diff (changes superio.c (IT8712F)): Added the missing I/O resources for IT8712F GPIOs. Our boards need these e.g. to switch the com ports between RS232 and RS485. Signed-off-by: Jens Rottmann <JRottmann(a)LiPPERTEmbedded.de> --- Above are fixes for some issues I tripped over while working on coreboot support for some of our boards. The patches can be applied in any order. (Should I have sent 7 seperate mails? I deemed it easier this way ...) I'll contribute the actual mainboard files as soon as I'm done. Regards, Jens Rottmann Index: src/stream/fs/ext2fs.c =================================================================== --- src/stream/fs/ext2fs.c (revision 3677) +++ src/stream/fs/ext2fs.c (working copy) @@ -239,7 +239,7 @@ * ffz = Find First Zero in word. Undefined if no zero exists, * so code should check against ~0UL first.. */ -#if ARCH == 'i386' +#ifdef __i386 static __inline__ unsigned long ffz (unsigned long word) { Index: src/stream/fs/fat.c =================================================================== --- src/stream/fs/fat.c (revision 3677) +++ src/stream/fs/fat.c (working copy) @@ -54,7 +54,7 @@ #define FAT_CACHE_SIZE 2048 -#if ARCH == 'i386' +#ifdef __i386 static __inline__ unsigned long log2 (unsigned long word) { Index: src/superio/ite/it8712f/superio.c =================================================================== --- src/superio/ite/it8712f/superio.c (revision 3677) +++ src/superio/ite/it8712f/superio.c (working copy) @@ -129,7 +129,7 @@ {&ops, IT8712F_EC, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0xff8, 0}, {0xff8, 4},}, {&ops, IT8712F_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0xfff, 0}, {0xfff, 4},}, {&ops, IT8712F_KBCM, PNP_IRQ0,}, - {&ops, IT8712F_GPIO,}, + {&ops, IT8712F_GPIO, PNP_IO0 | PNP_IO1 | PNP_IO2 | PNP_IRQ0, {0xfff, 0}, {0xff8, 0}, {0xff8, 0},}, {&ops, IT8712F_MIDI, PNP_IO0 | PNP_IRQ0, {0xff8, 0},}, {&ops, IT8712F_GAME, PNP_IO0, {0xfff, 0},}, {&ops, IT8712F_IR, PNP_IO0 | PNP_IRQ0, {0xff8, 0},}, Index: src/arch/i386/boot/pirq_routing.c =================================================================== --- src/arch/i386/boot/pirq_routing.c (revision 3677) +++ src/arch/i386/boot/pirq_routing.c (working copy) @@ -137,7 +137,7 @@ /* yet not routed */ if (!pirq[link - 1]) { - for (k = 2; k < 15; k++) { + for (k = 2; k <= 15; k++) { if (!((bitmap >> k) & 1)) continue; Index: src/northbridge/amd/lx/raminit.c =================================================================== --- src/northbridge/amd/lx/raminit.c (revision 3677) +++ src/northbridge/amd/lx/raminit.c (working copy) @@ -194,7 +194,7 @@ } /* Turn SPD ns time into MHZ. Check what the asm does to this math. */ - speed = 2 * ((10000 / (((spd_byte0 >> 4) * 10) + (spd_byte0 & 0x0F)))); + speed = 20000 / (((spd_byte0 >> 4) * 10) + (spd_byte0 & 0x0F)); /* current speed > max speed? */ if (GeodeLinkSpeed() > speed) { @@ -274,15 +274,14 @@ spd_byte = spd_read_byte(DIMM0, SPD_SDRAM_CYCLE_TIME_2ND); if (spd_byte != 0) { /* Turn SPD ns time into MHZ. Check what the asm does to this math. */ - dimm_speed = 2 * (10000 / (((spd_byte >> 4) * 10) + - (spd_byte & 0x0F))); + dimm_speed = 20000 / (((spd_byte >> 4) * 10) + (spd_byte & 0x0F)); if (dimm_speed >= glspeed) { casmap_shift = 1; /* -.5 is a shift of 1 */ /* IF -1 timing is supported, check -1 timing > GeodeLink */ spd_byte = spd_read_byte(DIMM0, SPD_SDRAM_CYCLE_TIME_3RD); if (spd_byte != 0) { /* Turn SPD ns time into MHZ. Check what the asm does to this math. */ - dimm_speed = 2 * (10000 / (((spd_byte >> 4) * 10) + (spd_byte & 0x0F))); + dimm_speed = 20000 / (((spd_byte >> 4) * 10) + (spd_byte & 0x0F)); if (dimm_speed >= glspeed) { casmap_shift = 2; /* -1 is a shift of 2 */ } @@ -306,14 +305,14 @@ spd_byte = spd_read_byte(DIMM1, SPD_SDRAM_CYCLE_TIME_2ND); if (spd_byte != 0) { /* Turn SPD ns time into MHZ. Check what the asm does to this math. */ - dimm_speed = 2 * (10000 / (((spd_byte >> 4) * 10) + (spd_byte & 0x0F))); + dimm_speed = 20000 / (((spd_byte >> 4) * 10) + (spd_byte & 0x0F)); if (dimm_speed >= glspeed) { casmap_shift = 1; /* -.5 is a shift of 1 */ /* IF -1 timing is supported, check -1 timing > GeodeLink */ spd_byte = spd_read_byte(DIMM1, SPD_SDRAM_CYCLE_TIME_3RD); if (spd_byte != 0) { /* Turn SPD ns time into MHZ. Check what the asm does to this math. */ - dimm_speed = 2 * (10000 / (((spd_byte >> 4) * 10) + (spd_byte & 0x0F))); + dimm_speed = 20000 / (((spd_byte >> 4) * 10) + (spd_byte & 0x0F)); if (dimm_speed >= glspeed) { casmap_shift = 2; /* -1 is a shift of 2 */ } Index: src/boot/filo.c =================================================================== --- src/boot/filo.c (revision 3677) +++ src/boot/filo.c (working copy) @@ -18,7 +18,7 @@ #define autoboot(mem) #endif -#ifndef AUTOBOOT_DELAY +#if !AUTOBOOT_DELAY #define autoboot_delay() 0 /* success */ #endif Index: src/pc80/ide/ide.c =================================================================== --- src/pc80/ide/ide.c (revision 3677) +++ src/pc80/ide/ide.c (working copy) @@ -29,6 +29,7 @@ struct controller *ctrl, unsigned long timeout) { int result; + timeout *= 100; /* timeout was ms; finer granularity => reacts faster */ for(;;) { result = done(ctrl); if (result) { @@ -38,7 +39,7 @@ if (timeout-- <= 0) { break; } - udelay(1000); /* Added to avoid spinning GRW */ + udelay(10); /* Added to avoid spinning GRW */ } printk_info("IDE time out\n"); return -1; Index: src/arch/i386/init/crt0.S.lb =================================================================== --- src/arch/i386/init/crt0.S.lb (revision 3677) +++ src/arch/i386/init/crt0.S.lb (working copy) @@ -74,6 +74,11 @@ movl $_iseg, %edi movl $_eiseg, %ecx subl %edi, %ecx + movb %cl, %al + shrl $2, %ecx + andb $3, %al + rep movsl + movb %al, %cl rep movsb #else leal 4+_liseg, %esi @@ -215,7 +220,11 @@ #if defined(CONSOLE_DEBUG_TX_STRING) && (ASM_CONSOLE_LOGLEVEL > BIOS_DEBUG) .section ".rom.data" +#if CONFIG_COMPRESS +str_copying_to_ram: .string "Uncompressing coreboot to RAM.\r\n" +#else str_copying_to_ram: .string "Copying coreboot to RAM.\r\n" +#endif str_pre_main: .string "Jumping to coreboot.\r\n" .previous Index: src/cpu/amd/model_lx/cache_as_ram.inc =================================================================== --- src/cpu/amd/model_lx/cache_as_ram.inc (revision 3677) +++ src/cpu/amd/model_lx/cache_as_ram.inc (working copy) @@ -222,6 +222,11 @@ movl $_iseg, %edi movl $_eiseg, %ecx subl %edi, %ecx + movb %cl, %al + shrl $2, %ecx + andb $3, %al + rep movsl + movb %al, %cl rep movsb #else leal 4+_liseg, %esi @@ -363,7 +368,11 @@ #if defined(CONSOLE_DEBUG_TX_STRING) && (ASM_CONSOLE_LOGLEVEL > BIOS_DEBUG) .section ".rom.data" +#if CONFIG_COMPRESS +str_copying_to_ram: .string "Uncompressing coreboot to ram.\r\n" +#else str_copying_to_ram: .string "Copying coreboot to ram.\r\n" +#endif str_pre_main: .string "Jumping to coreboot.\r\n" .previous

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#114: Use GCCINCDIR instead of open-coding it
by coreboot 13 Mar '09

13 Mar '09

#114: Use GCCINCDIR instead of open-coding it -----------------------------------------+---------------------------------- Reporter: vincent.legoll(a)gmail.com | Type: enhancement Status: new | Priority: trivial Milestone: | Component: filo Version: v2 | Keywords: makefile Dependencies: | Patchstatus: patch is ready to be committed -----------------------------------------+---------------------------------- in trunk/filo/Makefile, there is duplicated code to get gcc include directory, the attached patch fixes that. -- Ticket URL: </trac/ticket/114> coreboot <http://www.coreboot.org/>

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#105: flashrom: add documentation files (ChangeLog etc) that need to be in the release
by coreboot 16 Feb '09

16 Feb '09

#105: flashrom: add documentation files (ChangeLog etc) that need to be in the release ---------------------------------+------------------------------------------ Reporter: stuge | Owner: somebody Type: enhancement | Status: new Priority: blocker | Milestone: flashrom v1.0 Component: flashrom | Version: Keywords: documentation | Dependencies: Patchstatus: there is no patch | ---------------------------------+------------------------------------------ -- Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/105> coreboot <http://www.coreboot.org/>

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[LinuxBIOS] Add initial support for intel i855gme northbridge
by Jon Dufresne 20 Jan '09

20 Jan '09

Add initial support for i855gme. This is a work in progress and I don't expect it to work on all boards, or even any besides mine. This is based heavily on i855pm. Signed off by Jon Dufresne <jon.dufresne(a)gmail.com>

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coreboot October 2008