coreboot October 2008

coreboot@coreboot.org

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608 discussions

[v2][patch] update k8 fid/vid setup
by Marc Jones 03 Nov '08

03 Nov '08

See attached patch. Marc -- Marc Jones Senior Firmware Engineer (970) 226-9684 Office mailto:Marc.Jones@amd.com http://www.amd.com/embeddedprocessors Update K8 FID/VID setup. Add support for 100MHz FIDs (revG). Signed-off-by: Marc Jones <marc.jones(a)amd.com> Index: coreboot-v2/src/cpu/amd/model_fxx/fidvid.c =================================================================== --- coreboot-v2.orig/src/cpu/amd/model_fxx/fidvid.c 2008-08-22 07:38:01.000000000 -0600 +++ coreboot-v2/src/cpu/amd/model_fxx/fidvid.c 2008-08-22 13:08:15.000000000 -0600 @@ -99,27 +99,34 @@ static unsigned set_fidvid(unsigned apicid, unsigned fidvid, int showmessage) { - /* for (cur, new) there is one <1600MHz x8 to find out next_fid */ - static const uint8_t next_fid_a[] = { - /* x4 x5 x6 x7 x8 x9 x10 x11 x12 x13 x14 x15 */ -/* x4 */ 0, 9, 9, 8, 9, 9, 9, 9, 9, 9, 9, 9, -/* x5 */ 9, 0, 11, 11, 9, 9, 10, 11, 11, 11, 11, 11, -/* x6 */ 11, 11, 0, 13, 11, 11, 11, 11, 12, 13, 13, 13, -/* x7 */ 13, 13, 13, 0, 13, 13, 13, 13, 13, 13, 14, 15, -/* x8 */ 4, 9, 9, 9, 0, 9, 9, 9, 9, 9, 9, 9, -/* x9 */ 4, 5, 10, 10, 8, 0, 0, 0, 0, 0, 0, 0, -/*x10 */ 9, 5, 11, 11, 9, 0, 0, 0, 0, 0, 0, 0, -/*x11 */ 10, 5, 6, 12, 10, 0, 0, 0, 0, 0, 0, 0, -/*x12 */ 11, 11, 6, 13, 11, 0, 0, 0, 0, 0, 0, 0, -/*x13 */ 12, 12, 6, 7, 12, 0, 0, 0, 0, 0, 0, 0, -/*x14 */ 13, 13, 13, 7, 13, 0, 0, 0, 0, 0, 0, 0, -/*x15 */ 14, 14, 14, 7, 14, 0, 0, 0, 0, 0, 0, 0, -/* 0:x4, 2:x5....BASE=4, MIN=4, MAX=25, INC=2 result = (xX-BASE)*INC */ + +/* CurrentFID--> 4x(00h) 5x(02h) 6x(04h) 7x(06h) ... + * -------------------------------------- + * TargetFID | Next_FID, Next_FID, Next_FID, Next_FID ... + * | | Next_FID, Next_FID, Next_FID, Next_FID ... + * \|/ | Next_FID, Next_FID, Next_FID, Next_FID ... + */ + static const uint8_t next_fid_200[] = { +/* x4 x5 x6 x7 x8 x9 x10 x11 x12 x13 x14 x15 x16 */ +/* x4 */ 0, -1, -1, -1, 0, 0, 9, 10, 11, 12, 13, 14, 15, /* 800 */ +/* x5 */ -1, 0, -1, -1, -1, 5, 5, 5, 11, 12, 13, 14, 15, /* 1000 */ +/* x6 */ -1, -1, 0, -1, -1, -1, -1, 6, 6, 6, 13, 14, 15, /* 1200 */ +/* x7 */ -1, -1, -1, 0, -1, -1, -1, -1, -1, 7, 7, 7, 15, /* 1400 */ +/* lower table to upper table boarder (table 70 and 71 in BKDG) */ +/* x8 */ 8, -1, -1, -1, 0, 8, 9, 10, 11, 12, 13, 14, 15, /* 1600 */ +/* x9 */ 9, 9, -1, -1, 9, 0, 9, 10, 11, 12, 13, 14, 15, /* 1800 */ +/*x10 */ 9, 10, -1, -1, 9, 10, 0, 10, 11, 12, 13, 14, 15, /* 2000 */ +/*x11 */ 9, 11, 11, -1, 9, 10, 11, 0, 11, 12, 13, 14, 15, /* 2200 */ +/*x12 */ 9, 11, 12, -1, 9, 10, 11, 12, 0, 12, 13, 14, 15, /* 2400 */ +/*x13 */ 9, 11, 13, 13, 9, 10, 11, 12, 13, 0, 13, 14, 15, /* 2600 */ +/*x14 */ 9, 11, 13, 14, 9, 10, 11, 12, 13, 14, 0, 14, 15, /* 2800 */ +/*x15 */ 9, 11, 13, 15, 9, 10, 11, 12, 13, 14, 15, 0, 15, /* 3000 */ +/*x15 */ 9, 11, 13, 15, 9, 10, 11, 12, 13, 14, 15, 16, 0, /* 3200 */ }; msr_t msr; - uint32_t vid; - uint32_t fid; + uint32_t vid_new; + uint32_t fid_new; uint32_t vid_max; uint32_t fid_max; uint32_t vid_cur; @@ -140,19 +147,20 @@ return fidvid; } - fid = (fidvid >> 8) & 0x3f; - vid = (fidvid >> 16) & 0x3f; + fid_new = (fidvid >> 8) & 0x3f; + vid_new = (fidvid >> 16) & 0x3f; msr = rdmsr(0xc0010042); vid_cur = msr.hi & 0x3f; fid_cur = msr.lo & 0x3f; - if ((vid_cur==vid) && (fid_cur==fid)) + if ((vid_cur==vid_new) && (fid_cur==fid_new)) return fidvid; vid_max = (msr.hi>>(48-32)) & 0x3f; fid_max = ((msr.lo>>16) & 0x3f); /* max fid */ + #if FX_SUPPORT if (fid_max>=((25-4)*2)) { /* FX max fid is 5G */ fid_max = ((msr.lo >> 8) & 0x3f) + 5 * 2; /* max FID is min fid + 1G */ @@ -163,10 +171,20 @@ #endif /* set vid to max */ + /* TODO - make this more correct. Not a big deal for setting max... + * BKDG figure 11 + * if TargetFID > InitialFID + * TargetVID = FinalVID - RVO + * else + * if CurrentVID > FinalVID + * TargetVID = FinalVID - RVO + * else + * TargetVID = CurrentVIDD - RVO + */ msr.hi = 1; msr.lo = (vid_max << 8) | (fid_cur); #if SB_VFSMAF == 1 - msr.lo |= (1<<16); /* init changes */ + msr.lo |= (1 << 16); /* init changes */ #endif wrmsr(0xc0010041, msr); #if SB_VFSMAF == 0 @@ -181,31 +199,63 @@ } vid_cur = msr.hi & 0x3f; - steps = 8; //?? - while ((fid_cur != fid) && (steps-- > 0)) { + /* BKDG figure 12 and 13 + * if current fid is odd + * current fid -1 (next lower and even fid)(odd fid for rev G) + * if current fid in high-freq table + * while current fid < target fid + * transition to next higher fid in table + * else if target fid > VCO portal of current fid + * transition to highest portal fid in higher fid table + * while current fid < target fid + * transition to next higher fid in table + * else + * transition to target fid + */ + + steps = 8; /* max 8 steps just in case... */ + while ((fid_cur != fid_new) && (steps-- > 0)) { uint32_t fid_temp; - if ((fid_cur > (8-4)*2) && (fid> (8-4)*2)) { - if (fid_cur<fid) { - fid_temp = fid_cur + 2; - } else { + + /* If more than a 200Mhz step */ + if ((fid_cur - 2 != fid_new) && (fid_cur + 2 != fid_new)) { + /* Find the table value if it is in the table */ + if (fid_new <= 0x18) { /* 3200 max table value */ + int temp; + + temp = next_fid_200[((fid_cur/2) * 13) + (fid_new/2)]; + + if (temp > 0) + fid_temp = (temp-4) * 2; + else if (temp == 0) + fid_temp = fid_new; + else + break; /* table error */ + + } else { /* above table, step +/- 200MHz at a time */ + if (fid_cur < fid_new) + fid_temp = fid_cur + 2; + else fid_temp = fid_cur - 2; - } - } else { - /* there is one < 8, So we need to lookup the table to - * find the fid_cur */ - int temp; - temp = next_fid_a[(fid_cur/2)*12+(fid/2)]; - if (temp <= 0) break; - fid_temp = (temp-4) * 2; + } + } else { /* just do the 200Mhz step */ + fid_temp = fid_new; + } + + /* The table adjust in 200MHz increments. If the next table + * entry is higher than the requested fid we can do + * the 100MHz increment if the CPU supports it.*/ + if (cpuid_ecx(0x80000007) & (1 << 6)) { /* 100MHz? */ + if ((fid_temp > fid_new) && (fid_cur < fid_new)) + fid_temp = fid_new; } - if (fid_temp > fid_max) - break; - fid_cur = fid_temp; + if(fid_temp>fid_max) + break; /* set target fid */ - msr.hi = (100000/5); - msr.lo = (vid_cur << 8) | fid_cur; + msr.hi = 0x190; /* 2 us for AMD NPT Family 0Fh Processors */ + msr.lo = (vid_cur << 8) | fid_temp; #if SB_VFSMAF == 1 msr.lo |= (1 << 16); /* init changes */ #endif @@ -231,14 +281,24 @@ #if K8_SET_FIDVID_DEBUG == 1 if (showmessage) { - print_debug_fv_64("status msr fid, vid ", msr.hi, msr.lo); + print_debug_fv_64("status msr fid, vid ", msr.hi, msr.lo); } #endif } /* set vid to final */ + /* TODO - make this more correct. Not a big deal for setting max... + * BKDG figure 11 + * if TargetFID > InitialFID + * TargetVID = FinalVID - RVO + * else + * if CurrentVID > FinalVID + * TargetVID = FinalVID - RVO + * else + * TargetVID = CurrentVIDD - RVO + */ msr.hi = 1; - msr.lo = (vid << 8) | (fid_cur); + msr.lo = (vid_new << 8) | (fid_cur); #if SB_VFSMAF == 1 msr.lo |= (1 << 16); // init changes #endif @@ -257,10 +317,10 @@ fidvid = (vid_cur << 16) | (fid_cur << 8); if (showmessage) { - if (vid!=vid_cur) { + if (vid_new!=vid_cur) { print_err("set vid failed for apicid ="); print_err_hex8(apicidx); print_err("\r\n"); } - if (fid!=fid_cur) { + if (fid_new!=fid_cur) { print_err("set fid failed for apicid ="); print_err_hex8(apicidx); print_err("\r\n"); } }

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[PATCH] flashrom: More SPI erase functions
by Carl-Daniel Hailfinger 03 Nov '08

03 Nov '08

As promised to Stefan, here's the flashrom patch I've been talking about. Add additional SPI sector erase and chip erase command functions to flashrom. Not all chips support all commands, so allow the implementer to select the matching function. Fix a layering violation in ICH SPI code to be less bad. Still not perfect, but the new code is shorter, more generic and architecturally more sound. TODO (in a separate patch): - move the generic sector erase code to spi.c - decide which erase command to use based on info about the chip - create a generic spi_erase_all_sectors function which calls the generic sector erase function Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-spi_erase/flash.h =================================================================== --- flashrom-spi_erase/flash.h (Revision 3471) +++ flashrom-spi_erase/flash.h (Arbeitskopie) @@ -417,7 +417,10 @@ int spi_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); void spi_write_enable(); void spi_write_disable(); +int spi_chip_erase_60(struct flashchip *flash); int spi_chip_erase_c7(struct flashchip *flash); +int spi_block_erase_52(const struct flashchip *flash, unsigned long addr); +int spi_block_erase_d8(const struct flashchip *flash, unsigned long addr); int spi_chip_write(struct flashchip *flash, uint8_t *buf); int spi_chip_read(struct flashchip *flash, uint8_t *buf); uint8_t spi_read_status_register(); Index: flashrom-spi_erase/spi.c =================================================================== --- flashrom-spi_erase/spi.c (Revision 3471) +++ flashrom-spi_erase/spi.c (Arbeitskopie) @@ -266,6 +266,22 @@ } } +int spi_chip_erase_60(struct flashchip *flash) +{ + const unsigned char cmd[JEDEC_CE_60_OUTSIZE] = {JEDEC_CE_60}; + + spi_disable_blockprotect(); + spi_write_enable(); + /* Send CE (Chip Erase) */ + spi_command(sizeof(cmd), 0, cmd, NULL); + /* Wait until the Write-In-Progress bit is cleared. + * This usually takes 1-85 s, so wait in 1 s steps. + */ + while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) + sleep(1); + return 0; +} + int spi_chip_erase_c7(struct flashchip *flash) { const unsigned char cmd[JEDEC_CE_C7_OUTSIZE] = {JEDEC_CE_C7}; @@ -282,6 +298,24 @@ return 0; } +int spi_block_erase_52(const struct flashchip *flash, unsigned long addr) +{ + unsigned char cmd[JEDEC_BE_52_OUTSIZE] = {JEDEC_BE_52}; + + cmd[1] = (addr & 0x00ff0000) >> 16; + cmd[2] = (addr & 0x0000ff00) >> 8; + cmd[3] = (addr & 0x000000ff); + spi_write_enable(); + /* Send BE (Block Erase) */ + spi_command(sizeof(cmd), 0, cmd, NULL); + /* Wait until the Write-In-Progress bit is cleared. + * This usually takes 100-4000 ms, so wait in 100 ms steps. + */ + while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) + usleep(100 * 1000); + return 0; +} + /* Block size is usually * 64k for Macronix * 32k for SST Index: flashrom-spi_erase/ichspi.c =================================================================== --- flashrom-spi_erase/ichspi.c (Revision 3471) +++ flashrom-spi_erase/ichspi.c (Arbeitskopie) @@ -452,17 +452,8 @@ static int ich_spi_erase_block(struct flashchip *flash, int offset) { - printf_debug("ich_spi_erase_block: offset=%d, sectors=%d\n", - offset, 1); - - if (run_opcode(2, curopcodes->opcode[2], offset, 0, NULL) != 0) { - printf_debug("Error erasing sector at 0x%x", offset); - return -1; - } - - printf("DONE BLOCK 0x%x\n", offset); - - return 0; + /* FIMXE: call the chip-specific spi_block_erase_XX instead. */ + return spi_block_erase_d8(flash, offset); } static int ich_spi_read_page(struct flashchip *flash, uint8_t * buf, int offset, int maxdata) -- http://www.hailfinger.org/

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coreboot.v2+seabios on 440bx: option roms not found
by Andriy Gapon 03 Nov '08

03 Nov '08

In northbridge/intel/i440bx/raminit.c:sdram_set_spd_registers all PAM registers are programmed for RAM R/W access (0x33). When SeaBIOS searches for option ROMs (including VGA ROM) it doesn't do anything about PAM, so it sees empty memory instead of the ROMs. I am not sure what is the best solution here. It is debatable how coreboot should set PAM register, and it is not right to make SeaBIOS too hardware dependent. Maybe coreboot could somehow export functions for setting access to option ROM space (aka legacy memory segments) and SeaBIOS could call them. -- Andriy Gapon

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Fwd: Flashrom problem
by Collin Gregory 02 Nov '08

02 Nov '08

The problem is still unsolved, does ainyone have got an idear ? Could it be a kernel configuration problem ? ---------- Forwarded message ---------- From: Collin Gregory <collin.gregory(a)gmail.com> Date: 2008/10/31 Subject: Re: [coreboot] Flashrom problem To: Myles Watson <mylesgw(a)gmail.com> Hello Myles, Thanks for your quick answer. Here is my command line that i typed : ./flashrom -r test Here is what ./flashrom -r test -V gives : Calibrating Delay loop... 797M loops per second, 100 myus = 201 us, OK. Can't mmap memory using /dev/mem : Invalid Argument. That's for it. The version of flashrom is the r3708. 2008/10/31 Myles Watson <mylesgw(a)gmail.com> From the comment in flashrom.c, it looks like flashrom is trying to > allocate memory smaller than a page, and failing. It would be helpful if > you posted your command line and the complete output. Probably the output > of ./flashrom –V too. > > > > Thanks, > > Myles > > > ------------------------------ > > *From:* coreboot-bounces(a)coreboot.org [mailto: > coreboot-bounces(a)coreboot.org] *On Behalf Of *Collin Gregory > *Sent:* Friday, October 31, 2008 2:17 PM > *To:* coreboot(a)coreboot.org > *Subject:* [coreboot] Flashrom problem > > > > Hello everyone, > > I'm a newbies in coreboot installation but not in linux, hopefully :) > When i'm launching flashrom, i get this error message : > > Can't mmap memory using /dev/mem : Invalid ARgument ... > > Does anyone knows what does it means ? > > My motherboard is the D945gclf with these technical informations : > > - Soldered-down Intel(R) Atom(R) processor 230 with a 533 MHz system bus > - Intel(R) 945GC Chipset, consisting of: > > • Intel(R) 82945GC Graphics Memory Controller Hub (GMCH) > > • Intel(R) 82801GB I/O Controller Hub (ICH7) > > - Realtek* ALC662 for the sound chipset > - Intel(R) GMA950 onboard graphics subsystem Video > - SMSC LPC47M997 based Legacy I/O controller for hardware management, > serial, parallel, and PS/2* ports > - Realtek RTL8102EL LAN adapter device > > Thanks for your help !!!! > > Greg >

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[PATCH] v2: Trim i82801xx driver to only a sensible subset
by Uwe Hermann 02 Nov '08

02 Nov '08

See patch. ICH0-ICH6 make sense for this driver, ICH7 and higher will be in a different driver/directory. AFAIK Stefan has been (or still is) working on a (yet to be released) ICH7 driver which is totally different from the other i82801xx stuff so it makes perfect sense to put it in a different driver/directory. Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org

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assistance with updating my bios
by Elia Yehuda 02 Nov '08

02 Nov '08

Hi all, I'm trying to play with coreboot to flash my bios on my PC, with no success. here are the computer hardware information followed by the commands I'm trying to execute. <INFO BEGIN> cpu: Socket370 Intel Pentium III Celeron northbridge: Intel 82810E southbridge: Intel 8281AA mainboard: 810 R 4.1 with lan super i/o: Winbond W8362F-AW bios device: ST M50FW002 lspci ooutput: 00:00.0 Host bridge: Intel Corporation 82810E DC-133 (GMCH) Graphics Memory Controller Hub (rev 03) 00:01.0 VGA compatible controller: Intel Corporation 82810E DC-133 (CGC) Chipset Graphics Controller (rev 03) 00:1e.0 PCI bridge: Intel Corporation 82801AA PCI Bridge (rev 02) 00:1f.0 ISA bridge: Intel Corporation 82801AA ISA Bridge (LPC) (rev 02) 00:1f.1 IDE interface: Intel Corporation 82801AA IDE Controller (rev 02) 00:1f.2 USB Controller: Intel Corporation 82801AA USB Controller (rev 02) 00:1f.3 SMBus: Intel Corporation 82801AA SMBus Controller (rev 02) 00:1f.5 Multimedia audio controller: Intel Corporation 82801AA AC'97 Audio Controller (rev 02) 01:05.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL-8139/8139C/8139C+ (rev 10) <INFO END> $ flashrom -f -r -c M50FW016 mydump Calibrating delay loop... OK. No coreboot table found. Found chipset "Intel ICH", enabling flash write... OK. No EEPROM/flash device found. Force read (-f -r -c) requested, forcing chip probe success: Found chip "ST M50FW016" (2048 KB) at physical address 0xffe00000. Force reading flash...done $ flashrom -f -w -c M50FW016 mydump Calibrating delay loop... OK. No coreboot table found. Found chipset "Intel ICH", enabling flash write... OK. No EEPROM/flash device found. I'd appreciate any assistance as all this flashing stuff is new to me. Basically what i'm trying to accomplish is having my linux system running as the payload, but i'm stuck with even re-writing the same bios-dump i've just read from the bios... I'll post any further information required to diagnose this further. thanks in advance, Elia Yehuda.

2 4

via epia-cn and v3
by ron minnich 01 Nov '08

01 Nov '08

coreboot-3.0.974 Fri Oct 31 15:11:04 PDT 2008 starting... (console_loglevel=8) Choosing fallback boot. LAR: Attempting to open 'fallback/initram/segment0'. LAR: Start 0xfffc0000 len 0x40000 LAR: seen member normal/option_table@0xfffc0000, size 1008 LAR: seen member normal/initram/segment0@0xfffc0440, size 8876 LAR: seen member normal/stage2/segment0@0xfffc2740, size 1 LAR: seen member normal/stage2/segment1@0xfffc27a0, size 17676 LAR: seen member normal/stage2/segment2@0xfffc6d00, size 579 LAR: seen member bootblock@0xffffafc0, size 20480 LAR: File not found! LAR: Run file fallback/initram/segment0 failed: No such file. Fallback failed. Try normal boot LAR: Attempting to open 'normal/initram/segment0'. LAR: Start 0xfffc0000 len 0x40000 LAR: seen member normal/option_table@0xfffc0000, size 1008 LAR: seen member normal/initram/segment0@0xfffc0440, size 8876 LAR: CHECK normal/initram/segment0 @ 0xfffc0440 start 0xfffc0490 len 8876 reallen 8876 compression 0 entry 0x00001475 loadaddre0 Entry point is 0xfffc1905 In initram.c main() Enabling Via V-Link pci_conf1_find_on_bus: bus 0, find 0x1106:3227 pci_conf1_find_on_bus: bus 1, find 0x1106:3227 pci_conf1_find_on_bus: bus 0, find 0x1106:0571 pci_conf1_find_on_bus: bus 1, find 0x1106:0571 Enabling shadow ram pci_conf1_find_on_bus: bus 0, find 0x1106:3227 pci_conf1_find_on_bus: bus 1, find 0x1106:3227 VT8237R Power management controller found at 0x8800 SMBus Ready/Completed Successfully Configuring DRAM Bank 0 SMBus Read from DIMM 80 at address 0x1f SMBus Ready/Completed Successfully Waiting until SMBus ready SMBus Ready/Completed Successfully Waiting until SMBus ready SMBus Ready/Completed Successfully Read: 0x80 SMBus Ready/Completed Successfully Found 512MB module in slot 0 Setting Top of Usable DRAM to 512MB Calculating tWR and tRFC SMBus Read from DIMM 80 at address 0x24 SMBus Ready/Completed Successfully Waiting until SMBus ready SMBus Ready/Completed Successfully Waiting until SMBus ready SMBus Ready/Completed Successfully Read: 0x3c SMBus Ready/Completed Successfully SMBus Read from DIMM 80 at address 0x2a SMBus Ready/Completed Successfully Waiting until SMBus ready SMBus Ready/Completed Successfully Waiting until SMBus ready SMBus Ready/Completed Successfully Read: 0x69 SMBus Ready/Completed Successfully SMBus Read from DIMM 80 at address 0x28 SMBus Ready/Completed Successfully Waiting until SMBus ready SMBus Ready/Completed Successfully Waiting until SMBus ready SMBus Ready/Completed Successfully Read: 0x0 SMBus Ready/Completed Successfully Calculating tRAS and CAS SMBus Read from DIMM 80 at address 0x1e SMBus Ready/Completed Successfully Waiting until SMBus ready SMBus Ready/Completed Successfully Waiting until SMBus ready SMBus Ready/Completed Successfully Read: 0x27 SMBus Ready/Completed Successfully SMBus Read from DIMM 80 at address 0x12 SMBus Ready/Completed Successfully Waiting until SMBus ready SMBus Ready/Completed Successfully Waiting until SMBus ready SMBus Ready/Completed Successfully Read: 0x38 SMBus Ready/Completed Successfully Calculating tRRD, tRTP, and tWTR SMBus Read from DIMM 80 at address 0x1c SMBus Ready/Completed Successfully Waiting until SMBus ready SMBus Ready/Completed Successfully Waiting until SMBus ready SMBus Ready/Completed Successfully Read: 0x1e SMBus Ready/Completed Successfully SMBus Read from DIMM 80 at address 0x26 SMBus Ready/Completed Successfully Waiting until SMBus ready SMBus Ready/Completed Successfully Waiting until SMBus ready SMBus Ready/Completed Successfully Read: 0x1e SMBus Ready/Completed Successfully SMBus Read from DIMM 80 at address 0x25 SMBus Ready/Completed Successfully Waiting until SMBus ready SMBus Ready/Completed Successfully Waiting until SMBus ready SMBus Ready/Completed Successfully Read: 0x1e SMBus Ready/Completed Successfully Calculating tRCD and tRP SMBus Read from DIMM 80 at address 0x1d SMBus Ready/Completed Successfully Waiting until SMBus ready SMBus Ready/Completed Successfully Waiting until SMBus ready SMBus Ready/Completed Successfully Read: 0x3c SMBus Ready/Completed Successfully SMBus Read from DIMM 80 at address 0x1b SMBus Ready/Completed Successfully Waiting until SMBus ready SMBus Ready/Completed Successfully Waiting until SMBus ready SMBus Ready/Completed Successfully Read: 0x3c SMBus Ready/Completed Successfully calculating MA map SMBus Read from DIMM 80 at address 0x5 SMBus Ready/Completed Successfully Waiting until SMBus ready SMBus Ready/Completed Successfully Waiting until SMBus ready SMBus Ready/Completed Successfully Read: 0x60 SMBus Ready/Completed Successfully SMBus Read from DIMM 80 at address 0x4 SMBus Ready/Completed Successfully Waiting until SMBus ready SMBus Ready/Completed Successfully Waiting until SMBus ready SMBus Ready/Completed Successfully Read: 0xa SMBus Ready/Completed Successfully Setting Memory Address Map type to 0x1 Configuring DRAM Bank 1 SMBus Read from DIMM 0 at address 0x1f SMBus Ready/Completed Successfully Waiting until SMBus ready SMBus Ready/Completed Successfully Waiting until SMBus ready Device error Read: 0x0 SMBus Ready/Completed Successfully No memory in slot 1 RAM Enable 1: Apply NOP Sending RAM command 'No-op' to 0x0 RAM Enable 2: Precharge all Sending RAM command 'Precharge' to 0x0 RAM Enable 3: Mode register set (DLL Reset) Sending RAM command 'MRS' to 0x12000 RAM Enable 4: Precharge all Sending RAM command 'Precharge' to 0x0 RAM Enable 5: CBR Sending RAM command 'CBR' to 0x0 RAM Enable 6: Mode register set (OCD Calibration) Mode Register Set (MRS) value is 0x1001d8 Sending RAM command 'MRS' to 0x1001d8 RAM Enable 7: Normal operation Sending RAM command 'Normal' to 0x0 Sending RAM command 'Normal' to 0x30 run_file returns with 0 Done RAM init code In hardware_stage1() resets at this point and restarts. Very slow, as though it were not caching ROM? ron

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Re: [coreboot] assistance with updating my bios
by z4ziggy＠gmail.com 01 Nov '08

01 Nov '08

any plans on fixing the issue or using alternative? is there a way i can assist? On Oct 30, 2008 5:47pm, Corey Osgood <corey.osgood(a)gmail.com> wrote: > AFAIK, flashrom is broken for most ICHx. > > -Corey > > On Thu, Oct 30, 2008 at 9:57 AM, z4ziggy(a)gmail.com> wrote: > > here is the output you've requested : > > > Calibrating delay loop... 366M loops per second, 100 myus = 350 us. OK. > No coreboot table found. > Found chipset "Intel ICH", enabling flash write... > > > BIOS Lock Enable: disabled, BIOS Write Enable: enabled, BIOS_CNTL is 0x1 > OK. > Probing for AMD Am29F002(N)BB, 256 KB: probe_jedec: id1 0x25, id2 0x81 > Probing for AMD Am29F002(N)BT, 256 KB: probe_jedec: id1 0x25, id2 0x81 > > Probing for AMD Am29F016D, 2048 KB: probe_29f040b: id1 0xff, id2 0xff > Probing for AMD Am29F040B, 512 KB: probe_29f040b: id1 0x25, id2 0x81 > Probing for AMD Am29LV040B, 512 KB: probe_29f040b: id1 0x25, id2 0x81 > Probing for ASD AE49F2008, 256 KB: probe_jedec: id1 0x25, id2 0x81 > > Probing for Atmel AT29C020, 256 KB: probe_jedec: id1 0x25, id2 0x81 > Probing for Atmel AT29C040A, 512 KB: probe_jedec: id1 0x25, id2 0x81 > Probing for Atmel AT49F002(N), 256 KB: probe_jedec: id1 0x25, id2 0x81 > Probing for Atmel AT49F002(N)T, 256 KB: probe_jedec: id1 0x25, id2 0x81 > > Probing for Atmel AT25DF321, 4096 KB: spi_command called, but no SPI chipset/strapping detected > Probing for AMIC A25L40P, 512 KB: 4b ID not supported on this SPI controller > Probing for AMIC A29002B, 256 KB: probe_29f002: id1 0xda, id2 0x32 > > Probing for AMIC A29002T, 256 KB: probe_29f002: id1 0xda, id2 0x32 > Probing for AMIC A29040B, 512 KB: probe_29f040b: id1 0x25, id2 0x81 > Probing for AMIC A49LF040A, 512 KB: probe_jedec: id1 0x25, id2 0x81 > Probing for EMST F49B002UA, 256 KB: probe_jedec: id1 0x25, id2 0x81 > > Probing for EON EN29F002(A)(N)B, 256 KB: probe_jedec: id1 0x25, id2 0x81 > Probing for EON EN29F002(A)(N)T, 256 KB: probe_jedec: id1 0x25, id2 0x81 > Probing for Fujitsu MBM29F400TC, 512 KB: probe_m29f400bt: id1 0x25, id2 0x2d > > Probing for Intel 82802AB, 512 KB: probe_82802ab: id1 0x25, id2 0x81 > Probing for Intel 82802AC, 1024 KB: probe_82802ab: id1 0x25, id2 0x81 > Probing for Macronix MX25L4005, 512 KB: spi_command called, but no SPI chipset/strapping detected > > Probing for Macronix MX25L8005, 1024 KB: spi_command called, but no SPI chipset/strapping detected > Probing for Macronix MX25L1605, 2048 KB: spi_command called, but no SPI chipset/strapping detected > Probing for Macronix MX25L3205, 4096 KB: spi_command called, but no SPI chipset/strapping detected > > Probing for Macronix MX29F002, 256 KB: probe_29f002: id1 0xda, id2 0x32 > Probing for Numonyx M25PE10, 128 KB: spi_command called, but no SPI chipset/strapping detected > Probing for Numonyx M25PE20, 256 KB: spi_command called, but no SPI chipset/strapping detected > > Probing for Numonyx M25PE40, 256 KB: spi_command called, but no SPI chipset/strapping detected > Probing for Numonyx M25PE80, 1024 KB: spi_command called, but no SPI chipset/strapping detected > Probing for Numonyx M25PE16, 2048 KB: spi_command called, but no SPI chipset/strapping detected > > Probing for PMC Pm25LV010, 128 KB: spi_command called, but no SPI chipset/strapping detected > Probing for PMC Pm25LV016B, 2048 KB: spi_command called, but no SPI chipset/strapping detected > Probing for PMC Pm25LV020, 256 KB: spi_command called, but no SPI chipset/strapping detected > > Probing for PMC Pm25LV040, 512 KB: spi_command called, but no SPI chipset/strapping detected > Probing for PMC Pm25LV080B, 1024 KB: spi_command called, but no SPI chipset/strapping detected > Probing for PMC Pm25LV512, 64 KB: spi_command called, but no SPI chipset/strapping detected > > Probing for PMC Pm49FL002, 256 KB: probe_jedec: id1 0x25, id2 0x81 > Probing for PMC Pm49FL004, 512 KB: probe_jedec: id1 0x25, id2 0x81 > Probing for Sharp LHF00L04, 1024 KB: probe_lhf00l04: id1 0x25, id2 0x81 > Probing for Spansion S25FL016A, 2048 KB: spi_command called, but no SPI chipset/strapping detected > > Probing for SST SST25VF016B, 2048 KB: spi_command called, but no SPI chipset/strapping detected > Probing for SST SST25VF040B, 512 KB: spi_command called, but no SPI chipset/strapping detected > Probing for SST SST28SF040A, 512 KB: probe_28sf040: id1 0x25, id2 0x81 > > Probing for SST SST29EE010, 128 KB: probe_jedec: id1 0xdb, id2 0x1c, id1 parity violation > Probing for SST SST29LE010, 128 KB: probe_jedec: id1 0xdb, id2 0x1c, id1 parity violation > Probing for SST SST29EE020A, 256 KB: probe_jedec: id1 0x25, id2 0x81 > > Probing for SST SST29LE020, 256 KB: probe_jedec: id1 0x25, id2 0x81 > Probing for SST SST39SF010A, 128 KB: probe_jedec: id1 0xdb, id2 0x1c, id1 parity violation > Probing for SST SST39SF020A, 256 KB: probe_jedec: id1 0x25, id2 0x81 > > Probing for SST SST39SF040, 512 KB: probe_jedec: id1 0x25, id2 0x81 > Probing for SST SST39VF512, 64 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation > Probing for SST SST39VF010, 128 KB: probe_jedec: id1 0xdb, id2 0x1c, id1 parity violation > > Probing for SST SST39VF020, 256 KB: probe_jedec: id1 0x25, id2 0x81 > Probing for SST SST39VF040, 512 KB: probe_jedec: id1 0x25, id2 0x81 > Probing for SST SST49LF002A/B, 256 KB: probe_jedec: id1 0x25, id2 0x81 > Probing for SST SST49LF003A/B, 384 KB: probe_jedec: id1 0xdb, id2 0x1c, id1 parity violation > > Probing for SST SST49LF004A/B, 512 KB: probe_jedec: id1 0x25, id2 0x81 > Probing for SST SST49LF004C, 512 KB: probe_49lfxxxc: id1 0x25, id2 0x81 > Probing for SST SST49LF008A, 1024 KB: probe_jedec: id1 0x25, id2 0x81 > > Probing for SST SST49LF008C, 1024 KB: probe_49lfxxxc: id1 0x25, id2 0x81 > Probing for SST SST49LF016C, 2048 KB: probe_49lfxxxc: id1 0xff, id2 0xff > Probing for SST SST49LF020A, 256 KB: probe_jedec: id1 0x25, id2 0x81 > > Probing for SST SST49LF040, 512 KB: probe_jedec: id1 0x25, id2 0x81 > Probing for SST SST49LF040B, 512 KB: probe_jedec: id1 0x25, id2 0x81 > Probing for SST SST49LF080A, 1024 KB: probe_jedec: id1 0x25, id2 0x81 > Probing for SST SST49LF160C, 2048 KB: probe_49lfxxxc: id1 0xff, id2 0xff > > Probing for ST M25P05-A, 64 KB: spi_command called, but no SPI chipset/strapping detected > Probing for ST M25P10-A, 128 KB: spi_command called, but no SPI chipset/strapping detected > Probing for ST M25P20, 256 KB: spi_command called, but no SPI chipset/strapping detected > > Probing for ST M25P40, 512 KB: spi_command called, but no SPI chipset/strapping detected > Probing for ST M25P40-old, 512 KB: spi_command called, but no SPI chipset/strapping detected > Probing for ST M25P80, 1024 KB: spi_command called, but no SPI chipset/strapping detected > > Probing for ST M25P16, 2048 KB: spi_command called, but no SPI chipset/strapping detected > Probing for ST M25P32, 4096 KB: spi_command called, but no SPI chipset/strapping detected > Probing for ST M25P64, 8192 KB: spi_command called, but no SPI chipset/strapping detected > > Probing for ST M25P128, 16384 KB: spi_command called, but no SPI chipset/strapping detected > Probing for ST M29F002B, 256 KB: probe_jedec: id1 0x25, id2 0x81 > Probing for ST M29F002T/NT, 256 KB: probe_jedec: id1 0x25, id2 0x81 > > Probing for ST M29F040B, 512 KB: probe_29f040b: id1 0x25, id2 0x81 > Probing for ST M29F400BT, 512 KB: probe_m29f400bt: id1 0x25, id2 0x2d > Probing for ST M29W010B, 128 KB: probe_jedec: id1 0xdb, id2 0x1c, id1 parity violation > > Probing for ST M29W040B, 512 KB: probe_jedec: id1 0x25, id2 0x81 > Probing for ST M50FLW040A, 512 KB: probe_stm50flw0x0x: id1 0xda, id2 0x32 > Probing for ST M50FLW040B, 512 KB: probe_stm50flw0x0x: id1 0xda, id2 0x32 > > Probing for ST M50FLW080A, 1024 KB: probe_stm50flw0x0x: id1 0xda, id2 0x32 > Probing for ST M50FLW080B, 1024 KB: probe_stm50flw0x0x: id1 0xda, id2 0x32 > Probing for ST M50FW016, 2048 KB: probe_82802ab: id1 0xff, id2 0xff > > Probing for ST M50FW040, 512 KB: probe_82802ab: id1 0x25, id2 0x81 > Probing for ST M50FW080, 1024 KB: probe_82802ab: id1 0x25, id2 0x81 > Probing for ST M50LPW116, 2048 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation > > Probing for SyncMOS S29C31004T, 512 KB: probe_jedec: id1 0x25, id2 0x81 > Probing for SyncMOS S29C51001T, 128 KB: probe_jedec: id1 0xdb, id2 0x1c, id1 parity violation > Probing for SyncMOS S29C51002T, 256 KB: probe_jedec: id1 0x25, id2 0x81 > > Probing for SyncMOS S29C51004T, 512 KB: probe_jedec: id1 0x25, id2 0x81 > Probing for Winbond W25x10, 128 KB: spi_command called, but no SPI chipset/strapping detected > Probing for Winbond W25x20, 256 KB: spi_command called, but no SPI chipset/strapping detected > > Probing for Winbond W25x40, 512 KB: spi_command called, but no SPI chipset/strapping detected > Probing for Winbond W25x80, 1024 KB: spi_command called, but no SPI chipset/strapping detected > Probing for Winbond W29C011, 128 KB: probe_jedec: id1 0xdb, id2 0x1c, id1 parity violation > > Probing for Winbond W29C020C, 256 KB: probe_jedec: id1 0x25, id2 0x81 > Probing for Winbond W29C040P, 512 KB: probe_jedec: id1 0x25, id2 0x81 > Probing for Winbond W29EE011, 128 KB: > === > Probing disabled for Winbond W29EE011 because the probing sequence puts the > > AMIC A49LF040A in a funky state. > Use 'flashrom -c W29EE011' if you have a board with this chip. > === > Probing for Winbond W39V040A, 512 KB: probe_jedec: id1 0x25, id2 0x81 > Probing for Winbond W39V040B, 512 KB: probe_jedec: id1 0x25, id2 0x81 > > Probing for Winbond W39V040C, 512 KB: probe_w39v040c: id1 0xda, id2 0x32 > Probing for Winbond W39V040FA, 512 KB: probe_jedec: id1 0x25, id2 0x81 > Probing for Winbond W39V080A, 1024 KB: probe_jedec: id1 0x25, id2 0x81 > > Probing for Winbond W49F002U, 256 KB: probe_jedec: id1 0x25, id2 0x81 > Probing for Winbond W49V002A, 256 KB: probe_jedec: id1 0x25, id2 0x81 > Probing for Winbond W49V002FA, 256 KB: probe_jedec: id1 0x25, id2 0x81 > Probing for Winbond W39V080FA, 1024 KB: probe_winbond_fwhub: vid 0xda, did 0x32 > > Probing for Winbond W39V080FA (dual mode), 512 KB: probe_winbond_fwhub: vid 0xda, did 0x32 > Probing for EON unknown EON SPI chip, 0 KB: spi_command called, but no SPI chipset/strapping detected > Probing for Macronix unknown Macronix SPI chip, 0 KB: spi_command called, but no SPI chipset/strapping detected > > Probing for PMC unknown PMC SPI chip, 0 KB: spi_command called, but no SPI chipset/strapping detected > Probing for SST unknown SST SPI chip, 0 KB: spi_command called, but no SPI chipset/strapping detected > Probing for ST unknown ST SPI chip, 0 KB: spi_command called, but no SPI chipset/strapping detected > > No EEPROM/flash device found. > > If you know which flash chip you have, and if this version of flashrom > supports a similar flash chip, you can try to force read your chip. Run: > flashrom -f -r -c similar_supported_flash_chip filename > > > Note: flashrom can never write when the flash chip isn't found automatically. > > > > Blessings, > Elia Yehuda. > > > On Oct 30, 2008 2:30pm, Carl-Daniel Hailfinger cd.hailfinger.devel.2006(a)gmx.net> wrote: > > > Hi Elia, > > > > > > > > On 30.10.2008 11:45, Elia Yehuda wrote: > > > > > I'm trying to play with coreboot to flash my bios on my PC, with no success. > > > > > here are the computer hardware information followed by the commands I'm > > > > > > trying to execute. > > > > > > > > > > cpu: Socket370 Intel Pentium III Celeron > > > > > northbridge: Intel 82810E > > > > > southbridge: Intel 8281AA > > > > > > mainboard: 810 R 4.1 with lan > > > > > super i/o: Winbond W8362F-AW > > > > > bios device: ST M50FW002 > > > > > > > > > > lspci output: > > > > > > [...] > > > > > > > > > > $ flashrom -f -r -c M50FW016 mydump > > > > > Calibrating delay loop... OK. > > > > > No coreboot table found. > > > > > Found chipset "Intel ICH", enabling flash write... OK. > > > > > > No EEPROM/flash device found. > > > > > Force read (-f -r -c) requested, forcing chip probe success: > > > > > Found chip "ST M50FW016" (2048 KB) at physical address 0xffe00000. > > > > > > Force reading flash...done > > > > > > > > > > > > > It is a bad sign if you had to force the chip type for the read operation. > > > > > > > > > $ flashrom -f -w -c M50FW016 mydump > > > > > > Calibrating delay loop... OK. > > > > > No coreboot table found. > > > > > Found chipset "Intel ICH", enabling flash write... OK. > > > > > No EEPROM/flash device found. > > > > > > > > > > > > > > Force write can't work because the strategy for access is unknown. > > > > > > > > > I'd appreciate any assistance as all this flashing stuff is new to me. > > > > > > Basically what i'm trying to accomplish is having my linux system running as > > > > > the payload, but i'm stuck with even re-writing the same bios-dump i've just > > > > > read from the bios... I'll post any further information required to diagnose > > > > > > this further. > > > > > > > > > > > > > Can you run > > > > flashrom -V > > > > and report the results to this list? > > > > > > > > We may need to change the chipset/board enable sequence for your board. > > > > > > > > > Regards, > > > > Carl-Daniel > > > > > > > > -- > > > > http://www.hailfinger.org/ > > > > > > > > > > -- > > coreboot mailing list: coreboot(a)coreboot.org > > http://www.coreboot.org/mailman/listinfo/coreboot > > >

5 5

r975 - in coreboot-v3: arch/x86 mainboard/via mainboard/via/epia-cn
by svn＠coreboot.org 31 Oct '08

31 Oct '08

Author: rminnich Date: 2008-10-31 23:43:02 +0100 (Fri, 31 Oct 2008) New Revision: 975 Modified: coreboot-v3/arch/x86/Makefile coreboot-v3/mainboard/via/Kconfig coreboot-v3/mainboard/via/epia-cn/cmos.layout Log: no PIRQ table Make cmos.layout work with incomprehensible tool -- just turn off checksums. Add static.c to list of files covered by kscope Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Modified: coreboot-v3/arch/x86/Makefile =================================================================== --- coreboot-v3/arch/x86/Makefile 2008-10-31 22:04:29 UTC (rev 974) +++ coreboot-v3/arch/x86/Makefile 2008-10-31 22:43:02 UTC (rev 975) @@ -288,7 +288,7 @@ kscope: $(obj)/mainboard/$(MAINBOARDDIR)/kscope/cscope.files kscope $(obj)/mainboard/$(MAINBOARDDIR)/kscope -ALLSRC=$(STAGE0_SRC) $(INITRAM_SRC) $(STAGE2_SRC) $(PCIROM_SRC) +ALLSRC=$(STAGE0_SRC) $(INITRAM_SRC) $(STAGE2_SRC) $(PCIROM_SRC) $(STAGE2_DYNAMIC_SRC) $(obj)/mainboard/$(MAINBOARDDIR)/kscope/cscope.files: $(ALLSRC) $(Q)mkdir -p $(obj)/mainboard/$(MAINBOARDDIR)/kscope $(Q)cp cscope.proj $(obj)/mainboard/$(MAINBOARDDIR)/kscope Modified: coreboot-v3/mainboard/via/Kconfig =================================================================== --- coreboot-v3/mainboard/via/Kconfig 2008-10-31 22:04:29 UTC (rev 974) +++ coreboot-v3/mainboard/via/Kconfig 2008-10-31 22:43:02 UTC (rev 975) @@ -30,7 +30,6 @@ select NORTHBRIDGE_VIA_CN700 select SOUTHBRIDGE_VIA_VT8237 select SUPERIO_VIA_VT1211 - select PIRQ_TABLE help VIA EPIA-CN Modified: coreboot-v3/mainboard/via/epia-cn/cmos.layout =================================================================== --- coreboot-v3/mainboard/via/epia-cn/cmos.layout 2008-10-31 22:04:29 UTC (rev 974) +++ coreboot-v3/mainboard/via/epia-cn/cmos.layout 2008-10-31 22:43:02 UTC (rev 975) @@ -80,12 +80,12 @@ # coreboot config options: console 392 3 e 5 baud_rate 395 4 e 6 debug_level -#399 1 r 0 unused +399 1 r 0 unused # coreboot config options: southbridge 408 1 e 1 nmi 409 1 e 1 power_on_after_fail -#410 6 r 0 unused +410 6 r 0 unused # coreboot config options: bootloader 416 512 s 0 boot_devices @@ -124,8 +124,8 @@ 6 9 Spew # ----------------------------------------------------------------- -checksums +#checksums -checksum 392 983 984 +#checksum 392 983 984

1 0

Flashrom problem
by Collin Gregory 31 Oct '08

31 Oct '08

Hello everyone, I'm a newbies in coreboot installation but not in linux, hopefully :) When i'm launching flashrom, i get this error message : Can't mmap memory using /dev/mem : Invalid ARgument ... Does anyone knows what does it means ? My motherboard is the D945gclf with these technical informations : - Soldered-down Intel(R) Atom(R) processor 230 with a 533 MHz system bus - Intel(R) 945GC Chipset, consisting of: • Intel(R) 82945GC Graphics Memory Controller Hub (GMCH) • Intel(R) 82801GB I/O Controller Hub (ICH7) - Realtek* ALC662 for the sound chipset - Intel(R) GMA950 onboard graphics subsystem Video - SMSC LPC47M997 based Legacy I/O controller for hardware management, serial, parallel, and PS/2* ports - Realtek RTL8102EL LAN adapter device Thanks for your help !!!! Greg

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coreboot October 2008