October 2008 - coreboot - mail.coreboot.org

r974 - coreboot-v3/mainboard/via/epia-cn
by svn＠coreboot.org Oct. 31, 2008

Oct. 31, 2008

Author: stuge Date: 2008-10-31 23:04:29 +0100 (Fri, 31 Oct 2008) New Revision: 974 Modified: coreboot-v3/mainboard/via/epia-cn/Makefile Log: Add file that provides enable_smbus() Signed-off-by: Peter Stuge <peter(a)stuge.se> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Modified: coreboot-v3/mainboard/via/epia-cn/Makefile =================================================================== --- coreboot-v3/mainboard/via/epia-cn/Makefile 2008-10-31 18:57:37 UTC (rev 973) +++ coreboot-v3/mainboard/via/epia-cn/Makefile 2008-10-31 22:04:29 UTC (rev 974) @@ -22,6 +22,7 @@ INITRAM_SRC = $(src)/mainboard/$(MAINBOARDDIR)/initram.c \ $(src)/northbridge/via/cn700/initram.c \ + $(src)/southbridge/via/vt8237/stage1.c \ $(src)/lib/ramtest.c STAGE2_MAINBOARD_SRC =

1 0

Help with Coreboot
by Sean Tilley Oct. 31, 2008

Oct. 31, 2008

Hey there, uid313 on the Ubuntu forums said you guys needed help with just simply doing some instructions listed here: http://ubuntuforums.org/showthread.php?t=961975 In any case, here's my output! I'm not sure if you need my system's specs. If you do, just mail me back and I'll send my specs in a reply. Cheers, -Sean Tilley PS: Has there been any progress or work on making Coreboot work with Hurd: L4?

1 0

Re: [coreboot] Flashrom problem
by Myles Watson Oct. 31, 2008

Oct. 31, 2008

On Fri, Oct 31, 2008 at 2:40 PM, Collin Gregory <collin.gregory(a)gmail.com>wrote: > Hello Myles, > > Thanks for your quick answer. > Here is my command line that i typed : ./flashrom -r test > Here is what ./flashrom -r test -V gives : > Calibrating Delay loop... 797M loops per second, 100 myus = 201 us, OK. > Can't mmap memory using /dev/mem : Invalid Argument. > > That's for it. > The version of flashrom is the r3708. If you were root when you tried it, I'm stumped. Someone else who knows more about flashrom will have to help. Thanks, Myles

1 0

Re: [coreboot] r973 - coreboot-v3/mainboard/via/epia-cn
by Uwe Hermann Oct. 31, 2008

Oct. 31, 2008

On Fri, Oct 31, 2008 at 07:57:37PM +0100, svn(a)coreboot.org wrote: > Added: coreboot-v3/mainboard/via/epia-cn/initram.c > =================================================================== > --- coreboot-v3/mainboard/via/epia-cn/initram.c (rev 0) > +++ coreboot-v3/mainboard/via/epia-cn/initram.c 2008-10-31 18:57:37 UTC (rev 973) > +void dump_smbus_registers(void) > +{ > + int device; > + for(device = 1; device < (int)0x80; device++) { > + int j; > + //if(spd_read_byte(device, 0) < 0 ) > + // continue; > + printk(BIOS_DEBUG, "smbus: %02x", device); > + for(j = 0; j < 256; j++) { > + int status; > + u8 byte; > + status = spd_read_byte(device, j); > + if (status < 0) { > + break; > + } > + if ((j & 0xf) == 0) { > + printk(BIOS_DEBUG, "\n%02x: ",j); > + } > + byte = status & 0xff; > + printk(BIOS_DEBUG, "%02x ", byte); > + } > + printk(BIOS_DEBUG, "\n"); > + } > +} Note for later: Move this to some lib/ file, this is not epia-cn specific in any way. > Added: coreboot-v3/mainboard/via/epia-cn/mainboard.h > =================================================================== > --- coreboot-v3/mainboard/via/epia-cn/mainboard.h (rev 0) > +++ coreboot-v3/mainboard/via/epia-cn/mainboard.h 2008-10-31 18:57:37 UTC (rev 973) > @@ -0,0 +1,20 @@ > +/* > + * This file is part of the coreboot project. > + * > + * Copyright (C) 2008 Corey Osgood <corey.osgood(a)gmail.com> > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation; either version 2 of the License, or > + * (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program; if not, write to the Free Software > + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA > + */ Empty file? Drop? At least until it's actually needed (if it ever is). > Added: coreboot-v3/mainboard/via/epia-cn/stage1.c > =================================================================== > --- coreboot-v3/mainboard/via/epia-cn/stage1.c (rev 0) > +++ coreboot-v3/mainboard/via/epia-cn/stage1.c 2008-10-31 18:57:37 UTC (rev 973) > @@ -0,0 +1,58 @@ > +/* > + * This file is part of the coreboot project. > + * > + * Copyright (C) 2007 Advanced Micro Devices, Inc. I doubt that someone at AMD wrote any of this code in 2007. Please don't carry around (C) lines for any such trivial files where almost nothing (if anything at all) if from the copyright holder you're listing... (it _is_ important to keep the (C) lines when you copy/reuse a non-trivial amount of non-trivial code, of course!) Just Copyright (C) 2008 Ronald G. Minnich <rminnich(a)gmail.com> is fully sufficient here, IMO. > + * Copyright (C) 2008 Ronald G. Minnich <rminnich(a)gmail.com> > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation; either version 2 of the License, or > + * (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program; if not, write to the Free Software > + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA > + */ > + > +#include <types.h> > +#include <lib.h> > +#include <console.h> > +#include <io.h> > +#include <arch/x86/pci_ops.h> > +#include <device/pci.h> > +#include <device/pci_ids.h> > +#include <superio/fintek/f71805f/f71805f.h> > +#include <northbridge/via/cn700/cn700.h> > + > +/* Someday, we're all going multicore. */ > +void stop_ap(void) > +{ > +} > + > +void hardware_stage1(void) > +{ > + void vt1211_enable_serial(u8 dev, u8 serial, u16 iobase); > + u32 dev; > + > + post_code(POST_START_OF_MAIN); > + vt1211_enable_serial(0x2e, 2, 0x3f8); > + > + /* Enable multifunction for northbridge. */ > + pci_conf1_write_config8(0x00, 0x4f, 0x01); > + > + printk(BIOS_SPEW, "In hardware_stage1()\n"); > + /* Disabled GP3, to keep the system from rebooting automatically */ > + //pci_conf1_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VT8237R_LPC, &dev); > + dev = PCI_BDF(0, 17, 0); > + pci_conf1_write_config8(dev, 0x98, 0x00); > +} Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org

1 0

v3: superio/via/vt1211 with serial port init but nothing else
by Peter Stuge Oct. 31, 2008

Oct. 31, 2008

Maybe this works.. //Peter

3 5

r3715 build service
by coreboot information Oct. 31, 2008

Oct. 31, 2008

Dear coreboot readers! This is the automated build check service of coreboot. The developer "uwe" checked in revision 3715 to the coreboot source repository and caused the following changes: Change Log: Revert i945/ICH7 PCI IDs to be hard-coded numbers instead of #defines. Build-tested on kontron_986lcd_m. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Build Log: Compilation of gigabyte:ga_2761gxdk has been fixed If something broke during this checkin please be a pain in uwe's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

1 0

r973 - coreboot-v3/mainboard/via/epia-cn
by svn＠coreboot.org Oct. 31, 2008

Oct. 31, 2008

Author: rminnich Date: 2008-10-31 19:57:37 +0100 (Fri, 31 Oct 2008) New Revision: 973 Added: coreboot-v3/mainboard/via/epia-cn/cmos.layout coreboot-v3/mainboard/via/epia-cn/dts coreboot-v3/mainboard/via/epia-cn/initram.c coreboot-v3/mainboard/via/epia-cn/mainboard.h coreboot-v3/mainboard/via/epia-cn/stage1.c Log: new files Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Added: coreboot-v3/mainboard/via/epia-cn/cmos.layout =================================================================== --- coreboot-v3/mainboard/via/epia-cn/cmos.layout (rev 0) +++ coreboot-v3/mainboard/via/epia-cn/cmos.layout 2008-10-31 18:57:37 UTC (rev 973) @@ -0,0 +1,131 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2007-2008 coresystems GmbH +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; version 2 of +# the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +# MA 02110-1301 USA +# + +# TODO verify that these are correct for this part on the VIA + +# ----------------------------------------------------------------- +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +# ----------------------------------------------------------------- +# Status Register A +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +# ----------------------------------------------------------------- +# Status Register B +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +385 1 e 4 last_boot +388 4 r 0 reboot_bits +#390 2 r 0 unused? + +# ----------------------------------------------------------------- +# coreboot config options: console +392 3 e 5 baud_rate +395 4 e 6 debug_level +#399 1 r 0 unused + +# coreboot config options: southbridge +408 1 e 1 nmi +409 1 e 1 power_on_after_fail +#410 6 r 0 unused + +# coreboot config options: bootloader +416 512 s 0 boot_devices +#928 80 r 0 unused + +# coreboot config options: check sums +984 16 h 0 check_sum + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 1 Emergency +6 2 Alert +6 3 Critical +6 4 Error +6 5 Warning +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew + +# ----------------------------------------------------------------- +checksums + +checksum 392 983 984 + + Added: coreboot-v3/mainboard/via/epia-cn/dts =================================================================== --- coreboot-v3/mainboard/via/epia-cn/dts (rev 0) +++ coreboot-v3/mainboard/via/epia-cn/dts 2008-10-31 18:57:37 UTC (rev 973) @@ -0,0 +1,76 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Corey Osgood <corey.osgood(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* +-[0000:00]-+-00.0 VIA Technologies, Inc. CN700/VN800/P4M800CE/Pro Host Bridge + +-00.1 VIA Technologies, Inc. CN700/VN800/P4M800CE/Pro Host Bridge + +-00.2 VIA Technologies, Inc. CN700/VN800/P4M800CE/Pro Host Bridge + +-00.3 VIA Technologies, Inc. PT890 Host Bridge + +-00.4 VIA Technologies, Inc. CN700/VN800/P4M800CE/Pro Host Bridge + +-00.7 VIA Technologies, Inc. CN700/VN800/P4M800CE/Pro Host Bridge + +-01.0-[0000:01]----00.0 VIA Technologies, Inc. UniChrome Pro IGP + +-08.0 RaLink RT2561/RT61 802.11g PCI + +-0a.0 VIA Technologies, Inc. IEEE 1394 Host Controller + +-0f.0 VIA Technologies, Inc. VIA VT6420 SATA RAID Controller + +-0f.1 VIA Technologies, Inc. VT82C586A/B/VT82C686/A/B/VT823x/A/C PIPC Bus Master IDE + +-10.0 VIA Technologies, Inc. VT82xxxxx UHCI USB 1.1 Controller + +-10.1 VIA Technologies, Inc. VT82xxxxx UHCI USB 1.1 Controller + +-10.2 VIA Technologies, Inc. VT82xxxxx UHCI USB 1.1 Controller + +-10.3 VIA Technologies, Inc. VT82xxxxx UHCI USB 1.1 Controller + +-10.4 VIA Technologies, Inc. USB 2.0 + +-11.0 VIA Technologies, Inc. VT8237 ISA bridge [KT600/K8T800/K8T890 South] + +-11.5 VIA Technologies, Inc. VT8233/A/8235/8237 AC97 Audio Controller + \-12.0 VIA Technologies, Inc. VT6102 [Rhine-II] +*/ + +/{ + mainboard_vendor = "VIA"; + mainboard_name = "EPIA-CN"; + mainboard_pci_subsystem_vendor = "0xdead"; /* TODO */ + mainboard_pci_subsystem_device = "0xbeef"; /* TODO */ + cpus { }; + apic@0 { + }; + domain@0 { + pci@0,0 {}; + pci@0,1 {}; + pci@0,2 {}; + pci@0,3 {}; + pci@0,4 {}; + pci@0,7 {}; + pci@1,0 {}; + pci@f,0 {}; + pci@10,0 { + /config/("southbridge/via/vt8237/sata.dts"); + }; + pci@10,1 { + /config/("southbridge/via/vt8237/ide.dts"); + }; + pci@11,0 { + /config/("southbridge/via/vt8237/lpc.dts"); + }; + ioport@4e { +/* + /config/("superio/via/vt1221/dts"); + com1enable = "1"; +*/ + }; + }; +}; Added: coreboot-v3/mainboard/via/epia-cn/initram.c =================================================================== --- coreboot-v3/mainboard/via/epia-cn/initram.c (rev 0) +++ coreboot-v3/mainboard/via/epia-cn/initram.c 2008-10-31 18:57:37 UTC (rev 973) @@ -0,0 +1,213 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Corey Osgood <corey.osgood(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define _MAINOBJECT + +#include <types.h> +#include <lib.h> +#include <console.h> +#include <io.h> +#include <spd.h> +#include <via_c7.h> +#include <arch/x86/pci_ops.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <superio/via/vt1211/vt1211.h> +#include <southbridge/via/vt8237/vt8237.h> +#include <northbridge/via/cn700/cn700.h> + +#define SMBUS_IO_BASE 0x0400 + +u8 spd_read_byte(u16 dev, u8 addr) +{ + return smbus_read_byte(dev, addr, SMBUS_IO_BASE); +} + +void find_smbus_devices(u8 min, u8 max) +{ + u8 dev; + u8 result; + for(dev = min; dev < max; dev++) + { + result = spd_read_byte(dev, SPD_MEMORY_TYPE); + switch(result) + { + case SPD_MEMORY_TYPE_SDRAM: printk(BIOS_DEBUG, + "Possible SDRAM spd at address 0x%2x\n", dev); + break; + case SPD_MEMORY_TYPE_SDRAM_DDR: printk(BIOS_DEBUG, + "Possible DDR SDRAM spd at address 0x%2x\n", dev); + break; + case SPD_MEMORY_TYPE_SDRAM_DDR2: printk(BIOS_DEBUG, + "Possible DDR2 SDRAM spd at address 0x%2x\n", dev); + break; + }; + } +} + + +void dump_smbus_registers(void) +{ + int device; + for(device = 1; device < (int)0x80; device++) { + int j; + //if(spd_read_byte(device, 0) < 0 ) + // continue; + printk(BIOS_DEBUG, "smbus: %02x", device); + for(j = 0; j < 256; j++) { + int status; + u8 byte; + status = spd_read_byte(device, j); + if (status < 0) { + break; + } + if ((j & 0xf) == 0) { + printk(BIOS_DEBUG, "\n%02x: ",j); + } + byte = status & 0xff; + printk(BIOS_DEBUG, "%02x ", byte); + } + printk(BIOS_DEBUG, "\n"); + } +} + +static void enable_mainboard_devices(void) +{ + u32 dev; + + pci_conf1_find_device(0x1106, 0x3227, &dev); + /* Disable GP3 */ + pci_conf1_write_config8(dev, 0x98, 0x00); + + pci_conf1_write_config8(dev, 0x50, 0x88);//disable mc97, sata + pci_conf1_write_config8(dev, 0x51, 0x1f); + pci_conf1_write_config8(dev, 0x58, 0x60); + pci_conf1_write_config8(dev, 0x59, 0x80); + pci_conf1_write_config8(dev, 0x5b, 0x08); + + pci_conf1_find_device(0x1106, 0x0571, &dev); + + /* Make it respond to IO space */ + pci_conf1_write_config8(dev, 0x04, 0x07); + + /* Compatibility mode addresses */ + //pci_conf1_write_config32(dev, 0x10, 0); + //pci_conf1_write_config32(dev, 0x14, 0); + //pci_conf1_write_config32(dev, 0x18, 0); + //pci_conf1_write_config32(dev, 0x1b, 0); + + /* Native mode base address */ + //pci_conf1_write_config32(dev, 0x20, BUS_MASTER_ADDR | 1); + + pci_conf1_write_config8(dev, 0x40, 0x4b);//was 0x3 + pci_conf1_write_config8(dev, 0x41, 0xf2); + pci_conf1_write_config8(dev, 0x42, 0x09); + /* I'll be damned if I know what these do */ + pci_conf1_write_config8(dev, 0x3c, 0xff);//was 0x0e + pci_conf1_write_config8(dev, 0x3d, 0x00);//was 0x00 +} + +static void enable_shadow_ram(void) +{ + u8 shadowreg; + + printk(BIOS_DEBUG, "Enabling shadow ram\n"); + /* Enable shadow ram as normal dram */ + /* 0xc0000-0xcffff */ + pci_conf1_write_config8(PCI_BDF(0, 0, 3), 0x80, 0xff); + pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x61, 0xff); + /* 0xd0000-0xdffff */ + pci_conf1_write_config8(PCI_BDF(0, 0, 3), 0x81, 0xff); + pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x62, 0xff); + /* 0xe0000-0xeffff */ + pci_conf1_write_config8(PCI_BDF(0, 0, 3), 0x82, 0xff); + pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x64, 0xff); + + /* 0xf0000-0xfffff */ + shadowreg = pci_conf1_read_config8(PCI_BDF(0, 0, 3), 0x83); + shadowreg |= 0x30; + pci_conf1_write_config8(PCI_BDF(0, 0, 3), 0x83, shadowreg); + + /* Do it again for the vlink controller */ + shadowreg = pci_conf1_read_config8(PCI_BDF(0, 0, 7), 0x63); + shadowreg |= 0x30; + pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x63, shadowreg); +} + +static void enable_vlink(void) +{ + printk(BIOS_DEBUG, "Enabling Via V-Link\n"); + + /* Enable V-Link statically in 8x mode, using Jetway default values */ +//40: 14 19 88 80 82 44 00 04 13 b9 88 80 82 44 00 01 + pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x42, 0x88); + pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x45, 0x44); + pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x46, 0x00); + pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x47, 0x04); + //pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x48, 0x13); + pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x4b, 0x80); + pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x4c, 0x82); + pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x4d, 0x44); + pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x4e, 0x00); + pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x4f, 0x01); +//b0: 05 01 00 83 35 66 66 64 45 98 77 11 00 00 00 00 + pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0xb4, 0x35); + pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0xb5, 0x66); + pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0xb6, 0x66); + pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0xb7, 0x64); + pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0xb8, 0x45); + pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0xb9, 0x98); + pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0xba, 0x77); + + /* This has to be done last, I think */ + pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x48, 0x13); +} + +int main(void) +{ + struct board_info ctrl[] = { + { + .d0f2 = PCI_BDF(0, 0, 2), + .d0f3 = PCI_BDF(0, 0, 3), + .d0f4 = PCI_BDF(0, 0, 4), + .d0f7 = PCI_BDF(0, 0, 7), + .d1f0 = PCI_BDF(0, 1, 0), + .spd_channel0 = {0x50}, + }, + }; + + printk(BIOS_DEBUG, "In initram.c main()\n"); + + enable_vlink(); + enable_mainboard_devices(); + enable_shadow_ram(); + + c7_cpu_setup(PCI_BDF(0, 0, 2)); + + enable_smbus(SMBUS_IO_BASE); + //find_smbus_devices(0x00, 0xff); + sdram_set_registers(ctrl); + sdram_set_spd_registers(ctrl); + ddr2_sdram_enable(ctrl); + + //ram_check(0, 640*1024); + //ram_check((8 * 1024 * 1024), (16 * 1024 * 1024)); + + return 0; +} Added: coreboot-v3/mainboard/via/epia-cn/mainboard.h =================================================================== --- coreboot-v3/mainboard/via/epia-cn/mainboard.h (rev 0) +++ coreboot-v3/mainboard/via/epia-cn/mainboard.h 2008-10-31 18:57:37 UTC (rev 973) @@ -0,0 +1,20 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Corey Osgood <corey.osgood(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + Added: coreboot-v3/mainboard/via/epia-cn/stage1.c =================================================================== --- coreboot-v3/mainboard/via/epia-cn/stage1.c (rev 0) +++ coreboot-v3/mainboard/via/epia-cn/stage1.c 2008-10-31 18:57:37 UTC (rev 973) @@ -0,0 +1,58 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Advanced Micro Devices, Inc. + * Copyright (C) 2008 Ronald G. Minnich <rminnich(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <types.h> +#include <lib.h> +#include <console.h> +#include <io.h> +#include <arch/x86/pci_ops.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <superio/fintek/f71805f/f71805f.h> +#include <northbridge/via/cn700/cn700.h> + +/* Someday, we're all going multicore. */ +void stop_ap(void) +{ +} + +void hardware_stage1(void) +{ + void vt1211_enable_serial(u8 dev, u8 serial, u16 iobase); + u32 dev; + + post_code(POST_START_OF_MAIN); + vt1211_enable_serial(0x2e, 2, 0x3f8); + + /* Enable multifunction for northbridge. */ + pci_conf1_write_config8(0x00, 0x4f, 0x01); + + printk(BIOS_SPEW, "In hardware_stage1()\n"); + /* Disabled GP3, to keep the system from rebooting automatically */ + //pci_conf1_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VT8237R_LPC, &dev); + dev = PCI_BDF(0, 17, 0); + pci_conf1_write_config8(dev, 0x98, 0x00); +} + +void mainboard_pre_payload(void) +{ + //banner(BIOS_DEBUG, "mainboard_pre_payload: done"); +}

1 0

r972 - in coreboot-v3: include/arch/x86 mainboard/jetway/j7f2
by svn＠coreboot.org Oct. 31, 2008

Oct. 31, 2008

Author: rminnich Date: 2008-10-31 19:56:53 +0100 (Fri, 31 Oct 2008) New Revision: 972 Modified: coreboot-v3/include/arch/x86/via_c7.h coreboot-v3/mainboard/jetway/j7f2/mainboard.h Log: All of these CPUS have 32 address bits in all cases. Move this to the cpu.h Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Modified: coreboot-v3/include/arch/x86/via_c7.h =================================================================== --- coreboot-v3/include/arch/x86/via_c7.h 2008-10-31 18:44:57 UTC (rev 971) +++ coreboot-v3/include/arch/x86/via_c7.h 2008-10-31 18:56:53 UTC (rev 972) @@ -25,6 +25,7 @@ #define SYSCFG_MSR 0xC0010010 #define SYSCFG_MSR_MtrrFixDramModEn (1 << 19) #define SYSCFG_MSR_MtrrFixDramEn (1 << 18) +#define CPU_ADDR_BITS 32 #ifndef __ASSEMBLER__ Modified: coreboot-v3/mainboard/jetway/j7f2/mainboard.h =================================================================== --- coreboot-v3/mainboard/jetway/j7f2/mainboard.h 2008-10-31 18:44:57 UTC (rev 971) +++ coreboot-v3/mainboard/jetway/j7f2/mainboard.h 2008-10-31 18:56:53 UTC (rev 972) @@ -18,4 +18,3 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define CPU_ADDR_BITS 32

1 0

[PATCH] v2: Revert i945/ICH7 PCI ID #define usage
by Uwe Hermann Oct. 31, 2008

Oct. 31, 2008

Hi, As there's obviously no consensus on whether or not to use #defines for PCI IDs in 'struct pci_driver' fields (I hope that we all _do_ agree that #defines are _usually_ better for readability, except in some rare cases), I suggest we declare this as a matter of taste and accept both variants in svn, depending on the preferences of the author of the code (Stefan in this case). Thus, here's a patch to revert i945/ICH7 back to hard-coded numbers. Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org

2 2

r971 - in coreboot-v3: . superio superio/via superio/via/vt1211
by svn＠coreboot.org Oct. 31, 2008

Oct. 31, 2008

Author: stuge Date: 2008-10-31 19:44:57 +0100 (Fri, 31 Oct 2008) New Revision: 971 Added: coreboot-v3/superio/via/ coreboot-v3/superio/via/vt1211/ coreboot-v3/superio/via/vt1211/Makefile coreboot-v3/superio/via/vt1211/stage1.c coreboot-v3/superio/via/vt1211/superio.c coreboot-v3/superio/via/vt1211/vt1211.h Modified: coreboot-v3/Kconfig Log: v3: superio/via/vt1211 with serial port init but nothing else Signed-off-by: Peter Stuge <peter(a)stuge.se> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Modified: coreboot-v3/Kconfig =================================================================== --- coreboot-v3/Kconfig 2008-10-31 18:39:46 UTC (rev 970) +++ coreboot-v3/Kconfig 2008-10-31 18:44:57 UTC (rev 971) @@ -122,6 +122,8 @@ boolean config SUPERIO_ITE_IT8712F boolean +config SUPERIO_VIA_VT1211 + boolean menu "Payload" Added: coreboot-v3/superio/via/vt1211/Makefile =================================================================== --- coreboot-v3/superio/via/vt1211/Makefile (rev 0) +++ coreboot-v3/superio/via/vt1211/Makefile 2008-10-31 18:44:57 UTC (rev 971) @@ -0,0 +1,29 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2008 Peter Stuge <peter(a)stuge.se> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +ifeq ($(CONFIG_SUPERIO_VIA_VT1211),y) + +STAGE0_CHIPSET_SRC += $(src)/superio/via/vt1211/stage1.c +STAGE0_CHIPSET_SRC += $(src)/device/pnp_raw.c + +# Always add to variables, as there could be more than one Super I/O. +#STAGE2_CHIPSET_SRC += $(src)/superio/via/vt1211/superio.c + +endif Added: coreboot-v3/superio/via/vt1211/stage1.c =================================================================== --- coreboot-v3/superio/via/vt1211/stage1.c (rev 0) +++ coreboot-v3/superio/via/vt1211/stage1.c 2008-10-31 18:44:57 UTC (rev 971) @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Peter Stuge <peter(a)stuge.se> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <io.h> +#include <device/pnp.h> +#include "vt1211.h" + +void vt1211_enable_serial(u8 dev, u8 serial, u16 iobase) +{ + rawpnp_enter_ext_func_mode(dev); + rawpnp_set_logical_device(dev, serial); + rawpnp_set_enable(dev, 0); + rawpnp_set_iobase(dev, 2, (iobase>>2) & 0xff); + rawpnp_set_enable(dev, 1); + rawpnp_exit_ext_func_mode(dev); +} Added: coreboot-v3/superio/via/vt1211/superio.c =================================================================== --- coreboot-v3/superio/via/vt1211/superio.c (rev 0) +++ coreboot-v3/superio/via/vt1211/superio.c 2008-10-31 18:44:57 UTC (rev 971) @@ -0,0 +1,216 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2000 AG Electronics Ltd. + * Copyright 2003-2004 Linux Networx + * Copyright 2004 Tyan + * By LYH change from PC87360 + * Copyright 2007 coresystems GmbH + * + * FIXME: This is total hack and slash of v2 code + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <io.h> +#include <lib.h> +#include <device/device.h> +#include <device/pnp.h> +#include <console.h> +#include <string.h> +//#include <bitops.h> +#include <uart8250.h> +#include <keyboard.h> +// #include <pc80/mc146818rtc.h> +#include <statictree.h> +#include "w83627hf.h" + +static void pnp_enter_ext_func_mode(struct device * dev) +{ + outb(0x87, dev->path.pnp.port); + outb(0x87, dev->path.pnp.port); +} + +static void pnp_exit_ext_func_mode(struct device * dev) +{ + outb(0xaa, dev->path.pnp.port); +} + +static void pnp_write_index(u16 port_base, u8 reg, u8 value) +{ + outb(reg, port_base); + outb(value, port_base + 1); +} + +static u8 pnp_read_index(u16 port_base, u8 reg) +{ + outb(reg, port_base); + return inb(port_base + 1); +} + +static void enable_hwm_smbus(struct device * dev) { + /* set the pin 91,92 as I2C bus */ + u8 reg, value; + reg = 0x2b; + value = pnp_read_config(dev, reg); + value &= 0x3f; + pnp_write_config(dev, reg, value); +} + +static void init_acpi(struct device * dev) +{ + u8 value = 0x20; + int power_on = 1; +#warning Fix CMOS handling + // get_option(&power_on, "power_on_after_fail"); + pnp_enter_ext_func_mode(dev); + pnp_write_index(dev->path.pnp.port,7,0x0a); + value = pnp_read_config(dev, 0xE4); + value &= ~(3<<5); + if(power_on) { + value |= (1<<5); + } + pnp_write_config(dev, 0xE4, value); + pnp_exit_ext_func_mode(dev); +} + +static void init_hwm(u16 base) +{ + u8 reg, value; + int i; + + unsigned hwm_reg_values[] = { + /* reg, mask, data */ + 0x40, 0xff, 0x81, /* start HWM */ + 0x48, 0xaa, 0x2a, /* set SMBus base to 0x54>>1 */ + 0x4a, 0x21, 0x21, /* set T2 SMBus base to 0x92>>1 and T3 SMBus base to 0x94>>1 */ + 0x4e, 0x80, 0x00, + 0x43, 0x00, 0xff, + 0x44, 0x00, 0x3f, + 0x4c, 0xbf, 0x18, + 0x4d, 0xff, 0x80 /* turn off beep */ + }; + + for (i = 0; i < ARRAY_SIZE(hwm_reg_values); i += 3) { + reg = hwm_reg_values[i]; + value = pnp_read_index(base, reg); + value &= 0xff & hwm_reg_values[i+1]; + value |= 0xff & hwm_reg_values[i+2]; + + printk(BIOS_SPEW, "base = 0x%04x, reg = 0x%02x, value = 0x%02x\r\n", base, reg,value); + + pnp_write_index(base, reg, value); + } +} + +static void w83627hf_init(struct device * dev) +{ + struct superio_winbond_w83627hf_dts_config *conf; + struct resource *res0, *res1; + struct pc_keyboard keyboard; + +#if 1 + printk(BIOS_ERR, "dummy init XXXX\n"); +#endif + + if (!dev->enabled) { + return; + } + + conf = dev->device_configuration; + switch(dev->path.pnp.device) { + case W83627HF_SP1: + res0 = find_resource(dev, PNP_IDX_IO0); +#warning init_uart8250 + //init_uart8250(res0->base, &conf->com1); + break; + case W83627HF_SP2: + res0 = find_resource(dev, PNP_IDX_IO0); +#warning init_uart8250 + //init_uart8250(res0->base, &conf->com2); + break; + case W83627HF_KBC: + res0 = find_resource(dev, PNP_IDX_IO0); + res1 = find_resource(dev, PNP_IDX_IO1); + init_pc_keyboard(res0->base, res1->base, &keyboard); + break; + case W83627HF_HWM: + res0 = find_resource(dev, PNP_IDX_IO0); +#define HWM_INDEX_PORT 5 + init_hwm(res0->base + HWM_INDEX_PORT); + break; + case W83627HF_ACPI: + init_acpi(dev); + break; + } +} + +void w83627hf_pnp_set_resources(struct device * dev) +{ + pnp_enter_ext_func_mode(dev); + pnp_set_resources(dev); + pnp_exit_ext_func_mode(dev); +} + +void w83627hf_pnp_enable_resources(struct device * dev) +{ + pnp_enter_ext_func_mode(dev); + pnp_enable_resources(dev); + switch(dev->path.pnp.device) { + case W83627HF_HWM: + printk(BIOS_DEBUG, "w83627hf hwm smbus enabled\n"); + enable_hwm_smbus(dev); + break; + } + pnp_exit_ext_func_mode(dev); +} + +void w83627hf_pnp_enable(struct device * dev) +{ + if (!dev->enabled) { + pnp_enter_ext_func_mode(dev); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_exit_ext_func_mode(dev); + } +} +static void phase2_setup_scan_bus(struct device *dev); +struct device_operations w83627hf_ops = { + .phase2_setup_scan_bus = phase2_setup_scan_bus, + .phase4_read_resources = pnp_read_resources, + .phase4_set_resources = w83627hf_pnp_set_resources, + .phase4_enable_disable = w83627hf_pnp_enable_resources, + .phase5_enable_resources = w83627hf_pnp_enable, + .phase6_init = w83627hf_init, +}; + +static struct pnp_info pnp_dev_info[] = { + { &w83627hf_ops, W83627HF_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, }, + { &w83627hf_ops, W83627HF_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, }, + { &w83627hf_ops, W83627HF_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, + { &w83627hf_ops, W83627HF_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, + // No 4 { 0,}, + { &w83627hf_ops, W83627HF_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, { 0x7ff, 0x4}, }, + { &w83627hf_ops, W83627HF_CIR, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, + { &w83627hf_ops, W83627HF_GAME_MIDI_GPIO1, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x7ff, 0 }, {0x7fe, 0x4}, }, + { &w83627hf_ops, W83627HF_GPIO2, }, + { &w83627hf_ops, W83627HF_GPIO3, }, + { &w83627hf_ops, W83627HF_ACPI, }, + { &w83627hf_ops, W83627HF_HWM, PNP_IO0 | PNP_IRQ0, { 0xff8, 0 }, }, +}; + +static void phase2_setup_scan_bus(struct device *dev) +{ + pnp_enable_devices(dev, &w83627hf_ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); +} Added: coreboot-v3/superio/via/vt1211/vt1211.h =================================================================== --- coreboot-v3/superio/via/vt1211/vt1211.h (rev 0) +++ coreboot-v3/superio/via/vt1211/vt1211.h 2008-10-31 18:44:57 UTC (rev 971) @@ -0,0 +1,36 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2007 Ronald G. Minnich <rminnich(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef SUPERIO_VIA_VT1211_VT122_H +#define SUPERIO_VIA_VT1211_VT122_H + +#define VT1211_FDC 0 /* Floppy */ +#define VT1211_PP 1 /* Parallel Port */ +#define VT1211_SP1 2 /* Com1 */ +#define VT1211_SP2 3 /* Com2 */ +#define VT1211_KBC 5 /* Keyboard & Mouse */ +#define VT1211_CIR 6 +#define VT1211_GAME_MIDI_GPIO1 7 +#define VT1211_GPIO2 8 +#define VT1211_GPIO3 9 +#define VT1211_ACPI 10 +#define VT1211_HWM 11 /* Hardware Monitor */ + +#endif /* SUPERIO_VIA_VT1211_VT122_H */

1 0