Re: [coreboot] r973 - coreboot-v3/mainboard/via/epia-cn

[Uwe Hermann]

On Fri, Oct 31, 2008 at 07:57:37PM +0100, [e-mail] wrote:
> Added: coreboot-v3/mainboard/via/epia-cn/initram.c
>
> --- coreboot-v3/mainboard/via/epia-cn/initram.c	                        (rev 0)
> +++ coreboot-v3/mainboard/via/epia-cn/initram.c	2008-10-31 18:57:37 UTC (rev 973)
> +void dump_smbus_registers(void)
> +{
> int device;
> for(device = 1; device < (int)0x80; device++) {
> int j;
> //if(spd_read_byte(device, 0) < 0 )
> //	continue;
> printk(BIOS_DEBUG, "smbus: %02x", device);
> for(j = 0; j < 256; j++) {
> 	int status;
> 	u8 byte;
> 	status = spd_read_byte(device, j);
> 	if (status < 0) {
> 		break;
> 	}
> 	if ((j & 0xf) == 0) {
> 		printk(BIOS_DEBUG, "\n%02x: ",j);
> 	}
> 	byte = status & 0xff;
> 	printk(BIOS_DEBUG, "%02x ", byte);
> }
> printk(BIOS_DEBUG, "\n");
> }
>
> +}

Note for later: Move this to some lib/ file, this is not epia-cn
specific in any way.
> Added: coreboot-v3/mainboard/via/epia-cn/mainboard.h
>
> --- coreboot-v3/mainboard/via/epia-cn/mainboard.h	                        (rev 0)
> +++ coreboot-v3/mainboard/via/epia-cn/mainboard.h	2008-10-31 18:57:37 UTC (rev 973)
> @@ -0,0 +1,20 @@
> +/*
> This file is part of the coreboot project.
> Copyright (C) 2008 Corey Osgood
> This program is free software; you can redistribute it and/or modify
> it under the terms of the GNU General Public License as published by
> the Free Software Foundation; either version 2 of the License, or
> (at your option) any later version.
> This program is distributed in the hope that it will be useful,
> but WITHOUT ANY WARRANTY; without even the implied warranty of
> MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> GNU General Public License for more details.
> You should have received a copy of the GNU General Public License
> along with this program; if not, write to the Free Software
> Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
> */

Empty file? Drop? At least until it's actually needed (if it ever is).
> Added: coreboot-v3/mainboard/via/epia-cn/stage1.c
>
> --- coreboot-v3/mainboard/via/epia-cn/stage1.c	                        (rev 0)
> +++ coreboot-v3/mainboard/via/epia-cn/stage1.c	2008-10-31 18:57:37 UTC (rev 973)
> @@ -0,0 +1,58 @@
> +/*
> This file is part of the coreboot project.
> Copyright (C) 2007 Advanced Micro Devices, Inc.

I doubt that someone at AMD wrote any of this code in 2007. Please don't
carry around (C) lines for any such trivial files where almost nothing
(if anything at all) if from the copyright holder you're listing...

(it _is_ important to keep the (C) lines when you copy/reuse a
non-trivial amount of non-trivial code, of course!)

Just
  Copyright (C) 2008 Ronald G. Minnich 
is fully sufficient here, IMO.
> Copyright (C) 2008 Ronald G. Minnich
> This program is free software; you can redistribute it and/or modify
> it under the terms of the GNU General Public License as published by
> the Free Software Foundation; either version 2 of the License, or
> (at your option) any later version.
> This program is distributed in the hope that it will be useful,
> but WITHOUT ANY WARRANTY; without even the implied warranty of
> MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> GNU General Public License for more details.
> You should have received a copy of the GNU General Public License
> along with this program; if not, write to the Free Software
> Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
> */
>
> +#include <types.h>
> +#include <lib.h>
> +#include <console.h>
> +#include <io.h>
> +#include <arch/x86/pci_ops.h>
> +#include <device/pci.h>
> +#include <device/pci_ids.h>
> +#include <superio/fintek/f71805f/f71805f.h>
> +#include <northbridge/via/cn700/cn700.h>
>
> +/* Someday, we're all going multicore. */
> +void stop_ap(void)
> +{
> +}
>
> +void hardware_stage1(void)
> +{
> void vt1211_enable_serial(u8 dev, u8 serial, u16 iobase);
> u32 dev;
> post_code(POST_START_OF_MAIN);
> vt1211_enable_serial(0x2e, 2, 0x3f8);
> /* Enable multifunction for northbridge. */
> pci_conf1_write_config8(0x00, 0x4f, 0x01);
> printk(BIOS_SPEW, "In hardware_stage1()\n");
> /* Disabled GP3, to keep the system from rebooting automatically */
> //pci_conf1_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VT8237R_LPC, &dev);
> dev = PCI_BDF(0, 17, 0);
> pci_conf1_write_config8(dev, 0x98, 0x00);
>
> +}

Uwe.