Please correct me if I'm wrong (I don't have NDA'd Intel datasheets, I
can only check the public ones), but I think the enable_hpet() in the
ICH7 code will not work for ICH7. It should work for ICH4/ICH5 or so,
but ICH7 requires a completely different init involving RCBA, offset
0x3404, it seems.
Thus, drop the non-working code, add a TODO until somebody writes the
proper code for ICH7. Maybe I'll do that if nobody beats me to it, but
it may take a while.
Uwe.
--
http://www.hermann-uwe.de | http://www.holsham-traders.dehttp://www.crazy-hacks.org | http://www.unmaintained-free-software.org
Hello Carldani,
You were right about the flash : this board is equipped with a ST flash
and not with a Spansion...
Now, I check the modifications we made yesterday night in flashrom. With
them, flashrom is now working fine :
I can read, I can write the flash content. Erase not tested.
flashrom indicates that the ST M25P16 has a status 'untested' for
operations PROBE READ ERASE WRITE.
Tests and relevant traces are attached. If you need anything else,
please, let me know.
Best regards, and thx for help.
Stéphan.
PROBE works better with the 2nd fix (ich7 instead of ich_dc)
READ/WRITE looks to work fine
ERASE not tested
Some modifications I added in flashrom code to have this work :
1) ST M25P16 works better with ich7 on EP80579
2) Initialize tmp to avoid garbage in the variable.
----------------------------------------------------------------------------------
diff -c flashrom-V2-3695/chipset_enable.c flashrom/chipset_enable.c
*** flashrom-V2-3695/chipset_enable.c Sun Oct 26 19:40:42 2008
--- flashrom/chipset_enable.c Tue Oct 28 14:47:28 2008
***************
*** 765,771 ****
{0x8086, 0x25a1, "Intel 6300ESB", enable_flash_ich_4e},
{0x8086, 0x2640, "Intel ICH6/ICH6R", enable_flash_ich_dc},
{0x8086, 0x2641, "Intel ICH6-M", enable_flash_ich_dc},
! {0x8086, 0x5031, "Intel EP80579", enable_flash_ich_dc},
{0x8086, 0x27b0, "Intel ICH7DH", enable_flash_ich7},
{0x8086, 0x27b8, "Intel ICH7/ICH7R", enable_flash_ich7},
{0x8086, 0x27b9, "Intel ICH7M", enable_flash_ich7},
--- 765,771 ----
{0x8086, 0x25a1, "Intel 6300ESB", enable_flash_ich_4e},
{0x8086, 0x2640, "Intel ICH6/ICH6R", enable_flash_ich_dc},
{0x8086, 0x2641, "Intel ICH6-M", enable_flash_ich_dc},
! {0x8086, 0x5031, "Intel EP80579", enable_flash_ich7},
{0x8086, 0x27b0, "Intel ICH7DH", enable_flash_ich7},
{0x8086, 0x27b8, "Intel ICH7/ICH7R", enable_flash_ich7},
{0x8086, 0x27b9, "Intel ICH7M", enable_flash_ich7},
----------------------------------------------------------------------------------
diff -c flashrom-V2-3695/board_enable.c flashrom/board_enable.c
*** flashrom-V2-3695/board_enable.c Sat Oct 18 23:14:13 2008
--- flashrom/board_enable.c Mon Oct 27 19:02:12 2008
***************
*** 250,256 ****
*/
static int board_asus_p5a(const char *name)
{
! uint8_t tmp;
int i;
#define ASUSP5A_LOOP 5000
--- 250,256 ----
*/
static int board_asus_p5a(const char *name)
{
! uint8_t tmp = 0;
int i;
#define ASUSP5A_LOOP 5000
----------------------------------------------------------------------------------
[root@lion04 root]# flashrom --read flash_content.rom
Calibrating delay loop... OK.
No coreboot table found.
Found chipset "Intel EP80579", enabling flash write... OK.
Found chip "ST M25P16" (2048 KB) at physical address 0xffe00000.
===
This flash part has status UNTESTED for operations: PROBE READ ERASE WRITE
Please email a report to flashrom(a)coreboot.org if any of the above operations
work correctly for you with this flash part. Please include the full output
from the program, including chipset found. Thank you for your help!
===
Reading Flash...done
[root@lion04 root]#
----------------------------------------------------------------------------------
[root@lion04 root]# flashrom --write 0ABPT907.ROM
Calibrating delay loop... OK.
No coreboot table found.
Found chipset "Intel EP80579", enabling flash write... OK.
Found chip "ST M25P16" (2048 KB) at physical address 0xffe00000.
===
This flash part has status UNTESTED for operations: PROBE READ ERASE WRITE
Please email a report to flashrom(a)coreboot.org if any of the above operations
work correctly for you with this flash part. Please include the full output
from the program, including chipset found. Thank you for your help!
===
Flash image seems to be a legacy BIOS. Disabling checks.
Programming page:
DONE BLOCK 0x0
DONE BLOCK 0x10000
DONE BLOCK 0x20000
DONE BLOCK 0x30000
DONE BLOCK 0x40000
DONE BLOCK 0x50000
DONE BLOCK 0x60000
DONE BLOCK 0x70000
DONE BLOCK 0x80000
DONE BLOCK 0x90000
DONE BLOCK 0xa0000
DONE BLOCK 0xb0000
DONE BLOCK 0xc0000
DONE BLOCK 0xd0000
DONE BLOCK 0xe0000
DONE BLOCK 0xf0000
DONE BLOCK 0x100000
DONE BLOCK 0x110000
DONE BLOCK 0x120000
DONE BLOCK 0x130000
DONE BLOCK 0x140000
DONE BLOCK 0x150000
DONE BLOCK 0x160000
DONE BLOCK 0x170000
DONE BLOCK 0x180000
DONE BLOCK 0x190000
DONE BLOCK 0x1a0000
DONE BLOCK 0x1b0000
DONE BLOCK 0x1c0000
DONE BLOCK 0x1d0000
DONE BLOCK 0x1e0000
DONE BLOCK 0x1f0000
[root@lion04 root]#
----------------------------------------------------------------------------------
[root@lion04 BIOS_AMI]# flashrom --verify 0ABPT907.ROM
Calibrating delay loop... OK.
No coreboot table found.
Found chipset "Intel EP80579", enabling flash write... OK.
Found chip "ST M25P16" (2048 KB) at physical address 0xffe00000.
===
This flash part has status UNTESTED for operations: PROBE READ ERASE WRITE
Please email a report to flashrom(a)coreboot.org if any of the above operations
work correctly for you with this flash part. Please include the full output
from the program, including chipset found. Thank you for your help!
===
Flash image seems to be a legacy BIOS. Disabling checks.
Verifying flash... VERIFIED.
[root@lion04 root]#
----------------------------------------------------------------------------------
[root@lion04 BIOS_AMI]# flashrom --verify flash_content.rom
Calibrating delay loop... OK.
No coreboot table found.
Found chipset "Intel EP80579", enabling flash write... OK.
Found chip "ST M25P16" (2048 KB) at physical address 0xffe00000.
===
This flash part has status UNTESTED for operations: PROBE READ ERASE WRITE
Please email a report to flashrom(a)coreboot.org if any of the above operations
work correctly for you with this flash part. Please include the full output
from the program, including chipset found. Thank you for your help!
===
Flash image seems to be a legacy BIOS. Disabling checks.
Verifying flash... FAILED! Expected=0x4e, Read=0xff
[root@lion04 root]#
----------------------------------------------------------------------------------
[root@lion04 BIOS_AMI]# flashrom --erase
Calibrating delay loop... OK.
No coreboot table found.
Found chipset "Intel EP80579", enabling flash write... OK.
Found chip "ST M25P16" (2048 KB) at physical address 0xffe00000.
===
This flash part has status UNTESTED for operations: PROBE READ ERASE WRITE
Please email a report to flashrom(a)coreboot.org if any of the above operations
work correctly for you with this flash part. Please include the full output
from the program, including chipset found. Thank you for your help!
===
Erasing flash chip.
[root@lion04 root]#
----------------------------------------------------------------------------------
[root@lion04 BIOS_AMI]# flashrom --read zero.rom
Calibrating delay loop... OK.
No coreboot table found.
Found chipset "Intel EP80579", enabling flash write... OK.
Found chip "ST M25P16" (2048 KB) at physical address 0xffe00000.
===
This flash part has status UNTESTED for operations: PROBE READ ERASE WRITE
Please email a report to flashrom(a)coreboot.org if any of the above operations
work correctly for you with this flash part. Please include the full output
from the program, including chipset found. Thank you for your help!
===
Reading Flash...done
[root@lion04 BIOS_AMI]# hexdump zero.rom
0000000 ffff ffff ffff ffff ffff ffff ffff ffff
*
0200000
[root@lion04 root]#
Hi,
The latest svn revisions of filo and libpayload (r83 and r3708) conspire
to add the video console driver twice to the console_out list. This
causes the list to become circular, with the effect that device_putchar
spins in a loop printing the first character it is given. ("F".)
Trivial patch and .config appended. (One might perhaps also consider
making device_putchar or console_add_* more robust in the face of this
kind of error, but I settled for this.)
--
Arne.
#
# Automatically generated make config: don't edit
# FILO version: 0.6.0rc1
# Thu Oct 30 12:01:16 2008
#
CONFIG_TARGET_I386=y
# CONFIG_REVIEW is not set
#
# Interface Options
#
CONFIG_USE_GRUB=y
CONFIG_PROMPT="filo"
CONFIG_MENULST_FILE="hde1:/grub/menu.lst"
CONFIG_MENULST_TIMEOUT=3
CONFIG_USE_MD5_PASSWORDS=y
#
# Drivers
#
CONFIG_IDE_DISK=y
CONFIG_IDE_DISK_POLL_DELAY=0
# CONFIG_SLOW_SATA is not set
# CONFIG_PCMCIA_CF is not set
CONFIG_USB_NEW_DISK=y
# CONFIG_USB_DISK is not set
# CONFIG_FLASH_DISK is not set
CONFIG_SUPPORT_PCI=y
# CONFIG_PCI_BRUTE_SCAN is not set
# CONFIG_SUPPORT_SOUND is not set
#
# Filesystems
#
CONFIG_FSYS_EXT2FS=y
CONFIG_FSYS_FAT=y
# CONFIG_FSYS_JFS is not set
# CONFIG_FSYS_MINIX is not set
# CONFIG_FSYS_REISERFS is not set
# CONFIG_FSYS_XFS is not set
CONFIG_FSYS_ISO9660=y
CONFIG_ELTORITO=y
# CONFIG_FSYS_CRAMFS is not set
# CONFIG_FSYS_SQUASHFS is not set
#
# Loaders
#
CONFIG_LINUX_LOADER=y
# CONFIG_WINCE_LOADER is not set
# CONFIG_ARTEC_BOOT is not set
#
# Debugging & Experimental
#
# CONFIG_EXPERIMENTAL is not set
# CONFIG_DEBUG_ALL is not set
# CONFIG_DEBUG_ELFBOOT is not set
# CONFIG_DEBUG_ELFNOTE is not set
# CONFIG_DEBUG_SEGMENT is not set
# CONFIG_DEBUG_SYS_INFO is not set
# CONFIG_DEBUG_BLOCKDEV is not set
# CONFIG_DEBUG_VFS is not set
# CONFIG_DEBUG_FSYS_EXT2FS is not set
# CONFIG_DEBUG_PCI is not set
# CONFIG_DEBUG_LINUXLOAD is not set
# CONFIG_DEBUG_IDE is not set
# CONFIG_DEBUG_ELTORITO is not set
CONFIG_DEVELOPER_TOOLS=y
Attached patches for cn700, vt8237(r/s), and the mainboard, Jetway J7F2,
along with a boot log. Currently, we're stuck in a reboot loop and I have no
idea why, seems to be related to CAR disabling (this wasn't happening when
disable_car was a noop). Carl-Daniel, any ideas?
-Corey
Hi,
Does anyone know what "ELF boot notes" are? I've seen this reference in
coreboot-v2/src/arch/i386/boot/boot.c. There's a struct named elf_boot_notes
whose pointer is passed to the payload via %ebx, and a magic signature in
%eax as well.
Which is very similar to Multiboot (possibly inspired by it?), as it uses the
same registers and is therefore impossible to support both things at the same
time.
This interface is not in v3. Does this mean it's no longer being used? If
it's still in use with v2, I could add a build option that selects between
them.
--
Robert Millan
The DRM opt-in fallacy: "Your data belongs to us. We will decide when (and
how) you may access your data; but nobody's threatening your freedom: we
still allow you to remove your data and not access it at all."