October 2008 - coreboot - mail.coreboot.org

[PATCH] v3: s/BIOS_DEBUG/DEBUG/ etc. for printk()

by Uwe Hermann

See patch. Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org

11 years

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coreboot bios

by Parts & Repair

Is there a Coreboot bios for the TP 600x? Northbridge Intel i440BX/ZX rev. C1 Mainboard Model 26454EU (0x19F - 0x44C0F5) Name Intel Pentium III E Codename Coppermine Specification Package MMC (platform ID = 3h) CPUID 6.8.1 root@darkstar:/# lspci 00:00.0 Host bridge: Intel Corporation 440BX/ZX/DX - 82443BX/ZX/DX Host bridge (rev 03) 00:01.0 PCI bridge: Intel Corporation 440BX/ZX/DX - 82443BX/ZX/DX AGP bridge (rev 03) 00:02.0 CardBus bridge: Texas Instruments PCI1450 (rev 03) 00:02.1 CardBus bridge: Texas Instruments PCI1450 (rev 03) 00:03.0 Communication controller: Agere Systems WinModem 56k (rev 01) 00:06.0 Multimedia audio controller: Cirrus Logic CS 4614/22/24/30 [CrystalClear SoundFusion Audio Accelerator] (rev 01) 00:07.0 Bridge: Intel Corporation 82371AB/EB/MB PIIX4 ISA (rev 02) 00:07.1 IDE interface: Intel Corporation 82371AB/EB/MB PIIX4 IDE (rev 01) 00:07.2 USB Controller: Intel Corporation 82371AB/EB/MB PIIX4 USB (rev 01) 00:07.3 Bridge: Intel Corporation 82371AB/EB/MB PIIX4 ACPI (rev 03) 01:00.0 VGA compatible controller: Neomagic Corporation NM2360 [MagicMedia 256ZX] 06:00.0 Ethernet controller: Atheros Communications Inc. AR2413 802.11bg NIC (rev 01)

11 years

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[PATCH] new board: LiPPERT Cool SpaceRunner-LX

by Jens Rottmann

Add support for the LiPPERT Cool SpaceRunner-LX embedded PC board: - PC/104+ form factor - AMD Geode-LX CPU/northbridge - AMD CS5536 southbridge - ITE IT8712F superio Signed-off-by: Jens Rottmann <JRottmann(a)LiPPERTEmbedded.de> --- My previous mail still awaits list moderator approval, but I'm sending this anyway. :) Maybe you'll have to apply the patches from my previous mail first for this to compile. There are still large parts of coreboot's design that I don't fully understand yet, but I hope I did all right. All mainboard files are based on the AMD DB800. By the way, cmos.layout doesn't seem to be used (HAVE_OPTION_TABLE=0), still coreboot doesn't compile without it. Is there a designated way to use a global, generic file instead? Best regards, Jens Rottmann Index: src/mainboard/lippert/spacerunner-lx/cache_as_ram_auto.c =================================================================== --- src/mainboard/lippert/spacerunner-lx/cache_as_ram_auto.c (revision 0) +++ src/mainboard/lippert/spacerunner-lx/cache_as_ram_auto.c (working copy) @@ -0,0 +1,213 @@ +/* + * (C)2008 LiPPERT Embedded Computers GmbH, released under the GNU GPLv2 + * + * Based on cache_as_ram_auto.c from AMD's DB800 and DBM690T mainboards. + */ + +#define ASSEMBLY 1 + +#include <stdlib.h> +#include <stdint.h> +#include <spd.h> +#include <device/pci_def.h> +#include <arch/io.h> +#include <device/pnp_def.h> +#include <arch/hlt.h> +#include "pc80/serial.c" +#include "arch/i386/lib/console.c" +#include "ram/ramtest.c" +#include "cpu/x86/bist.h" +#include "cpu/x86/msr.h" +#include <cpu/amd/lxdef.h> +#include <cpu/amd/geode_post_code.h> +#include "southbridge/amd/cs5536/cs5536.h" + +#define POST_CODE(x) outb(x, 0x80) + +#include "southbridge/amd/cs5536/cs5536_early_smbus.c" +#include "southbridge/amd/cs5536/cs5536_early_setup.c" +#include "superio/ite/it8712f/it8712f_early_serial.c" + +#define SMC_CONFIG 0x01 /* bit0 enables Spread Spectrum, bit1 makes on-board SSD act as IDE Slave */ + +#define ManualConf 1 /* No automatic strapped PLL config */ +#define PLLMSRhi 0x0000059C /* Manual settings for the PLL */ +#define PLLMSRlo 0x00DE6001 +#define DIMM0 0xA0 +#define DIMM1 0xA2 + +static const unsigned char spdbytes[] = { // 4x Promos V58C2512164SA-J5I + 0xFF, 0xFF, // only values used by Geode-LX raminit.c are set + [SPD_MEMORY_TYPE] = SPD_MEMORY_TYPE_SDRAM_DDR, // (Fundamental) memory type + [SPD_NUM_ROWS] = 0x0D, // Number of row address bits [13] + [SPD_NUM_COLUMNS] = 0x0A, // Number of column address bits [10] + [SPD_NUM_DIMM_BANKS] = 1, // Number of module rows (banks) + 0xFF, 0xFF, 0xFF, + [SPD_MIN_CYCLE_TIME_AT_CAS_MAX] = 0x50, // SDRAM cycle time (highest CAS latency), RAS access time (tRAC) [5.0 ns in BCD] + 0xFF, 0xFF, + [SPD_REFRESH] = 0x82, // Refresh rate/type [Self Refresh, 7.8 us] + [SPD_PRIMARY_SDRAM_WIDTH] = 64, // SDRAM width (primary SDRAM) [64 bits] + 0xFF, 0xFF, 0xFF, + [SPD_NUM_BANKS_PER_SDRAM] = 4, // SDRAM device attributes, number of banks on SDRAM device + [SPD_ACCEPTABLE_CAS_LATENCIES] = 0x1C, // SDRAM device attributes, CAS latency [3, 2.5, 2] + 0xFF, 0xFF, + [SPD_MODULE_ATTRIBUTES] = 0x20, // SDRAM module attributes [differential clk] + [SPD_DEVICE_ATTRIBUTES_GENERAL] = 0x40, // SDRAM device attributes, general [Concurrent AP] + [SPD_SDRAM_CYCLE_TIME_2ND] = 0x60, // SDRAM cycle time (2nd highest CAS latency) [6.0 ns in BCD] + 0xFF, + [SPD_SDRAM_CYCLE_TIME_3RD] = 0x75, // SDRAM cycle time (3rd highest CAS latency) [7.5 ns in BCD] + 0xFF, + [SPD_tRP] = 60, // Min. row precharge time [15 ns in units of 0.25 ns] + [SPD_tRRD] = 40, // Min. row active to row active [10 ns in units of 0.25 ns] + [SPD_tRCD] = 60, // Min. RAS to CAS delay [15 ns in units of 0.25 ns] + [SPD_tRAS] = 40, // Min. RAS pulse width = active to precharge delay [40 ns] + [SPD_BANK_DENSITY] = 0x40, // Density of each row on module [256 MB] + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + [SPD_tRFC] = 70 // SDRAM Device Minimum Auto Refresh to Active/Auto Refresh [70 ns] +}; + +static inline int spd_read_byte(unsigned int device, unsigned int address) +{ + if (device != DIMM0) return 0xFF; // no DIMM1, don't even try +#if DEBUG + if (address >= sizeof(spdbytes) || spdbytes[address] == 0xFF) { + print_err("ERROR: spd_read_byte(DIMM0, 0x"); + print_err_hex8(address); + print_err(") returns 0xff\r\n"); + } +#endif + return (address < sizeof(spdbytes)) ? spdbytes[address] : 0xFF; // fake SPD ROM value +} + +/* Send config data to System Management Controller via SMB. */ +static int smc_send_config(unsigned char config_data) +{ + if (smbus_check_stop_condition(SMBUS_IO_BASE)) + return 1; + if (smbus_start_condition(SMBUS_IO_BASE)) + return 2; + if (smbus_send_slave_address(SMBUS_IO_BASE, 0x50)) // SMC address + return 3; + if (smbus_send_command(SMBUS_IO_BASE, 0x28)) // set config data + return 4; + if (smbus_send_command(SMBUS_IO_BASE, 0x01)) // data length + return 5; + if (smbus_send_command(SMBUS_IO_BASE, config_data)) + return 6; + smbus_stop_condition(SMBUS_IO_BASE); + return 0; +} + +#include "northbridge/amd/lx/raminit.h" +#include "northbridge/amd/lx/pll_reset.c" +#include "northbridge/amd/lx/raminit.c" +#include "sdram/generic_sdram.c" +#include "cpu/amd/model_lx/cpureginit.c" +#include "cpu/amd/model_lx/syspreinit.c" + +static void msr_init(void) +{ + msr_t msr; + + /* Setup access to the cache for under 1MB. */ + msr.hi = 0x24fffc02; + msr.lo = 0x1000A000; /* 0-A0000 write back */ + wrmsr(CPU_RCONF_DEFAULT, msr); + + msr.hi = 0x0; /* Write back */ + msr.lo = 0x0; + wrmsr(CPU_RCONF_A0_BF, msr); + wrmsr(CPU_RCONF_C0_DF, msr); + wrmsr(CPU_RCONF_E0_FF, msr); + + /* Setup access to the cache for under 640K. Note MC not setup yet. */ + msr.hi = 0x20000000; + msr.lo = 0xfff80; + wrmsr(MSR_GLIU0 + 0x20, msr); + + msr.hi = 0x20000000; + msr.lo = 0x80fffe0; + wrmsr(MSR_GLIU0 + 0x21, msr); + + msr.hi = 0x20000000; + msr.lo = 0xfff80; + wrmsr(MSR_GLIU1 + 0x20, msr); + + msr.hi = 0x20000000; + msr.lo = 0x80fffe0; + wrmsr(MSR_GLIU1 + 0x21, msr); +} + +static const unsigned short sio_init_table[] = { // hi=data, lo=index + 0x0707, // select LDN 7 (GPIO, SPI, watchdog, ...) + 0x1E2C, // disable ATXPowerGood + 0x0423, // don't delay POWerOK1/2 + 0x9072, // watchdog triggers POWOK, counts seconds +#if !USE_WATCHDOG_ON_BOOT + 0x0073, 0x0074, // disable watchdog by setting timeout to 0 +#endif + 0xBF25, 0x172A, 0xF326, // select GPIO function for most pins + 0xFF27, 0xDF28, 0x2729, // (GP45=SUSB, GP23,22,16,15=SPI, GP13=PWROK1) + 0x072C, // VIN6=enabled?, FAN4/5 disabled, VIN7=internal, VIN3=internal + 0x66B8, 0x0CB9, // enable pullups + 0x07C0, // enable Simple-I/O for GP12-10= RS485_EN2,1, LIVE_LED + 0x07C8, // config GP12-10 as output + 0x2DF5, // map Hw Monitor Thermal Output to GP55 + 0x08F8, // map GP LED Blinking 1 to GP10=LIVE_LED (deactivate Simple I/O to use) + 0x0202 // exit conf mode +}; + +/* Early mainboard specific GPIO setup. */ +static void mb_gpio_init(void) +{ + int i; + + /* Init SuperIO WDT, GPIOs. Done early, WDT init may trigger reset! */ + it8712f_enter_conf(); + for (i=0; i<ARRAY_SIZE(sio_init_table); i++) { + unsigned short val = sio_init_table[i]; + outb((unsigned char)val, SIO_INDEX); outb(val>>8, SIO_DATA); + } + //it8712f_exit_conf() is included in sio_init_table +} + +void cache_as_ram_main(void) +{ + int err; + POST_CODE(0x01); + + static const struct mem_controller memctrl[] = { + {.channel0 = {(0xa << 3) | 0, (0xa << 3) | 1}} + }; + + SystemPreInit(); + msr_init(); + + cs5536_early_setup(); + + /* Note: must do this AFTER the early_setup! It is counting on some + * early MSR setup for CS5536. + */ + it8712f_enable_serial(0, TTYS0_BASE); // does not use its 1st parameter + mb_gpio_init(); + uart_init(); + console_init(); + + pll_reset(ManualConf); + + cpuRegInit(); + + if ((err=smc_send_config(SMC_CONFIG))) { // bit1=on-board IDE is Slave, bit0=Spread Spectrum + print_err("ERROR "); + print_err_char('0'+err); + print_err(" sending config data to SMC\r\n"); + } + + sdram_initialize(1, memctrl); + + /* Check memory. */ + /* ram_check(0x00000000, 640 * 1024); */ + + /* Memory is setup. Return to cache_as_ram.inc and continue to boot. */ + return; +} Index: src/mainboard/lippert/spacerunner-lx/chip.h =================================================================== --- src/mainboard/lippert/spacerunner-lx/chip.h (revision 0) +++ src/mainboard/lippert/spacerunner-lx/chip.h (working copy) @@ -0,0 +1,11 @@ +/* + * (C)2008 LiPPERT Embedded Computers GmbH, released under the GNU GPLv2 + * + * Based on chip.h from AMD's DB800 mainboard. + */ + +extern struct chip_operations mainboard_lippert_spacerunner_lx_ops; + +struct mainboard_lippert_spacerunner_lx_config { + unsigned char sio_gp1x_config; // bit2=RS485_EN2, bit1=RS485_EN1, bit0=Live LED +}; Index: src/mainboard/lippert/spacerunner-lx/cmos.layout =================================================================== --- src/mainboard/lippert/spacerunner-lx/cmos.layout (revision 0) +++ src/mainboard/lippert/spacerunner-lx/cmos.layout (working copy) @@ -0,0 +1,74 @@ +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +1008 16 h 0 check_sum + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD +7 10 Fallback_Floppy +#7 3 ROM + +checksums + +checksum 392 1007 1008 + + Index: src/mainboard/lippert/spacerunner-lx/Config.lb =================================================================== --- src/mainboard/lippert/spacerunner-lx/Config.lb (revision 0) +++ src/mainboard/lippert/spacerunner-lx/Config.lb (working copy) @@ -0,0 +1,213 @@ +## +## Compute the location and size of where this firmware image +## (coreboot plus bootloader) will live in the boot rom chip. +## +if USE_FALLBACK_IMAGE + default ROM_SECTION_SIZE = FALLBACK_SIZE + default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE ) +else + default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) + default ROM_SECTION_OFFSET = 0 +end + +## +## Compute the start location and size size of +## The coreboot bootloader. +## + +default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) +default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) + +## +## Compute where this copy of coreboot will start in the boot rom +## +default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) + +## +## Compute a range of ROM that can cached to speed up coreboot, +## execution speed. +## +## XIP_ROM_SIZE must be a power of 2. +## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE +## +default XIP_ROM_SIZE=65536 +default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE ) + + +## +## Set all of the defaults for an x86 architecture +## + +arch i386 end + +## +## Build the objects we have code for in this directory. +## + +driver mainboard.o + +if HAVE_PIRQ_TABLE + object irq_tables.o +end + +if USE_DCACHE_RAM + #compile cache_as_ram.c to auto.inc + makerule ./cache_as_ram_auto.inc + depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@" + action "perl -e 's/.rodata/.rom.data/g' -pi $@" + action "perl -e 's/.text/.section .rom.text/g' -pi $@" + end +end + + +## +## Build our 16 bit and 32 bit coreboot entry code +## +mainboardinit cpu/x86/16bit/entry16.inc +mainboardinit cpu/x86/32bit/entry32.inc +ldscript /cpu/x86/16bit/entry16.lds +ldscript /cpu/x86/32bit/entry32.lds + +## +## Build our reset vector (This is where coreboot is entered) +## +if USE_FALLBACK_IMAGE + mainboardinit cpu/x86/16bit/reset16.inc + ldscript /cpu/x86/16bit/reset16.lds +else + mainboardinit cpu/x86/32bit/reset32.inc + ldscript /cpu/x86/32bit/reset32.lds +end + +### Should this be in the northbridge code? +#not in serengeti_cheetah mainboardinit arch/i386/lib/cpu_reset.inc + +## +## Include an id string (For safe flashing) +## +mainboardinit arch/i386/lib/id.inc +ldscript /arch/i386/lib/id.lds + +### +### This is the early phase of coreboot startup +### Things are delicate and we test to see if we should +### failover to another image. +### +if USE_FALLBACK_IMAGE + ldscript /arch/i386/lib/failover.lds +# mainboardinit ./failover.inc +end + +### +### O.k. We aren't just an intermediary anymore! +### + +## +## Setup RAM +## +mainboardinit cpu/x86/fpu/enable_fpu.inc + +if USE_DCACHE_RAM + mainboardinit cpu/amd/model_lx/cache_as_ram.inc + mainboardinit ./cache_as_ram_auto.inc +end + +## +## Include the secondary Configuration files +## +dir /pc80 +config chip.h +# see also SMC_CONFIG in cache_as_ram_auto.c +register "sio_gp1x_config" = "0x01" # bit0 turns off Live LED, bit1 switches Com1 to RS485, bit2 same for Com2 + +chip northbridge/amd/lx + device pci_domain 0 on + device pci 1.0 on end # Northbridge + device pci 1.1 on end # Graphics + device pci 1.2 on end # AES + chip southbridge/amd/cs5536 + # IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK + # SIRQ Mode = Active(Quiet) mode. Save power.... + # Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse, UARTs, etc IRQs. OK + register "lpc_serirq_enable" = "0x000012DA" # 00010010 11011010 + register "lpc_serirq_polarity" = "0x0000ED25" # inverse of above + register "lpc_serirq_mode" = "1" + register "enable_gpio_int_route" = "0x0D0C0700" + register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash + register "enable_USBP4_device" = "0" # 0: host, 1:device + register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381) + register "com1_enable" = "0" + register "com1_address" = "0x3E8" + register "com1_irq" = "6" + register "com2_enable" = "0" + register "com2_address" = "0x2E8" + register "com2_irq" = "6" + register "unwanted_vpci[0]" = "0x80007B00" # Audio: 1<<31 + Device 0x0F<<11 + Function 3<<8 + register "unwanted_vpci[1]" = "0" # End of list has a zero + device pci 8.0 on end # Slot4 + device pci 9.0 on end # Slot3 + device pci a.0 on end # Slot2 + device pci b.0 on end # Slot1 + device pci c.0 on end # IT8888 + device pci e.0 on end # Ethernet + device pci f.0 on # ISA Bridge + chip superio/ite/it8712f + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.2 on # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.3 on # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.4 on # EC + io 0x60 = 0x290 + io 0x62 = 0x230 + irq 0x70 = 9 + end + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + device pnp 2e.6 on # Mouse + irq 0x70 = 12 + end + device pnp 2e.7 on # GPIO + io 0x62 = 0x1220 + io 0x64 = 0x1200 + end + device pnp 2e.8 off # MIDI + io 0x60 = 0x300 + irq 0x70 = 9 + end + device pnp 2e.9 off # GAME + io 0x60 = 0x220 + end + device pnp 2e.a off end # CIR + end + end + device pci f.2 on end # IDE Controller + device pci f.3 off end # Audio + device pci f.4 on end # OHCI + device pci f.5 on end # EHCI + end + end + # APIC cluster is late CPU init. + device apic_cluster 0 on + chip cpu/amd/model_lx + device apic 0 on end + end + end +end + Index: src/mainboard/lippert/spacerunner-lx/irq_tables.c =================================================================== --- src/mainboard/lippert/spacerunner-lx/irq_tables.c (revision 0) +++ src/mainboard/lippert/spacerunner-lx/irq_tables.c (working copy) @@ -0,0 +1,59 @@ +/* + * (C)2008 LiPPERT Embedded Computers GmbH, released under the GNU GPLv2 + * + * Based on irq_tables.c from AMD's DB800 mainboard. + */ + +#include <arch/pirq_routing.h> +#include <console/console.h> +#include <arch/io.h> +#include <arch/pirq_routing.h> +#include "../../../southbridge/amd/cs5536/cs5536.h" + +/* Platform IRQs */ +#define PIRQA 10 +#define PIRQB 11 +#define PIRQC 5 +#define PIRQD 15 + +/* Map */ +#define M_PIRQA (1 << PIRQA) /* Bitmap of supported IRQs */ +#define M_PIRQB (1 << PIRQB) /* Bitmap of supported IRQs */ +#define M_PIRQC (1 << PIRQC) /* Bitmap of supported IRQs */ +#define M_PIRQD (1 << PIRQD) /* Bitmap of supported IRQs */ + +/* Link */ +#define L_PIRQA 1 /* Means Slot INTx# Connects To Chipset INTA# */ +#define L_PIRQB 2 /* Means Slot INTx# Connects To Chipset INTB# */ +#define L_PIRQC 3 /* Means Slot INTx# Connects To Chipset INTC# */ +#define L_PIRQD 4 /* Means Slot INTx# Connects To Chipset INTD# */ + +const struct irq_routing_table intel_irq_routing_table = { + PIRQ_SIGNATURE, /* u32 signature */ + PIRQ_VERSION, /* u16 version */ + 32 + 16 * IRQ_SLOT_COUNT, /* there can be total 7 devices on the bus */ + 0x00, /* Where the interrupt router lies (bus) */ + (0x0F << 3) | 0x0, /* Where the interrupt router lies (dev) */ + 0x00, /* IRQs devoted exclusively to PCI usage */ + 0x100B, /* Vendor */ + 0x002B, /* Device */ + 0, /* Crap (miniport) */ + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* u8 rfu[11] */ + 0xE0, /* u8 checksum , this has to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ + { + /* If you change the number of entries, change the IRQ_SLOT_COUNT above! */ + /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* cpu */ + {0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0}, /* chipset */ + {0x00, (0x0E << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* ethernet */ + {0x00, (0x0B << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x1, 0x0}, /* slot1 */ + {0x00, (0x0A << 3) | 0x0, {{L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}}, 0x2, 0x0}, /* slot2 */ + {0x00, (0x09 << 3) | 0x0, {{L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}}, 0x3, 0x0}, /* slot3 */ + {0x00, (0x08 << 3) | 0x0, {{L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}}, 0x4, 0x0}, /* slot4 */ + } +}; + +unsigned long write_pirq_routing_table(unsigned long addr) +{ + return copy_pirq_routing_table(addr); +} Index: src/mainboard/lippert/spacerunner-lx/mainboard.c =================================================================== --- src/mainboard/lippert/spacerunner-lx/mainboard.c (revision 0) +++ src/mainboard/lippert/spacerunner-lx/mainboard.c (working copy) @@ -0,0 +1,61 @@ +/* + * (C)2008 LiPPERT Embedded Computers GmbH, released under the GNU GPLv2 + * + * Based on mainboard.c from AMD's DB800 mainboard. + */ + +#include <stdlib.h> +#include <console/console.h> +#include <device/device.h> +#include <arch/io.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include "chip.h" + +static const unsigned short ec_init_table[] = { // hi=data, lo=index + 0x1900, // enable monitoring + 0x3050, // VIN4,5 enabled + 0x0351, // TMPIN1,2 diode mode, TMPIN3 off + 0x805C, // unlock zero adjust + 0x7056, 0x3C57, // zero adjust TMPIN1,2 + 0x005C, // lock zero adjust + 0xD014 // also set FAN_CTL polarity to Active High +}; + +static void init(struct device *dev) +{ + struct mainboard_lippert_spacerunner_lx_config *mb = dev->chip_info; + unsigned int gpio_base, i; + printk_debug("LiPPERT SpaceRunner-LX ENTER %s\n", __FUNCTION__); + + /* Init CS5536 GPIOs */ + gpio_base = pci_read_config32(dev_find_device(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, 0), + PCI_BASE_ADDRESS_1) - 1; + outl(0x00000040, gpio_base + 0x00); // GPIO6 value 1 - LAN_PD# + outl(0x00000040, gpio_base + 0x04); // GPIO6 output 1 - LAN_PD# + outl(0x04000000, gpio_base + 0x18); // GPIO10 pull up 0 - THRM_ALRM# + outl(0x00000400, gpio_base + 0x34); // GPIO10 in aux1 1 - THRM_ALRM# + outl(0x00000400, gpio_base + 0x20); // GPIO10 input 1 - THRM_ALRM# + outl(0x00000800, gpio_base + 0x94); // GPIO27 out aux2 1 - 32kHz + outl(0x00000800, gpio_base + 0x84); // GPIO27 output 1 - 32kHz + outl(0x08000000, gpio_base + 0x98); // GPIO27 pull up 0 - 32kHz + + /* Init Environment Controller */ + for (i=0; i<ARRAY_SIZE(ec_init_table); i++) { + unsigned short val = ec_init_table[i]; + outb((unsigned char)val, 0x0295); outb(val>>8, 0x0296); + } + + outb(mb->sio_gp1x_config, 0x1220); // Simple-I/O GP17-10 + printk_debug("LiPPERT SpaceRunner-LX EXIT %s\n", __FUNCTION__); +} + +static void enable_dev(struct device *dev) +{ + dev->ops->init = init; +} + +struct chip_operations mainboard_lippert_spacerunner_lx_ops = { + CHIP_NAME("LiPPERT SpaceRunner-LX Mainboard") + .enable_dev = enable_dev, +}; Index: src/mainboard/lippert/spacerunner-lx/Options.lb =================================================================== --- src/mainboard/lippert/spacerunner-lx/Options.lb (revision 0) +++ src/mainboard/lippert/spacerunner-lx/Options.lb (working copy) @@ -0,0 +1,190 @@ +uses HAVE_MP_TABLE +uses HAVE_PIRQ_TABLE +uses USE_FALLBACK_IMAGE +uses HAVE_FALLBACK_BOOT +uses HAVE_HARD_RESET +uses HAVE_OPTION_TABLE +uses USE_OPTION_TABLE +uses CONFIG_ROM_PAYLOAD +uses CONFIG_IDE +uses CONFIG_FS_PAYLOAD +uses CONFIG_FS_EXT2 +uses AUTOBOOT_DELAY +uses AUTOBOOT_CMDLINE +uses IRQ_SLOT_COUNT +uses MAINBOARD +uses MAINBOARD_VENDOR +uses MAINBOARD_PART_NUMBER +uses COREBOOT_EXTRA_VERSION +uses ARCH +uses FALLBACK_SIZE +uses STACK_SIZE +uses HEAP_SIZE +uses ROM_SIZE +uses ROM_SECTION_SIZE +uses ROM_IMAGE_SIZE +uses ROM_SECTION_SIZE +uses ROM_SECTION_OFFSET +uses CONFIG_ROM_PAYLOAD_START +uses CONFIG_COMPRESS +uses CONFIG_COMPRESSED_PAYLOAD_NRV2B +uses CONFIG_COMPRESSED_PAYLOAD_LZMA +uses CONFIG_PRECOMPRESSED_PAYLOAD +uses PAYLOAD_SIZE +uses _ROMBASE +uses _RAMBASE +uses XIP_ROM_SIZE +uses XIP_ROM_BASE +uses HAVE_MP_TABLE +uses CROSS_COMPILE +uses CC +uses HOSTCC +uses OBJCOPY +uses DEBUG +uses DEFAULT_CONSOLE_LOGLEVEL +uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_CONSOLE_SERIAL8250 +uses TTYS0_BAUD +uses TTYS0_BASE +uses TTYS0_LCS +uses CONFIG_UDELAY_TSC +uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 +uses CONFIG_CONSOLE_VGA +uses CONFIG_PCI_ROM_RUN +uses CONFIG_VIDEO_MB +uses USE_DCACHE_RAM +uses DCACHE_RAM_BASE +uses DCACHE_RAM_SIZE +uses PIRQ_ROUTE + +## ROM_SIZE is the size of boot ROM that this board will use. +default ROM_SIZE = 512*1024 + +### +### Build options +### +default CONFIG_CONSOLE_VGA=0 +default CONFIG_VIDEO_MB=8 +default CONFIG_PCI_ROM_RUN=0 + +## +## Build code for the fallback boot +## +default HAVE_FALLBACK_BOOT=1 + +## +## no MP table +## +default HAVE_MP_TABLE=0 + +## +## Build code to reset the motherboard from coreboot +## +default HAVE_HARD_RESET=0 + +## Delay timer options +## +default CONFIG_UDELAY_TSC=1 +default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1 + +## +## Build code to export a programmable irq routing table +## +default HAVE_PIRQ_TABLE=1 +default IRQ_SLOT_COUNT=7 +default PIRQ_ROUTE=1 + +## +## Build code to export a CMOS option table +## +default HAVE_OPTION_TABLE=0 + +### +### coreboot layout values +### + +## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default ROM_IMAGE_SIZE = 65536 +default FALLBACK_SIZE = 131072 + +## +## enable CACHE_AS_RAM specifics +## +default USE_DCACHE_RAM=1 +default DCACHE_RAM_BASE=0xc8000 +default DCACHE_RAM_SIZE=0x08000 + +## +## Use a small 8K stack +## +default STACK_SIZE=0x2000 + +## +## Use a small 16K heap +## +default HEAP_SIZE=0x4000 + +## +## Only use the option table in a normal image +## +#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE +default USE_OPTION_TABLE = 0 + +default _RAMBASE = 0x00004000 + +default CONFIG_ROM_PAYLOAD = 1 + +## +## The default compiler +## +default CROSS_COMPILE="" +default CC="$(CROSS_COMPILE)gcc -m32" +default HOSTCC="gcc" + +## +## The Serial Console +## + +# To Enable the Serial Console +default CONFIG_CONSOLE_SERIAL8250=1 + +## Select the serial console baud rate +default TTYS0_BAUD=115200 +#default TTYS0_BAUD=57600 +#default TTYS0_BAUD=38400 +#default TTYS0_BAUD=19200 +#default TTYS0_BAUD=9600 +#default TTYS0_BAUD=4800 +#default TTYS0_BAUD=2400 +#default TTYS0_BAUD=1200 + +# Select the serial console base port +default TTYS0_BASE=0x3f8 + +# Select the serial protocol +# This defaults to 8 data bits, 1 stop bit, and no parity +default TTYS0_LCS=0x3 + +# Compile extra debugging code +default DEBUG=1 + +## +### Select the coreboot loglevel +## +## EMERG 1 system is unusable +## ALERT 2 action must be taken immediately +## CRIT 3 critical conditions +## ERR 4 error conditions +## WARNING 5 warning conditions +## NOTICE 6 normal but significant condition +## INFO 7 informational +## DEBUG 8 debug-level messages +## SPEW 9 Way too many details + +## Request this level of debugging output +default DEFAULT_CONSOLE_LOGLEVEL=8 +## At a maximum only compile in this level of debugging +default MAXIMUM_CONSOLE_LOGLEVEL=8 + +end + Index: targets/lippert/spacerunner-lx/Config.lb =================================================================== --- targets/lippert/spacerunner-lx/Config.lb (revision 0) +++ targets/lippert/spacerunner-lx/Config.lb (working copy) @@ -0,0 +1,45 @@ +## +## (C)2008 LiPPERT Embedded Computers GmbH, released under the GNU GPLv2 +## + +# Config file for the LiPPERT Cool SpaceRunner-LX, --JR 10/2008 +# based on Config.lb for the AMD Geode LX/5536 DB800 platform. + +target spacerunner-lx +mainboard lippert/spacerunner-lx + +# HACK to get the right TSC support. +option CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1 + +option CONFIG_COMPRESSED_PAYLOAD_NRV2B=0 +option CONFIG_COMPRESSED_PAYLOAD_LZMA=0 + +## Load payload (e.g. Linux) from IDE +#option CONFIG_ROM_PAYLOAD=0 +#option CONFIG_IDE=1 +#option CONFIG_FS_PAYLOAD=1 +#option CONFIG_FS_EXT2=1 +#option AUTOBOOT_DELAY=0 +#option AUTOBOOT_CMDLINE="hda1:/payload.elf" + +# Leave 36k for VSA. Board is equipped with a 1 MB SPI flash, however, due to +# limitations of the IT8712F SIO, only the top 512 KB are directly mapped. +option ROM_SIZE=512*1024-36*1024 +option FALLBACK_SIZE=ROM_SIZE + +#option DEFAULT_CONSOLE_LOGLEVEL = 4 +#option MAXIMUM_CONSOLE_LOGLEVEL = 4 + +# Saves space on ROM_IMAGE_SIZE, but decompression costs a second on boot +option CONFIG_COMPRESS = 1 + +romimage "fallback" + option USE_FALLBACK_IMAGE=1 + option ROM_IMAGE_SIZE=64*1024 + option COREBOOT_EXTRA_VERSION=".0Fallback" + payload ../payload.elf + # If getting payload from IDE + #payload /dev/null +end + +buildrom ./coreboot.rom ROM_SIZE "fallback"

11 years

5
11
0 0

[PATCH] v2: ICH7: Drop/fix some ICH7 register #defines

by Uwe Hermann

This patch will fail to compile without my other patch to drop/disable the non-working enable_hpet() function in ICH7. Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org

11 years

2
2
0 0

[PATCH] v2: ICH7: Drop non-working enable_hpet() for now

by Uwe Hermann

Please correct me if I'm wrong (I don't have NDA'd Intel datasheets, I can only check the public ones), but I think the enable_hpet() in the ICH7 code will not work for ICH7. It should work for ICH4/ICH5 or so, but ICH7 requires a completely different init involving RCBA, offset 0x3404, it seems. Thus, drop the non-working code, add a TODO until somebody writes the proper code for ICH7. Maybe I'll do that if nobody beats me to it, but it may take a while. Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org

11 years

2
2
0 0

flashrom on EP80759 + Spansion S25FL016A

by Stephan GUILLOUX

Hello Carldani, You were right about the flash : this board is equipped with a ST flash and not with a Spansion... Now, I check the modifications we made yesterday night in flashrom. With them, flashrom is now working fine : I can read, I can write the flash content. Erase not tested. flashrom indicates that the ST M25P16 has a status 'untested' for operations PROBE READ ERASE WRITE. Tests and relevant traces are attached. If you need anything else, please, let me know. Best regards, and thx for help. Stéphan. PROBE works better with the 2nd fix (ich7 instead of ich_dc) READ/WRITE looks to work fine ERASE not tested Some modifications I added in flashrom code to have this work : 1) ST M25P16 works better with ich7 on EP80579 2) Initialize tmp to avoid garbage in the variable. ---------------------------------------------------------------------------------- diff -c flashrom-V2-3695/chipset_enable.c flashrom/chipset_enable.c *** flashrom-V2-3695/chipset_enable.c Sun Oct 26 19:40:42 2008 --- flashrom/chipset_enable.c Tue Oct 28 14:47:28 2008 *************** *** 765,771 **** {0x8086, 0x25a1, "Intel 6300ESB", enable_flash_ich_4e}, {0x8086, 0x2640, "Intel ICH6/ICH6R", enable_flash_ich_dc}, {0x8086, 0x2641, "Intel ICH6-M", enable_flash_ich_dc}, ! {0x8086, 0x5031, "Intel EP80579", enable_flash_ich_dc}, {0x8086, 0x27b0, "Intel ICH7DH", enable_flash_ich7}, {0x8086, 0x27b8, "Intel ICH7/ICH7R", enable_flash_ich7}, {0x8086, 0x27b9, "Intel ICH7M", enable_flash_ich7}, --- 765,771 ---- {0x8086, 0x25a1, "Intel 6300ESB", enable_flash_ich_4e}, {0x8086, 0x2640, "Intel ICH6/ICH6R", enable_flash_ich_dc}, {0x8086, 0x2641, "Intel ICH6-M", enable_flash_ich_dc}, ! {0x8086, 0x5031, "Intel EP80579", enable_flash_ich7}, {0x8086, 0x27b0, "Intel ICH7DH", enable_flash_ich7}, {0x8086, 0x27b8, "Intel ICH7/ICH7R", enable_flash_ich7}, {0x8086, 0x27b9, "Intel ICH7M", enable_flash_ich7}, ---------------------------------------------------------------------------------- diff -c flashrom-V2-3695/board_enable.c flashrom/board_enable.c *** flashrom-V2-3695/board_enable.c Sat Oct 18 23:14:13 2008 --- flashrom/board_enable.c Mon Oct 27 19:02:12 2008 *************** *** 250,256 **** */ static int board_asus_p5a(const char *name) { ! uint8_t tmp; int i; #define ASUSP5A_LOOP 5000 --- 250,256 ---- */ static int board_asus_p5a(const char *name) { ! uint8_t tmp = 0; int i; #define ASUSP5A_LOOP 5000 ---------------------------------------------------------------------------------- [root@lion04 root]# flashrom --read flash_content.rom Calibrating delay loop... OK. No coreboot table found. Found chipset "Intel EP80579", enabling flash write... OK. Found chip "ST M25P16" (2048 KB) at physical address 0xffe00000. === This flash part has status UNTESTED for operations: PROBE READ ERASE WRITE Please email a report to flashrom(a)coreboot.org if any of the above operations work correctly for you with this flash part. Please include the full output from the program, including chipset found. Thank you for your help! === Reading Flash...done [root@lion04 root]# ---------------------------------------------------------------------------------- [root@lion04 root]# flashrom --write 0ABPT907.ROM Calibrating delay loop... OK. No coreboot table found. Found chipset "Intel EP80579", enabling flash write... OK. Found chip "ST M25P16" (2048 KB) at physical address 0xffe00000. === This flash part has status UNTESTED for operations: PROBE READ ERASE WRITE Please email a report to flashrom(a)coreboot.org if any of the above operations work correctly for you with this flash part. Please include the full output from the program, including chipset found. Thank you for your help! === Flash image seems to be a legacy BIOS. Disabling checks. Programming page: DONE BLOCK 0x0 DONE BLOCK 0x10000 DONE BLOCK 0x20000 DONE BLOCK 0x30000 DONE BLOCK 0x40000 DONE BLOCK 0x50000 DONE BLOCK 0x60000 DONE BLOCK 0x70000 DONE BLOCK 0x80000 DONE BLOCK 0x90000 DONE BLOCK 0xa0000 DONE BLOCK 0xb0000 DONE BLOCK 0xc0000 DONE BLOCK 0xd0000 DONE BLOCK 0xe0000 DONE BLOCK 0xf0000 DONE BLOCK 0x100000 DONE BLOCK 0x110000 DONE BLOCK 0x120000 DONE BLOCK 0x130000 DONE BLOCK 0x140000 DONE BLOCK 0x150000 DONE BLOCK 0x160000 DONE BLOCK 0x170000 DONE BLOCK 0x180000 DONE BLOCK 0x190000 DONE BLOCK 0x1a0000 DONE BLOCK 0x1b0000 DONE BLOCK 0x1c0000 DONE BLOCK 0x1d0000 DONE BLOCK 0x1e0000 DONE BLOCK 0x1f0000 [root@lion04 root]# ---------------------------------------------------------------------------------- [root@lion04 BIOS_AMI]# flashrom --verify 0ABPT907.ROM Calibrating delay loop... OK. No coreboot table found. Found chipset "Intel EP80579", enabling flash write... OK. Found chip "ST M25P16" (2048 KB) at physical address 0xffe00000. === This flash part has status UNTESTED for operations: PROBE READ ERASE WRITE Please email a report to flashrom(a)coreboot.org if any of the above operations work correctly for you with this flash part. Please include the full output from the program, including chipset found. Thank you for your help! === Flash image seems to be a legacy BIOS. Disabling checks. Verifying flash... VERIFIED. [root@lion04 root]# ---------------------------------------------------------------------------------- [root@lion04 BIOS_AMI]# flashrom --verify flash_content.rom Calibrating delay loop... OK. No coreboot table found. Found chipset "Intel EP80579", enabling flash write... OK. Found chip "ST M25P16" (2048 KB) at physical address 0xffe00000. === This flash part has status UNTESTED for operations: PROBE READ ERASE WRITE Please email a report to flashrom(a)coreboot.org if any of the above operations work correctly for you with this flash part. Please include the full output from the program, including chipset found. Thank you for your help! === Flash image seems to be a legacy BIOS. Disabling checks. Verifying flash... FAILED! Expected=0x4e, Read=0xff [root@lion04 root]# ---------------------------------------------------------------------------------- [root@lion04 BIOS_AMI]# flashrom --erase Calibrating delay loop... OK. No coreboot table found. Found chipset "Intel EP80579", enabling flash write... OK. Found chip "ST M25P16" (2048 KB) at physical address 0xffe00000. === This flash part has status UNTESTED for operations: PROBE READ ERASE WRITE Please email a report to flashrom(a)coreboot.org if any of the above operations work correctly for you with this flash part. Please include the full output from the program, including chipset found. Thank you for your help! === Erasing flash chip. [root@lion04 root]# ---------------------------------------------------------------------------------- [root@lion04 BIOS_AMI]# flashrom --read zero.rom Calibrating delay loop... OK. No coreboot table found. Found chipset "Intel EP80579", enabling flash write... OK. Found chip "ST M25P16" (2048 KB) at physical address 0xffe00000. === This flash part has status UNTESTED for operations: PROBE READ ERASE WRITE Please email a report to flashrom(a)coreboot.org if any of the above operations work correctly for you with this flash part. Please include the full output from the program, including chipset found. Thank you for your help! === Reading Flash...done [root@lion04 BIOS_AMI]# hexdump zero.rom 0000000 ffff ffff ffff ffff ffff ffff ffff ffff * 0200000 [root@lion04 root]#

11 years

2
1
0 0

filo circular console list

by Arne Georg Gleditsch

Hi, The latest svn revisions of filo and libpayload (r83 and r3708) conspire to add the video console driver twice to the console_out list. This causes the list to become circular, with the effect that device_putchar spins in a loop printing the first character it is given. ("F".) Trivial patch and .config appended. (One might perhaps also consider making device_putchar or console_add_* more robust in the face of this kind of error, but I settled for this.) -- Arne. # # Automatically generated make config: don't edit # FILO version: 0.6.0rc1 # Thu Oct 30 12:01:16 2008 # CONFIG_TARGET_I386=y # CONFIG_REVIEW is not set # # Interface Options # CONFIG_USE_GRUB=y CONFIG_PROMPT="filo" CONFIG_MENULST_FILE="hde1:/grub/menu.lst" CONFIG_MENULST_TIMEOUT=3 CONFIG_USE_MD5_PASSWORDS=y # # Drivers # CONFIG_IDE_DISK=y CONFIG_IDE_DISK_POLL_DELAY=0 # CONFIG_SLOW_SATA is not set # CONFIG_PCMCIA_CF is not set CONFIG_USB_NEW_DISK=y # CONFIG_USB_DISK is not set # CONFIG_FLASH_DISK is not set CONFIG_SUPPORT_PCI=y # CONFIG_PCI_BRUTE_SCAN is not set # CONFIG_SUPPORT_SOUND is not set # # Filesystems # CONFIG_FSYS_EXT2FS=y CONFIG_FSYS_FAT=y # CONFIG_FSYS_JFS is not set # CONFIG_FSYS_MINIX is not set # CONFIG_FSYS_REISERFS is not set # CONFIG_FSYS_XFS is not set CONFIG_FSYS_ISO9660=y CONFIG_ELTORITO=y # CONFIG_FSYS_CRAMFS is not set # CONFIG_FSYS_SQUASHFS is not set # # Loaders # CONFIG_LINUX_LOADER=y # CONFIG_WINCE_LOADER is not set # CONFIG_ARTEC_BOOT is not set # # Debugging & Experimental # # CONFIG_EXPERIMENTAL is not set # CONFIG_DEBUG_ALL is not set # CONFIG_DEBUG_ELFBOOT is not set # CONFIG_DEBUG_ELFNOTE is not set # CONFIG_DEBUG_SEGMENT is not set # CONFIG_DEBUG_SYS_INFO is not set # CONFIG_DEBUG_BLOCKDEV is not set # CONFIG_DEBUG_VFS is not set # CONFIG_DEBUG_FSYS_EXT2FS is not set # CONFIG_DEBUG_PCI is not set # CONFIG_DEBUG_LINUXLOAD is not set # CONFIG_DEBUG_IDE is not set # CONFIG_DEBUG_ELTORITO is not set CONFIG_DEVELOPER_TOOLS=y

11 years

3
4
0 0

[PATCH] CN700/VT8237R stage2

by Corey Osgood

Attached patches for cn700, vt8237(r/s), and the mainboard, Jetway J7F2, along with a boot log. Currently, we're stuck in a reboot loop and I have no idea why, seems to be related to CAR disabling (this wasn't happening when disable_car was a noop). Carl-Daniel, any ideas? -Corey

11 years

3
22
0 0

what are ELF boot notes?

by Robert Millan

Hi, Does anyone know what "ELF boot notes" are? I've seen this reference in coreboot-v2/src/arch/i386/boot/boot.c. There's a struct named elf_boot_notes whose pointer is passed to the payload via %ebx, and a magic signature in %eax as well. Which is very similar to Multiboot (possibly inspired by it?), as it uses the same registers and is therefore impossible to support both things at the same time. This interface is not in v3. Does this mean it's no longer being used? If it's still in use with v2, I could add a build option that selects between them. -- Robert Millan The DRM opt-in fallacy: "Your data belongs to us. We will decide when (and how) you may access your data; but nobody's threatening your freedom: we still allow you to remove your data and not access it at all."

11 years

3
6
0 0

HT revision 1.02 in K8

by Carl-Daniel Hailfinger

Hi, I'm getting the following message from lspci on my K8 machine: 00:18.0 Host bridge [0600]: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] HyperTransport Technology Configuration [1022:1100] Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Capabilities: [80] HyperTransport: Host or Secondary Interface !!! Possibly incomplete decoding for revision 1.02 Command: WarmRst+ DblEnd- Link Control: CFlE- CST- CFE- <LkFail- Init+ EOC- TXO- <CRCErr=0 Link Config: MLWI=16bit MLWO=16bit LWI=16bit LWO=16bit Revision ID: 1.02 Kernel modules: ipmi_si 00: 22 10 00 11 00 00 10 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 80 00 00 00 00 00 00 00 00 00 00 00 40: 01 01 01 00 01 01 01 00 01 01 01 00 01 01 01 00 50: 01 01 01 00 01 01 01 00 01 01 01 00 01 01 01 00 60: 00 00 00 00 e4 00 00 00 0f cc 00 0f 0c 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 08 00 01 21 20 00 11 11 22 05 35 80 02 00 00 00 90: 69 01 61 01 00 00 ff 00 07 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Note the warning about "Possibly incomplete decoding" which stems from the fact that the processor mentions HT revision 1.02 which is the last non-public revision. Every revision from 1.03 and beyond seems to be publically available. Now the big question is: Can we decode HT 1.02 like HT 1.03 or have there been fundamental changes in between? I'd like to create a patch for PCIutils (lspci) so we can have full info without a warning message. Regards, Carl-Daniel -- http://www.hailfinger.org/

11 years

4
6
0 0

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coreboot October 2008