coreboot October 2008

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[PATCH] v3: Disable VIA C7 CAR
by Carl-Daniel Hailfinger 23 Oct '08

23 Oct '08

This is the patch which will let VIA C7 continue in v3 during/after a CAR disabling operation. Untested, but it should work. Please note that the code is incomplete, but that should at least not affect stage2. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: corebootv3-via_car/include/arch/x86/via_c7.h =================================================================== --- corebootv3-via_car/include/arch/x86/via_c7.h (Revision 941) +++ corebootv3-via_car/include/arch/x86/via_c7.h (Arbeitskopie) @@ -22,6 +22,10 @@ #define CPU_VIA_C7_H +#define SYSCFG_MSR 0xC0010010 +#define SYSCFG_MSR_MtrrFixDramModEn (1 << 19) +#define SYSCFG_MSR_MtrrFixDramEn (1 << 18) + #ifndef __ASSEMBLER__ /* This is new. Index: corebootv3-via_car/arch/x86/via/stage1.c =================================================================== --- corebootv3-via_car/arch/x86/via/stage1.c (Revision 0) +++ corebootv3-via_car/arch/x86/via/stage1.c (Revision 0) @@ -0,0 +1,105 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Carl-Daniel Hailfinger + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <types.h> +#include <lib.h> +#include <console.h> +#include <msr.h> +#include <macros.h> +#include <cpu.h> +#include <stage1.h> +#include <globalvars.h> +#include <string.h> +#include <mtrr.h> +#include <via_c7.h> + +#ifdef NO_IDEA_WHETHER_THIS_IS_RELEVANT_ON_C7 +/** + * Set the MTRR for initial ram access. + * be warned, this will be used by core other than core 0/node 0 or core0/node0 when cpu_reset. + * This warning has some significance I don't yet understand. + */ +void set_init_ram_access(void) +{ + set_var_mtrr(0, 0x00000000, CONFIG_CBMEMK << 10, MTRR_TYPE_WRBACK); +} +#endif + +#define __stringify_1(x) #x +#define __stringify(x) __stringify_1(x) + +/** + * Disable Cache As RAM (CAR) after memory is setup. + */ +void disable_car(void) +{ + /* Determine new global variable location. Stack organization from top + * Top 4 bytes are reserved + * Pointer to global variables + * Global variables + * + * Align the result to 8 bytes + */ + const struct global_vars *newlocation = (struct global_vars *)((RAM_STACK_BASE - sizeof(struct global_vars *) - sizeof(struct global_vars)) & ~0x7); + /* Copy global variables to new location. */ + memcpy(newlocation, global_vars(), sizeof(struct global_vars)); + /* Set the new global variable pointer. */ + *(struct global_vars **)(RAM_STACK_BASE - sizeof(struct global_vars *)) = newlocation; + + __asm__ __volatile__( + /* We don't need cache as ram for now on */ + /* disable cache */ + " movl %%cr0, %%eax \n" + " orl $(0x1<<30),%%eax \n" + " movl %%eax, %%cr0 \n" + + /* disable fixed mtrr from now on, it will be enabled by coreboot_ram again*/ + " movl %[_SYSCFG_MSR], %%ecx \n" + " rdmsr \n" + " andl %[_SYSCFG_MSR_newval], %%eax\n" +// " andl $(~(SYSCFG_MSR_MtrrFixDramModEn | SYSCFG_MSR_MtrrFixDramEn)), %%eax\n" + /* clear sth */ + " wrmsr \n" +#warning Must clear MTRR 0x200 and 0x201 + + /* Set the default memory type and disable fixed and enable variable MTRRs */ + " movl %[_MTRRdefType_MSR], %%ecx \n" + " xorl %%edx, %%edx \n" + /* Enable Variable and Disable Fixed MTRRs */ + " movl $0x00000800, %%eax \n" + " wrmsr \n" + + /* enable cache */ + " movl %%cr0, %%eax \n" + " andl $0x9fffffff,%%eax \n" + " movl %%eax, %%cr0 \n" + + " wbinvd \n" + + " movl %[newesp], %%esp \n" + " call stage1_phase3 \n" + :: [newesp] "i" (newlocation), + [_SYSCFG_MSR] "i" (SYSCFG_MSR), + [_SYSCFG_MSR_newval] "i" (~(SYSCFG_MSR_MtrrFixDramModEn | SYSCFG_MSR_MtrrFixDramEn)), + [_SYSCFG_MSR_MtrrFixDramModEn] "i" (SYSCFG_MSR_MtrrFixDramModEn), + [_SYSCFG_MSR_MtrrFixDramEn] "i" (SYSCFG_MSR_MtrrFixDramEn), + [_MTRRdefType_MSR] "i" (MTRRdefType_MSR) + : "memory"); +} Index: corebootv3-via_car/arch/x86/Makefile =================================================================== --- corebootv3-via_car/arch/x86/Makefile (Revision 941) +++ corebootv3-via_car/arch/x86/Makefile (Arbeitskopie) @@ -125,6 +125,7 @@ else ifeq ($(CONFIG_CPU_VIA_C7),y) STAGE0_CAR_OBJ = via/stage0.o + STAGE0_ARCH_X86_SRC += via/stage1.c endif endif endif -- http://www.hailfinger.org/

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v3 starter project
by Carl-Daniel Hailfinger 23 Oct '08

23 Oct '08

Hi, some of you are looking for an easy way to get involved with coreboot v3. Maybe the easiest task would be a refactoring of northbridge/amd/geodelx/raminit.c. That code has lots of duplications all over the map due to the fact the code was originally written for ROMCC efficiency. You may save more than 30% code size and probably quite a bit of execution time by killing duplicates and moving the "invalid SPD" checks to some generic function. There's simply no need to check and calculate the same stuff over and over again. Regards, Carl-Daniel -- http://www.hailfinger.org/

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[PATCH] v3: First parts of EPIA-CN support
by Carl-Daniel Hailfinger 23 Oct '08

23 Oct '08

First parts of VIA EPIA-CN support. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: mainboard/via/Kconfig =================================================================== --- mainboard/via/Kconfig (Revision 0) +++ mainboard/via/Kconfig (Revision 0) @@ -0,0 +1,43 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2008 Carl-Daniel Hailfinger +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +choice + prompt "Mainboard model" + depends on VENDOR_VIA + +config BOARD_VIA_EPIA_CN + bool "EPIA-CN" + select ARCH_X86 + select CPU_VIA_C7 + select OPTION_TABLE + select NORTHBRIDGE_VIA_CN700 + select SOUTHBRIDGE_VIA_VT8237 + select SUPERIO_VIA_VT1211 + select PIRQ_TABLE + help + VIA EPIA-CN + +endchoice + +config MAINBOARD_DIR + string + default via/epia-cn + depends BOARD_VIA_EPIA_CN + Index: mainboard/via/epia-cn/Makefile =================================================================== --- mainboard/via/epia-cn/Makefile (Revision 0) +++ mainboard/via/epia-cn/Makefile (Revision 0) @@ -0,0 +1,32 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2008 Carl-Daniel Hailfinger +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +STAGE0_MAINBOARD_SRC := $(src)/mainboard/$(MAINBOARDDIR)/stage1.c + +INITRAM_SRC = $(src)/mainboard/$(MAINBOARDDIR)/initram.c \ + $(src)/northbridge/via/cn700/initram.c \ + $(src)/lib/ramtest.c + +STAGE2_MAINBOARD_SRC = + +$(obj)/coreboot.vpd: + $(Q)printf " BUILD DUMMY VPD\n" + $(Q)dd if=/dev/zero of=$(obj)/coreboot.vpd bs=256 count=1 $(SILENT) + Index: mainboard/Kconfig =================================================================== --- mainboard/Kconfig (Revision 941) +++ mainboard/Kconfig (Arbeitskopie) @@ -62,6 +62,11 @@ help Select this option for PC Engines systems. +config VENDOR_VIA + bool "VIA" + help + Select this option for VIA systems. + endchoice source "mainboard/adl/Kconfig" @@ -71,6 +76,7 @@ source "mainboard/emulation/Kconfig" source "mainboard/gigabyte/Kconfig" source "mainboard/pcengines/Kconfig" +source "mainboard/via/Kconfig" choice prompt "ROM chip size" -- http://www.hailfinger.org/

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r946 - in coreboot-v3/mainboard: . via via/epia-cn
by svn＠coreboot.org 23 Oct '08

23 Oct '08

Author: hailfinger Date: 2008-10-23 03:18:30 +0200 (Thu, 23 Oct 2008) New Revision: 946 Added: coreboot-v3/mainboard/via/ coreboot-v3/mainboard/via/Kconfig coreboot-v3/mainboard/via/epia-cn/ coreboot-v3/mainboard/via/epia-cn/Makefile Modified: coreboot-v3/mainboard/Kconfig Log: First parts of VIA EPIA-CN support. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Modified: coreboot-v3/mainboard/Kconfig =================================================================== --- coreboot-v3/mainboard/Kconfig 2008-10-23 00:28:28 UTC (rev 945) +++ coreboot-v3/mainboard/Kconfig 2008-10-23 01:18:30 UTC (rev 946) @@ -5,6 +5,7 @@ ## Copyright (C) 2006-2007 coresystems GmbH ## (Written by Stefan Reinauer <stepan(a)coresystems.de> for coresystems GmbH) ## Copyright (C) 2007 Uwe Hermann <uwe(a)hermann-uwe.de> +## Copyright (C) 2008 Carl-Daniel Hailfinger ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by @@ -62,6 +63,11 @@ help Select this option for PC Engines systems. +config VENDOR_VIA + bool "VIA" + help + Select this option for VIA systems. + endchoice source "mainboard/adl/Kconfig" @@ -71,6 +77,7 @@ source "mainboard/emulation/Kconfig" source "mainboard/gigabyte/Kconfig" source "mainboard/pcengines/Kconfig" +source "mainboard/via/Kconfig" choice prompt "ROM chip size" Added: coreboot-v3/mainboard/via/Kconfig =================================================================== --- coreboot-v3/mainboard/via/Kconfig (rev 0) +++ coreboot-v3/mainboard/via/Kconfig 2008-10-23 01:18:30 UTC (rev 946) @@ -0,0 +1,43 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2008 Carl-Daniel Hailfinger +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +choice + prompt "Mainboard model" + depends on VENDOR_VIA + +config BOARD_VIA_EPIA_CN + bool "EPIA-CN" + select ARCH_X86 + select CPU_VIA_C7 + select OPTION_TABLE + select NORTHBRIDGE_VIA_CN700 + select SOUTHBRIDGE_VIA_VT8237 + select SUPERIO_VIA_VT1211 + select PIRQ_TABLE + help + VIA EPIA-CN + +endchoice + +config MAINBOARD_DIR + string + default via/epia-cn + depends BOARD_VIA_EPIA_CN + Added: coreboot-v3/mainboard/via/epia-cn/Makefile =================================================================== --- coreboot-v3/mainboard/via/epia-cn/Makefile (rev 0) +++ coreboot-v3/mainboard/via/epia-cn/Makefile 2008-10-23 01:18:30 UTC (rev 946) @@ -0,0 +1,32 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2008 Carl-Daniel Hailfinger +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +STAGE0_MAINBOARD_SRC := $(src)/mainboard/$(MAINBOARDDIR)/stage1.c + +INITRAM_SRC = $(src)/mainboard/$(MAINBOARDDIR)/initram.c \ + $(src)/northbridge/via/cn700/initram.c \ + $(src)/lib/ramtest.c + +STAGE2_MAINBOARD_SRC = + +$(obj)/coreboot.vpd: + $(Q)printf " BUILD DUMMY VPD\n" + $(Q)dd if=/dev/zero of=$(obj)/coreboot.vpd bs=256 count=1 $(SILENT) +

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r945 - in coreboot-v3: arch/x86 arch/x86/via include/arch/x86
by svn＠coreboot.org 23 Oct '08

23 Oct '08

Author: hailfinger Date: 2008-10-23 02:28:28 +0200 (Thu, 23 Oct 2008) New Revision: 945 Added: coreboot-v3/arch/x86/via/stage1.c Modified: coreboot-v3/arch/x86/Makefile coreboot-v3/include/arch/x86/via_c7.h Log: This is the patch which will let VIA C7 continue in v3 during/after a CAR disabling operation. Untested, but it should work. Please note that the code is incomplete, but that should at least not affect stage2. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Modified: coreboot-v3/arch/x86/Makefile =================================================================== --- coreboot-v3/arch/x86/Makefile 2008-10-22 19:18:04 UTC (rev 944) +++ coreboot-v3/arch/x86/Makefile 2008-10-23 00:28:28 UTC (rev 945) @@ -125,6 +125,7 @@ else ifeq ($(CONFIG_CPU_VIA_C7),y) STAGE0_CAR_OBJ = via/stage0.o + STAGE0_ARCH_X86_SRC += via/stage1.c endif endif endif Added: coreboot-v3/arch/x86/via/stage1.c =================================================================== --- coreboot-v3/arch/x86/via/stage1.c (rev 0) +++ coreboot-v3/arch/x86/via/stage1.c 2008-10-23 00:28:28 UTC (rev 945) @@ -0,0 +1,105 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Carl-Daniel Hailfinger + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <types.h> +#include <lib.h> +#include <console.h> +#include <msr.h> +#include <macros.h> +#include <cpu.h> +#include <stage1.h> +#include <globalvars.h> +#include <string.h> +#include <mtrr.h> +#include <via_c7.h> + +#ifdef NO_IDEA_WHETHER_THIS_IS_RELEVANT_ON_C7 +/** + * Set the MTRR for initial ram access. + * be warned, this will be used by core other than core 0/node 0 or core0/node0 when cpu_reset. + * This warning has some significance I don't yet understand. + */ +void set_init_ram_access(void) +{ + set_var_mtrr(0, 0x00000000, CONFIG_CBMEMK << 10, MTRR_TYPE_WRBACK); +} +#endif + +#define __stringify_1(x) #x +#define __stringify(x) __stringify_1(x) + +/** + * Disable Cache As RAM (CAR) after memory is setup. + */ +void disable_car(void) +{ + /* Determine new global variable location. Stack organization from top + * Top 4 bytes are reserved + * Pointer to global variables + * Global variables + * + * Align the result to 8 bytes + */ + const struct global_vars *newlocation = (struct global_vars *)((RAM_STACK_BASE - sizeof(struct global_vars *) - sizeof(struct global_vars)) & ~0x7); + /* Copy global variables to new location. */ + memcpy(newlocation, global_vars(), sizeof(struct global_vars)); + /* Set the new global variable pointer. */ + *(struct global_vars **)(RAM_STACK_BASE - sizeof(struct global_vars *)) = newlocation; + + __asm__ __volatile__( + /* We don't need cache as ram for now on */ + /* disable cache */ + " movl %%cr0, %%eax \n" + " orl $(0x1<<30),%%eax \n" + " movl %%eax, %%cr0 \n" + + /* disable fixed mtrr from now on, it will be enabled by coreboot_ram again*/ + " movl %[_SYSCFG_MSR], %%ecx \n" + " rdmsr \n" + " andl %[_SYSCFG_MSR_newval], %%eax\n" +// " andl $(~(SYSCFG_MSR_MtrrFixDramModEn | SYSCFG_MSR_MtrrFixDramEn)), %%eax\n" + /* clear sth */ + " wrmsr \n" +#warning Must clear MTRR 0x200 and 0x201 + + /* Set the default memory type and disable fixed and enable variable MTRRs */ + " movl %[_MTRRdefType_MSR], %%ecx \n" + " xorl %%edx, %%edx \n" + /* Enable Variable and Disable Fixed MTRRs */ + " movl $0x00000800, %%eax \n" + " wrmsr \n" + + /* enable cache */ + " movl %%cr0, %%eax \n" + " andl $0x9fffffff,%%eax \n" + " movl %%eax, %%cr0 \n" + + " wbinvd \n" + + " movl %[newesp], %%esp \n" + " call stage1_phase3 \n" + :: [newesp] "i" (newlocation), + [_SYSCFG_MSR] "i" (SYSCFG_MSR), + [_SYSCFG_MSR_newval] "i" (~(SYSCFG_MSR_MtrrFixDramModEn | SYSCFG_MSR_MtrrFixDramEn)), + [_SYSCFG_MSR_MtrrFixDramModEn] "i" (SYSCFG_MSR_MtrrFixDramModEn), + [_SYSCFG_MSR_MtrrFixDramEn] "i" (SYSCFG_MSR_MtrrFixDramEn), + [_MTRRdefType_MSR] "i" (MTRRdefType_MSR) + : "memory"); +} Modified: coreboot-v3/include/arch/x86/via_c7.h =================================================================== --- coreboot-v3/include/arch/x86/via_c7.h 2008-10-22 19:18:04 UTC (rev 944) +++ coreboot-v3/include/arch/x86/via_c7.h 2008-10-23 00:28:28 UTC (rev 945) @@ -22,6 +22,10 @@ #define CPU_VIA_C7_H +#define SYSCFG_MSR 0xC0010010 +#define SYSCFG_MSR_MtrrFixDramModEn (1 << 19) +#define SYSCFG_MSR_MtrrFixDramEn (1 << 18) + #ifndef __ASSEMBLER__ /* This is new.

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Re: [coreboot] r83 - in trunk/filo: . configs drivers drivers/newusb fs include/grub main main/grub util
by Marc Jones 23 Oct '08

23 Oct '08

svn(a)coreboot.org wrote: > Author: stepan > Date: 2008-10-22 13:19:52 +0200 (Wed, 22 Oct 2008) > New Revision: 83 > > Modified: > trunk/filo/Config.in > trunk/filo/Makefile > trunk/filo/build.sh > trunk/filo/configs/defconfig > trunk/filo/drivers/ide.c > trunk/filo/drivers/newusb/usb.c > trunk/filo/fs/blockdev.c > trunk/filo/fs/fsys_ext2fs.c > trunk/filo/include/grub/shared.h > trunk/filo/main/filo.c > trunk/filo/main/grub/builtins.c > trunk/filo/main/grub/char_io.c > trunk/filo/main/grub/cmdline.c > trunk/filo/main/grub/grub.c > trunk/filo/util/checksum_elf.c > Log: > New FILO code drop from coresystems' internal repository: > > * add "developer commands" to filo (lspci, setpci, io) > * use staged libpayload per default now. > * use libpayload-config.h where appropriate. > * fix an ext3 filesystem issues > * use libpayload functions to implement grub_printf instead of the incomplete > duplication > * fix broken "weak" symbol handling. > * fix string issue with boot_devices > * fix a couple of problems with colors > * fix endless loop in case of file open error > I tried this code today with the latest libpayload and it is blowing up. It is stuck looping outputting F to the screen. r81 with the latest libpayload seems to work ok. Marc -- Marc Jones Senior Firmware Engineer (970) 226-9684 Office mailto:Marc.Jones@amd.com http://www.amd.com/embeddedprocessors

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filo serial console problems
by Marc Jones 23 Oct '08

23 Oct '08

It looks like filo has some problems with serial console. 1. left arrow: reboots the system 2. tab: carriage return 3. backspace: leaves B characters Marc -- Marc Jones Senior Firmware Engineer (970) 226-9684 Office mailto:Marc.Jones@amd.com http://www.amd.com/embeddedprocessors

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r3690 - trunk/coreboot-v2/src/pc80/ide
by svn＠coreboot.org 23 Oct '08

23 Oct '08

Author: mjones Date: 2008-10-23 00:30:17 +0200 (Thu, 23 Oct 2008) New Revision: 3690 Modified: trunk/coreboot-v2/src/pc80/ide/ide.c Log: Made await_ide(), which polls for an ide status change, check the status reg much more often. In my case this reduced the time spent in coreboot by 1.5 sec! The timeout values of course aren't changed, only the granularity. Also, I didn't see any udelay() implementation that looked like it couldn't cope with 10 us delays. (Most are written as for (...) inb(0x80) loops.) Signed-off-by: Jens Rottmann <JRottmann(a)LiPPERTEmbedded.de> Acked-by: Marc Jones <marc.jones(a)amd.com> Modified: trunk/coreboot-v2/src/pc80/ide/ide.c =================================================================== --- trunk/coreboot-v2/src/pc80/ide/ide.c 2008-10-22 22:26:09 UTC (rev 3689) +++ trunk/coreboot-v2/src/pc80/ide/ide.c 2008-10-22 22:30:17 UTC (rev 3690) @@ -29,6 +29,7 @@ struct controller *ctrl, unsigned long timeout) { int result; + timeout *= 100; /* timeout was ms; finer granularity => reacts faster */ for(;;) { result = done(ctrl); if (result) { @@ -38,7 +39,7 @@ if (timeout-- <= 0) { break; } - udelay(1000); /* Added to avoid spinning GRW */ + udelay(10); /* Added to avoid spinning GRW */ } printk_info("IDE time out\n"); return -1;

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r3689 - trunk/coreboot-v2/src/northbridge/amd/lx
by svn＠coreboot.org 23 Oct '08

23 Oct '08

Author: mjones Date: 2008-10-23 00:26:09 +0200 (Thu, 23 Oct 2008) New Revision: 3689 Modified: trunk/coreboot-v2/src/northbridge/amd/lx/raminit.c Log: Changed RAM speed calculation to fix RAM modules getting rejected only due to integer rounding errors. Previously, the formula was: speed = 2 * (10000/spd_value) For spd_value=60 this means speed = 2 * 166 = 332, which is less than 333 and coreboot died saying RAM was incompatible. The new formula is: speed = 20000 / spd_value For spd_value=60, speed=333, which is fine. Signed-off-by: Jens Rottmann <JRottmann(a)LiPPERTEmbedded.de> Acked-by: Marc Jones <marc.jones(a)amd.com> Modified: trunk/coreboot-v2/src/northbridge/amd/lx/raminit.c =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/lx/raminit.c 2008-10-22 22:24:47 UTC (rev 3688) +++ trunk/coreboot-v2/src/northbridge/amd/lx/raminit.c 2008-10-22 22:26:09 UTC (rev 3689) @@ -194,7 +194,7 @@ } /* Turn SPD ns time into MHZ. Check what the asm does to this math. */ - speed = 2 * ((10000 / (((spd_byte0 >> 4) * 10) + (spd_byte0 & 0x0F)))); + speed = 20000 / (((spd_byte0 >> 4) * 10) + (spd_byte0 & 0x0F)); /* current speed > max speed? */ if (GeodeLinkSpeed() > speed) { @@ -274,15 +274,14 @@ spd_byte = spd_read_byte(DIMM0, SPD_SDRAM_CYCLE_TIME_2ND); if (spd_byte != 0) { /* Turn SPD ns time into MHZ. Check what the asm does to this math. */ - dimm_speed = 2 * (10000 / (((spd_byte >> 4) * 10) + - (spd_byte & 0x0F))); + dimm_speed = 20000 / (((spd_byte >> 4) * 10) + (spd_byte & 0x0F)); if (dimm_speed >= glspeed) { casmap_shift = 1; /* -.5 is a shift of 1 */ /* IF -1 timing is supported, check -1 timing > GeodeLink */ spd_byte = spd_read_byte(DIMM0, SPD_SDRAM_CYCLE_TIME_3RD); if (spd_byte != 0) { /* Turn SPD ns time into MHZ. Check what the asm does to this math. */ - dimm_speed = 2 * (10000 / (((spd_byte >> 4) * 10) + (spd_byte & 0x0F))); + dimm_speed = 20000 / (((spd_byte >> 4) * 10) + (spd_byte & 0x0F)); if (dimm_speed >= glspeed) { casmap_shift = 2; /* -1 is a shift of 2 */ } @@ -306,14 +305,14 @@ spd_byte = spd_read_byte(DIMM1, SPD_SDRAM_CYCLE_TIME_2ND); if (spd_byte != 0) { /* Turn SPD ns time into MHZ. Check what the asm does to this math. */ - dimm_speed = 2 * (10000 / (((spd_byte >> 4) * 10) + (spd_byte & 0x0F))); + dimm_speed = 20000 / (((spd_byte >> 4) * 10) + (spd_byte & 0x0F)); if (dimm_speed >= glspeed) { casmap_shift = 1; /* -.5 is a shift of 1 */ /* IF -1 timing is supported, check -1 timing > GeodeLink */ spd_byte = spd_read_byte(DIMM1, SPD_SDRAM_CYCLE_TIME_3RD); if (spd_byte != 0) { /* Turn SPD ns time into MHZ. Check what the asm does to this math. */ - dimm_speed = 2 * (10000 / (((spd_byte >> 4) * 10) + (spd_byte & 0x0F))); + dimm_speed = 20000 / (((spd_byte >> 4) * 10) + (spd_byte & 0x0F)); if (dimm_speed >= glspeed) { casmap_shift = 2; /* -1 is a shift of 2 */ }

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r3688 - in trunk/coreboot-v2/src: arch/i386/init cpu/amd/model_lx
by svn＠coreboot.org 23 Oct '08

23 Oct '08

Author: mjones Date: 2008-10-23 00:24:47 +0200 (Thu, 23 Oct 2008) New Revision: 3688 Modified: trunk/coreboot-v2/src/arch/i386/init/crt0.S.lb trunk/coreboot-v2/src/cpu/amd/model_lx/cache_as_ram.inc Log: Speed up copying coreboot to ram by using "movsl" instead of "movsb". Also use different console messages for copying and uncompressing, like it's already done in similar code in other places. Signed-off-by: Jens Rottmann <JRottmann(a)LiPPERTEmbedded.de> Acked-by: Marc Jones <marc.jones(a)amd.com> Modified: trunk/coreboot-v2/src/arch/i386/init/crt0.S.lb =================================================================== --- trunk/coreboot-v2/src/arch/i386/init/crt0.S.lb 2008-10-22 22:20:48 UTC (rev 3687) +++ trunk/coreboot-v2/src/arch/i386/init/crt0.S.lb 2008-10-22 22:24:47 UTC (rev 3688) @@ -74,6 +74,11 @@ movl $_iseg, %edi movl $_eiseg, %ecx subl %edi, %ecx + movb %cl, %al + shrl $2, %ecx + andb $3, %al + rep movsl + movb %al, %cl rep movsb #else leal 4+_liseg, %esi @@ -215,7 +220,11 @@ #if defined(CONSOLE_DEBUG_TX_STRING) && (ASM_CONSOLE_LOGLEVEL > BIOS_DEBUG) .section ".rom.data" +#if CONFIG_COMPRESS +str_copying_to_ram: .string "Uncompressing coreboot to RAM.\r\n" +#else str_copying_to_ram: .string "Copying coreboot to RAM.\r\n" +#endif str_pre_main: .string "Jumping to coreboot.\r\n" .previous Modified: trunk/coreboot-v2/src/cpu/amd/model_lx/cache_as_ram.inc =================================================================== --- trunk/coreboot-v2/src/cpu/amd/model_lx/cache_as_ram.inc 2008-10-22 22:20:48 UTC (rev 3687) +++ trunk/coreboot-v2/src/cpu/amd/model_lx/cache_as_ram.inc 2008-10-22 22:24:47 UTC (rev 3688) @@ -222,6 +222,11 @@ movl $_iseg, %edi movl $_eiseg, %ecx subl %edi, %ecx + movb %cl, %al + shrl $2, %ecx + andb $3, %al + rep movsl + movb %al, %cl rep movsb #else leal 4+_liseg, %esi @@ -363,7 +368,11 @@ #if defined(CONSOLE_DEBUG_TX_STRING) && (ASM_CONSOLE_LOGLEVEL > BIOS_DEBUG) .section ".rom.data" +#if CONFIG_COMPRESS +str_copying_to_ram: .string "Uncompressing coreboot to ram.\r\n" +#else str_copying_to_ram: .string "Copying coreboot to ram.\r\n" +#endif str_pre_main: .string "Jumping to coreboot.\r\n" .previous

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coreboot October 2008