coreboot October 2008

coreboot@coreboot.org

84 participants
608 discussions

glitch in via support
by ron minnich 29 Oct '08

29 Oct '08

mainboard/via/Kconfig:32:warning: 'select' used by config symbol 'BOARD_VIA_EPIA_CN' refer to undefined symbol 'SUPERIO_VIA_VT1211' this found while doing dbm690t ron

4 4

cleanup
by ron minnich 29 Oct '08

29 Oct '08

Just some misc. cleanup ron

3 4

r961 - in coreboot-v3: device include/device mainboard/amd/dbm690t mainboard/emulation/qemu-x86 southbridge/intel/i82371eb
by svn＠coreboot.org 29 Oct '08

29 Oct '08

Author: rminnich Date: 2008-10-29 05:25:32 +0100 (Wed, 29 Oct 2008) New Revision: 961 Modified: coreboot-v3/device/device.c coreboot-v3/device/device_util.c coreboot-v3/include/device/device.h coreboot-v3/mainboard/amd/dbm690t/mainboard.c coreboot-v3/mainboard/emulation/qemu-x86/vga.c coreboot-v3/southbridge/intel/i82371eb/i82371eb.c Log: General cleanup and comments for things that should be fixed in future. Most substantive change is getting rid of 'initialized', which was only ever needed in v2 due to an implementation mistake. With Uwe's comments taken into account, Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Myles Watson <mylesgw(a)gmail.com> Modified: coreboot-v3/device/device.c =================================================================== --- coreboot-v3/device/device.c 2008-10-29 02:22:38 UTC (rev 960) +++ coreboot-v3/device/device.c 2008-10-29 04:25:32 UTC (rev 961) @@ -805,6 +805,7 @@ #warning do we call phase3_enable here. new_max = busdevice->ops->phase3_scan(busdevice, max); do_phase3 = 0; + /* do we *ever* use this path */ for (link = 0; link < busdevice->links; link++) { if (busdevice->link[link].reset_needed) { if (reset_bus(&busdevice->link[link])) { @@ -973,15 +974,13 @@ printk(BIOS_INFO, "Phase 6: Initializing devices...\n"); for (dev = all_devices; dev; dev = dev->next) { - if (dev->enabled && !dev->initialized && - dev->ops && dev->ops->phase6_init) { + if (dev->enabled && dev->ops && dev->ops->phase6_init) { if (dev->path.type == DEVICE_PATH_I2C) { printk(BIOS_DEBUG, "Phase 6: smbus: %s[%d]->", dev_path(dev->bus->dev), dev->bus->link); } printk(BIOS_DEBUG, "Phase 6: %s init.\n", dev_path(dev)); - dev->initialized = 1; dev->ops->phase6_init(dev); } } @@ -995,8 +994,8 @@ printk(BIOS_INFO, "Show all devs...\n"); for (dev = all_devices; dev; dev = dev->next) { printk(BIOS_SPEW, - "%s(%s): enabled %d have_resources %d initialized %d\n", + "%s(%s): enabled %d have_resources %d\n", dev->dtsname, dev_path(dev), dev->enabled, - dev->have_resources, dev->initialized); + dev->have_resources); } } Modified: coreboot-v3/device/device_util.c =================================================================== --- coreboot-v3/device/device_util.c 2008-10-29 02:22:38 UTC (rev 960) +++ coreboot-v3/device/device_util.c 2008-10-29 04:25:32 UTC (rev 961) @@ -430,10 +430,7 @@ for (i = 0; i < dev->resources;) { resource = &dev->resource[i]; if (!resource->flags) { - /* Note: memmove() was used here. But this can never - * overlap, right? - */ - memcpy(resource, resource + 1, (dev->resources-i)* sizeof(*resource)); + memmove(resource, resource + 1, (dev->resources-i)* sizeof(*resource)); dev->resources -= 1; memset(&dev->resource[dev->resources], 0, sizeof(*resource)); Modified: coreboot-v3/include/device/device.h =================================================================== --- coreboot-v3/include/device/device.h 2008-10-29 02:22:38 UTC (rev 960) +++ coreboot-v3/include/device/device.h 2008-10-29 04:25:32 UTC (rev 961) @@ -214,7 +214,6 @@ unsigned int class; /* 3 bytes: (base,sub,prog-if) */ unsigned int hdr_type; /* PCI header type */ unsigned int enabled : 1; /* set if we should enable the device */ - unsigned int initialized : 1; /* set if we have initialized the device */ unsigned int have_resources : 1; /* Set if we have read the devices resources */ unsigned int on_mainboard : 1; unsigned long rom_address; Modified: coreboot-v3/mainboard/amd/dbm690t/mainboard.c =================================================================== --- coreboot-v3/mainboard/amd/dbm690t/mainboard.c 2008-10-29 02:22:38 UTC (rev 960) +++ coreboot-v3/mainboard/amd/dbm690t/mainboard.c 2008-10-29 04:25:32 UTC (rev 961) @@ -17,6 +17,11 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +/* N.B. This file should be removed in the long term. */ +/* the nic code goes to the south support. The UMA code should + * be moved to the cpu support. + */ + #include <mainboard.h> #include <config.h> #include <types.h> Modified: coreboot-v3/mainboard/emulation/qemu-x86/vga.c =================================================================== --- coreboot-v3/mainboard/emulation/qemu-x86/vga.c 2008-10-29 02:22:38 UTC (rev 960) +++ coreboot-v3/mainboard/emulation/qemu-x86/vga.c 2008-10-29 04:25:32 UTC (rev 961) @@ -38,6 +38,8 @@ /* * FIXME: This should be in the Super I/O code some day, * but since QEMU has no Super I/O... + * we need to create superio/emulation/qemu and move the keyboard + * bits there. */ init_pc_keyboard(0x60, 0x64, &conf); /* now run the rom */ Modified: coreboot-v3/southbridge/intel/i82371eb/i82371eb.c =================================================================== --- coreboot-v3/southbridge/intel/i82371eb/i82371eb.c 2008-10-29 02:22:38 UTC (rev 960) +++ coreboot-v3/southbridge/intel/i82371eb/i82371eb.c 2008-10-29 04:25:32 UTC (rev 961) @@ -43,6 +43,7 @@ { unsigned short c; + /* These should be controlled in the dts. */ printk(BIOS_DEBUG, "Enabling IDE channel 1\n"); c = pci_read_config16(dev, 0x40); c |= 0x8000; @@ -82,6 +83,9 @@ pci_write_config8(dev, 0x80, 1); } +/*NOTE: We need our own read and set resources for this part! It has + * BARS that are not in the normal place (such as SMBUS) + */ /* You can override or extend each operation as needed for the device. */ struct device_operations i82371eb_isa = { .id = {.type = DEVICE_ID_PCI,

1 0

r3699 - in trunk/coreboot-v2/src: config devices
by svn＠coreboot.org 29 Oct '08

29 Oct '08

Author: stepan Date: 2008-10-29 04:15:42 +0100 (Wed, 29 Oct 2008) New Revision: 3699 Modified: trunk/coreboot-v2/src/config/Options.lb trunk/coreboot-v2/src/devices/device.c trunk/coreboot-v2/src/devices/pci_device.c Log: Changes required to the device allocator: - leave a hole for mmapped PCIe config space if CONFIG_PCIE_CONFIGSPACE_HOLE is set. - Mask moving bits to 32bit when resources are not supposed above 4G. Linux does not like this, even though the resource is disabled. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Myles Watson <mylesgw(a)gmail.com> Modified: trunk/coreboot-v2/src/config/Options.lb =================================================================== --- trunk/coreboot-v2/src/config/Options.lb 2008-10-28 22:13:38 UTC (rev 3698) +++ trunk/coreboot-v2/src/config/Options.lb 2008-10-29 03:15:42 UTC (rev 3699) @@ -1115,6 +1115,12 @@ # 4 for 1280x1024 end +define CONFIG_PCIE_CONFIGSPACE_HOLE + default 0 + export always + comment "Leave a hole for PCIe config space in the device allocator" +end + ############################################### # Board specific options ############################################### Modified: trunk/coreboot-v2/src/devices/device.c =================================================================== --- trunk/coreboot-v2/src/devices/device.c 2008-10-28 22:13:38 UTC (rev 3698) +++ trunk/coreboot-v2/src/devices/device.c 2008-10-29 03:15:42 UTC (rev 3699) @@ -366,6 +366,12 @@ (resource->flags & IORESOURCE_IO)? "io": (resource->flags & IORESOURCE_PREFETCH)? "prefmem": "mem"); } +#if CONFIG_PCIE_CONFIGSPACE_HOLE +#warning Handle PCIe hole differently... + if (base >= 0xf0000000 && base < 0xf4000000) { + base = 0xf4000000; + } +#endif } /* A pci bridge resource does not need to be a power * of two size, but it does have a minimum granularity. Modified: trunk/coreboot-v2/src/devices/pci_device.c =================================================================== --- trunk/coreboot-v2/src/devices/pci_device.c 2008-10-28 22:13:38 UTC (rev 3698) +++ trunk/coreboot-v2/src/devices/pci_device.c 2008-10-29 03:15:42 UTC (rev 3699) @@ -377,7 +377,11 @@ * clear it and forget it. */ if (resource->size == 0) { +#if CONFIG_PCI_64BIT_PREF_MEM == 1 resource->base = moving; +#else + resource->base = moving & 0xffffffff; +#endif resource->flags |= IORESOURCE_ASSIGNED; resource->flags &= ~IORESOURCE_STORED; pci_set_resource(dev, resource);

1 0

v3 __func0 cleanup
by Myles Watson 29 Oct '08

29 Oct '08

This patch documents the unreadable function in northbridge/amd/k8/pci.c and cleans up the NULL pointer protection. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> It also begs the question why cpu_bus_scan and cpu_bus_init aren't needed in v3. They aren't called. Is that an oversight, or should they be removed. Thanks, Myles

3 4

v3 stage1 warnings
by Myles Watson 29 Oct '08

29 Oct '08

This patch removes an unused variable, adds a necessary cast, and moves a declaration into an #ifdef. It removes these warnings: /home/myles/buildrom/try/buildrom/buildrom-devel/work/coreboot-v3/svn/arch/x86/stage1.c: In function 'stage1_phase1': /home/myles/buildrom/try/buildrom/buildrom-devel/work/coreboot-v3/svn/arch/x86/stage1.c:173: warning: unused variable 'me' /home/myles/buildrom/try/buildrom/buildrom-devel/work/coreboot-v3/svn/arch/x86/stage1.c: In function 'stage1_phase3': /home/myles/buildrom/try/buildrom/buildrom-devel/work/coreboot-v3/svn/arch/x86/stage1.c:308: warning: assignment makes pointer from integer without a cast /home/myles/buildrom/try/buildrom/buildrom-devel/work/coreboot-v3/svn/arch/x86/stage1.c:282: warning: unused variable 'ret' Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Thanks, Myles

3 3

r960 - coreboot-v3/northbridge/amd/k8
by svn＠coreboot.org 29 Oct '08

29 Oct '08

Author: myles Date: 2008-10-29 03:22:38 +0100 (Wed, 29 Oct 2008) New Revision: 960 Modified: coreboot-v3/northbridge/amd/k8/common.c coreboot-v3/northbridge/amd/k8/domain.c coreboot-v3/northbridge/amd/k8/pci.c Log: This patch documents the unreadable function in northbridge/amd/k8/pci.c and cleans up the NULL pointer protection. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Marc Jones <marc.jones(a)amd.com> Modified: coreboot-v3/northbridge/amd/k8/common.c =================================================================== --- coreboot-v3/northbridge/amd/k8/common.c 2008-10-29 02:19:42 UTC (rev 959) +++ coreboot-v3/northbridge/amd/k8/common.c 2008-10-29 02:22:38 UTC (rev 960) @@ -80,28 +80,27 @@ void get_fx_devs(void) { int i; - if (__f1_dev[0]) { - return; - } for(i = 0; i < FX_DEVS; i++) { __f0_dev[i] = dev_find_slot(0, PCI_DEVFN(0x18 + i, 0)); __f1_dev[i] = dev_find_slot(0, PCI_DEVFN(0x18 + i, 1)); } - if (!__f1_dev[0]) { - die("Cannot find 0:0x18.1\n"); + if (__f1_dev[0] == NULL || __f0_dev[0] == NULL) { + die("Cannot find 0:0x18.[0|1]\n"); } } u32 f1_read_config32(unsigned int reg) { - get_fx_devs(); + if ( __f1_dev[0] == NULL) + get_fx_devs(); return pci_read_config32(__f1_dev[0], reg); } void f1_write_config32(unsigned int reg, u32 value) { int i; - get_fx_devs(); + if ( __f1_dev[0] == NULL) + get_fx_devs(); for(i = 0; i < FX_DEVS; i++) { struct device * dev; dev = __f1_dev[i]; Modified: coreboot-v3/northbridge/amd/k8/domain.c =================================================================== --- coreboot-v3/northbridge/amd/k8/domain.c 2008-10-29 02:19:42 UTC (rev 959) +++ coreboot-v3/northbridge/amd/k8/domain.c 2008-10-29 02:22:38 UTC (rev 960) @@ -52,7 +52,6 @@ #define FX_DEVS 8 extern struct device * __f0_dev[FX_DEVS]; -void get_fx_devs(void); u32 f1_read_config32(unsigned int reg); void f1_write_config32(unsigned int reg, u32 value); unsigned int amdk8_nodeid(struct device * dev); @@ -103,7 +102,6 @@ /* Find the already assigned resource pairs */ printk(BIOS_DEBUG, "k8_pci_domain_read_resources\n"); - get_fx_devs(); for(reg = 0x80; reg <= 0xd8; reg+= 0x08) { u32 base, limit; base = f1_read_config32(reg); @@ -114,7 +112,7 @@ struct device * dev; nodeid = limit & 7; link = (limit >> 4) & 3; - dev = __f0_dev[nodeid]; + dev = __f0_dev[nodeid]; /* Initialized by f1_read_config32. */ if (dev) { /* Reserve the resource */ struct resource *resource; @@ -379,10 +377,9 @@ /* Tune the hypertransport transaction for best performance. * Including enabling relaxed ordering if it is safe. */ - get_fx_devs(); for(i = 0; i < FX_DEVS; i++) { struct device * f0_dev; - f0_dev = __f0_dev[i]; + f0_dev = __f0_dev[i]; /* Initialized by f1_write_config32. */ if (f0_dev && f0_dev->enabled) { u32 httc; httc = pci_read_config32(f0_dev, HT_TRANSACTION_CONTROL); Modified: coreboot-v3/northbridge/amd/k8/pci.c =================================================================== --- coreboot-v3/northbridge/amd/k8/pci.c 2008-10-29 02:19:42 UTC (rev 959) +++ coreboot-v3/northbridge/amd/k8/pci.c 2008-10-29 02:22:38 UTC (rev 960) @@ -48,6 +48,7 @@ #define FX_DEVS 8 extern struct device * __f0_dev[FX_DEVS]; +extern void get_fx_devs(void); u32 f1_read_config32(unsigned int reg); void f1_write_config32(unsigned int reg, u32 value); unsigned int amdk8_nodeid(struct device * dev); @@ -63,7 +64,7 @@ unsigned max_bus; unsigned min_bus; unsigned max_devfn; - printk(BIOS_SPEW, "amdk8_scan_chain\n"); + printk(BIOS_SPEW, "amdk8_scan_chain link %x\n",link); dev->link[link].cap = 0x80 + (link *0x20); do { link_type = pci_read_config32(dev, dev->link[link].cap + 0x18); @@ -242,16 +243,25 @@ return max; } -#warning document this unreadable function reg_useable +/** + * reg_useable + * @param reg register to check + * @param goal_dev device to own the resource + * @param goal_nodeid node number + * @param goal_link link number + * @return 0 if not useable, 1 if useable, or 2 if the pair is free + * __f0 is initialized once in amdk8_read_resources + */ static int reg_useable(unsigned reg, struct device * goal_dev, unsigned goal_nodeid, unsigned goal_link) { struct resource *res; - unsigned nodeid, link; + unsigned nodeid, link=0; int result; - res = 0; -#warning fix hard-coded 8 in for loop. - for(nodeid = 0; !res && (nodeid < 8); nodeid++) { + res = NULL; + + /* Look for the resource that matches this register. */ + for(nodeid = 0; !res && (nodeid < CONFIG_MAX_PHYSICAL_CPUS); nodeid++) { struct device * dev; dev = __f0_dev[nodeid]; if (! dev) @@ -260,9 +270,12 @@ res = probe_resource(dev, 0x100 + (reg | link)); } } + + /* If no allocated resource was found, it is free - return 2 */ result = 2; if (res) { result = 0; + /* If the resource is allocated to the link and node already */ if ( (goal_link == (link - 1)) && (goal_nodeid == (nodeid - 1)) && (res->flags <= 1)) { @@ -277,7 +290,7 @@ { struct resource *resource; unsigned free_reg, reg; - resource = 0; + resource = NULL; free_reg = 0; for(reg = 0xc0; reg <= 0xd8; reg += 0x8) { int result; @@ -304,7 +317,7 @@ { struct resource *resource; unsigned free_reg, reg; - resource = 0; + resource = NULL; free_reg = 0; for(reg = 0x80; reg <= 0xb8; reg += 0x8) { int result; @@ -378,6 +391,9 @@ printk(BIOS_DEBUG, "amdk8_read_resources\n"); unsigned nodeid, link; nodeid = amdk8_nodeid(dev); + + get_fx_devs(); /* Make sure __f0 is initialized*/ + for(link = 0; link < dev->links; link++) { if (dev->link[link].children) { printk(BIOS_DEBUG, "amdk8_read_resources link %d\n", link); @@ -583,7 +599,7 @@ {.pci = {.vendor = PCI_VENDOR_ID_AMD, .device = 0x1100}}}, .constructor = default_device_constructor, - .reset_bus = pci_bus_reset, + .reset_bus = pci_bus_reset, .phase3_scan = amdk8_scan_chains, .phase4_read_resources = amdk8_read_resources, .phase4_set_resources = amdk8_set_resources,

1 0

r959 - coreboot-v3/arch/x86
by svn＠coreboot.org 29 Oct '08

29 Oct '08

Author: myles Date: 2008-10-29 03:19:42 +0100 (Wed, 29 Oct 2008) New Revision: 959 Modified: coreboot-v3/arch/x86/stage1.c Log: This patch clears up a few warnings in stage1 code. It removes an unused variable, moves a declaration into an ifdef, and adds a cast. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Modified: coreboot-v3/arch/x86/stage1.c =================================================================== --- coreboot-v3/arch/x86/stage1.c 2008-10-28 17:29:07 UTC (rev 958) +++ coreboot-v3/arch/x86/stage1.c 2008-10-29 02:19:42 UTC (rev 959) @@ -170,7 +170,6 @@ struct global_vars globvars; int ret; struct mem_file archive; - struct node_core_id me; post_code(POST_STAGE1_MAIN); @@ -279,11 +278,11 @@ void __attribute__((stdcall)) stage1_phase3(void) { void *entry; - int ret; struct mem_file archive; struct multiboot_info *mbi; #ifdef CONFIG_PAYLOAD_ELF_LOADER + int ret; struct mem_file result; int elfboot_mem(struct lb_memory *mem, void *where, int size); @@ -305,7 +304,7 @@ entry = load_file_segments(&archive, "normal/stage2"); if (entry == (void *)-1) die("FATAL: Failed loading stage2."); - mbi = run_address(entry); + mbi = (struct multiboot_info*) run_address(entry); if (! mbi) die("FATAL: Failed in stage2 code.");

1 0

doxygen link for v3?
by Marc Jones 29 Oct '08

29 Oct '08

Is there a v3 doxygen page like v2? Since the doxygen is much better we should use it.... Marc -- Marc Jones Senior Firmware Engineer (970) 226-9684 Office mailto:Marc.Jones@amd.com http://www.amd.com/embeddedprocessors

2 1

flashrom on EP80759 + Spansion S25FL016A
by Stephan GUILLOUX 29 Oct '08

29 Oct '08

Hello, We have a mother board, based on EP80579. On board, there is a flash from SPANSION S25FL016A. Both are indicated as supported by flashrom (from coreboot v2-3695). When I start flashrom on my machine, only the EP80579 is seen. For the flash, it says : spi_command called, but no SPI chipset/strapping detected. Any idea ? Stephan.

2 1

← Newer
1
...
11
12
13
14
15
16
17
...
61
Older →

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

2009

2008

2007

2006

2005

2004

2003

2002

coreboot October 2008