coreboot October 2008

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r3708 - trunk/util/flashrom
by svn＠coreboot.org 30 Oct '08

30 Oct '08

Author: uwe Date: 2008-10-30 04:10:17 +0100 (Thu, 30 Oct 2008) New Revision: 3708 Modified: trunk/util/flashrom/flashchips.c Log: Mark two more chips as fully tested (trivial). - SST SST39SF010A - Winbond W29C011 Tested by me on actual hardware, all operations. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/util/flashrom/flashchips.c =================================================================== --- trunk/util/flashrom/flashchips.c 2008-10-29 22:13:20 UTC (rev 3707) +++ trunk/util/flashrom/flashchips.c 2008-10-30 03:10:17 UTC (rev 3708) @@ -81,7 +81,7 @@ {"SST", "SST29LE010", SST_ID, SST_29LE010, 128, 128, TEST_UNTESTED, probe_jedec, erase_chip_jedec, write_jedec}, {"SST", "SST29EE020A", SST_ID, SST_29EE020A, 256, 128, TEST_UNTESTED, probe_jedec, erase_chip_jedec, write_jedec}, {"SST", "SST29LE020", SST_ID, SST_29LE020, 256, 128, TEST_UNTESTED, probe_jedec, erase_chip_jedec, write_jedec}, - {"SST", "SST39SF010A", SST_ID, SST_39SF010, 128, 4096, TEST_UNTESTED, probe_jedec, erase_chip_jedec, write_39sf020}, + {"SST", "SST39SF010A", SST_ID, SST_39SF010, 128, 4096, TEST_OK_PREW, probe_jedec, erase_chip_jedec, write_39sf020}, {"SST", "SST39SF020A", SST_ID, SST_39SF020, 256, 4096, TEST_OK_PREW, probe_jedec, erase_chip_jedec, write_39sf020}, {"SST", "SST39SF040", SST_ID, SST_39SF040, 512, 4096, TEST_UNTESTED, probe_jedec, erase_chip_jedec, write_39sf020}, {"SST", "SST39VF512", SST_ID, SST_39VF512, 64, 4096, TEST_UNTESTED, probe_jedec, erase_chip_jedec, write_39sf020}, @@ -133,7 +133,7 @@ {"Winbond", "W25x20", WINBOND_NEX_ID, W_25X20, 256, 256, TEST_UNTESTED, probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, {"Winbond", "W25x40", WINBOND_NEX_ID, W_25X40, 512, 256, TEST_OK_PREW, probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, {"Winbond", "W25x80", WINBOND_NEX_ID, W_25X80, 1024, 256, TEST_OK_PREW, probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, - {"Winbond", "W29C011", WINBOND_ID, W_29C011, 128, 128, TEST_UNTESTED, probe_jedec, erase_chip_jedec, write_jedec}, + {"Winbond", "W29C011", WINBOND_ID, W_29C011, 128, 128, TEST_OK_PREW, probe_jedec, erase_chip_jedec, write_jedec}, {"Winbond", "W29C020C", WINBOND_ID, W_29C020C, 256, 128, TEST_OK_PREW, probe_jedec, erase_chip_jedec, write_jedec}, {"Winbond", "W29C040P", WINBOND_ID, W_29C040P, 512, 256, TEST_UNTESTED, probe_jedec, erase_chip_jedec, write_jedec}, {"Winbond", "W29EE011", WINBOND_ID, W_29C011, 128, 128, TEST_OK_PREW, probe_w29ee011, erase_chip_jedec, write_jedec},

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newest
by ron minnich 30 Oct '08

30 Oct '08

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Compal DL70 Dumps
by Jeremy Wahl 30 Oct '08

30 Oct '08

-- Use GNU/Linux to free yourself from the restrictions of Vista! ubuntu.com | mandriva.com | opensuse.org

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Re: [coreboot] r3705 - in trunk/coreboot-v2/src: include/device northbridge/intel/i945 southbridge/intel/i82801gx
by Peter Stuge 30 Oct '08

30 Oct '08

svn(a)coreboot.org wrote: > static const struct pci_driver mc_driver __pci_driver = { > .ops = &mc_ops, > .vendor = PCI_VENDOR_ID_INTEL, > - .device = 0x27a0, > + .device = PCI_DEVICE_ID_INTEL_945_HOST_BRIDGE, Sorry, but I don't really agree with these changes. > static const struct pci_driver i82801gx_ide __pci_driver = { > .ops = &ide_ops, > .vendor = PCI_VENDOR_ID_INTEL, > - .device = 0x27df, > + .device = PCI_DEVICE_ID_INTEL_82801GB_IDE, > }; My reasoning is that #defines should add information to the code and not be an end in itself. > -static const struct pci_driver i82801ex_usb_ehci __pci_driver = { > .ops = &usb_ehci_ops, > .vendor = PCI_VENDOR_ID_INTEL, > - .device = 0x27cc, > + .device = PCI_DEVICE_ID_INTEL_82801GB_EHCI, > }; In all these cases I quote above it is already perfectly clear from the struct name which device is refered to, in which case I think it would be more informative to have the literal device PCI id. //Peter

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r3707 build service
by coreboot information 29 Oct '08

29 Oct '08

Dear coreboot readers! This is the automated build check service of coreboot. The developer "stepan" checked in revision 3707 to the coreboot source repository and caused the following changes: Change Log: Flashrom support for some Numonyx parts (M25PE) using block erase d8 as discussed with Peter Stuge Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Build Log: Compilation of emulation:qemu-x86 has been fixed If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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r3707 - trunk/util/flashrom
by svn＠coreboot.org 29 Oct '08

29 Oct '08

Author: stepan Date: 2008-10-29 23:13:20 +0100 (Wed, 29 Oct 2008) New Revision: 3707 Modified: trunk/util/flashrom/flash.h trunk/util/flashrom/flashchips.c trunk/util/flashrom/spi.c Log: Flashrom support for some Numonyx parts (M25PE) using block erase d8 as discussed with Peter Stuge Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/util/flashrom/flash.h =================================================================== --- trunk/util/flashrom/flash.h 2008-10-29 14:54:36 UTC (rev 3706) +++ trunk/util/flashrom/flash.h 2008-10-29 22:13:20 UTC (rev 3707) @@ -424,6 +424,7 @@ void spi_write_enable(); void spi_write_disable(); int spi_chip_erase_c7(struct flashchip *flash); +int spi_chip_erase_d8(struct flashchip *flash); int spi_chip_write(struct flashchip *flash, uint8_t *buf); int spi_chip_read(struct flashchip *flash, uint8_t *buf); uint8_t spi_read_status_register(); Modified: trunk/util/flashrom/flashchips.c =================================================================== --- trunk/util/flashrom/flashchips.c 2008-10-29 14:54:36 UTC (rev 3706) +++ trunk/util/flashrom/flashchips.c 2008-10-29 22:13:20 UTC (rev 3707) @@ -59,6 +59,11 @@ {"Macronix", "MX25L1605", MX_ID, MX_25L1605, 2048, 256, TEST_UNTESTED, probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, {"Macronix", "MX25L3205", MX_ID, MX_25L3205, 4096, 256, TEST_OK_PREW, probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, {"Macronix", "MX29F002", MX_ID, MX_29F002, 256, 64 * 1024, TEST_UNTESTED, probe_29f002, erase_29f002, write_29f002}, + {"Numonyx", "M25PE10", ST_ID, 0x8011, 128, 256, TEST_UNTESTED, probe_spi_rdid, spi_chip_erase_d8, spi_chip_write, spi_chip_read}, + {"Numonyx", "M25PE20", ST_ID, 0x8012, 256, 256, TEST_UNTESTED, probe_spi_rdid, spi_chip_erase_d8, spi_chip_write, spi_chip_read}, + {"Numonyx", "M25PE40", ST_ID, 0x8013, 256, 256, TEST_UNTESTED, probe_spi_rdid, spi_chip_erase_d8, spi_chip_write, spi_chip_read}, + {"Numonyx", "M25PE80", ST_ID, 0x8014, 1024, 256, TEST_OK_PREW, probe_spi_rdid, spi_chip_erase_d8, spi_chip_write, spi_chip_read}, + {"Numonyx", "M25PE16", ST_ID, 0x8015, 2048, 256, TEST_UNTESTED, probe_spi_rdid, spi_chip_erase_d8, spi_chip_write, spi_chip_read}, {"PMC", "Pm25LV010", PMC_ID, PMC_25LV010, 128, 256, TEST_UNTESTED, probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, {"PMC", "Pm25LV016B", PMC_ID, PMC_25LV016B, 2048, 256, TEST_UNTESTED, probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, {"PMC", "Pm25LV020", PMC_ID, PMC_25LV020, 256, 256, TEST_UNTESTED, probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, Modified: trunk/util/flashrom/spi.c =================================================================== --- trunk/util/flashrom/spi.c 2008-10-29 14:54:36 UTC (rev 3706) +++ trunk/util/flashrom/spi.c 2008-10-29 22:13:20 UTC (rev 3707) @@ -310,6 +310,29 @@ return 0; } +int spi_chip_erase_d8(struct flashchip *flash) +{ + int i, rc = 0; + int total_size = flash->total_size * 1024; + int erase_size = 64 * 1024; + + spi_disable_blockprotect(); + + printf("Erasing chip: \n"); + + for (i = 0; i < total_size / erase_size; i++) { + rc = spi_block_erase_d8(flash, i * erase_size); + if (rc) { + printf("Error erasing block at 0x%x\n", i); + break; + } + } + + printf("\n"); + + return rc; +} + /* Sector size is usually 4k, though Macronix eliteflash has 64k */ int spi_sector_erase(const struct flashchip *flash, unsigned long addr) {

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Re: [coreboot] __attribute__((stdcall)) vs. __attribute__((regparm(0)))
by Myles Watson 29 Oct '08

29 Oct '08

> > > This patch makes the vm86 call succeed. It > > 1. moves the run_bios function down so it can call setup_realmode_idt > > 2. adds the __attribute__((regnum(0))) to biosint because it is called > > from assembly > > > > Signed-off-by: Myles Watson <mylesgw(a)gmail.com <mailto:mylesgw@gmail.com > >> > > Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Rev 964. Thanks! Myles

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r964 - coreboot-v3/util/x86emu
by svn＠coreboot.org 29 Oct '08

29 Oct '08

Author: myles Date: 2008-10-29 21:39:32 +0100 (Wed, 29 Oct 2008) New Revision: 964 Modified: coreboot-v3/util/x86emu/vm86.c Log: This patch makes the vm86 call succeed. It 1. moves the run_bios function down so it can call setup_realmode_idt 2. adds the __attribute__((regnum(0))) to biosint because it is called from assembly Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: coreboot-v3/util/x86emu/vm86.c =================================================================== --- coreboot-v3/util/x86emu/vm86.c 2008-10-29 18:29:19 UTC (rev 963) +++ coreboot-v3/util/x86emu/vm86.c 2008-10-29 20:39:32 UTC (rev 964) @@ -29,7 +29,6 @@ #include <string.h> #include <io.h> - /* The address arguments to this function are PHYSICAL ADDRESSES */ static void real_mode_switch_call_vga(unsigned long devfn) { @@ -240,19 +239,6 @@ ); } -void run_bios(struct device *dev, unsigned long addr) -{ - int i; - - /* clear vga bios data area */ - for (i = 0x400; i < 0x500; i++) { - *(unsigned char *) i = 0; - } - - real_mode_switch_call_vga((dev->bus->secondary << 8) | dev->path.pci.devfn); -} - - // we had hoped to avoid this. // this is a stub IDT only. It's main purpose is to ignore calls // to the BIOS. @@ -415,7 +401,7 @@ extern void vga_exit(void); -int biosint(unsigned long intnumber, +int __attribute__((regparm(0))) biosint(unsigned long intnumber, unsigned long gsfs, unsigned long dses, unsigned long edi, unsigned long esi, unsigned long ebp, unsigned long esp, @@ -484,7 +470,6 @@ return ret; } - void setup_realmode_idt(void) { extern unsigned char idthandle, end_idthandle; @@ -543,12 +528,21 @@ idts[1].offset = 16384; memcpy((void *)16384, &debughandle, &end_debughandle - &debughandle); #endif - - } +void run_bios(struct device *dev, unsigned long addr) +{ + int i; + /* clear vga bios data area */ + for (i = 0x400; i < 0x500; i++) { + *(unsigned char *) i = 0; + } + setup_realmode_idt(); + real_mode_switch_call_vga((dev->bus->secondary << 8) | dev->path.pci.devfn); +} + enum { CHECK = 0xb001, FINDDEV = 0xb102,

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coreboot-2 on a DFI NF570 motherboard
by Chris Lingard 29 Oct '08

29 Oct '08

Motherboards DFI NF-570 range, (NF570SLI-M2/G, NF570-M2/G and NF550-M2/G). This is a suggestion to port coreboot to the NF570 series. I have already posted a patch, but this just duplicates the entire M57SLI stuff just for a two line change. If the build script could set a flag, shown in the example as dfi_nf570, then coreboot would work on the above motherboards. After discussion on IRC this would be a better implementation From mptable.c PCI_INT(0,sbdn+6,1, 23); /* HD Audio */ PCI_INT(0,sbdn+5,0, 20); /* SATA */ PCI_INT(0,sbdn+5,2, 22); /* SATA */ PCI_INT(0,sbdn+5,1, 23); /* SATA */ #ifdef dfi_nf570 PCI_INT(0,sbdn+5,2, 22); /* SATA */ PCI_INT(0,sbdn+8,0, 21); /* GBit Ether */ #else PCI_INT(0,sbdn+5,2, 21); /* SATA */ PCI_INT(0,sbdn+8,0, 22); /* GBit Ether */ #endif /* The PCIe slots, each on its own bus */ Taken and modified from the Gigabyte M57SLI tree signed-of-by: Chris Lingard chris(a)stockwith.co.uk Tested on a DSI NF570-M2/G motherboard The use of this motherboard eases the learning path into coreboot, because it has a socketed BIOS, and needs no modification. I had never hot plugged a chip nor flashed a BIOS until this week Chris Lingard

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commit message for devcleanup
by ron minnich 29 Oct '08

29 Oct '08

This was maybe missing. Make it so that read_resources only reads resources. dev_phase4 will call compute_allocate. This is an early pass at making the device tree code a little more readable. We have done a pass on the stage2 code and are comfortable with phases 1-3 and 5-6; phase 4 is the phase that is really tough to follow. We are working on cleaning that up today. This change tested and working on dbe62. We are well aware that as more complex targets appear this code may break on them. At the same time, we are determined to untangle the thicket of code in phase 4, since this code has been a source of confusion for several years now. Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com>

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coreboot October 2008