coreboot October 2008

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r3705 - in trunk/coreboot-v2/src: include/device northbridge/intel/i945 southbridge/intel/i82801gx
by svn＠coreboot.org 29 Oct '08

29 Oct '08

Author: uwe Date: 2008-10-29 14:51:31 +0100 (Wed, 29 Oct 2008) New Revision: 3705 Modified: trunk/coreboot-v2/src/include/device/pci_ids.h trunk/coreboot-v2/src/northbridge/intel/i945/northbridge.c trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx.c trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_ac97.c trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_ide.c trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_lpc.c trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_nic.c trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_pci.c trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_pcie.c trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_sata.c trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_smbus.c trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_usb.c trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_usb_ehci.c Log: i945/ICH7: Use #defines from pci_ids.h (trivial). Build-tested with the kontron/986lcd-m target. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/coreboot-v2/src/include/device/pci_ids.h =================================================================== --- trunk/coreboot-v2/src/include/device/pci_ids.h 2008-10-29 04:52:57 UTC (rev 3704) +++ trunk/coreboot-v2/src/include/device/pci_ids.h 2008-10-29 13:51:31 UTC (rev 3705) @@ -2395,6 +2395,9 @@ #define PCI_DEVICE_ID_INTEL_EP80579_PCIE_PA0 0x5024 #define PCI_DEVICE_ID_INTEL_EP80579_PCIE_PA1 0x5025 +/* Intel 945 */ +#define PCI_DEVICE_ID_INTEL_945_HOST_BRIDGE 0x27a0 + #define PCI_DEVICE_ID_INTEL_80310 0x530d #define PCI_DEVICE_ID_INTEL_82810_MC1 0x7120 #define PCI_DEVICE_ID_INTEL_82810_IG1 0x7121 Modified: trunk/coreboot-v2/src/northbridge/intel/i945/northbridge.c =================================================================== --- trunk/coreboot-v2/src/northbridge/intel/i945/northbridge.c 2008-10-29 04:52:57 UTC (rev 3704) +++ trunk/coreboot-v2/src/northbridge/intel/i945/northbridge.c 2008-10-29 13:51:31 UTC (rev 3705) @@ -247,7 +247,7 @@ static const struct pci_driver mc_driver __pci_driver = { .ops = &mc_ops, .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x27a0, + .device = PCI_DEVICE_ID_INTEL_945_HOST_BRIDGE, }; static void cpu_bus_init(device_t dev) Modified: trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx.c =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx.c 2008-10-29 04:52:57 UTC (rev 3704) +++ trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx.c 2008-10-29 13:51:31 UTC (rev 3705) @@ -25,7 +25,6 @@ void i82801gx_enable(device_t dev) { - } struct chip_operations southbridge_intel_i82801gx_ops = { Modified: trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_ac97.c =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_ac97.c 2008-10-29 04:52:57 UTC (rev 3704) +++ trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_ac97.c 2008-10-29 13:51:31 UTC (rev 3705) @@ -52,20 +52,18 @@ .enable = i82801gx_enable, }; - - /* 82801GB/GR/GDH/GBM/GHM (ICH7/ICH7R/ICH7DH/ICH7-M/ICH7-M DH) */ -/* Note: 82801GU (ICH7-U) doesn't have AC97 audio/modem. */ - -static const struct pci_driver i82801gb_ac97_audio __pci_driver = { +/* Note: 82801GU (ICH7-U) doesn't have AC97 audio. */ +static const struct pci_driver i82801gx_ac97_audio __pci_driver = { .ops = &ac97_audio_ops, .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_82801GB_AC97_AUDIO, }; -static const struct pci_driver i82801gb_ac97_modem __pci_driver = { +/* 82801GB/GR/GDH/GBM/GHM (ICH7/ICH7R/ICH7DH/ICH7-M/ICH7-M DH) */ +/* Note: 82801GU (ICH7-U) doesn't have AC97 modem. */ +static const struct pci_driver i82801gx_ac97_modem __pci_driver = { .ops = &ac97_modem_ops, .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_82801GB_AC97_MODEM, }; - Modified: trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_ide.c =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_ide.c 2008-10-29 04:52:57 UTC (rev 3704) +++ trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_ide.c 2008-10-29 13:51:31 UTC (rev 3705) @@ -92,9 +92,9 @@ .enable = i82801gx_enable, }; -/* 82801Gx */ +/* 82801GB/GR/GDH/GBM/GHM/GU (ICH7/ICH7R/ICH7DH/ICH7-M/ICH7-M DH/ICH7-U) */ static const struct pci_driver i82801gx_ide __pci_driver = { .ops = &ide_ops, .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x27df, + .device = PCI_DEVICE_ID_INTEL_82801GB_IDE, }; Modified: trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_lpc.c =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_lpc.c 2008-10-29 04:52:57 UTC (rev 3704) +++ trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_lpc.c 2008-10-29 13:51:31 UTC (rev 3705) @@ -338,24 +338,23 @@ .ops_pci = &pci_ops, }; -/* ICH7 / ICH7R */ -static const struct pci_driver ich7_ich7r_lpc __pci_driver = { +/* 82801GB/GR/GDH (ICH7/ICH7R/ICH7DH) */ +static const struct pci_driver ich7_ich7r_ich7dh_lpc __pci_driver = { .ops = &device_ops, .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x27b8, + .device = PCI_DEVICE_ID_INTEL_82801GB_LPC, }; -/* ICH7M / ICH7U */ +/* 82801GBM/GU (ICH7-M/ICH7-U) */ static const struct pci_driver ich7m_ich7u_lpc __pci_driver = { .ops = &device_ops, .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x27b9, + .device = PCI_DEVICE_ID_INTEL_82801GBM_LPC, }; -/* ICH7M DH */ +/* 82801GHM (ICH7-M DH) */ static const struct pci_driver ich7m_dh_lpc __pci_driver = { .ops = &device_ops, .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x27bd, + .device = PCI_DEVICE_ID_INTEL_82801GHM_LPC, }; - Modified: trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_nic.c =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_nic.c 2008-10-29 04:52:57 UTC (rev 3704) +++ trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_nic.c 2008-10-29 13:51:31 UTC (rev 3705) @@ -40,11 +40,9 @@ /* 82801GB/GR/GDH/GBM/GHM (ICH7/ICH7R/ICH7DH/ICH7-M/ICH7-M DH) */ /* Note: 82801GU (ICH7-U) doesn't have a NIC. */ -/* PCI ID loaded from EEPROM. If EEPROM is 0, 0x27dc is used */ -static const struct pci_driver i82801gb_nic __pci_driver = { +/* PCI ID loaded from EEPROM. If EEPROM is 0, 0x27dc is used. */ +static const struct pci_driver i82801gx_nic __pci_driver = { .ops = &nic_ops, .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_82801GB_LAN, }; - - Modified: trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_pci.c =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_pci.c 2008-10-29 04:52:57 UTC (rev 3704) +++ trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_pci.c 2008-10-29 13:51:31 UTC (rev 3705) @@ -124,18 +124,18 @@ .ops_pci = &pci_ops, }; - /* Desktop */ +/* 82801BA/CA/DB/EB/ER/FB/FR/FW/FRW/GB/GR/GDH/HB/IB/6300ESB/i3100 */ static const struct pci_driver i82801g_pci __pci_driver = { .ops = &device_ops, - .vendor = 0x8086, - .device = 0x244e, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82801GB_PCI, }; /* Mobile / Ultra Mobile */ +/* 82801BAM/CAM/DBL/DBM/FBM/GBM/GHM/GU/HBM/HEM */ static const struct pci_driver i82801gmu_pci __pci_driver = { .ops = &device_ops, - .vendor = 0x8086, - .device = 0x2448, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82801FBM_PCI, }; - Modified: trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_pcie.c =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_pcie.c 2008-10-29 04:52:57 UTC (rev 3704) +++ trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_pcie.c 2008-10-29 13:51:31 UTC (rev 3705) @@ -84,43 +84,44 @@ .ops_pci = &pci_ops, }; +/* 82801GB/GR/GDH/GBM/GHM (ICH7/ICH7R/ICH7DH/ICH7-M/ICH7-M DH) */ static const struct pci_driver i82801gx_pcie_port1 __pci_driver = { .ops = &device_ops, - .vendor = 0x8086, - .device = 0x27d0, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82801GB_PCIE1, }; +/* 82801GB/GR/GDH/GBM/GHM (ICH7/ICH7R/ICH7DH/ICH7-M/ICH7-M DH) */ static const struct pci_driver i82801gx_pcie_port2 __pci_driver = { .ops = &device_ops, - .vendor = 0x8086, - .device = 0x27d2, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82801GB_PCIE2, }; +/* 82801GB/GR/GDH/GBM/GHM (ICH7/ICH7R/ICH7DH/ICH7-M/ICH7-M DH) */ static const struct pci_driver i82801gx_pcie_port3 __pci_driver = { .ops = &device_ops, - .vendor = 0x8086, - .device = 0x27d4, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82801GB_PCIE3, }; +/* 82801GB/GR/GDH/GBM/GHM (ICH7/ICH7R/ICH7DH/ICH7-M/ICH7-M DH) */ static const struct pci_driver i82801gx_pcie_port4 __pci_driver = { .ops = &device_ops, - .vendor = 0x8086, - .device = 0x27d6, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82801GB_PCIE4, }; +/* 82801GR/GDH/GHM (ICH7R/ICH7DH/ICH7-M DH) */ static const struct pci_driver i82801gx_pcie_port5 __pci_driver = { .ops = &device_ops, - .vendor = 0x8086, - .device = 0x27e0, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82801GR_PCIE5, }; +/* 82801GR/GDH/GHM (ICH7R/ICH7DH/ICH7-M DH) */ static const struct pci_driver i82801gx_pcie_port6 __pci_driver = { .ops = &device_ops, - .vendor = 0x8086, - .device = 0x27e2, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82801GR_PCIE6, }; - - - - - Modified: trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_sata.c =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_sata.c 2008-10-29 04:52:57 UTC (rev 3704) +++ trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_sata.c 2008-10-29 13:51:31 UTC (rev 3705) @@ -145,46 +145,51 @@ }; /* Desktop Non-AHCI and Non-RAID Mode */ +/* 82801GB/GR/GDH (ICH7/ICH7R/ICH7DH) */ static const struct pci_driver i82801gx_sata_normal_driver __pci_driver = { .ops = &sata_ops, .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x27c0, + .device = PCI_DEVICE_ID_INTEL_82801GB_SATA, }; -/* NOTE: Any of the below are not properly supported yet */ +/* NOTE: Any of the below are not properly supported yet. */ /* Desktop AHCI Mode */ +/* 82801GB/GR/GDH (ICH7/ICH7R/ICH7DH) */ static const struct pci_driver i82801gx_sata_ahci_driver __pci_driver = { .ops = &sata_ops, .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x27c1, + .device = PCI_DEVICE_ID_INTEL_82801GB_SATA_AHCI, }; /* Desktop RAID mode */ +/* 82801GB/GR/GDH (ICH7/ICH7R/ICH7DH) */ static const struct pci_driver i82801gx_sata_raid_driver __pci_driver = { .ops = &sata_ops, .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x27c3, + .device = PCI_DEVICE_ID_INTEL_82801GB_SATA_RAID, }; /* Mobile Non-AHCI and Non-RAID Mode */ +/* 82801GBM/GHM (ICH7-M/ICH7-M DH) */ static const struct pci_driver i82801gx_sata_mobile_normal_driver __pci_driver = { .ops = &sata_ops, .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x27c4, + .device = PCI_DEVICE_ID_INTEL_82801GBM_SATA, }; /* Mobile AHCI Mode */ +/* 82801GBM/GHM (ICH7-M/ICH7-M DH) */ static const struct pci_driver i82801gx_sata_mobile_ahci_driver __pci_driver = { .ops = &sata_ops, .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x27c5, + .device = PCI_DEVICE_ID_INTEL_82801GBM_SATA_AHCI, }; /* ICH7M DH Raid Mode */ +/* 82801GHM (ICH7-M DH) */ static const struct pci_driver i82801gx_sata_ich7dh_raid_driver __pci_driver = { .ops = &sata_ops, .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x27c6, + .device = PCI_DEVICE_ID_INTEL_82801GHM_SATA_RAID, }; - Modified: trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_smbus.c =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_smbus.c 2008-10-29 04:52:57 UTC (rev 3704) +++ trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_smbus.c 2008-10-29 13:51:31 UTC (rev 3705) @@ -21,6 +21,7 @@ #include <stdint.h> #include <smbus.h> #include <pci.h> +#include <pci_ids.h> #include <arch/io.h> #include "i82801gx.h" #include "i82801_smbus.h" @@ -56,4 +57,3 @@ .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_82801GB_SMB, }; - Modified: trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_usb.c =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_usb.c 2008-10-29 04:52:57 UTC (rev 3704) +++ trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_usb.c 2008-10-29 13:51:31 UTC (rev 3705) @@ -58,22 +58,23 @@ .device = PCI_DEVICE_ID_INTEL_82801GB_USB1, }; +/* 82801GB/GR/GDH/GBM/GHM/GU (ICH7/ICH7R/ICH7DH/ICH7-M/ICH7-M DH/ICH7-U) */ static const struct pci_driver i82801gb_usb2 __pci_driver = { .ops = &usb_ops, .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_82801GB_USB2, }; +/* 82801GB/GR/GDH/GBM/GHM/GU (ICH7/ICH7R/ICH7DH/ICH7-M/ICH7-M DH/ICH7-U) */ static const struct pci_driver i82801gb_usb3 __pci_driver = { .ops = &usb_ops, .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_82801GB_USB3, }; +/* 82801GB/GR/GDH/GBM/GHM/GU (ICH7/ICH7R/ICH7DH/ICH7-M/ICH7-M DH/ICH7-U) */ static const struct pci_driver i82801gb_usb4 __pci_driver = { .ops = &usb_ops, .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_82801GB_USB4, }; - - Modified: trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_usb_ehci.c =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_usb_ehci.c 2008-10-29 04:52:57 UTC (rev 3704) +++ trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_usb_ehci.c 2008-10-29 13:51:31 UTC (rev 3705) @@ -76,9 +76,9 @@ .ops_pci = &lops_pci, }; -/* 82801Gx */ -static const struct pci_driver i82801ex_usb_ehci __pci_driver = { +/* 82801GB/GR/GDH/GBM/GHM/GU (ICH7/ICH7R/ICH7DH/ICH7-M/ICH7-M DH/ICH7-U) */ +static const struct pci_driver i82801gx_usb_ehci __pci_driver = { .ops = &usb_ehci_ops, .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x27cc, + .device = PCI_DEVICE_ID_INTEL_82801GB_EHCI, };

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SB600 SPI driver for flashrom and sst25vf040
by Wang, Qingpei 29 Oct '08

29 Oct '08

Hi, Sean Have you finished the patch about SB600 SPI driver? I found that the patch you posted can not be compiled, and I had made another two patches, one is for SB600 SPI and the other one is for sst25vf040. If you have any latest work, please tell me, maybe we can merge our patches into one. Thanks Jason Wang BeiJing Technology Development Center Advanced Micro Devices (AMD)

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piix4: cmos memory bank 2
by Andriy Gapon 29 Oct '08

29 Oct '08

Was the following a revelation only to me or is it a generally obscure knowledge? PIIX4 documentation says that bit 2 of PCI config register 0xCB (of function 0) enables access to CMOS memory bank2 via IO ports 0x72 and 0x73 similarly to regular CMOS memory access via 0x70/0x71. I tested this on my 440BX-based system and this does indeed work: $ od -t xC extcmos.img 0000000 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff * 0000040 aa 04 ff ff ff ff ff 83 06 ff ff ff ff ff ff ff 0000060 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff * 0000200 Most registers are 0xff, but several contain some data, e.g. "83 06" seems to be 0x683, ID of my Pentium III CPU. When bit 2 of 0xCB is zero, then 0x72/0x73 ports seem to provide access to regular CMOS just like 0x70/0x71. -- Andriy Gapon

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Re: [coreboot] [PATCH] CN700/VT8237R stage2 (Corey Osgood)
by JasonZhao＠viatech.com.cn 29 Oct '08

29 Oct '08

Maybe you can try more times with different values of these MACRO? default DCACHE_RAM_BASE=0xffef0000 default DCACHE_RAM_SIZE=0x8000 default XIP_ROM_SIZE = 128 * 1024 One time, we have our DDR2 init process stopped on one of VIA's board, and after changing the XIP_ROM_SIZE=128K to 192K (128+64 in two var-mtrr-seg), this problem disappear. ------------------------------ Message: 2 Date: Wed, 29 Oct 2008 04:02:08 -0400 From: "Corey Osgood" <corey.osgood(a)gmail.com> Subject: [coreboot] [PATCH] CN700/VT8237R stage2 To: Coreboot <coreboot(a)coreboot.org> Message-ID: <dd3c80060810290102o7b28a867y4b103e8b6ee4c621(a)mail.gmail.com> Content-Type: text/plain; charset="iso-8859-1" Attached patches for cn700, vt8237(r/s), and the mainboard, Jetway J7F2, along with a boot log. Currently, we're stuck in a reboot loop and I have no idea why, seems to be related to CAR disabling (this wasn't happening when disable_car was a noop). Carl-Daniel, any ideas? -Corey

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r3704 build service
by coreboot information 29 Oct '08

29 Oct '08

Dear coreboot readers! This is the automated build check service of coreboot. The developer "stepan" checked in revision 3704 to the coreboot source repository and caused the following changes: Change Log: Support for the Kontron 986LCD-M mainboard series. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Build Log: Compilation of iwill:dk8x has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3704&device=dk8x&vendor=iw… If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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r3704 - in trunk/coreboot-v2: src/mainboard src/mainboard/kontron src/mainboard/kontron/986lcd-m targets targets/kontron targets/kontron/986lcd-m
by svn＠coreboot.org 29 Oct '08

29 Oct '08

Author: stepan Date: 2008-10-29 05:52:57 +0100 (Wed, 29 Oct 2008) New Revision: 3704 Added: trunk/coreboot-v2/src/mainboard/kontron/ trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/ trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/Config.lb trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/Options.lb trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/acpi_tables.c trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/auto.c trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/chip.h trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/cmos.layout trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/debug.c trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/dmi.h trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/dsdt.dsl trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/fadt.c trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/irq_tables.c trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/mainboard.c trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/mptable.c trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/power_reset_check.c trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/reset.c trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/rtl8168.c trunk/coreboot-v2/targets/kontron/ trunk/coreboot-v2/targets/kontron/986lcd-m/ trunk/coreboot-v2/targets/kontron/986lcd-m/Config-abuild.lb trunk/coreboot-v2/targets/kontron/986lcd-m/Config.lb Log: Support for the Kontron 986LCD-M mainboard series. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Added: trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/Config.lb (rev 0) +++ trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/Config.lb 2008-10-29 04:52:57 UTC (rev 3704) @@ -0,0 +1,284 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## +## This program is free software; you can redistribute it and/or +## modify it under the terms of the GNU General Public License as +## published by the Free Software Foundation; version 2 of +## the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +## MA 02110-1301 USA +## + +## +## This mainboard requires DCACHE_AS_RAM enabled. It won't work without. +## + +## +## Only use the option table in a normal image +## +default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE + +## +## Compute the location and size of where this firmware image +## (coreboot plus bootloader) will live in the boot rom chip. +## +if USE_FALLBACK_IMAGE + default ROM_SECTION_SIZE = FALLBACK_SIZE + default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE ) +else + default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) + default ROM_SECTION_OFFSET = 0 +end + +## +## Compute the start location and size size of +## The coreboot bootloader. +## +default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) +default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) + +## +## Compute where this copy of coreboot will start in the boot rom +## +default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) + +## +## Compute a range of ROM that can cached to speed up coreboot, +## execution speed. +## +## XIP_ROM_SIZE must be a power of 2. +## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE +## +default XIP_ROM_SIZE=(64*1024) +default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE ) + +## +## Set all of the defaults for an x86 architecture +## + +arch i386 end + +## +## Build the objects we have code for in this directory. +## + +driver mainboard.o +driver rtl8168.o +if HAVE_MP_TABLE object mptable.o end +if HAVE_PIRQ_TABLE object irq_tables.o end + +if HAVE_ACPI_TABLES + object fadt.o + object acpi_tables.o + makerule dsdt.c + depends "$(MAINBOARD)/dsdt.dsl" + action "iasl -p $(PWD)/dsdt -tc $(MAINBOARD)/dsdt.dsl" + action "mv $(PWD)/dsdt.hex dsdt.c" + end + object ./dsdt.o +end + +object reset.o + +if CONFIG_USE_INIT + +makerule ./auto.o + depends "$(MAINBOARD)/auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o auto.o" +end + +else + +makerule ./auto.inc + depends "$(MAINBOARD)/auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@" + action "perl -e 's/.rodata/.rom.data/g' -pi $@" + action "perl -e 's/.text/.section .rom.text/g' -pi $@" +end + +end + +## +## Build our 16 bit and 32 bit coreboot entry code +## +mainboardinit cpu/x86/16bit/entry16.inc +mainboardinit cpu/x86/32bit/entry32.inc +ldscript /cpu/x86/16bit/entry16.lds +if CONFIG_USE_INIT + ldscript /cpu/x86/32bit/entry32.lds + ldscript /cpu/x86/car/cache_as_ram.lds +end + +## +## Build our reset vector (This is where coreboot is entered) +## +if USE_FALLBACK_IMAGE + mainboardinit cpu/x86/16bit/reset16.inc + ldscript /cpu/x86/16bit/reset16.lds +else + mainboardinit cpu/x86/32bit/reset32.inc + ldscript /cpu/x86/32bit/reset32.lds +end + + +## +## Include an id string (For safe flashing) +## +mainboardinit arch/i386/lib/id.inc +ldscript /arch/i386/lib/id.lds + +## +## Setup Cache-As-Ram +## +mainboardinit cpu/intel/model_6ex/cache_as_ram.inc + +### +### This is the early phase of coreboot startup +### Things are delicate and we test to see if we should +### failover to another image. +### +if USE_FALLBACK_IMAGE + ldscript /arch/i386/lib/failover.lds +end + +### +### O.k. We aren't just an intermediary anymore! +### + +if CONFIG_USE_INIT +initobject auto.o +else +mainboardinit ./auto.inc +end + +## +## Include the secondary Configuration files +## +dir /pc80 +config chip.h + +chip northbridge/intel/i945 + + device apic_cluster 0 on + chip cpu/intel/socket_mFCPGA478 + device apic 0 on end + end + end + + device pci_domain 0 on + device pci 00.0 on end # host bridge + device pci 01.0 off end # i945 PCIe root port + chip drivers/pci/onboard + device pci 02.0 on end # vga controller + register "rom_address" = "0xfff00000" + end + device pci 02.1 on end # display controller + + chip southbridge/intel/i82801gx + register "ide_legacy_combined" = "0x1" + register "ide_enable_primary" = "0x1" + register "ide_enable_secondary" = "0x1" + register "sata_ahci" = "0x0" + + device pci 1b.0 on end # High Definition Audio + device pci 1c.0 on end # PCIe + device pci 1c.1 on end # PCIe + device pci 1c.2 on end # PCIe + #device pci 1c.3 off end # PCIe port 4 + #device pci 1c.4 off end # PCIe port 5 + #device pci 1c.5 off end # PCIe port 6 + device pci 1d.0 on end # USB UHCI + device pci 1d.1 on end # USB UHCI + device pci 1d.2 on end # USB UHCI + device pci 1d.3 on end # USB UHCI + device pci 1d.7 on end # USB2 EHCI + device pci 1e.0 on end # PCI bridge + #device pci 1e.2 off end # AC'97 Audio + #device pci 1e.3 off end # AC'97 Modem + device pci 1f.0 on # LPC bridge + chip superio/winbond/w83627thg + device pnp 2e.0 off # Floppy + end + device pnp 2e.1 off # Parport + end + device pnp 2e.2 on + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on + io 0x60 = 0x2f8 + irq 0x70 = 3 + irq 0xf1 = 4 # set IRMODE 0 # XXX not an irq + end + device pnp 2e.5 on # Keyboard+Mouse + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + irq 0xf0 = 0x82 # HW accel A20. + end + device pnp 2e.7 on # GPIO1, GAME, MIDI + io 0x62 = 0x330 + irq 0x70 = 9 + end + device pnp 2e.8 on # GPIO2 + # all default + end + device pnp 2e.9 on # GPIO3/4 + irq 0x30 = 0x03 # does this work? + irq 0xf0 = 0xfb # set inputs/outputs + irq 0xf1 = 0x66 + end + device pnp 2e.a off # ACPI + end + device pnp 2e.b on # HWM + io 0x60 = 0xa00 + irq 0x70 = 0 + end + + end + chip superio/winbond/w83627thg + device pnp 4e.0 off # Floppy + end + device pnp 4e.1 off # Parport + end + device pnp 4e.2 on # COM3 + io 0x60 = 0x3e8 + irq 0x70 = 11 + end + device pnp 4e.3 on # COM4 + io 0x60 = 0x2e8 + irq 0x70 = 10 + end + device pnp 4e.5 off # Keyboard + end + device pnp 4e.7 off # GPIO1, GAME, MIDI + end + device pnp 4e.8 off # GPIO2 + end + device pnp 4e.9 off # GPIO3/4 + end + device pnp 4e.a off # ACPI + end + device pnp 4e.b off # HWM + end + end + + end + #device pci 1f.1 off end # IDE + device pci 1f.2 on end # SATA + device pci 1f.3 on end # SMBus + #device pci 1f.4 off end # Realtek ID Codec + end + end +end Added: trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/Options.lb (rev 0) +++ trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/Options.lb 2008-10-29 04:52:57 UTC (rev 3704) @@ -0,0 +1,311 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## +## This program is free software; you can redistribute it and/or +## modify it under the terms of the GNU General Public License as +## published by the Free Software Foundation; version 2 of +## the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +## MA 02110-1301 USA +## + +# Tables +uses HAVE_MP_TABLE +uses HAVE_PIRQ_TABLE +uses IRQ_SLOT_COUNT +uses HAVE_OPTION_TABLE +uses USE_OPTION_TABLE +uses LB_CKS_RANGE_START +uses LB_CKS_RANGE_END +uses LB_CKS_LOC +uses HAVE_ACPI_TABLES +# SMP +uses CONFIG_SMP +uses CONFIG_LOGICAL_CPUS +uses CONFIG_AP_IN_SIPI_WAIT +uses CONFIG_MAX_CPUS +uses CONFIG_MAX_PHYSICAL_CPUS +uses CONFIG_IOAPIC +# Image Size +uses USE_FALLBACK_IMAGE +uses HAVE_FALLBACK_BOOT +uses FALLBACK_SIZE +uses ROM_SIZE +uses ROM_SECTION_SIZE +uses ROM_IMAGE_SIZE +uses ROM_SECTION_SIZE +uses ROM_SECTION_OFFSET +# Payload +uses CONFIG_ROM_PAYLOAD +uses CONFIG_ROM_PAYLOAD_START +uses CONFIG_COMPRESSED_PAYLOAD_LZMA +uses CONFIG_PRECOMPRESSED_PAYLOAD +uses PAYLOAD_SIZE +# Build Internals +uses _RAMBASE +uses _ROMBASE +uses STACK_SIZE +uses HEAP_SIZE +uses CONFIG_CHIP_NAME +uses USE_DCACHE_RAM +uses DCACHE_RAM_BASE +uses DCACHE_RAM_SIZE +uses CONFIG_USE_INIT +uses CONFIG_USE_PRINTK_IN_CAR +uses XIP_ROM_BASE +uses XIP_ROM_SIZE +uses HAVE_HARD_RESET +uses HAVE_SMI_HANDLER +uses CONFIG_PCIE_CONFIGSPACE_HOLE +# +uses MAINBOARD +uses MAINBOARD_PART_NUMBER +uses MAINBOARD_VENDOR +uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID +uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID +# Timers +uses CONFIG_UDELAY_TSC +uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 +# Console +uses CONFIG_CONSOLE_SERIAL8250 +uses TTYS0_BAUD +uses TTYS0_BASE +uses TTYS0_LCS +uses DEFAULT_CONSOLE_LOGLEVEL +uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_CONSOLE_VGA +uses CONFIG_PCI_ROM_RUN +# Toolchain +uses CC +uses HOSTCC +uses CROSS_COMPILE +uses OBJCOPY +# Tweaks +uses CONFIG_GDB_STUB +uses MAX_REBOOT_CNT +uses USE_WATCHDOG_ON_BOOT +uses COREBOOT_EXTRA_VERSION +uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL + +### +### Build options +### + +## +## +default MAX_REBOOT_CNT=3 + +## +## Use the watchdog to break out of a lockup condition +## +default USE_WATCHDOG_ON_BOOT=0 + +## +## ROM_SIZE is the size of boot ROM that this board will use. +## +default ROM_SIZE=1024*1024 + + +## +## Build code for the fallback boot +## +default HAVE_FALLBACK_BOOT=1 + +## +## Delay timer options +## Use timer2 +## +default CONFIG_UDELAY_TSC=1 +default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1 + +## +## Build code to reset the motherboard from coreboot +## +default HAVE_HARD_RESET=1 + +## +## Build SMI handler +## +default HAVE_SMI_HANDLER=1 + +## +## Leave a hole for mmapped PCIe config space +## + +default CONFIG_PCIE_CONFIGSPACE_HOLE=1 + +## +## Build code to export a programmable irq routing table +## +default HAVE_PIRQ_TABLE=1 +default IRQ_SLOT_COUNT=18 + +## +## Build code to export an x86 MP table +## Useful for specifying IRQ routing values +## +default HAVE_MP_TABLE=1 + +## +## Build code to provide ACPI support +## +default HAVE_ACPI_TABLES=1 + +## +## Build code to export a CMOS option table +## +default HAVE_OPTION_TABLE=1 + +## +## Move the default coreboot cmos range off of AMD RTC registers +## +default LB_CKS_RANGE_START=49 +default LB_CKS_RANGE_END=122 +default LB_CKS_LOC=123 + +#VGA Console +default CONFIG_CONSOLE_VGA=1 +default CONFIG_PCI_ROM_RUN=1 + +## +## Build code for SMP support +## Only worry about 2 micro processors +## +default CONFIG_SMP=1 +default CONFIG_MAX_CPUS=4 +default CONFIG_MAX_PHYSICAL_CPUS=2 +default CONFIG_LOGICAL_CPUS=1 +default CONFIG_AP_IN_SIPI_WAIT=1 + +## +## enable CACHE_AS_RAM specifics +## +default USE_DCACHE_RAM=1 +default DCACHE_RAM_SIZE=0x8000 +default DCACHE_RAM_BASE=( 0xfff00000 - DCACHE_RAM_SIZE - 1024*1024) +default CONFIG_USE_PRINTK_IN_CAR=1 + +## +## Build code to setup a generic IOAPIC +## +default CONFIG_IOAPIC=1 + +## +## Clean up the motherboard id strings +## +default MAINBOARD_PART_NUMBER="986LCD-M" +default MAINBOARD_VENDOR= "KONTRON" + +### +### coreboot layout values +### + +## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default ROM_IMAGE_SIZE = 65536 + +## +## Use a small 8K stack +## +default STACK_SIZE=0x2000 + +## +## Use a small 32K heap +## +default HEAP_SIZE=0x8000 + + +### +### Compute the location and size of where this firmware image +### (coreboot plus bootloader) will live in the boot rom chip. +### +default FALLBACK_SIZE=131072 + +## +## coreboot C code runs at this location in RAM +## +default _RAMBASE=0x00004000 + +## +## Load the payload from the ROM +## +default CONFIG_ROM_PAYLOAD=1 + +### +### Defaults of options that you may want to override in the target config file +### + +## +## The default compiler +## +default CC="$(CROSS_COMPILE)gcc -m32" +default HOSTCC="gcc" + +## +## Disable the gdb stub by default +## +default CONFIG_GDB_STUB=0 + +## +## The Serial Console +## + +# To Enable the Serial Console +default CONFIG_CONSOLE_SERIAL8250=1 + +## Select the serial console baud rate +default TTYS0_BAUD=115200 +#default TTYS0_BAUD=57600 +#default TTYS0_BAUD=38400 +#default TTYS0_BAUD=19200 +#default TTYS0_BAUD=9600 +#default TTYS0_BAUD=4800 +#default TTYS0_BAUD=2400 +#default TTYS0_BAUD=1200 + +# Select the serial console base port +default TTYS0_BASE=0x3f8 + +# Select the serial protocol +# This defaults to 8 data bits, 1 stop bit, and no parity +default TTYS0_LCS=0x3 + +## +### Select the coreboot loglevel +## +## EMERG 1 system is unusable +## ALERT 2 action must be taken immediately +## CRIT 3 critical conditions +## ERR 4 error conditions +## WARNING 5 warning conditions +## NOTICE 6 normal but significant condition +## INFO 7 informational +## DEBUG 8 debug-level messages +## SPEW 9 Way too many details + +## Request this level of debugging output +default DEFAULT_CONSOLE_LOGLEVEL=5 +## At a maximum only compile in this level of debugging +default MAXIMUM_CONSOLE_LOGLEVEL=9 + +## +## Select power on after power fail setting +default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" + +## +## chip name +## +default CONFIG_CHIP_NAME=1 + + +### End Options.lb +end Added: trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/acpi_tables.c =================================================================== --- trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/acpi_tables.c (rev 0) +++ trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/acpi_tables.c 2008-10-29 04:52:57 UTC (rev 3704) @@ -0,0 +1,295 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <string.h> +#include <console/console.h> +#include <arch/acpi.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include "dmi.h" + +extern unsigned char AmlCode[]; + +typedef struct acpi_oemb { + acpi_header_t header; + u8 ss; + u16 iost; + u32 topm; + u32 roms; + u32 mg1b; + u32 mg1l; + u32 mg2b; + u32 mg2l; + u8 rsvd; + u8 dmax; + u32 hpta; + u32 cpb0; + u32 cpb1; + u32 cpb2; + u32 cpb3; + u8 assb; + u8 aotb; + u32 aaxb; + u8 smif; + u8 dtse; + u8 dts1; + u8 dts2; + u8 mpen; +} __attribute__((packed)) acpi_oemb_t; + +void acpi_create_oemb(acpi_oemb_t *oemb) +{ + acpi_header_t *header = &(oemb->header); + unsigned long tolud; + + memset (oemb, 0, sizeof(oemb)); + + /* fill out header fields */ + memcpy(header->signature, "OEMB", 4); + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, "COREBOOT", 8); + memcpy(header->asl_compiler_id, ASLC, 4); + + header->length = sizeof(acpi_oemb_t); + header->revision = 1; + + oemb->ss = 0x09; // ss1 + ss 4 + oemb->iost = 0x0403; // ?? + + tolud = pci_read_config32(dev_find_slot(0, PCI_DEVFN(2, 0)), 0x5c); + oemb->topm = tolud; + + oemb->roms = 0xfff00000; // 1M hardcoded + + oemb->mg1b = 0x000d0000; + oemb->mg1l = 0x00010000; + + oemb->mg2b = tolud; + oemb->mg2l = 0-tolud; + + oemb->dmax = 0x87; + oemb->hpta = 0x000e36c0; + + header->checksum = + acpi_checksum((void *) oemb, sizeof(acpi_oemb_t)); + +}; + +unsigned long acpi_fill_mcfg(unsigned long current) +{ +#if 0 + device_t dev; + u64 mmcfg; + + dev = dev_find_device(0x1106, 0x324b, 0); // 0:0x13.0 + if (!dev) + return current; + + // MMCFG not supported or not enabled. + if ((pci_read_config8(dev, 0x40) & 0xC0) != 0xC0) + return current; + + mmcfg = ((u64) pci_read_config8(dev, 0x41)) << 28; + if (!mmcfg) + return current; + + current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) current, mmcfg, 0x0, 0x0, 0xff); +#endif + return current; +} + +void acpi_create_intel_hpet(acpi_hpet_t * hpet) +{ +#define HPET_ADDR 0xfe800000ULL + acpi_header_t *header = &(hpet->header); + acpi_addr_t *addr = &(hpet->addr); + + memset((void *) hpet, 0, sizeof(acpi_hpet_t)); + + /* fill out header fields */ + memcpy(header->signature, HPET_NAME, 4); + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, "COREBOOT", 8); + memcpy(header->asl_compiler_id, ASLC, 4); + + header->length = sizeof(acpi_hpet_t); + header->revision = 1; + + /* fill out HPET address */ + // XXX factory bios just puts an address here -- who's right? + addr->space_id = 0; /* Memory */ + addr->bit_width = 64; + addr->bit_offset = 0; + addr->addrl = HPET_ADDR & 0xffffffff; + addr->addrh = HPET_ADDR >> 32; + + hpet->id = 0x80861234; /* VIA */ + hpet->number = 0x00; + hpet->min_tick = 0x0090; + + header->checksum = + acpi_checksum((void *) hpet, sizeof(acpi_hpet_t)); +} + + + +#define IO_APIC_ADDR 0xfec00000UL + +unsigned long acpi_fill_madt(unsigned long current) +{ + /* Local Apic */ + current += acpi_create_madt_lapic((acpi_madt_lapic_t *) current, 1, 0); + // This one is for the second core... Will it hurt? + current += acpi_create_madt_lapic((acpi_madt_lapic_t *) current, 2, 1); + + /* IOAPIC */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 2, IO_APIC_ADDR, 0); + + /* INT_SRC_OVR */ + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current, 0, 0, 2, 0); + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current, 0, 9, 9, 0x000d); // high/level + + return current; +} + +unsigned long acpi_fill_srat(unsigned long current) +{ + /* No NUMA, no SRAT */ + return current; +} + + +#define ALIGN_CURRENT current = ((current + 0x0f) & -0x10) +unsigned long write_acpi_tables(unsigned long start) +{ + unsigned long current; + int i; + acpi_rsdp_t *rsdp; + acpi_rsdt_t *rsdt; + acpi_hpet_t *hpet; + acpi_madt_t *madt; + acpi_mcfg_t *mcfg; + acpi_fadt_t *fadt; + acpi_facs_t *facs; + acpi_oemb_t *oemb; + acpi_header_t *dsdt; + + /* Align ACPI tables to 16byte */ + start = (start + 0x0f) & -0x10; + current = start; + + printk_info("ACPI: Writing ACPI tables at %lx.\n", start); + + /* We need at least an RSDP and an RSDT Table */ + rsdp = (acpi_rsdp_t *) current; + current += sizeof(acpi_rsdp_t); + ALIGN_CURRENT; + rsdt = (acpi_rsdt_t *) current; + current += sizeof(acpi_rsdt_t); + ALIGN_CURRENT; + + /* clear all table memory */ + memset((void *) start, 0, current - start); + + acpi_write_rsdp(rsdp, rsdt); + acpi_write_rsdt(rsdt); + + /* + * We explicitly add these tables later on: + */ +#if 0 + printk_debug("ACPI: * HPET\n"); + + hpet = (acpi_hpet_t *) current; + current += sizeof(acpi_hpet_t); + ALIGN_CURRENT; + acpi_create_intel_hpet(hpet); + acpi_add_table(rsdt, hpet); +#endif + /* If we want to use HPET Timers Linux wants an MADT */ + printk_debug("ACPI: * MADT\n"); + + madt = (acpi_madt_t *) current; + acpi_create_madt(madt); + current += madt->header.length; + ALIGN_CURRENT; + acpi_add_table(rsdt, madt); +#if 0 + printk_debug("ACPI: * MCFG\n"); + mcfg = (acpi_mcfg_t *) current; + acpi_create_mcfg(mcfg); + current += mcfg->header.length; + ALIGN_CURRENT; + acpi_add_table(rsdt, mcfg); +#endif + + printk_debug("ACPI: * OEMB\n"); + oemb=(acpi_oemb_t *)current; + current += sizeof(acpi_oemb_t); + ALIGN_CURRENT; + acpi_create_oemb(oemb); + acpi_add_table(rsdt, oemb); + + printk_debug("ACPI: * FACS\n"); + facs = (acpi_facs_t *) current; + current += sizeof(acpi_facs_t); + ALIGN_CURRENT; + acpi_create_facs(facs); + + dsdt = (acpi_header_t *) current; + current += ((acpi_header_t *) AmlCode)->length; + ALIGN_CURRENT; + memcpy((void *) dsdt, (void *) AmlCode, + ((acpi_header_t *) AmlCode)->length); + +#if 1 + for (i=0; i < dsdt->length; i++) { + if (*(u32*)(((u32)dsdt) + i) == 0xC0DEBABE) { + printk_debug("ACPI: Patching up DSDT at offset 0x%04x -> 0x%08x\n", i, 0x24 + (u32)oemb); + *(u32*)(((u32)dsdt) + i) = 0x24 + (u32)oemb; + break; + } + } + + /* We patched up the DSDT, so we need to recalculate the checksum */ + dsdt->checksum = 0; + dsdt->checksum = acpi_checksum(dsdt, dsdt->length); +#endif + + printk_debug("ACPI: * DSDT @ %08x Length %x\n", dsdt, + dsdt->length); + + printk_debug("ACPI: * FADT\n"); + fadt = (acpi_fadt_t *) current; + current += sizeof(acpi_fadt_t); + ALIGN_CURRENT; + + acpi_create_fadt(fadt, facs, dsdt); + acpi_add_table(rsdt, fadt); + printk_debug("current = %x\n", current); + + printk_debug("ACPI: * DMI (Linux workaround)\n"); + memcpy((void *)0xfff80, dmi_table, DMI_TABLE_SIZE); + + printk_info("ACPI: done.\n"); + return current; +} Added: trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/auto.c (rev 0) +++ trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/auto.c 2008-10-29 04:52:57 UTC (rev 3704) @@ -0,0 +1,364 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +// __ROMCC__ means: use "unsigned" for device, not a struct. +#define __ROMCC__ + +#include <stdint.h> +#include <arch/io.h> +#include <arch/romcc_io.h> +#include <device/pci_def.h> +#include <device/pnp_def.h> +#include <cpu/x86/lapic.h> + +#include "superio/winbond/w83627thg/w83627thg.h" + +#include "option_table.h" +#include "pc80/mc146818rtc_early.c" + +#include "pc80/serial.c" +#include "arch/i386/lib/console.c" +#include <cpu/x86/bist.h> + +#include "ram/ramtest.c" +#include "southbridge/intel/i82801gx/i82801gx_early_smbus.c" +#include "reset.c" +#include "superio/winbond/w83627thg/w83627thg_early_serial.c" + +#include "northbridge/intel/i945/udelay.c" + +#if CONFIG_USE_INIT == 0 +#include "lib/memcpy.c" +#endif + +#define SERIAL_DEV PNP_DEV(0x2e, W83627THG_SP1) + +#include "northbridge/intel/i945/ich7.h" +static void setup_ich7_gpios(void) +{ + /* TODO: This is highly board specific and should be moved */ + printk_debug(" GPIOS..."); + /* General Registers */ + outl(0x1f1ff7c0, DEFAULT_GPIOBASE + 0x00); /* GPIO_USE_SEL */ + outl(0xe0e8efc3, DEFAULT_GPIOBASE + 0x04); /* GP_IO_SEL */ + outl(0xebffeeff, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */ + /* Output Control Registers */ + outl(0x00000000, DEFAULT_GPIOBASE + 0x18); /* GPO_BLINK */ + /* Input Control Registers */ + outl(0x00002180, DEFAULT_GPIOBASE + 0x2c); /* GPI_INV */ + outl(0x000000ff, DEFAULT_GPIOBASE + 0x30); /* GPIO_USE_SEL2 */ + outl(0x00000030, DEFAULT_GPIOBASE + 0x34); /* GP_IO_SEL2 */ + outl(0x00010035, DEFAULT_GPIOBASE + 0x38); /* GP_LVL */ +} + +#include "northbridge/intel/i945/early_init.c" + +static inline int spd_read_byte(unsigned device, unsigned address) +{ + return smbus_read_byte(device, address); +} + +/* Usually system firmware turns off system memory clock signals to + * unused SO-DIMM slots to reduce EMI and power consumption. + * However, the Kontron 986LCD-M does not like unused clock signals to + * be disabled. If other similar mainboard occur, it would make sense + * to make this an entry in the sysinfo structure, and pre-initialize that + * structure in the mainboard's auto.c main() function. For now a + * #define will do. + */ +#define OVERRIDE_CLOCK_DISABLE 1 +#include "northbridge/intel/i945/raminit.h" +#include "northbridge/intel/i945/raminit.c" +#include "northbridge/intel/i945/reset_test.c" +#include "northbridge/intel/i945/errata.c" +#include "debug.c" + +static void ich7_enable_lpc(void) +{ + // Enable Serial IRQ + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0); + // Set COM1/COM2 decode range + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010); + // Enable COM1/COM2/KBD/SuperIO1+2 + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x340b); + // Enable HWM at 0xa00 + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x84, 0x0a01); + // COM3 decode + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x000403e9); + // COM4 decode + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x000402e9); + // io 0x300 decode + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x00000301); +} + + +/* This box has two superios, so enabling serial becomes slightly excessive. + * We disable a lot of stuff to make sure that there are no conflicts between + * the two. Also set up the GPIOs from the beginning. This is the "no schematic + * but safe anyways" method. + */ +static void early_superio_config_w83627thg(void) +{ + device_t dev; + + dev=PNP_DEV(0x2e, W83627THG_SP1); + pnp_enter_ext_func_mode(dev); + + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, 0x3f8); + pnp_set_irq(dev, PNP_IDX_IRQ0, 4); + pnp_set_enable(dev, 1); + + dev=PNP_DEV(0x2e, W83627THG_SP2); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, 0x2f8); + pnp_set_irq(dev, PNP_IDX_IRQ0, 3); + // pnp_write_config(dev, 0xf1, 4); // IRMODE0 + pnp_set_enable(dev, 1); + + dev=PNP_DEV(0x2e, W83627THG_KBC); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, 0x60); + pnp_set_iobase(dev, PNP_IDX_IO1, 0x64); + // pnp_write_config(dev, 0xf0, 0x82); + pnp_set_enable(dev, 1); + + dev=PNP_DEV(0x2e, W83627THG_GAME_MIDI_GPIO1); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_write_config(dev, 0xf5, 0xff); // invert all GPIOs + pnp_set_enable(dev, 1); + + dev=PNP_DEV(0x2e, W83627THG_GPIO2); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 1); // Just enable it + + dev=PNP_DEV(0x2e, W83627THG_GPIO3); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_write_config(dev, 0xf0, 0xfb); // GPIO bit 2 is output + pnp_write_config(dev, 0xf1, 0x00); // GPIO bit 2 is 0 + pnp_write_config(dev, 0x30, 0x03); // Enable GPIO3+4. pnp_set_enable is not sufficient + + dev=PNP_DEV(0x2e, W83627THG_FDC); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + + dev=PNP_DEV(0x2e, W83627THG_PP); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + + pnp_exit_ext_func_mode(dev); + + dev=PNP_DEV(0x4e, W83627THG_SP1); + pnp_enter_ext_func_mode(dev); + + pnp_set_logical_device(dev); // Set COM3 to sane non-conflicting values + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, 0x3e8); + pnp_set_irq(dev, PNP_IDX_IRQ0, 11); + pnp_set_enable(dev, 1); + + dev=PNP_DEV(0x4e, W83627THG_SP2); + pnp_set_logical_device(dev); // Set COM4 to sane non-conflicting values + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, 0x2e8); + pnp_set_irq(dev, PNP_IDX_IRQ0, 10); + pnp_set_enable(dev, 1); + + dev=PNP_DEV(0x4e, W83627THG_FDC); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + + dev=PNP_DEV(0x4e, W83627THG_PP); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + + dev=PNP_DEV(0x4e, W83627THG_KBC); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, 0x00); + pnp_set_iobase(dev, PNP_IDX_IO1, 0x00); + + pnp_exit_ext_func_mode(dev); +} + +static void rcba_config(void) +{ + /* Set up virtual channel 0 */ + //RCBA32(0x0014) = 0x80000001; + //RCBA32(0x001c) = 0x03128010; + + /* Device 1f interrupt pin register */ + RCBA32(0x3100) = 0x00042210; + /* Device 1d interrupt pin register */ + RCBA32(0x310c) = 0x00214321; + + /* dev irq route register */ + RCBA16(0x3140) = 0x0132; + RCBA16(0x3142) = 0x3241; + RCBA16(0x3144) = 0x0237; + RCBA16(0x3146) = 0x3210; + RCBA16(0x3148) = 0x3210; + + /* Enable IOAPIC */ + RCBA8(0x31ff) = 0x03; + + /* Enable upper 128bytes of CMOS */ + RCBA32(0x3400) = (1 << 2); + + /* Disable unused devices */ + RCBA32(0x3418) = 0x000e0063; + + /* Enable PCIe Root Port Clock Gate */ + // RCBA32(0x341c) = 0x00000001; +} + +static void early_ich7_init(void) +{ + uint8_t reg8; + uint32_t reg32; + + // program secondary mlt XXX byte? + pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20); + + // reset rtc power status + reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4); + reg8 &= ~(1 << 2); + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8); + + // usb transient disconnect + reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad); + reg8 |= (3 << 0); + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8); + + reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc); + reg32 |= (1 << 29) | (1 << 17); + pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32); + + reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc); + reg32 |= (1 << 31) | (1 << 27); + pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32); + + RCBA32(0x0088) = 0x0011d000; + RCBA16(0x01fc) = 0x060f; + RCBA32(0x01f4) = 0x86000040; + RCBA32(0x0214) = 0x10030549; + RCBA32(0x0218) = 0x00020504; + RCBA8(0x0220) = 0xc5; + reg32 = RCBA32(0x3410); + reg32 |= (1 << 6); + RCBA32(0x3410) = reg32; + reg32 = RCBA32(0x3430); + reg32 &= ~(3 << 0); + reg32 |= (1 << 0); + RCBA32(0x3430) = reg32; + RCBA32(0x3418) |= (1 << 0); + RCBA16(0x0200) = 0x2008; + RCBA8(0x2027) = 0x0d; + RCBA16(0x3e08) |= (1 << 7); + RCBA16(0x3e48) |= (1 << 7); + RCBA32(0x3e0e) |= (1 << 7); + RCBA32(0x3e4e) |= (1 << 7); + + // next step only on ich7m b0 and later: + reg32 = RCBA32(0x2034); + reg32 &= ~(0x0f << 16); + reg32 |= (5 << 16); + RCBA32(0x2034) = reg32; +} + +#if USE_FALLBACK_IMAGE == 1 +#include "southbridge/intel/i82801gx/cmos_failover.c" +#endif + +void real_main(unsigned long bist) +{ + int boot_mode = 0; + + if (bist == 0) { + enable_lapic(); + } + + ich7_enable_lpc(); + early_superio_config_w83627thg(); + + /* Set up the console */ + uart_init(); + console_init(); + + /* Halt if there was a built in self test failure */ + report_bist_failure(bist); + + if (MCHBAR16(SSKPD) == 0xCAFE) { + printk_debug("soft reset detected.\n"); + boot_mode = 1; + } + + /* Perform some early chipset initialization required + * before RAM initialization can work + */ + i945_early_initialization(); + + /* Enable SPD ROMs and DDR-II DRAM */ + enable_smbus(); + +#if DEFAULT_CONSOLE_LOGLEVEL > 8 + dump_spd_registers(); +#endif + + sdram_initialize(boot_mode); + + /* Perform some initialization that must run before stage2 */ + early_ich7_init(); + + /* This should probably go away. Until now it is required + * and mainboard specific + */ + rcba_config(); + + /* Chipset Errata! */ + fixup_i945_errata(); + + /* Initialize the internal PCIe links before we go into stage2 */ + i945_late_initialization(); + +#if DEFAULT_CONSOLE_LOGLEVEL > 8 +#if defined(DEBUG_RAM_SETUP) + sdram_dump_mchbar_registers(); +#endif + + { + /* This will not work if TSEG is in place! */ + u32 tom = pci_read_config32(PCI_DEV(0,2,0), 0x5c); + + printk_debug("TOM: 0x%08x\n", tom); + ram_check(0x00000000, 0x000a0000); + ram_check(0x00100000, tom); + } +#endif + MCHBAR16(SSKPD) = 0xCAFE; +} + +#include "cpu/intel/model_6ex/cache_as_ram_disable.c" Added: trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/chip.h =================================================================== --- trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/chip.h (rev 0) +++ trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/chip.h 2008-10-29 04:52:57 UTC (rev 3704) @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +struct chip_operations mainboard_kontron_986lcd_m_ops; +struct mainboard_kontron_986lcd_m_config { + int nothing; +}; Added: trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/cmos.layout (rev 0) +++ trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/cmos.layout 2008-10-29 04:52:57 UTC (rev 3704) @@ -0,0 +1,134 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2007-2008 coresystems GmbH +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; version 2 of +# the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +# MA 02110-1301 USA +# + +# ----------------------------------------------------------------- +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +# ----------------------------------------------------------------- +# Status Register A +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +# ----------------------------------------------------------------- +# Status Register B +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +385 1 e 4 last_boot +388 4 r 0 reboot_bits +#390 2 r 0 unused? + +# ----------------------------------------------------------------- +# coreboot config options: console +392 3 e 5 baud_rate +395 4 e 6 debug_level +#399 1 r 0 unused + +# coreboot config options: cpu +400 1 e 2 hyper_threading +#401 7 r 0 unused + +# coreboot config options: southbridge +408 1 e 1 nmi +409 1 e 1 power_on_after_fail +#410 6 r 0 unused + +# coreboot config options: bootloader +416 512 s 0 boot_devices +#928 80 r 0 unused + +# coreboot config options: check sums +984 16 h 0 check_sum +#1000 24 r 0 amd_reserved + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 1 Emergency +6 2 Alert +6 3 Critical +6 4 Error +6 5 Warning +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew + +# ----------------------------------------------------------------- +checksums + +checksum 392 983 984 + + Added: trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/debug.c =================================================================== --- trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/debug.c (rev 0) +++ trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/debug.c 2008-10-29 04:52:57 UTC (rev 3704) @@ -0,0 +1,128 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#define SMBUS_MEM_DEVICE_START 0x50 +#define SMBUS_MEM_DEVICE_END 0x53 +#define SMBUS_MEM_DEVICE_INC 1 + +static void print_pci_devices(void) +{ + device_t dev; + for(dev = PCI_DEV(0, 0, 0); + dev <= PCI_DEV(0, 0x1f, 0x7); + dev += PCI_DEV(0,0,1)) { + uint32_t id; + id = pci_read_config32(dev, PCI_VENDOR_ID); + if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) || + (((id >> 16) & 0xffff) == 0xffff) || + (((id >> 16) & 0xffff) == 0x0000)) { + continue; + } + printk_debug("PCI: %02x:%02x.%02x", (dev >> 20) & 0xff, + (dev >> 15) & 0x1f, (dev >> 12) & 7); + printk_debug(" [%04x:%04x]\r\n", id &0xffff, id >> 16); + } +} + +static void dump_pci_device(unsigned dev) +{ + int i; + + printk_debug("PCI: %02x:%02x.%02x\r\n", (dev >> 20) & 0xff, (dev >> 15) & 0x1f, (dev >> 12) & 7); + + for(i = 0; i <= 255; i++) { + unsigned char val; + if ((i & 0x0f) == 0) { + printk_debug("%02x:", i); + } + val = pci_read_config8(dev, i); + printk_debug(" %02x", val); + if ((i & 0x0f) == 0x0f) { + printk_debug("\r\n"); + } + } +} + +static void dump_pci_devices(void) +{ + device_t dev; + for(dev = PCI_DEV(0, 0, 0); + dev <= PCI_DEV(0, 0x1f, 0x7); + dev += PCI_DEV(0,0,1)) { + uint32_t id; + id = pci_read_config32(dev, PCI_VENDOR_ID); + if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) || + (((id >> 16) & 0xffff) == 0xffff) || + (((id >> 16) & 0xffff) == 0x0000)) { + continue; + } + dump_pci_device(dev); + } +} + +void dump_spd_registers(void) +{ + unsigned device; + device = SMBUS_MEM_DEVICE_START; + while(device <= SMBUS_MEM_DEVICE_END) { + int status = 0; + int i; + printk_debug("\r\ndimm %02x", device); + + for(i = 0; (i < 256) ; i++) { + if ((i % 16) == 0) { + printk_debug("\r\n%02x: ", i); + } + status = smbus_read_byte(device, i); + if (status < 0) { + printk_debug("bad device: %02x\r\n", -status); + break; + } + printk_debug("%02x ", status); + } + device += SMBUS_MEM_DEVICE_INC; + printk_debug("\r\n"); + } +} + +static void dump_mem(unsigned start, unsigned end) +{ + unsigned i; + print_debug("dump_mem:"); + for(i=start;i<end;i++) { + if((i & 0xf)==0) { +#if CONFIG_USE_INIT + printk_debug("\r\n%08x:", i); +#else + print_debug("\r\n"); + print_debug_hex32(i); + print_debug(":"); +#endif + } +#if CONFIG_USE_INIT + printk_debug(" %02x", (unsigned char)*((unsigned char *)i)); +#else + print_debug(" "); + print_debug_hex8((unsigned char)*((unsigned char *)i)); +#endif + } + print_debug("\r\n"); + } Added: trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/dmi.h =================================================================== --- trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/dmi.h (rev 0) +++ trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/dmi.h 2008-10-29 04:52:57 UTC (rev 3704) @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#define DMI_TABLE_SIZE 0x55 + +static u8 dmi_table[DMI_TABLE_SIZE] = { + 0x5f, 0x53, 0x4d, 0x5f, 0x2d, 0x1f, 0x02, 0x03, 0x51, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x5f, 0x44, 0x4d, 0x49, 0x5f, 0xeb, 0xa8, 0x03, 0xa0, 0xff, 0x0f, 0x00, 0x01, 0x00, 0x23, 0x00, + 0x00, 0x14, 0x00, 0x00, 0x01, 0x02, 0x00, 0xe0, 0x03, 0x07, 0x90, 0xde, 0xcb, 0x7f, 0x00, 0x00, + 0x00, 0x00, 0x37, 0x01, 0x63, 0x6f, 0x72, 0x65, 0x73, 0x79, 0x73, 0x74, 0x65, 0x6d, 0x73, 0x20, + 0x47, 0x6d, 0x62, 0x48, 0x00, 0x32, 0x2e, 0x30, 0x00, 0x30, 0x33, 0x2f, 0x31, 0x33, 0x2f, 0x32, + 0x30, 0x30, 0x38, 0x00, 0x00 +}; Added: trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/dsdt.dsl =================================================================== --- trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/dsdt.dsl (rev 0) +++ trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/dsdt.dsl 2008-10-29 04:52:57 UTC (rev 3704) @@ -0,0 +1,303 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +DefinitionBlock ("DSDT", "DSDT", 1, "986LCD", "COREBOOT", 0x0000001) +{ + Scope (\_PR) + { + Processor (CPU1, 0x01, 0x00000810, 0x06) + { + OperationRegion (STBL, SystemMemory, 0xFFFF0000, 0xFFFF) + Name (NCPU, 0x80) + Name (TYPE, 0x80000000) + Name (HNDL, 0x80000000) + Name (CFGD, 0x80000000) + Name (TBLD, 0x80) + Method (_PDC, 1, NotSerialized) + { + } + } + } + + Scope (\_PR) + { + Processor (CPU2, 0x02, 0x00000000, 0x00) + { + OperationRegion (STBL, SystemMemory, 0xFFFF0000, 0xFFFF) + Name (NCPU, 0x80) + Name (TYPE, 0x80000000) + Name (HNDL, 0x80000000) + Name (CFGD, 0x80000000) + Name (TBLD, 0x80) + Method (_PDC, 1, NotSerialized) + { + } + } + } + + Name (PICM, 0x00) + Method (_PIC, 1, NotSerialized) + { + Store (Arg0, PICM) + } + + Scope (\_SB) + { + Name (PR00, Package (0x12) + { + Package (0x04) { 0x0001FFFF, 0x00, LNKA, 0x00 }, + Package (0x04) { 0x0001FFFF, 0x01, LNKB, 0x00 }, + Package (0x04) { 0x0001FFFF, 0x02, LNKC, 0x00 }, + Package (0x04) { 0x0001FFFF, 0x03, LNKD, 0x00 }, + Package (0x04) { 0x001FFFFF, 0x00, LNKC, 0x00 }, + Package (0x04) { 0x001FFFFF, 0x01, LNKD, 0x00 }, + Package (0x04) { 0x001DFFFF, 0x00, LNKH, 0x00 }, + Package (0x04) { 0x001DFFFF, 0x01, LNKD, 0x00 }, + Package (0x04) { 0x001DFFFF, 0x02, LNKC, 0x00 }, + Package (0x04) { 0x001DFFFF, 0x03, LNKA, 0x00 }, + Package (0x04) { 0x001EFFFF, 0x00, LNKB, 0x00 }, + Package (0x04) { 0x001EFFFF, 0x01, LNKE, 0x00 }, + Package (0x04) { 0x001BFFFF, 0x00, LNKA, 0x00 }, + Package (0x04) { 0x001CFFFF, 0x00, LNKA, 0x00 }, + Package (0x04) { 0x001CFFFF, 0x01, LNKB, 0x00 }, + Package (0x04) { 0x001CFFFF, 0x02, LNKC, 0x00 }, + Package (0x04) { 0x001CFFFF, 0x03, LNKD, 0x00 }, + Package (0x04) { 0x0002FFFF, 0x00, LNKA, 0x00 } + }) + Name (AR00, Package (0x12) + { + Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x10 }, + Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x11 }, + Package (0x04) { 0x0001FFFF, 0x02, 0x00, 0x12 }, + Package (0x04) { 0x0001FFFF, 0x03, 0x00, 0x13 }, + Package (0x04) { 0x001FFFFF, 0x00, 0x00, 0x12 }, + Package (0x04) { 0x001FFFFF, 0x01, 0x00, 0x13 }, + Package (0x04) { 0x001DFFFF, 0x00, 0x00, 0x17 }, + Package (0x04) { 0x001DFFFF, 0x01, 0x00, 0x13 }, + Package (0x04) { 0x001DFFFF, 0x02, 0x00, 0x12 }, + Package (0x04) { 0x001DFFFF, 0x03, 0x00, 0x10 }, + Package (0x04) { 0x001EFFFF, 0x00, 0x00, 0x11 }, + Package (0x04) { 0x001EFFFF, 0x01, 0x00, 0x14 }, + Package (0x04) { 0x001BFFFF, 0x00, 0x00, 0x10 }, + Package (0x04) { 0x001CFFFF, 0x00, 0x00, 0x10 }, + Package (0x04) { 0x001CFFFF, 0x01, 0x00, 0x11 }, + Package (0x04) { 0x001CFFFF, 0x02, 0x00, 0x12 }, + Package (0x04) { 0x001CFFFF, 0x03, 0x00, 0x13 }, + Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x10 } + }) + Name (PR01, Package (0x1D) + { + Package (0x04) { 0xFFFF, 0x00, LNKA, 0x00 }, + Package (0x04) { 0x0001FFFF, 0x00, LNKE, 0x00 }, + Package (0x04) { 0x0001FFFF, 0x01, LNKF, 0x00 }, + Package (0x04) { 0x0001FFFF, 0x02, LNKG, 0x00 }, + Package (0x04) { 0x0001FFFF, 0x03, LNKH, 0x00 }, + Package (0x04) { 0x0002FFFF, 0x00, LNKF, 0x00 }, + Package (0x04) { 0x0002FFFF, 0x01, LNKG, 0x00 }, + Package (0x04) { 0x0002FFFF, 0x02, LNKH, 0x00 }, + Package (0x04) { 0x0002FFFF, 0x03, LNKE, 0x00 }, + Package (0x04) { 0x0003FFFF, 0x00, LNKG, 0x00 }, + Package (0x04) { 0x0003FFFF, 0x01, LNKH, 0x00 }, + Package (0x04) { 0x0003FFFF, 0x02, LNKE, 0x00 }, + Package (0x04) { 0x0003FFFF, 0x03, LNKF, 0x00 }, + Package (0x04) { 0x0004FFFF, 0x00, LNKH, 0x00 }, + Package (0x04) { 0x0004FFFF, 0x01, LNKE, 0x00 }, + Package (0x04) { 0x0004FFFF, 0x02, LNKF, 0x00 }, + Package (0x04) { 0x0004FFFF, 0x03, LNKG, 0x00 }, + Package (0x04) { 0x0005FFFF, 0x00, LNKD, 0x00 }, + Package (0x04) { 0x0005FFFF, 0x01, LNKC, 0x00 }, + Package (0x04) { 0x0005FFFF, 0x02, LNKB, 0x00 }, + Package (0x04) { 0x0005FFFF, 0x03, LNKA, 0x00 }, + Package (0x04) { 0x0006FFFF, 0x00, LNKC, 0x00 }, + Package (0x04) { 0x0006FFFF, 0x01, LNKB, 0x00 }, + Package (0x04) { 0x0006FFFF, 0x02, LNKA, 0x00 }, + Package (0x04) { 0x0006FFFF, 0x03, LNKD, 0x00 }, + Package (0x04) { 0x0009FFFF, 0x00, LNKF, 0x00 }, + Package (0x04) { 0x0009FFFF, 0x01, LNKG, 0x00 }, + Package (0x04) { 0x0009FFFF, 0x02, LNKH, 0x00 }, + Package (0x04) { 0x0009FFFF, 0x03, LNKE, 0x00 } + }) + Name (AR01, Package (0x1D) + { + Package (0x04) { 0xFFFF, 0x00, 0x00, 0x10 }, + Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x14 }, + Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x15 }, + Package (0x04) { 0x0001FFFF, 0x02, 0x00, 0x16 }, + Package (0x04) { 0x0001FFFF, 0x03, 0x00, 0x17 }, + Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x15 }, + Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x16 }, + Package (0x04) { 0x0002FFFF, 0x02, 0x00, 0x17 }, + Package (0x04) { 0x0002FFFF, 0x03, 0x00, 0x14 }, + Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x16 }, + Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x17 }, + Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x14 }, + Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x15 }, + Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x17 }, + Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x14 }, + Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x15 }, + Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x16 }, + Package (0x04) { 0x0005FFFF, 0x00, 0x00, 0x13 }, + Package (0x04) { 0x0005FFFF, 0x01, 0x00, 0x12 }, + Package (0x04) { 0x0005FFFF, 0x02, 0x00, 0x11 }, + Package (0x04) { 0x0005FFFF, 0x03, 0x00, 0x10 }, + Package (0x04) { 0x0006FFFF, 0x00, 0x00, 0x12 }, + Package (0x04) { 0x0006FFFF, 0x01, 0x00, 0x11 }, + Package (0x04) { 0x0006FFFF, 0x02, 0x00, 0x10 }, + Package (0x04) { 0x0006FFFF, 0x03, 0x00, 0x13 }, + Package (0x04) { 0x0009FFFF, 0x00, 0x00, 0x15 }, + Package (0x04) { 0x0009FFFF, 0x01, 0x00, 0x16 }, + Package (0x04) { 0x0009FFFF, 0x02, 0x00, 0x17 }, + Package (0x04) { 0x0009FFFF, 0x03, 0x00, 0x14 } + }) + Name (PR04, Package (0x04) + { + Package (0x04) { 0xFFFF, 0x00, LNKA, 0x00 }, + Package (0x04) { 0xFFFF, 0x01, LNKB, 0x00 }, + Package (0x04) { 0xFFFF, 0x02, LNKC, 0x00 }, + Package (0x04) { 0xFFFF, 0x03, LNKD, 0x00 } + }) + Name (AR04, Package (0x04) + { + Package (0x04) { 0xFFFF, 0x00, 0x00, 0x10 }, + Package (0x04) { 0xFFFF, 0x01, 0x00, 0x11 }, + Package (0x04) { 0xFFFF, 0x02, 0x00, 0x12 }, + Package (0x04) { 0xFFFF, 0x03, 0x00, 0x13 } + }) + Name (PR05, Package (0x01) + { + Package (0x04) { 0xFFFF, 0x00, LNKB, 0x00 } + }) + Name (AR05, Package (0x01) + { + Package (0x04) { 0xFFFF, 0x00, 0x00, 0x11 } + }) + Name (PR06, Package (0x01) + { + Package (0x04) { 0xFFFF, 0x00, LNKC, 0x00 } + }) + Name (AR06, Package (0x01) + { + Package (0x04) { 0xFFFF, 0x00, 0x00, 0x12 } + }) + Name (PR07, Package (0x04) + { + Package (0x04) { 0xFFFF, 0x00, LNKD, 0x00 }, + Package (0x04) { 0xFFFF, 0x01, LNKA, 0x00 }, + Package (0x04) { 0xFFFF, 0x02, LNKB, 0x00 }, + Package (0x04) { 0xFFFF, 0x03, LNKC, 0x00 } + }) + Name (AR07, Package (0x04) + { + Package (0x04) { 0xFFFF, 0x00, 0x00, 0x13 }, + Package (0x04) { 0xFFFF, 0x01, 0x00, 0x10 }, + Package (0x04) { 0xFFFF, 0x02, 0x00, 0x11 }, + Package (0x04) { 0xFFFF, 0x03, 0x00, 0x12 } + }) + Name (PR08, Package (0x04) + { + Package (0x04) { 0xFFFF, 0x00, LNKA, 0x00 }, + Package (0x04) { 0xFFFF, 0x01, LNKB, 0x00 }, + Package (0x04) { 0xFFFF, 0x02, LNKC, 0x00 }, + Package (0x04) { 0xFFFF, 0x03, LNKD, 0x00 } + }) + Name (AR08, Package (0x04) + { + Package (0x04) { 0xFFFF, 0x00, 0x00, 0x10 }, + Package (0x04) { 0xFFFF, 0x01, 0x00, 0x11 }, + Package (0x04) { 0xFFFF, 0x02, 0x00, 0x12 }, + Package (0x04) { 0xFFFF, 0x03, 0x00, 0x13 } + }) + Name (PR09, Package (0x04) + { + Package (0x04) { 0xFFFF, 0x00, LNKB, 0x00 }, + Package (0x04) { 0xFFFF, 0x01, LNKC, 0x00 }, + Package (0x04) { 0xFFFF, 0x02, LNKD, 0x00 }, + Package (0x04) { 0xFFFF, 0x03, LNKA, 0x00 } + }) + Name (AR09, Package (0x04) + { + Package (0x04) { 0xFFFF, 0x00, 0x00, 0x11 }, + Package (0x04) { 0xFFFF, 0x01, 0x00, 0x12 }, + Package (0x04) { 0xFFFF, 0x02, 0x00, 0x13 }, + Package (0x04) { 0xFFFF, 0x03, 0x00, 0x10 } + }) + + Device (LNKA) + { + Name (_HID, EisaId ("PNP0C0F")) + Name (_UID, 0x01) + } + + Device (LNKB) + { + Name (_HID, EisaId ("PNP0C0F")) + Name (_UID, 0x02) + } + + Device (LNKC) + { + Name (_HID, EisaId ("PNP0C0F")) + Name (_UID, 0x03) + } + + Device (LNKD) + { + Name (_HID, EisaId ("PNP0C0F")) + Name (_UID, 0x04) + } + + Device (LNKE) + { + Name (_HID, EisaId ("PNP0C0F")) + Name (_UID, 0x05) + } + + Device (LNKF) + { + Name (_HID, EisaId ("PNP0C0F")) + Name (_UID, 0x06) + } + + Device (LNKG) + { + Name (_HID, EisaId ("PNP0C0F")) + Name (_UID, 0x07) + } + + Device (LNKH) + { + Name (_HID, EisaId ("PNP0C0F")) + Name (_UID, 0x08) + } + } + + Name (\_S0, Package (0x04) + { 0x00, 0x00, 0x00, 0x00 }) + Name (\_S1, Package (0x04) + { 0x01, 0x00, 0x00, 0x00 }) + Name (\_S3, Package (0x04) + { 0x05, 0x00, 0x00, 0x00 }) + Name (\_S4, Package (0x04) + { 0x06, 0x00, 0x00, 0x00 }) + Name (\_S5, Package (0x04) + { 0x07, 0x00, 0x00, 0x00 }) +} + Added: trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/fadt.c =================================================================== --- trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/fadt.c (rev 0) +++ trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/fadt.c 2008-10-29 04:52:57 UTC (rev 3704) @@ -0,0 +1,86 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <string.h> +#include <device/pci.h> +#include <arch/acpi.h> + +void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) +{ + acpi_header_t *header = &(fadt->header); + u16 pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f,0)), 0x40) & 0xfffe; + + memset((void *) fadt, 0, sizeof(acpi_fadt_t)); + memcpy(header->signature, "FACP", 4); + header->length = 132; + header->revision = 1; + memcpy(header->oem_id, "CORE ", 6); + memcpy(header->oem_table_id, "COREBOOT", 8); + memcpy(header->asl_compiler_id, "CORE", 4); + header->asl_compiler_revision = 0; + + fadt->firmware_ctrl = (unsigned long) facs; + fadt->dsdt = (unsigned long) dsdt; + fadt->preferred_pm_profile = 0; + fadt->sci_int = 0x9; + fadt->smi_cmd = 0xb2; + fadt->acpi_enable = 0xe1; + fadt->acpi_disable = 0x1e; + fadt->s4bios_req = 0x0; + fadt->pstate_cnt = 0xe2; + + fadt->pm1a_evt_blk = pmbase; + fadt->pm1b_evt_blk = 0x0; + fadt->pm1a_cnt_blk = pmbase + 0x4; + fadt->pm1b_cnt_blk = 0x0; + fadt->pm2_cnt_blk = pmbase + 0x20; + fadt->pm_tmr_blk = pmbase + 0x8; + fadt->gpe0_blk = pmbase + 0x28; + fadt->gpe1_blk = 0; + + fadt->pm1_evt_len = 4; + fadt->pm1_cnt_len = 2; + fadt->pm2_cnt_len = 1; + fadt->pm_tmr_len = 4; + fadt->gpe0_blk_len = 8; + fadt->gpe1_blk_len = 0; + fadt->gpe1_base = 0; + fadt->cst_cnt = 0xe3; + fadt->p_lvl2_lat = 1; + fadt->p_lvl3_lat = 85; + fadt->flush_size = 1024; + fadt->flush_stride = 16; + fadt->duty_offset = 1; + fadt->duty_width = 0; + fadt->day_alrm = 0xd; + fadt->mon_alrm = 0x00; + fadt->century = 0x00; + fadt->iapc_boot_arch = 0x03; + fadt->flags = 0x80a5; + // wbinvd is operational + // all cpus support c1 + // sleep button is generic + // rtc wakeup/s4 not possible + + header->checksum = + acpi_checksum((void *) fadt, header->length); + +} Added: trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/irq_tables.c =================================================================== --- trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/irq_tables.c (rev 0) +++ trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/irq_tables.c 2008-10-29 04:52:57 UTC (rev 3704) @@ -0,0 +1,63 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <arch/pirq_routing.h> + +const struct irq_routing_table intel_irq_routing_table = { + PIRQ_SIGNATURE, /* u32 signature */ + PIRQ_VERSION, /* u16 version */ + 32+16*18, /* There can be total 18 devices on the bus */ + 0x00, /* Where the interrupt router lies (bus) */ + (0x1f<<3)|0x0, /* Where the interrupt router lies (dev) */ + 0, /* IRQs devoted exclusively to PCI usage */ + 0x8086, /* Vendor */ + 0x27b0, /* Device */ + 0, /* miniport */ + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ + 0xf, /* u8 checksum. */ + { + /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + {0x00,(0x01<<3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // PCIe? + {0x00,(0x02<<3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // VGA + {0x00,(0x1e<<3)|0x0, {{0x61, 0xdcf8}, {0x68, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // PCI bridge + {0x00,(0x1f<<3)|0x0, {{0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // LPC + {0x00,(0x1d<<3)|0x0, {{0x6b, 0xdcf8}, {0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x60, 0x0dcf8}}, 0x0, 0x0}, // USB#1 + {0x00,(0x1b<<3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // Audio device + {0x00,(0x1c<<3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x2, 0x0}, // PCIe bridge + {0x04,(0x00<<3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // Firewire + {0x04,(0x01<<3)|0x0, {{0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0x0dcf8}}, 0x1, 0x0}, // PCI Bridge + {0x04,(0x02<<3)|0x0, {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x2, 0x0}, + {0x04,(0x03<<3)|0x0, {{0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0x0dcf8}}, 0x3, 0x0}, + {0x04,(0x04<<3)|0x0, {{0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0x0dcf8}}, 0x4, 0x0}, + {0x04,(0x05<<3)|0x0, {{0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0x0dcf8}}, 0x5, 0x0}, + {0x04,(0x06<<3)|0x0, {{0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0xdcf8}, {0x63, 0x0dcd8}}, 0x6, 0x0}, + {0x04,(0x09<<3)|0x0, {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x9, 0x0}, + {0x01,(0x00<<3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // Ethernet 8168 + {0x02,(0x00<<3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x9, 0x0}, + {0x03,(0x00<<3)|0x0, {{0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x60, 0x0dcf8}}, 0xa, 0x0}, + } +}; + +unsigned long write_pirq_routing_table(unsigned long addr) +{ + return copy_pirq_routing_table(addr); +} + Added: trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/mainboard.c =================================================================== --- trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/mainboard.c (rev 0) +++ trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/mainboard.c 2008-10-29 04:52:57 UTC (rev 3704) @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + + +#include <device/device.h> +#include "chip.h" + +struct chip_operations mainboard_kontron_986lcd_m_ops = { + CHIP_NAME("Kontron 986LCD-M Mainboard") +}; + Added: trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/mptable.c =================================================================== --- trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/mptable.c (rev 0) +++ trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/mptable.c 2008-10-29 04:52:57 UTC (rev 3704) @@ -0,0 +1,131 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + + +#include <device/device.h> +#include <device/pci.h> +#include <console/console.h> +#include <arch/smp/mpspec.h> +#include <string.h> +#include <stdint.h> + +void *smp_write_config_table(void *v) +{ + static const char sig[4] = "PCMP"; + static const char oem[8] = "COREBOOT"; + static const char productid[12] = "986LCD-M "; + struct mp_config_table *mc; + int i; + int max_pci_bus, isa_bus; + + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); + memset(mc, 0, sizeof(*mc)); + + memcpy(mc->mpc_signature, sig, sizeof(sig)); + mc->mpc_length = sizeof(*mc); /* initially just the header */ + mc->mpc_spec = 0x04; + mc->mpc_checksum = 0; /* not yet computed */ + memcpy(mc->mpc_oem, oem, sizeof(oem)); + memcpy(mc->mpc_productid, productid, sizeof(productid)); + mc->mpc_oemptr = 0; + mc->mpc_oemsize = 0; + mc->mpc_entry_count = 0; /* No entries yet... */ + mc->mpc_lapic = LAPIC_ADDR; + mc->mpe_length = 0; + mc->mpe_checksum = 0; + mc->reserved = 0; + + smp_write_processors(mc); + + max_pci_bus = 5; // XXX read me from bridges. + + /* ISA bus follows */ + isa_bus = max_pci_bus + 1; + + /* Bus: Bus ID Type */ + for (i=0; i <= max_pci_bus; i++) + smp_write_bus(mc, i, "PCI "); + + smp_write_bus(mc, isa_bus, "ISA "); + + /* I/O APICs: APIC ID Version State Address */ + smp_write_ioapic(mc, 2, 0x20, 0xfec00000); + + /* Legacy Interrupts */ + + /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, 0x2, 0x0); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x1, 0x2, 0x1); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, 0x2, 0x2); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x3, 0x2, 0x3); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x4, 0x2, 0x4); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, isa_bus, 0x8, 0x2, 0x8); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x9, 0x2, 0x9); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xa, 0x2, 0xa); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xb, 0x2, 0xb); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xc, 0x2, 0xc); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xd, 0x2, 0xd); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xe, 0x2, 0xe); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xf, 0x2, 0xf); + + /* Builtin devices on Bus 0 */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x8, 0x2, 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x7d, 0x2, 0x13); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x74, 0x2, 0x17); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x75, 0x2, 0x13); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x76, 0x2, 0x12); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x77, 0x2, 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x6c, 0x2, 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x70, 0x2, 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x71, 0x2, 0x11); + + /* Firewire 4:0.0 */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, 0x0, 0x2, 0x10); + + // riser slot top 5:8.0 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x20, 0x2, 0x14); + // riser slot middle 5:9.0 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x24, 0x2, 0x15); + // riser slot bottom 5:a.0 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x28, 0x2, 0x16); + + /* Onboard Ethernet */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x0, 0x2, 0x10); + + /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x0); + smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x1); + + /* Compute the checksums */ + mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length); + mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length); + + printk_debug("Wrote the mp table end at: %p - %p\n", mc, smp_next_mpe_entry(mc)); + + return smp_next_mpe_entry(mc); +} + +unsigned long write_smp_table(unsigned long addr) +{ + void *v; + v = smp_write_floating_table(addr); + return (unsigned long)smp_write_config_table(v); +} Added: trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/power_reset_check.c =================================================================== --- trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/power_reset_check.c (rev 0) +++ trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/power_reset_check.c 2008-10-29 04:52:57 UTC (rev 3704) @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + + +static void power_down_reset_check(void) +{ + uint8_t cmos; + + cmos=cmos_read(RTC_BOOT_BYTE)>>4 ; + printk_debug("Boot byte = %x\r\n", cmos); + + if((cmos>2)&&(cmos&1)) full_reset(); +} Added: trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/reset.c =================================================================== --- trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/reset.c (rev 0) +++ trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/reset.c 2008-10-29 04:52:57 UTC (rev 3704) @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <arch/io.h> + +void soft_reset(void) +{ + outb(0x04, 0xcf9); +} + +void hard_reset(void) +{ + outb(0x02, 0xcf9); + outb(0x06, 0xcf9); +} Added: trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/rtl8168.c =================================================================== --- trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/rtl8168.c (rev 0) +++ trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/rtl8168.c 2008-10-29 04:52:57 UTC (rev 3704) @@ -0,0 +1,49 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* This code should work for all ICH* southbridges with a NIC. */ + +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> + +static void nic_init(struct device *dev) +{ + printk_debug("Initializing RTL8168 Gigabit Ethernet\n"); + // Nothing to do yet, but this has to be here to keep + // coreboot from trying to execute an option ROM. +} + +static struct device_operations nic_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = nic_init, + .scan_bus = 0, +}; + +static const struct pci_driver rtl8169_nic __pci_driver = { + .ops = &nic_ops, + .vendor = 0x10ec, + .device = 0x8168, +}; + + Added: trunk/coreboot-v2/targets/kontron/986lcd-m/Config-abuild.lb =================================================================== --- trunk/coreboot-v2/targets/kontron/986lcd-m/Config-abuild.lb (rev 0) +++ trunk/coreboot-v2/targets/kontron/986lcd-m/Config-abuild.lb 2008-10-29 04:52:57 UTC (rev 3704) @@ -0,0 +1,30 @@ +# This will make a target directory of ./VENDOR_MAINBOARD + +target VENDOR_MAINBOARD +mainboard VENDOR/MAINBOARD + +option CC="CROSSCC" +option CROSS_COMPILE="CROSS_PREFIX" +option HOSTCC="CROSS_HOSTCC" + +__COMPRESSION__ + +option ROM_SIZE=1024*(1024-64) +option FALLBACK_SIZE=1024*512 + +romimage "normal" + option USE_FALLBACK_IMAGE=0 + option ROM_IMAGE_SIZE=0x19000 + option COREBOOT_EXTRA_VERSION=".0-normal" + payload __PAYLOAD__ +end + +romimage "fallback" + option USE_FALLBACK_IMAGE=1 + option ROM_IMAGE_SIZE=0x19000 + option COREBOOT_EXTRA_VERSION=".0-fallback" + payload __PAYLOAD__ +end + +buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" + Added: trunk/coreboot-v2/targets/kontron/986lcd-m/Config.lb =================================================================== --- trunk/coreboot-v2/targets/kontron/986lcd-m/Config.lb (rev 0) +++ trunk/coreboot-v2/targets/kontron/986lcd-m/Config.lb 2008-10-29 04:52:57 UTC (rev 3704) @@ -0,0 +1,22 @@ +target kontron_986lcd_m +mainboard kontron/986lcd-m + +## ROM_SIZE is the total number of bytes allocated for LinuxBIOS use +## (normal AND fallback images and payloads). +option ROM_SIZE = 1024*1024 + +## ROM_IMAGE_SIZE is the maximum number of bytes allowed for a LinuxBIOS image, +## not including any payload. +option ROM_IMAGE_SIZE = 0x20000 + +## FALLBACK_SIZE is the amount of the ROM the complete fallback image +## (including payload) will use +option FALLBACK_SIZE = ROM_SIZE + +romimage "fallback" + option USE_FALLBACK_IMAGE=1 + #payload $(HOME)/filo.elf + payload /dev/zero +end + +buildrom ./linuxbios.rom ROM_SIZE "fallback"

1 0

r3703 - in trunk/coreboot-v2/src/northbridge/intel: . i945
by svn＠coreboot.org 29 Oct '08

29 Oct '08

Author: stepan Date: 2008-10-29 05:51:07 +0100 (Wed, 29 Oct 2008) New Revision: 3703 Added: trunk/coreboot-v2/src/northbridge/intel/i945/ trunk/coreboot-v2/src/northbridge/intel/i945/Config.lb trunk/coreboot-v2/src/northbridge/intel/i945/chip.h trunk/coreboot-v2/src/northbridge/intel/i945/early_init.c trunk/coreboot-v2/src/northbridge/intel/i945/errata.c trunk/coreboot-v2/src/northbridge/intel/i945/i945.h trunk/coreboot-v2/src/northbridge/intel/i945/ich7.h trunk/coreboot-v2/src/northbridge/intel/i945/northbridge.c trunk/coreboot-v2/src/northbridge/intel/i945/pcie_config.c trunk/coreboot-v2/src/northbridge/intel/i945/raminit.c trunk/coreboot-v2/src/northbridge/intel/i945/raminit.h trunk/coreboot-v2/src/northbridge/intel/i945/rcven.c trunk/coreboot-v2/src/northbridge/intel/i945/reset_test.c trunk/coreboot-v2/src/northbridge/intel/i945/udelay.c Log: Support for the Intel 945 northbridge. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Added: trunk/coreboot-v2/src/northbridge/intel/i945/Config.lb =================================================================== --- trunk/coreboot-v2/src/northbridge/intel/i945/Config.lb (rev 0) +++ trunk/coreboot-v2/src/northbridge/intel/i945/Config.lb 2008-10-29 04:51:07 UTC (rev 3703) @@ -0,0 +1,21 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2007-2008 coresystems GmbH +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +config chip.h +driver northbridge.o Added: trunk/coreboot-v2/src/northbridge/intel/i945/chip.h =================================================================== --- trunk/coreboot-v2/src/northbridge/intel/i945/chip.h (rev 0) +++ trunk/coreboot-v2/src/northbridge/intel/i945/chip.h 2008-10-29 04:51:07 UTC (rev 3703) @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +struct northbridge_intel_i945_config { +}; + +extern struct chip_operations northbridge_intel_i945_ops; Added: trunk/coreboot-v2/src/northbridge/intel/i945/early_init.c =================================================================== --- trunk/coreboot-v2/src/northbridge/intel/i945/early_init.c (rev 0) +++ trunk/coreboot-v2/src/northbridge/intel/i945/early_init.c 2008-10-29 04:51:07 UTC (rev 3703) @@ -0,0 +1,567 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "i945.h" +#include "pcie_config.c" + +static int i945_silicon_revision(void) +{ + return pci_read_config8(PCI_DEV(0, 0x00, 0), 8); +} + +static void i945_detect_chipset(void) +{ + u8 reg8; + + printk_info("\r\n"); + reg8 = (pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe7) & 0x70) >> 4; + switch (reg8) { + case 1: + printk_info("Mobile Intel(R) 945GM/GME Express"); + break; + case 2: + printk_info("Mobile Intel(R) 945GMS/GU Express"); + break; + case 3: + printk_info("Mobile Intel(R) 945PM Express"); + break; + case 5: + printk_info("Intel(R) 945GT Express"); + break; + case 6: + printk_info("Mobile Intel(R) 943/940GML Express"); + break; + default: + printk_info("Unknown (%02x)", reg8); /* Others reserved. */ + } + printk_info(" Chipset\r\n"); + + printk_debug("(G)MCH capable of up to FSB "); + reg8 = (pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe3) & 0xe0) >> 5; + switch (reg8) { + case 2: + printk_debug("800 MHz"); /* According to 965 spec */ + break; + case 3: + printk_debug("667 MHz"); + break; + case 4: + printk_debug("533 MHz"); + break; + default: + printk_debug("N/A MHz (%02x)", reg8); + } + printk_debug("\r\n"); + + printk_debug("(G)MCH capable of "); + reg8 = (pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe4) & 0x07); + switch (reg8) { + case 2: + printk_debug("up to DDR2-667"); + break; + case 3: + printk_debug("up to DDR2-533"); + break; + case 4: + printk_debug("DDR2-400"); + break; + default: + printk_info("unknown max. RAM clock (%02x).", reg8); /* Others reserved. */ + } + printk_debug("\r\n"); +} + +static void i945_setup_bars(void) +{ + u8 reg8; + + /* As of now, we don't have all the A0 workarounds implemented */ + if (i945_silicon_revision() == 0) + printk_info + ("Warning: i945 silicon revision A0 might not work correctly.\r\n"); + + /* Setting up Southbridge. In the northbridge code. */ + printk_debug("Setting up static southbridge registers..."); + pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA, DEFAULT_RCBA | 1); + + pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1); + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */ , 0x80); /* Enable ACPI BAR */ + + pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIOBASE, DEFAULT_GPIOBASE | 1); + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x4c /* GC */ , 0x10); /* Enable GPIOs */ + setup_ich7_gpios(); + printk_debug(" done.\r\n"); + + printk_debug("Disabling Watchdog reboot..."); + RCBA32(GCS) = (RCBA32(0x3410)) | (1 << 5); /* No reset */ + outw((1 << 11), DEFAULT_PMBASE | 0x60 | 0x08); /* halt timer */ + printk_debug(" done.\r\n"); + + printk_debug("Setting up static northbridge registers..."); + /* Set up all hardcoded northbridge BARs */ + pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR, DEFAULT_EPBAR | 1); + pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR, DEFAULT_MCHBAR | 1); + pci_write_config32(PCI_DEV(0, 0x00, 0), PCIEXBAR, DEFAULT_PCIEXBAR | 5); /* 64MB - busses 0-63 */ + pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR, DEFAULT_DMIBAR | 1); + pci_write_config32(PCI_DEV(0, 0x00, 0), X60BAR, DEFAULT_X60BAR | 1); + + /* Hardware default is 8MB UMA. If someone wants to make this a + * CMOS or compile time option, send a patch. + * pci_write_config16(PCI_DEV(0, 0x00, 0), GGC, 0x30); + */ + + /* Set C0000-FFFFF to access RAM on both reads and writes */ + pci_write_config8(PCI_DEV(0, 0x00, 0), PAM0, 0x30); + pci_write_config8(PCI_DEV(0, 0x00, 0), PAM1, 0x33); + pci_write_config8(PCI_DEV(0, 0x00, 0), PAM2, 0x33); + pci_write_config8(PCI_DEV(0, 0x00, 0), PAM3, 0x33); + pci_write_config8(PCI_DEV(0, 0x00, 0), PAM4, 0x33); + pci_write_config8(PCI_DEV(0, 0x00, 0), PAM5, 0x33); + pci_write_config8(PCI_DEV(0, 0x00, 0), PAM6, 0x33); + + pci_write_config8(PCI_DEV(0, 0x00, 0), TOLUD, 0x40); /* 1G XXX dynamic! */ + + pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafebabe); + printk_debug(" done.\r\n"); + + /* Wait for MCH BAR to come up */ + printk_debug("Waiting for MCHBAR to come up..."); + if ((pci_read_config8(PCI_DEV(0, 0x0f, 0), 0xe6) & 0x2) == 0x00) { /* Bit 49 of CAPID0 */ + do { + reg8 = *(volatile u8 *)0xfed40000; + } while (!(reg8 & 0x80)); + } + printk_debug("ok\r\n"); +} + +static void i945_setup_egress_port(void) +{ + u32 reg32; + u32 timeout; + + printk_debug("Setting up Egress Port RCRB\n"); + + /* Egress Port Virtual Channel 0 Configuration */ + + /* map only TC0 to VC0 */ + reg32 = EPBAR32(EPVC0RCTL); + reg32 &= 0xffffff01; + EPBAR32(EPVC0RCTL) = reg32; + + + reg32 = EPBAR32(EPPVCCAP1); + reg32 &= ~(7 << 0); + reg32 |= 1; + EPBAR32(EPPVCCAP1) = reg32; + + /* Egress Port Virtual Channel 1 Configuration */ + reg32 = EPBAR32(0x2c); + reg32 &= 0xffffff00; + if ((MCHBAR32(CLKCFG) & 7) == 1) + reg32 |= 0x0d; /* 533MHz */ + if ((MCHBAR32(CLKCFG) & 7) == 3) + reg32 |= 0x10; /* 667MHz */ + EPBAR32(0x2c) = reg32; + + EPBAR32(EPVC1MTS) = 0x0a0a0a0a; + + reg32 = EPBAR32(EPVC1RCAP); + reg32 &= ~(0x7f << 16); + reg32 |= (0x0a << 16); + EPBAR32(EPVC1RCAP) = reg32; + + if ((MCHBAR32(CLKCFG) & 7) == 1) { /* 533MHz */ + EPBAR32(EPVC1IST + 0) = 0x009c009c; + EPBAR32(EPVC1IST + 4) = 0x009c009c; + } + + if ((MCHBAR32(CLKCFG) & 7) == 3) { /* 667MHz */ + EPBAR32(EPVC1IST + 0) = 0x00c000c0; + EPBAR32(EPVC1IST + 4) = 0x00c000c0; + } + + /* Is internal graphics enabled? */ + if (pci_read_config8(PCI_DEV(0, 0x0, 0), 54) & ((1 << 4) | (1 << 3))) { /* DEVEN */ + MCHBAR32(MMARB1) |= (1 << 17); + } + + /* Assign Virtual Channel ID 1 to VC1 */ + reg32 = EPBAR32(EPVC1RCTL); + reg32 &= ~(7 << 24); + reg32 |= (1 << 24); + EPBAR32(EPVC1RCTL) = reg32; + + reg32 = EPBAR32(EPVC1RCTL); + reg32 &= 0xffffff01; + reg32 |= (1 << 7); + EPBAR32(EPVC1RCTL) = reg32; + + EPBAR32(PORTARB + 0x00) = 0x01000001; + EPBAR32(PORTARB + 0x04) = 0x00040000; + EPBAR32(PORTARB + 0x08) = 0x00001000; + EPBAR32(PORTARB + 0x0c) = 0x00000040; + EPBAR32(PORTARB + 0x10) = 0x01000001; + EPBAR32(PORTARB + 0x14) = 0x00040000; + EPBAR32(PORTARB + 0x18) = 0x00001000; + EPBAR32(PORTARB + 0x1c) = 0x00000040; + + EPBAR32(EPVC1RCTL) |= (1 << 16); + EPBAR32(EPVC1RCTL) |= (1 << 16); + + printk_debug("Loading port arbitration table ..."); + /* Loop until bit 0 becomes 0 */ + timeout = 0x7fffff; + while ((EPBAR16(EPVC1RSTS) & 1) && --timeout) ; + if (!timeout) + printk_debug("timeout!\n"); + else + printk_debug("ok\n"); + + /* Now enable VC1 */ + EPBAR32(EPVC1RCTL) |= (1 << 31); + + printk_debug("Wait for VC1 negotiation ..."); + /* Wait for VC1 negotiation pending */ + timeout = 0x7fff; + while ((EPBAR16(EPVC1RSTS) & (1 << 1)) && --timeout) ; + if (!timeout) + printk_debug("timeout!\n"); + else + printk_debug("ok\n"); + +} + +static void ich7_setup_dmi_rcrb(void) +{ + u16 reg16; + + + reg16 = RCBA16(LCTL); + reg16 &= ~(3 << 0); + reg16 |= 1; + RCBA16(LCTL) = reg16; + + RCBA32(V0CTL) = 0x80000001; + RCBA32(V1CAP) = 0x03128010; + RCBA32(ESD) = 0x00000810; + RCBA32(RP1D) = 0x01000003; + RCBA32(RP2D) = 0x02000002; + RCBA32(RP3D) = 0x03000002; + RCBA32(RP4D) = 0x04000002; + RCBA32(HDD) = 0x0f000003; + RCBA32(RP5D) = 0x05000002; + + RCBA32(RPFN) = 0x00543210; + + pci_write_config16(PCI_DEV(0, 0x1c, 0), 0x42, 0x0141); + pci_write_config16(PCI_DEV(0, 0x1c, 4), 0x42, 0x0141); + pci_write_config16(PCI_DEV(0, 0x1c, 5), 0x42, 0x0141); + + pci_write_config32(PCI_DEV(0, 0x1c, 4), 0x54, 0x00480ce0); + pci_write_config32(PCI_DEV(0, 0x1c, 5), 0x54, 0x00500ce0); +} + +static void i945_setup_dmi_rcrb(void) +{ + u32 reg32; + u32 timeout; + + printk_debug("Setting up DMI RCRB\n"); + + /* Virtual Channel 0 Configuration */ + reg32 = DMIBAR32(DMIVC0RCTL0); + reg32 &= 0xffffff01; + DMIBAR32(DMIVC0RCTL0) = reg32; + + reg32 = DMIBAR32(DMIPVCCAP1); + reg32 &= ~(7 << 0); + reg32 |= 1; + DMIBAR32(DMIPVCCAP1) = reg32; + + reg32 = DMIBAR32(DMIVC1RCTL); + reg32 &= ~(7 << 24); + reg32 |= (1 << 24); /* NOTE: This ID must match ICH7 side */ + DMIBAR32(DMIVC1RCTL) = reg32; + + reg32 = DMIBAR32(DMIVC1RCTL); + reg32 &= 0xffffff01; + reg32 |= (1 << 7); + DMIBAR32(DMIVC1RCTL) = reg32; + + /* Now enable VC1 */ + DMIBAR32(DMIVC1RCTL) |= (1 << 31); + + printk_debug("Wait for VC1 negotiation ..."); + /* Wait for VC1 negotiation pending */ + timeout = 0x7ffff; + while ((DMIBAR16(DMIVC1RSTS) & (1 << 1)) && --timeout) ; + if (!timeout) + printk_debug("timeout!\n"); + else + printk_debug("done..\n"); +#if 1 + /* Enable Active State Power Management (ASPM) L0 state */ + + reg32 = DMIBAR32(DMILCAP); + reg32 &= ~(7 << 12); + reg32 |= (2 << 12); + + reg32 &= ~(7 << 15); + + reg32 |= (2 << 15); + DMIBAR32(DMILCAP) = reg32; + + reg32 = DMIBAR32(DMICC); + reg32 &= 0x00ffffff; + reg32 &= ~(3 << 0); + reg32 |= (1 << 0); + DMIBAR32(DMICC) = reg32; + + if (0) { + DMIBAR32(DMILCTL) |= (3 << 0); + } +#endif + + /* Last but not least, some additional steps */ + reg32 = MCHBAR32(FSBSNPCTL); + reg32 &= ~(0xff << 2); + reg32 |= (0xaa << 2); + MCHBAR32(FSBSNPCTL) = reg32; + + DMIBAR32(0x2c) = 0x86000040; + + reg32 = DMIBAR32(0x204); + reg32 &= ~0x3ff; +#if 1 + reg32 |= 0x13f; /* for x4 DMI only */ +#else + reg32 |= 0x1e4; /* for x2 DMI only */ +#endif + DMIBAR32(0x204) = reg32; + + if (pci_read_config8(PCI_DEV(0, 0x0, 0), 54) & ((1 << 4) | (1 << 3))) { /* DEVEN */ + DMIBAR32(0x200) |= (1 << 21); + } else { + DMIBAR32(0x200) &= ~(1 << 21); + } + + reg32 = DMIBAR32(0x204); + reg32 &= ~((1 << 11) | (1 << 10)); + DMIBAR32(0x204) = reg32; + + reg32 = DMIBAR32(0x204); + reg32 &= ~(0xff << 12); + reg32 |= (0x0d << 12); + DMIBAR32(0x204) = reg32; + + DMIBAR32(DMICTL1) |= (3 << 24); + + reg32 = DMIBAR32(0x200); + reg32 &= ~(0x3 << 26); + reg32 |= (0x02 << 26); + DMIBAR32(0x200) = reg32; + + DMIBAR32(DMIDRCCFG) &= ~(1 << 31); + DMIBAR32(DMICTL2) |= (1 << 31); + + if (i945_silicon_revision() >= 3) { + reg32 = DMIBAR32(0xec0); + reg32 &= 0x0fffffff; + reg32 |= (2 << 28); + DMIBAR32(0xec0) = reg32; + + reg32 = DMIBAR32(0xed4); + reg32 &= 0x0fffffff; + reg32 |= (2 << 28); + DMIBAR32(0xed4) = reg32; + + reg32 = DMIBAR32(0xee8); + reg32 &= 0x0fffffff; + reg32 |= (2 << 28); + DMIBAR32(0xee8) = reg32; + + reg32 = DMIBAR32(0xefc); + reg32 &= 0x0fffffff; + reg32 |= (2 << 28); + DMIBAR32(0xefc) = reg32; + } + + /* wait for bit toggle to 0 */ + printk_debug("Waiting for DMI hardware..."); + timeout = 0x7fffff; + while ((DMIBAR8(0x32) & (1 << 1)) && --timeout) ; + if (!timeout) + printk_debug("timeout!\n"); + else + printk_debug("ok\n"); + + DMIBAR32(0x1c4) = 0xffffffff; + DMIBAR32(0x1d0) = 0xffffffff; + DMIBAR32(0x228) = 0xffffffff; + + DMIBAR32(0x308) = DMIBAR32(0x308); + DMIBAR32(0x314) = DMIBAR32(0x314); + DMIBAR32(0x324) = DMIBAR32(0x324); + DMIBAR32(0x328) = DMIBAR32(0x328); + DMIBAR32(0x338) = DMIBAR32(0x334); + DMIBAR32(0x338) = DMIBAR32(0x338); + + if (i945_silicon_revision() == 1 && ((MCHBAR8(0xe08) & (1 << 5)) == 1)) { + if ((MCHBAR32(0x214) & 0xf) != 0x3) { + printk_info + ("DMI link requires A1 stepping workaround. Rebooting.\n"); + reg32 = MCHBAR32(MMARB1); + reg32 &= 0xfffffff8; + reg32 |= 3; + outb(0x06, 0xcf9); + for (;;) ; /* wait for reset */ + } + } +} + +static void i945_setup_pci_express_x16(void) +{ + u32 timeout; + u32 reg32; + u16 reg16; + u8 reg8; + + /* For now we just disable the x16 link */ + printk_debug("Disabling PCI Express x16 Link\n"); + + MCHBAR16(UPMC1) |= (1 << 5) | (1 << 0); + + reg8 = pcie_read_config8(PCI_DEV(0, 0x01, 0), BCTRL1); + reg8 |= (1 << 6); + pcie_write_config8(PCI_DEV(0, 0x01, 0), BCTRL1, reg8); + + reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0x224); + reg32 |= (1 << 8); + pcie_write_config32(PCI_DEV(0, 0x01, 0), 0x224, reg32); + + reg8 = pcie_read_config8(PCI_DEV(0, 0x01, 0), BCTRL1); + reg8 &= ~(1 << 6); + pcie_write_config8(PCI_DEV(0, 0x01, 0), BCTRL1, reg8); + + printk_debug("Wait for link to enter detect state... "); + timeout = 0x7fffff; + for (reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0x214); + (reg32 & 0x000f0000) && --timeout;) ; + if (!timeout) + printk_debug("timeout!\n"); + else + printk_debug("ok\n"); + + /* Finally: Disable the PCI config header */ + reg16 = pci_read_config16(PCI_DEV(0, 0x00, 0), DEVEN); + reg16 &= ~DEVEN_D1F0; + pci_write_config16(PCI_DEV(0, 0x00, 0), DEVEN, reg16); +} + +static void i945_setup_root_complex_topology(void) +{ + u32 reg32; + + printk_debug("Setting up Root Complex Topology\n"); + /* Egress Port Root Topology */ + reg32 = EPBAR32(EPESD); + reg32 &= 0xff00ffff; + reg32 |= (1 << 16); + EPBAR32(EPESD) = reg32; + + EPBAR32(EPLE1D) |= (1 << 0); + + EPBAR32(EPLE1A) = DEFAULT_PCIEXBAR + 0x4000; + + EPBAR32(EPLE2D) |= (1 << 0); + + /* DMI Port Root Topology */ + reg32 = DMIBAR32(DMILE1D); + reg32 &= 0x00ffffff; + DMIBAR32(DMILE1D) = reg32; + + reg32 = DMIBAR32(DMILE1D); + reg32 &= 0xff00ffff; + reg32 |= (2 << 16); + DMIBAR32(DMILE1D) = reg32; + + DMIBAR32(DMILE1D) |= (1 << 0); + + DMIBAR32(DMILE1A) = DEFAULT_PCIEXBAR + 0x8000; + + DMIBAR32(DMILE2D) |= (1 << 0); + + DMIBAR32(DMILE2A) = DEFAULT_PCIEXBAR + 0x5000; + + /* PCI Express x16 Port Root Topology */ + if (pci_read_config8(PCI_DEV(0, 0x00, 0), DEVEN) & DEVEN_D1F0) { + pcie_write_config32(PCI_DEV(0, 0x01, 0), 0x158, + DEFAULT_PCIEXBAR + 0x5000); + + reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0x150); + reg32 |= (1 << 0); + pcie_write_config32(PCI_DEV(0, 0x01, 0), 0x150, reg32); + } +} + +static void ich7_setup_root_complex_topology(void) +{ + RCBA32(0x104) = 0x00000802; + RCBA32(0x110) = 0x00000001; + RCBA32(0x114) = 0x00000000; + RCBA32(0x118) = 0x00000000; +} + +static void ich7_setup_pci_express(void) +{ + RCBA32(CG) |= (1 << 0); + + pci_write_config32(PCI_DEV(0, 0x1c, 0), 0x54, 0x00000060); + + pci_write_config32(PCI_DEV(0, 0x1c, 0), 0xd8, 0x00110000); +} + +static void i945_early_initialization(void) +{ + /* Print some chipset specific information */ + i945_detect_chipset(); + + /* Setup all BARs required for early PCIe and raminit */ + i945_setup_bars(); + + /* Change port80 to LPC */ + RCBA32(GCS) &= (~0x04); +} + +static void i945_late_initialization(void) +{ + i945_setup_egress_port(); + + ich7_setup_root_complex_topology(); + + ich7_setup_pci_express(); + + ich7_setup_dmi_rcrb(); + + i945_setup_dmi_rcrb(); + + i945_setup_pci_express_x16(); + + i945_setup_root_complex_topology(); +} Added: trunk/coreboot-v2/src/northbridge/intel/i945/errata.c =================================================================== --- trunk/coreboot-v2/src/northbridge/intel/i945/errata.c (rev 0) +++ trunk/coreboot-v2/src/northbridge/intel/i945/errata.c 2008-10-29 04:51:07 UTC (rev 3703) @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +int fixup_i945_errata(void) +{ + u32 reg32; + + /* Mobile Intel 945 Express only */ + reg32 = MCHBAR32(FSBPMC3); + reg32 &= ~((1 << 13) | (1 << 29)); + MCHBAR32(FSBPMC3) = reg32; + + return 0; +} Added: trunk/coreboot-v2/src/northbridge/intel/i945/i945.h =================================================================== --- trunk/coreboot-v2/src/northbridge/intel/i945/i945.h (rev 0) +++ trunk/coreboot-v2/src/northbridge/intel/i945/i945.h 2008-10-29 04:51:07 UTC (rev 3703) @@ -0,0 +1,330 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __NORTHBRIDGE_INTEL_I945_I945_H__ +#define __NORTHBRIDGE_INTEL_I945_I945_H__ 1 + +#include "ich7.h" + +/* Device 0:0.0 PCI configuration space (Host Bridge) */ + +#define EPBAR 0x40 +#define MCHBAR 0x44 +#define PCIEXBAR 0x48 +#define DMIBAR 0x4c +#define X60BAR 0x60 + +/* Northbridge BARs */ +#define DEFAULT_PCIEXBAR 0xf0000000 +#define DEFAULT_X60BAR 0xfed13000 +#define DEFAULT_MCHBAR 0xfed14000 +#define DEFAULT_DMIBAR 0xfed18000 +#define DEFAULT_EPBAR 0xfed19000 + +#define GGC 0x52 + +#define DEVEN 0x54 +#define DEVEN_D0F0 (1 << 0) +#define DEVEN_D1F0 (1 << 1) +#define DEVEN_D2F0 (1 << 3) +#define DEVEN_D2F1 (1 << 4) +#ifndef BOARD_DEVEN +#define BOARD_DEVEN ( DEVEN_D0F0 | DEVEN_D2F0 | DEVEN_D2F1 ) +#endif + +#define PAM0 0x90 +#define PAM1 0x91 +#define PAM2 0x92 +#define PAM3 0x93 +#define PAM4 0x94 +#define PAM5 0x95 +#define PAM6 0x96 + +#define LAC 0x97 /* Legacy Access Control */ +#define TOLUD 0x9c /* Top of Low Used Memory */ +#define SMRAM 0x9d +#define ESMRAM 0x9e + +#define TOM 0xa0 + +#define SKPAD 0xdc /* Scratchpad */ + +/* Device 0:1.0 PCI configuration space (PCI Express) */ + +#define BCTRL1 0x3e /* 8bit */ + + +/* Device 0:2.0 PCI configuration space (Graphics Device) */ + +#define GCFC 0xf0 /* Graphics Clock Frequency and Gating Control */ + + +/* + * MCHBAR + */ + +#define MCHBAR8(x) *((volatile u8 *)(DEFAULT_MCHBAR + x)) +#define MCHBAR16(x) *((volatile u16 *)(DEFAULT_MCHBAR + x)) +#define MCHBAR32(x) *((volatile u32 *)(DEFAULT_MCHBAR + x)) + +/* Chipset Control Registers */ +#define FSBPMC3 0x40 /* 32bit */ +#define FSBPMC4 0x44 /* 32bit */ +#define FSBSNPCTL 0x48 /* 32bit */ +#define SLPCTL 0x90 /* 32bit */ + +#define C0DRB0 0x100 /* 8bit */ +#define C0DRB1 0x101 /* 8bit */ +#define C0DRB2 0x102 /* 8bit */ +#define C0DRB3 0x103 /* 8bit */ +#define C0DRA0 0x108 /* 8bit */ +#define C0DRA2 0x109 /* 8bit */ +#define C0DCLKDIS 0x10c /* 8bit */ +#define C0BNKARC 0x10e /* 16bit */ +#define C0DRT0 0x110 /* 32bit */ +#define C0DRT1 0x114 /* 32bit */ +#define C0DRT2 0x118 /* 32bit */ +#define C0DRT3 0x11c /* 32bit */ +#define C0DRC0 0x120 /* 32bit */ +#define C0DRC1 0x124 /* 32bit */ +#define C0DRC2 0x128 /* 32bit */ +#define C0AIT 0x130 /* 64bit */ +#define C0DCCFT 0x138 /* 64bit */ +#define C0GTEW 0x140 /* 32bit */ +#define C0GTC 0x144 /* 32bit */ +#define C0DTPEW 0x148 /* 64bit */ +#define C0DTAEW 0x150 /* 64bit */ +#define C0DTC 0x158 /* 32bit */ +#define C0DMC 0x164 /* 32bit */ +#define C0ODT 0x168 /* 64bit */ + +#define C1DRB0 0x180 /* 8bit */ +#define C1DRB1 0x181 /* 8bit */ +#define C1DRB2 0x182 /* 8bit */ +#define C1DRB3 0x183 /* 8bit */ +#define C1DRA0 0x188 /* 8bit */ +#define C1DCLKDIS 0x18c /* 8bit */ +#define C1BNKARC 0x18e /* 16bit */ +#define C1DRT0 0x190 /* 32bit */ +#define C1DRT1 0x194 /* 32bit */ +#define C1DRT2 0x198 /* 32bit */ +#define C1DRT3 0x19c /* 32bit */ +#define C1DRC0 0x1a0 /* 32bit */ +#define C1DRC1 0x1a4 /* 32bit */ +#define C1DRC2 0x1a8 /* 32bit */ +#define C1AIT 0x1b0 /* 64bit */ +#define C1DCCFT 0x1b8 /* 64bit */ +#define C1GTEW 0x1c0 /* 32bit */ +#define C1GTC 0x1c4 /* 32bit */ +#define C1DTPEW 0x1c8 /* 64bit */ +#define C1DTAEW 0x1d0 /* 64bit */ +#define C1DTC 0x1d8 /* 32bit */ +#define C1DMC 0x1e4 /* 32bit */ +#define C1ODT 0x1e8 /* 64bit */ + +#define DCC 0x200 /* 32bit */ +#define CCCFT 0x208 /* 64bit */ +#define WCC 0x218 /* 32bit */ +#define MMARB0 0x220 /* 32bit */ +#define MMARB1 0x224 /* 32bit */ +#define SBTEST 0x230 /* 32bit */ +#define SBOCC 0x238 /* 32bit */ +#define ODTC 0x284 /* 32bit */ +#define SMVREFC 0x2a0 /* 32bit */ +#define DRTST 0x2a8 /* 32bit */ +#define REPC 0x2e0 /* 32bit */ +#define DQSMT 0x2f4 /* 16bit */ +#define RCVENMT 0x2f8 /* 32bit */ + +#define C0R0B00DQST 0x300 /* 64bit */ + +#define C0WL0REOST 0x340 /* 8bit */ +#define C0WL1REOST 0x341 /* 8bit */ +#define C0WL2REOST 0x342 /* 8bit */ +#define C0WL3REOST 0x343 /* 8bit */ +#define WDLLBYPMODE 0x360 /* 16bit */ +#define C0WDLLCMC 0x36c /* 32bit */ +#define C0HCTC 0x37c /* 8bit */ + +#define C1R0B00DQST 0x380 /* 64bit */ + +#define C1WL0REOST 0x3c0 /* 8bit */ +#define C1WL1REOST 0x3c1 /* 8bit */ +#define C1WL2REOST 0x3c2 /* 8bit */ +#define C1WL3REOST 0x3c3 /* 8bit */ +#define C1WDLLCMC 0x3ec /* 32bit */ +#define C1HCTC 0x3fc /* 8bit */ + +#define GBRCOMPCTL 0x400 /* 32bit */ + +#define SMSRCTL 0x408 /* XXX who knows */ +#define C0DRAMW 0x40c /* 16bit */ +#define G1SC 0x410 /* 8bit */ +#define G2SC 0x418 /* 8bit */ +#define G3SC 0x420 /* 8bit */ +#define G4SC 0x428 /* 8bit */ +#define G5SC 0x430 /* 8bit */ +#define G6SC 0x438 /* 8bit */ + +#define C1DRAMW 0x48c /* 16bit */ +#define G7SC 0x490 /* 8bit */ +#define G8SC 0x498 /* 8bit */ + +#define G1SRPUT 0x500 /* 256bit */ +#define G1SRPDT 0x520 /* 256bit */ +#define G2SRPUT 0x540 /* 256bit */ +#define G2SRPDT 0x560 /* 256bit */ +#define G3SRPUT 0x580 /* 256bit */ +#define G3SRPDT 0x5a0 /* 256bit */ +#define G4SRPUT 0x5c0 /* 256bit */ +#define G4SRPDT 0x5e0 /* 256bit */ +#define G5SRPUT 0x600 /* 256bit */ +#define G5SRPDT 0x620 /* 256bit */ +#define G6SRPUT 0x640 /* 256bit */ +#define G6SRPDT 0x660 /* 256bit */ +#define G7SRPUT 0x680 /* 256bit */ +#define G7SRPDT 0x6a0 /* 256bit */ +#define G8SRPUT 0x6c0 /* 256bit */ +#define G8SRPDT 0x6e0 /* 256bit */ + +/* Clock Controls */ +#define CLKCFG 0xc00 /* 32bit */ +#define UPMC1 0xc14 /* 16bit */ +#define CPCTL 0xc16 /* 16bit */ +#define SSKPD 0xc1c /* 16bit (scratchpad) */ +#define UPMC2 0xc20 /* 16bit */ +#define UPMC4 0xc30 /* 32bit */ +#define PLLMON 0xc34 /* 32bit */ +#define HGIPMC2 0xc38 /* 32bit */ + +/* Thermal Management Controls */ +#define TSC1 0xc88 /* 8bit */ +#define TSS1 0xc8a /* 8bit */ +#define TR1 0xc8b /* 8bit */ +#define TSTTP1 0xc8c /* 32bit */ +#define TCO1 0xc92 /* 8bit */ +#define THERM1_1 0xc94 /* 8bit */ +#define TCOF1 0xc96 /* 8bit */ +#define TIS1 0xc9a /* 16bit */ +#define TSTTP1_2 0xc9c /* 32bit */ +#define IUB 0xcd0 /* 32bit */ +#define TSC0_1 0xcd8 /* 8bit */ +#define TSS0 0xcda /* 8bit */ +#define TR0 0xcdb /* 8bit */ +#define TSTTP0_1 0xcdc /* 32bit */ +#define TCO0 0xce2 /* 8bit */ +#define THERM0_1 0xce4 /* 8bit */ +#define TCOF0 0xce6 /* 8bit */ +#define TIS0 0xcea /* 16bit */ +#define TSTTP0_2 0xcec /* 32bit */ +#define TERRCMD 0xcf0 /* 8bit */ +#define TSMICMD 0xcf1 /* 8bit */ +#define TSCICMD 0xcf2 /* 8bit */ +#define TINTRCMD 0xcf3 /* 8bit */ +#define EXTTSCS 0xcff /* 8bit */ +#define DFT_STRAP1 0xe08 /* 32bit */ + +/* ACPI Power Management Controls */ + +#define MIPMC3 0xbd8 /* 32bit */ + +#define C2C3TT 0xf00 /* 32bit */ +#define C3C4TT 0xf04 /* 32bit */ + +#define MIPMC4 0xf08 /* 16bit */ +#define MIPMC5 0xf0a /* 16bit */ +#define MIPMC6 0xf0c /* 16bit */ +#define MIPMC7 0xf0e /* 16bit */ +#define PMCFG 0xf10 /* 32bit */ +#define SLFRCS 0xf14 /* 32bit */ +#define GIPMC1 0xfb0 /* 32bit */ +#define FSBPMC1 0xfb8 /* 32bit */ +#define UPMC3 0xfc0 /* 32bit */ +#define ECO 0xffc /* 32bit */ + +/* + * EPBAR - Egress Port Root Complex Register Block + */ + +#define EPBAR8(x) *((volatile u8 *)(DEFAULT_EPBAR + x)) +#define EPBAR16(x) *((volatile u16 *)(DEFAULT_EPBAR + x)) +#define EPBAR32(x) *((volatile u32 *)(DEFAULT_EPBAR + x)) + +#define EPPVCCAP1 0x004 /* 32bit */ +#define EPPVCCAP2 0x008 /* 32bit */ + +#define EPVC0RCAP 0x010 /* 32bit */ +#define EPVC0RCTL 0x014 /* 32bit */ +#define EPVC0RSTS 0x01a /* 16bit */ + +#define EPVC1RCAP 0x01c /* 32bit */ +#define EPVC1RCTL 0x020 /* 32bit */ +#define EPVC1RSTS 0x026 /* 16bit */ + +#define EPVC1MTS 0x028 /* 32bit */ +#define EPVC1IST 0x038 /* 64bit */ + +#define EPESD 0x044 /* 32bit */ + +#define EPLE1D 0x050 /* 32bit */ +#define EPLE1A 0x058 /* 64bit */ +#define EPLE2D 0x060 /* 32bit */ +#define EPLE2A 0x068 /* 64bit */ + +#define PORTARB 0x100 /* 256bit */ + +/* + * DMIBAR + */ + +#define DMIBAR8(x) *((volatile u8 *)(DEFAULT_DMIBAR + x)) +#define DMIBAR16(x) *((volatile u16 *)(DEFAULT_DMIBAR + x)) +#define DMIBAR32(x) *((volatile u32 *)(DEFAULT_DMIBAR + x)) + +#define DMIVCECH 0x000 /* 32bit */ +#define DMIPVCCAP1 0x004 /* 32bit */ +#define DMIPVCCAP2 0x008 /* 32bit */ + +#define DMIPVCCCTL 0x00c /* 16bit */ + +#define DMIVC0RCAP 0x010 /* 32bit */ +#define DMIVC0RCTL0 0x014 /* 32bit */ +#define DMIVC0RSTS 0x01a /* 16bit */ + +#define DMIVC1RCAP 0x01c /* 32bit */ +#define DMIVC1RCTL 0x020 /* 32bit */ +#define DMIVC1RSTS 0x026 /* 16bit */ + +#define DMILE1D 0x050 /* 32bit */ +#define DMILE1A 0x058 /* 64bit */ +#define DMILE2D 0x060 /* 32bit */ +#define DMILE2A 0x068 /* 64bit */ + +#define DMILCAP 0x084 /* 32bit */ +#define DMILCTL 0x088 /* 16bit */ +#define DMILSTS 0x08a /* 16bit */ + +#define DMICTL1 0x0f0 /* 32bit */ +#define DMICTL2 0x0fc /* 32bit */ + +#define DMICC 0x208 /* 32bit */ + +#define DMIDRCCFG 0xeb4 /* 32bit */ + +#endif Added: trunk/coreboot-v2/src/northbridge/intel/i945/ich7.h =================================================================== --- trunk/coreboot-v2/src/northbridge/intel/i945/ich7.h (rev 0) +++ trunk/coreboot-v2/src/northbridge/intel/i945/ich7.h 2008-10-29 04:51:07 UTC (rev 3703) @@ -0,0 +1,142 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __NORTHBRIDGE_INTEL_I945_ICH7_H__ +#define __NORTHBRIDGE_INTEL_I945_ICH7_H__ 1 + +/* Southbridge IO BARs */ +/* TODO Make sure these don't get changed by stage2 */ +#define GPIOBASE 0x48 +#define DEFAULT_GPIOBASE 0x480 + +#define PMBASE 0x40 +#define DEFAULT_PMBASE 0x500 + +/* Root Complex Register Block */ +#define RCBA 0xf0 +#define DEFAULT_RCBA 0xfed1c000 + +#define RCBA8(x) *((volatile u8 *)(DEFAULT_RCBA + x)) +#define RCBA16(x) *((volatile u16 *)(DEFAULT_RCBA + x)) +#define RCBA32(x) *((volatile u32 *)(DEFAULT_RCBA + x)) + +#define VCH 0x0000 /* 32bit */ +#define VCAP1 0x0004 /* 32bit */ +#define VCAP2 0x0008 /* 32bit */ +#define PVC 0x000c /* 16bit */ +#define PVS 0x000e /* 16bit */ + +#define V0CAP 0x0010 /* 32bit */ +#define V0CTL 0x0014 /* 32bit */ +#define V0STS 0x001a /* 16bit */ + +#define V1CAP 0x001c /* 32bit */ +#define V1CTL 0x0020 /* 32bit */ +#define V1STS 0x0026 /* 16bit */ + +#define RCTCL 0x0100 /* 32bit */ +#define ESD 0x0104 /* 32bit */ +#define ULD 0x0110 /* 32bit */ +#define ULBA 0x0118 /* 64bit */ + +#define RP1D 0x0120 /* 32bit */ +#define RP1BA 0x0128 /* 64bit */ +#define RP2D 0x0130 /* 32bit */ +#define RP2BA 0x0138 /* 64bit */ +#define RP3D 0x0140 /* 32bit */ +#define RP3BA 0x0138 /* 64bit */ +#define RP4D 0x0150 /* 32bit */ +#define RP4BA 0x0158 /* 64bit */ +#define HDD 0x0160 /* 32bit */ +#define HDBA 0x0168 /* 64bit */ +#define RP5D 0x0170 /* 32bit */ +#define RP5BA 0x0178 /* 64bit */ +#define RP6D 0x0180 /* 32bit */ +#define RP6BA 0x0188 /* 64bit */ + +#define ILCL 0x01a0 /* 32bit */ +#define LCAP 0x01a4 /* 32bit */ +#define LCTL 0x01a8 /* 16bit */ +#define LSTS 0x01aa /* 16bit */ + +#define RPC 0x0224 /* 32bit */ +#define RPFN 0x0238 /* 32bit */ + +#define TRSR 0x1e00 /* 8bit */ +#define TRCR 0x1e10 /* 64bit */ +#define TWDR 0x1e18 /* 64bit */ + +#define IOTR0 0x1e80 /* 64bit */ +#define IOTR1 0x1e88 /* 64bit */ +#define IOTR2 0x1e90 /* 64bit */ +#define IOTR3 0x1e98 /* 64bit */ + +#define TCTL 0x3000 /* 8bit */ + +#define D31IP 0x3100 /* 32bit */ +#define D30IP 0x3104 /* 32bit */ +#define D29IP 0x3108 /* 32bit */ +#define D28IP 0x310c /* 32bit */ +#define D27IP 0x3110 /* 32bit */ +#define D31IR 0x3140 /* 16bit */ +#define D30IR 0x3142 /* 16bit */ +#define D29IR 0x3144 /* 16bit */ +#define D28IR 0x3146 /* 16bit */ +#define D27IR 0x3148 /* 16bit */ +#define OIC 0x31ff /* 8bit */ + +#define RC 0x3400 /* 32bit */ +#define HPTC 0x3404 /* 32bit */ +#define GCS 0x3410 /* 32bit */ +#define BUC 0x3414 /* 32bit */ +#define FD 0x3418 /* 32bit */ +#define CG 0x341c /* 32bit */ + +/* Function Disable (FD) register values. + * Setting a bit disables the corresponding + * feature. + * Not all features might be disabled on + * all chipsets. Esp. ICH-7U is picky. + */ +#define FD_PCIE6 (1 << 21) +#define FD_PCIE5 (1 << 20) +#define FD_PCIE4 (1 << 19) +#define FD_PCIE3 (1 << 18) +#define FD_PCIE2 (1 << 17) +#define FD_PCIE1 (1 << 16) +#define FD_EHCI (1 << 15) +#define FD_LPCB (1 << 14) + +/* UHCI must be disabled from 4 downwards. + * If UHCI controllers get disabled, EHCI + * must know about it, too! */ +#define FD_UHCI4 (1 << 11) +#define FD_UHCI34 (1 << 10) | FD_UHCI4 +#define FD_UHCI234 (1 << 9) | FD_UHCI3 +#define FD_UHCI1234 (1 << 8) | FD_UHCI2 + +#define FD_INTLAN (1 << 7) +#define FD_ACMOD (1 << 6) +#define FD_ACAUD (1 << 5) +#define FD_HDAUD (1 << 4) +#define FD_SMBUS (1 << 3) +#define FD_SATA (1 << 2) +#define FD_PATA (1 << 1) + +#endif Added: trunk/coreboot-v2/src/northbridge/intel/i945/northbridge.c =================================================================== --- trunk/coreboot-v2/src/northbridge/intel/i945/northbridge.c (rev 0) +++ trunk/coreboot-v2/src/northbridge/intel/i945/northbridge.c 2008-10-29 04:51:07 UTC (rev 3703) @@ -0,0 +1,283 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <arch/io.h> +#include <stdint.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <device/hypertransport.h> +#include <stdlib.h> +#include <string.h> +#include <bitops.h> +#include <cpu/cpu.h> +#include "chip.h" +#include "i945.h" + +static void ram_resource(device_t dev, unsigned long index, unsigned long basek, + unsigned long sizek) +{ + struct resource *resource; + + resource = new_resource(dev, index); + resource->base = ((resource_t) basek) << 10; + resource->size = ((resource_t) sizek) << 10; + resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE | + IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; +} + +static void pci_domain_read_resources(device_t dev) +{ + struct resource *resource; + + /* Initialize the system wide io space constraints */ + resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); + resource->base = 0; + resource->size = 0; + resource->align = 0; + resource->gran = 0; + resource->limit = 0xffffUL; + resource->flags = + IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; + + /* Initialize the system wide memory resources constraints */ + resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); + resource->base = 0; + resource->size = 0; + resource->align = 0; + resource->gran = 0; + resource->limit = 0xffffffffUL; + resource->flags = + IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; +} + +static void tolm_test(void *gp, struct device *dev, struct resource *new) +{ + struct resource **best_p = gp; + struct resource *best; + best = *best_p; + if (!best || (best->base > new->base)) { + best = new; + } + *best_p = best; +} + +static uint32_t find_pci_tolm(struct bus *bus) +{ + struct resource *min; + uint32_t tolm; + min = 0; + search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, + &min); + tolm = 0xffffffffUL; + if (min && tolm > min->base) { + tolm = min->base; + } + return tolm; +} + +static void pci_domain_set_resources(device_t dev) +{ + uint32_t pci_tolm; + uint8_t tolud, reg8; + uint16_t reg16; + unsigned long long tomk, tolmk; + + pci_tolm = find_pci_tolm(&dev->link[0]); + + printk_spew("Base of stolen memory: 0x%08x\n", + pci_read_config32(dev_find_slot(0, PCI_DEVFN(2, 0)), 0x5c)); + + tolud = pci_read_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), 0x9c); + printk_spew("Top of Low Used DRAM: 0x%08x\n", tolud << 24); + + tomk = tolud << 14; + + /* Note: subtract IGD device and TSEG */ + reg8 = pci_read_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), 0x9e); + if (reg8 & 1) { + int tseg_size = 0; + printk_debug("TSEG decoded, subtracting "); + reg8 >>= 1; + reg8 &= 3; + switch (reg8) { + case 0: + tseg_size = 1024; + break; + case 1: + tseg_size = 2048; + break; + case 2: + tseg_size = 8192; + break; + } + + printk_debug("%dM\n", tseg_size >> 10); + tomk -= tseg_size; + } + + reg16 = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0, 0)), GGC); + if (!(reg16 & 2)) { + int uma_size = 0; + printk_debug("IGD decoded, subtracting "); + reg16 >>= 4; + reg16 &= 7; + switch (reg16) { + case 1: + uma_size = 1024; + break; + case 3: + uma_size = 8192; + break; + } + + printk_debug("%dM UMA\n", uma_size >> 10); + tomk -= uma_size; + } + + /* The following needs to be 2 lines, otherwise the second + * number is always 0 + */ + printk_info("Available memory: %dK", tomk); + printk_info(" (%dM)\n", (tomk >> 10)); + + tolmk = tomk; + + /* Report the memory regions */ + ram_resource(dev, 3, 0, 640); + ram_resource(dev, 4, 768, (tolmk - 768)); + if (tomk > 4 * 1024 * 1024) { + ram_resource(dev, 5, 4096 * 1024, tomk - 4 * 1024 * 1024); + } + + assign_resources(&dev->link[0]); +} + +static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max) +{ + max = pci_scan_bus(&dev->link[0], 0, 0xff, max); + /* TODO We could determine how many PCIe busses we need in + * the bar. For now that number is hardcoded to a max of 64. + */ + return max; +} + +static struct device_operations pci_domain_ops = { + .read_resources = pci_domain_read_resources, + .set_resources = pci_domain_set_resources, + .enable_resources = enable_childrens_resources, + .init = 0, + .scan_bus = pci_domain_scan_bus, + .ops_pci_bus = &pci_cf8_conf1, /* Do we want to use the memory mapped space here? */ +}; + +static void mc_read_resources(device_t dev) +{ + struct resource *resource; + + pci_dev_read_resources(dev); + + /* So, this is one of the big mysteries in the coreboot resource + * allocator. This resource should make sure that the address space + * of the PCIe memory mapped config space bar. But it does not. + */ + + /* We use 0xcf as an unused index for our PCIe bar so that we find it again */ + resource = new_resource(dev, 0xcf); + resource->base = DEFAULT_PCIEXBAR; + resource->size = 64 * 1024 * 1024; /* 64MB hard coded PCIe config space */ + resource->flags = + IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED | + IORESOURCE_ASSIGNED; + printk_debug("Adding PCIe enhanced config space BAR 0x%08x-0x%08x.\n", + resource->base, (resource->base + resource->size)); +} + +static void mc_set_resources(device_t dev) +{ + struct resource *resource, *last; + + /* Report the PCIe BAR */ + last = &dev->resource[dev->resources]; + resource = find_resource(dev, 0xcf); + if (resource) { + report_resource_stored(dev, resource, "<mmconfig>"); + } + + /* And call the normal set_resources */ + pci_dev_set_resources(dev); +} + +static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device) +{ + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, + ((device & 0xffff) << 16) | (vendor & 0xffff)); +} + +static struct pci_operations intel_pci_ops = { + .set_subsystem = intel_set_subsystem, +}; + +static struct device_operations mc_ops = { + .read_resources = mc_read_resources, + .set_resources = mc_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = 0, + .scan_bus = 0, + .ops_pci = &intel_pci_ops, +}; + +static const struct pci_driver mc_driver __pci_driver = { + .ops = &mc_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x27a0, +}; + +static void cpu_bus_init(device_t dev) +{ + initialize_cpus(&dev->link[0]); +} + +static void cpu_bus_noop(device_t dev) +{ +} + +static struct device_operations cpu_bus_ops = { + .read_resources = cpu_bus_noop, + .set_resources = cpu_bus_noop, + .enable_resources = cpu_bus_noop, + .init = cpu_bus_init, + .scan_bus = 0, +}; + +static void enable_dev(device_t dev) +{ + /* Set the operations if it is a special bus type */ + if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) { + dev->ops = &pci_domain_ops; + } else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) { + dev->ops = &cpu_bus_ops; + } +} + +struct chip_operations northbridge_intel_i945_ops = { + CHIP_NAME("Intel i945 Northbridge") + .enable_dev = enable_dev, +}; Added: trunk/coreboot-v2/src/northbridge/intel/i945/pcie_config.c =================================================================== --- trunk/coreboot-v2/src/northbridge/intel/i945/pcie_config.c (rev 0) +++ trunk/coreboot-v2/src/northbridge/intel/i945/pcie_config.c 2008-10-29 04:51:07 UTC (rev 3703) @@ -0,0 +1,68 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "i945.h" + +static inline __attribute__ ((always_inline)) +u8 pcie_read_config8(device_t dev, unsigned int where) +{ + unsigned long addr; + addr = DEFAULT_PCIEXBAR | dev | where; + return read8(addr); +} + +static inline __attribute__ ((always_inline)) +u16 pcie_read_config16(device_t dev, unsigned int where) +{ + unsigned long addr; + addr = DEFAULT_PCIEXBAR | dev | where; + return read16(addr); +} + +static inline __attribute__ ((always_inline)) +u32 pcie_read_config32(device_t dev, unsigned int where) +{ + unsigned long addr; + addr = DEFAULT_PCIEXBAR | dev | where; + return read32(addr); +} + +static inline __attribute__ ((always_inline)) +void pcie_write_config8(device_t dev, unsigned int where, u8 value) +{ + unsigned long addr; + addr = DEFAULT_PCIEXBAR | dev | where; + write8(addr, value); +} + +static inline __attribute__ ((always_inline)) +void pcie_write_config16(device_t dev, unsigned int where, u16 value) +{ + unsigned long addr; + addr = DEFAULT_PCIEXBAR | dev | where; + write16(addr, value); +} + +static inline __attribute__ ((always_inline)) +void pcie_write_config32(device_t dev, unsigned int where, u32 value) +{ + unsigned long addr; + addr = DEFAULT_PCIEXBAR | dev | where; + write32(addr, value); +} Added: trunk/coreboot-v2/src/northbridge/intel/i945/raminit.c =================================================================== --- trunk/coreboot-v2/src/northbridge/intel/i945/raminit.c (rev 0) +++ trunk/coreboot-v2/src/northbridge/intel/i945/raminit.c 2008-10-29 04:51:07 UTC (rev 3703) @@ -0,0 +1,2779 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +#include <cpu/x86/mem.h> +#include <cpu/x86/mtrr.h> +#include <cpu/x86/cache.h> +#include <spd.h> +#include "raminit.h" +#include "i945.h" + +#include "lib/memset.c" + +#define DEBUG_RAM_SETUP + +/* Debugging macros. */ +#if defined(DEBUG_RAM_SETUP) +#define PRINTK_DEBUG(x...) printk_debug(x) +#else +#define PRINTK_DEBUG(x...) +#endif + + +#define RAM_INITIALIZATION_COMPLETE (1 << 19) + +#define RAM_COMMAND_SELF_REFRESH (0x0 << 16) +#define RAM_COMMAND_NOP (0x1 << 16) +#define RAM_COMMAND_PRECHARGE (0x2 << 16) +#define RAM_COMMAND_MRS (0x3 << 16) +#define RAM_COMMAND_EMRS (0x4 << 16) +#define RAM_COMMAND_CBR (0x6 << 16) +#define RAM_COMMAND_NORMAL (0x7 << 16) + +#define RAM_EMRS_1 (0x0 << 21) +#define RAM_EMRS_2 (0x1 << 21) +#define RAM_EMRS_3 (0x2 << 21) + +static void do_ram_command(u32 command) +{ + u32 reg32; + + reg32 = MCHBAR32(DCC); + reg32 &= ~( (3<<21) | (1<<20) | (1<<19) | (7 << 16) ); + reg32 |= command; + + /* Also set Init Complete */ + if (command == RAM_COMMAND_NORMAL) + reg32 |= RAM_INITIALIZATION_COMPLETE; + + PRINTK_DEBUG(" Sending RAM command 0x%08x", reg32); + + MCHBAR32(DCC) = reg32; /* This is the actual magic */ + + PRINTK_DEBUG("...done\r\n"); +} + + +static void ram_read32(u32 offset) +{ + PRINTK_DEBUG(" ram read: %08x\r\n", offset); + + read32(offset); +} + +#ifdef DEBUG_RAM_SETUP +static void sdram_dump_mchbar_registers(void) +{ + int i; + printk_debug("Dumping MCHBAR Registers\r\n"); + + for (i=0; i<0xfff; i+=4) { + if (MCHBAR32(i) == 0) + continue; + printk_debug("0x%04x: 0x%08x\r\n", i, MCHBAR32(i)); + } +} +#endif + +static int sdram_capabilities_max_supported_memory_frequency(void) +{ + u32 reg32; + + reg32 = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xe4); + reg32 &= (7 << 0); + + switch (reg32) { + case 4: return 400; + case 3: return 533; + case 2: return 667; + } + /* Newer revisions of this chipset rather support faster memory clocks, + * so if it's a reserved value, return the fastest memory clock that we + * know of and can handle + */ + return 667; +} + +/** + * @brief determine whether chipset is capable of dual channel interleaved mode + * + * @return 1 if interleaving is supported, 0 otherwise + */ +static int sdram_capabilities_interleave(void) +{ + u32 reg32; + + reg32 = pci_read_config8(PCI_DEV(0, 0x00,0), 0xe4); + reg32 >>= 25; + reg32 &= 1; + + return (!reg32); +} + +/** + * @brief determine whether chipset is capable of two memory channels + * + * @return 1 if dual channel operation is supported, 0 otherwise + */ +static int sdram_capabilities_dual_channel(void) +{ + u32 reg32; + + reg32 = pci_read_config8(PCI_DEV(0, 0x00,0), 0xe4); + reg32 >>= 24; + reg32 &= 1; + + return (!reg32); +} + +static int sdram_capabilities_enhanced_addressing_xor(void) +{ + u8 reg8; + + reg8 = pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe5); /* CAPID0 + 5 */ + reg8 &= (1 << 7); + + return (!reg8); +} + +static int sdram_capabilities_two_dimms_per_channel(void) +{ + u8 reg8; + + reg8 = pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe8); /* CAPID0 + 8 */ + reg8 &= (1 << 0); + + return (reg8 != 0); +} + +static int sdram_capabilities_MEM4G_disable(void) +{ + u8 reg8; + + reg8 = pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe5); + reg8 &= (1 << 0); + + return (reg8 != 0); +} + +static void sdram_detect_errors(void) +{ + u8 reg8; + + reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2); + + if (reg8 & ((1<<7)|(1<<2))) { + if (reg8 & (1<<2)) { + printk_debug("SLP S4# Assertion Width Violation.\r\n"); + + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8); + } + + if (reg8 & (1<<7)) { + printk_debug("DRAM initialization was interrupted.\r\n"); + reg8 &= ~(1<<7); + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8); + } + + /* Set SLP_S3# Assertion Stretch Enable */ + reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4); /* GEN_PMCON_3 */ + reg8 |= (1 << 3); + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8); + + printk_debug("Reset required.\r\n"); + outb(0x00, 0xcf9); + outb(0x0e, 0xcf9); + for (;;) ; /* Wait for reset! */ + } + + /* Set DRAM initialization bit in ICH7 */ + reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2); + reg8 |= (1<<7); + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8); + +} + + +/** + * @brief Get generic DIMM parameters. + * @param sysinfo Central memory controller information structure + * + * This function gathers several pieces of information for each system DIMM: + * o DIMM width (x8 / x16) + * o DIMM sides (single sided / dual sided) + * + * Also, some non-supported scenarios are detected. + */ + +static void sdram_get_dram_configuration(struct sys_info *sysinfo) +{ + u32 dimm_mask = 0; + int i; + + /** + * i945 supports two DIMMs, in two configurations: + * + * - single channel with two dimms + * - dual channel with one dimm per channel + * + * In practice dual channel mainboards have their spd at 0x50, 0x52 + * whereas single channel configurations have their spd at 0x50/x51 + * + * The capability register knows a lot about the channel configuration + * but for now we stick with the information we gather from the SPD + * ROMs + */ + + if (sdram_capabilities_dual_channel()) { + sysinfo->dual_channel = 1; + printk_debug("This mainboard supports Dual Channel Operation.\n"); + } else { + sysinfo->dual_channel = 0; + printk_debug("This mainboard supports only Single Channel Operation.\n"); + } + + /** + * Since we only support two DIMMs in total, there is a limited number + * of combinations. This function returns the type of DIMMs. + * return value: + * [0:7] lower DIMM population + * [8-15] higher DIMM population + * [16] dual channel? + * + * There are 5 different possible populations for a DIMM socket: + * 1. x16 double sided (X16DS) + * 2. x8 double sided (X8DS) + * 3. x16 single sided (X16SS) + * 4. x8 double stacked (X8DDS) + * 5. not populated (NC) + * + * For the return value we start counting at zero. + * + */ + + for (i=0; i<(2 * DIMM_SOCKETS); i++) { + u8 reg8, device = DIMM_SPD_BASE + i; + + /* Initialize the socket information with a sane value */ + sysinfo->dimm[i] = SYSINFO_DIMM_NOT_POPULATED; + + if (!sdram_capabilities_dual_channel() && (i >> 1)) + continue; + if (!sdram_capabilities_two_dimms_per_channel() && (i& 1)) + continue; + + printk_debug("DDR II Channel %d Socket %d: ", (i >> 1), (i & 1)); + + if (spd_read_byte(device, SPD_MEMORY_TYPE) != SPD_MEMORY_TYPE_SDRAM_DDR2) { + printk_debug("N/A\n"); + continue; + } + + reg8 = spd_read_byte(device, SPD_DIMM_CONFIG_TYPE); + if (reg8 == ERROR_SCHEME_ECC) + die("Error: ECC memory not supported by this chipset\r\n"); + + reg8 = spd_read_byte(device, SPD_MODULE_ATTRIBUTES); + if (reg8 & MODULE_BUFFERED) + die("Error: Buffered memory not supported by this chipset\r\n"); + if (reg8 & MODULE_REGISTERED) + die("Error: Registered memory not supported by this chipset\r\n"); + + switch (spd_read_byte(device, SPD_PRIMARY_SDRAM_WIDTH)) { + case 0x08: + switch (spd_read_byte(device, SPD_NUM_DIMM_BANKS) & 0x0f) { + case 1: + printk_debug("x8DDS\r\n"); + sysinfo->dimm[i] = SYSINFO_DIMM_X8DDS; + break; + case 0: + printk_debug("x8DS\r\n"); + sysinfo->dimm[i] = SYSINFO_DIMM_X8DS; + break; + default: + printk_debug ("Unsupported.\r\n"); + } + break; + case 0x10: + switch (spd_read_byte(device, SPD_NUM_DIMM_BANKS) & 0x0f) { + case 1: + printk_debug("x16DS\r\n"); + sysinfo->dimm[i] = SYSINFO_DIMM_X16DS; + break; + case 0: + printk_debug("x16SS\r\n"); + sysinfo->dimm[i] = SYSINFO_DIMM_X16SS; + break; + default: + printk_debug ("Unsupported.\r\n"); + } + break; + default: + die("Unsupported DDR-II memory width.\r\n"); + } + + dimm_mask |= (1 << i); + } + + if (!dimm_mask) { + die("No memory installed.\r\n"); + } + + /* The chipset might be able to do this. What the heck, legacy bios + * just beeps when a single DIMM is in the Channel 1 socket. So let's + * not bother until someone needs this enough to cope with it. + */ + if (!(dimm_mask & ((1 << DIMM_SOCKETS) - 1))) { + printk_err("Channel 0 has no memory populated. This setup is not usable. Please move the DIMM.\r\n"); + } +} + +/** + * @brief determine if any DIMMs are stacked + * + * @param sysinfo central sysinfo data structure. + */ +static void sdram_verify_package_type(struct sys_info * sysinfo) +{ + int i; + + /* Assume no stacked DIMMs are available until we find one */ + sysinfo->package = 0; + for (i=0; i<2*DIMM_SOCKETS; i++) { + if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED) + continue; + + /* Is the current DIMM a stacked DIMM? */ + if (spd_read_byte(DIMM_SPD_BASE + i, SPD_NUM_DIMM_BANKS) & (1 << 4)) + sysinfo->package = 1; + } +} + +static u8 sdram_possible_cas_latencies(struct sys_info * sysinfo) +{ + int i; + u8 cas_mask; + + /* Setup CAS mask with all supported CAS Latencies */ + cas_mask = SPD_CAS_LATENCY_DDR2_3 | + SPD_CAS_LATENCY_DDR2_4 | + SPD_CAS_LATENCY_DDR2_5; + + for (i=0; i<2*DIMM_SOCKETS; i++) { + if (sysinfo->dimm[i] != SYSINFO_DIMM_NOT_POPULATED) + cas_mask &= spd_read_byte(DIMM_SPD_BASE + i, SPD_ACCEPTABLE_CAS_LATENCIES); + } + + if(!cas_mask) { + die("No DDR-II modules with accepted CAS latencies found.\n"); + } + + return cas_mask; +} + +static void sdram_detect_cas_latency_and_ram_speed(struct sys_info * sysinfo, u8 cas_mask) +{ + int i, j, idx; + int lowest_common_cas = 0; + int max_ram_speed; + + const u8 ddr2_speeds_table[] = { + 0x50, 0x60, /* DDR2 400: tCLK = 5.0ns tAC = 0.6ns */ + 0x3d, 0x50, /* DDR2 533: tCLK = 3.75ns tAC = 0.5ns */ + 0x30, 0x45, /* DDR2 667: tCLK = 3.0ns tAC = 0.45ns */ + }; + + const u8 spd_lookup_table[] = { + SPD_MIN_CYCLE_TIME_AT_CAS_MAX, SPD_ACCESS_TIME_FROM_CLOCK, + SPD_SDRAM_CYCLE_TIME_2ND, SPD_ACCESS_TIME_FROM_CLOCK_2ND, + SPD_SDRAM_CYCLE_TIME_3RD, SPD_ACCESS_TIME_FROM_CLOCK_3RD + }; + + switch (sdram_capabilities_max_supported_memory_frequency()) { + case 400: max_ram_speed = 0; break; + case 533: max_ram_speed = 1; break; + case 667: max_ram_speed = 2; break; + } + + sysinfo->memory_frequency = 0; + sysinfo->cas = 0; + + if (cas_mask & SPD_CAS_LATENCY_DDR2_3) { + lowest_common_cas = 3; + } else if (cas_mask & SPD_CAS_LATENCY_DDR2_4) { + lowest_common_cas = 4; + } else if (cas_mask & SPD_CAS_LATENCY_DDR2_5) { + lowest_common_cas = 5; + } + PRINTK_DEBUG("lowest common cas = %d\n", lowest_common_cas); + + for (j = max_ram_speed; j>=0; j--) { + int freq_cas_mask = cas_mask; + + PRINTK_DEBUG("Probing Speed %d\n", j); + for (i=0; i<2*DIMM_SOCKETS; i++) { + int current_cas_mask; + + PRINTK_DEBUG(" DIMM: %d\n", i); + if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED) { + continue; + } + + current_cas_mask = spd_read_byte(DIMM_SPD_BASE + i, SPD_ACCEPTABLE_CAS_LATENCIES); + + while (current_cas_mask) { + int highest_supported_cas = 0, current_cas = 0; + PRINTK_DEBUG(" Current CAS mask: %04x; ", current_cas_mask); + if (current_cas_mask & SPD_CAS_LATENCY_DDR2_5) { + highest_supported_cas = 5; + } else if (current_cas_mask & SPD_CAS_LATENCY_DDR2_4) { + highest_supported_cas = 4; + } else if (current_cas_mask & SPD_CAS_LATENCY_DDR2_3) { + highest_supported_cas = 3; + } + if (current_cas_mask & SPD_CAS_LATENCY_DDR2_3) { + current_cas = 3; + } else if (current_cas_mask & SPD_CAS_LATENCY_DDR2_4) { + current_cas = 4; + } else if (current_cas_mask & SPD_CAS_LATENCY_DDR2_5) { + current_cas = 5; + } + + idx = highest_supported_cas - current_cas; + PRINTK_DEBUG("idx=%d, ", idx); + PRINTK_DEBUG("tCLK=%x, ", spd_read_byte(DIMM_SPD_BASE + i, spd_lookup_table[2*idx])); + PRINTK_DEBUG("tAC=%x", spd_read_byte(DIMM_SPD_BASE + i, spd_lookup_table[(2*idx)+1])); + + if (spd_read_byte(DIMM_SPD_BASE + i, spd_lookup_table[2*idx]) <= ddr2_speeds_table[2*j] && + spd_read_byte(DIMM_SPD_BASE + i, spd_lookup_table[(2*idx)+1]) <= ddr2_speeds_table[(2*j)+1]) { + PRINTK_DEBUG(": OK\n"); + break; + } + + PRINTK_DEBUG(": Not fast enough!\n"); + + current_cas_mask &= ~(1 << (current_cas)); + } + + freq_cas_mask &= current_cas_mask; + if (!current_cas_mask) { + PRINTK_DEBUG(" No valid CAS for this speed on DIMM %d\n", i); + break; + } + } + PRINTK_DEBUG(" freq_cas_mask for speed %d: %04x\n", j, freq_cas_mask); + if (freq_cas_mask) { + switch (j) { + case 0: sysinfo->memory_frequency = 400; break; + case 1: sysinfo->memory_frequency = 533; break; + case 2: sysinfo->memory_frequency = 667; break; + } + if (freq_cas_mask & SPD_CAS_LATENCY_DDR2_3) { + sysinfo->cas = 3; + } else if (freq_cas_mask & SPD_CAS_LATENCY_DDR2_4) { + sysinfo->cas = 4; + } else if (freq_cas_mask & SPD_CAS_LATENCY_DDR2_5) { + sysinfo->cas = 5; + } + break; + } + } + + if (sysinfo->memory_frequency && sysinfo->cas) { + printk_debug("Memory will be driven at %dMHz with CAS=%d clocks\n", + sysinfo->memory_frequency, sysinfo->cas); + } else { + die("Could not find common memory frequency and CAS\n"); + } +} + +static void sdram_detect_smallest_tRAS(struct sys_info * sysinfo) +{ + int i; + int tRAS_time; + int tRAS_cycles; + int freq_multiplier = 0; + + switch (sysinfo->memory_frequency) { + case 400: freq_multiplier = 0x14; break; /* 5ns */ + case 533: freq_multiplier = 0x0f; break; /* 3.75ns */ + case 667: freq_multiplier = 0x0c; break; /* 3ns */ + } + + tRAS_cycles = 4; /* 4 clocks minimum */ + tRAS_time = tRAS_cycles * freq_multiplier; + + for (i=0; i<2*DIMM_SOCKETS; i++) { + u8 reg8; + + if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED) + continue; + + reg8 = spd_read_byte(DIMM_SPD_BASE + i, SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY); + if (!reg8) { + die("Invalid tRAS value.\n"); + } + + while ((tRAS_time >> 2) < reg8) { + tRAS_time += freq_multiplier; + tRAS_cycles++; + } + } + if(tRAS_cycles > 0x18) { + die("DDR-II Module does not support this frequency (tRAS error)\n"); + } + + printk_debug("tRAS = %d cycles\n", tRAS_cycles); + sysinfo->tras = tRAS_cycles; +} + +static void sdram_detect_smallest_tRP(struct sys_info * sysinfo) +{ + int i; + int tRP_time; + int tRP_cycles; + int freq_multiplier = 0; + + switch (sysinfo->memory_frequency) { + case 400: freq_multiplier = 0x14; break; /* 5ns */ + case 533: freq_multiplier = 0x0f; break; /* 3.75ns */ + case 667: freq_multiplier = 0x0c; break; /* 3ns */ + } + + tRP_cycles = 2; /* 2 clocks minimum */ + tRP_time = tRP_cycles * freq_multiplier; + + for (i=0; i<2*DIMM_SOCKETS; i++) { + u8 reg8; + + if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED) + continue; + + reg8 = spd_read_byte(DIMM_SPD_BASE + i, SPD_MIN_ROW_PRECHARGE_TIME); + if (!reg8) { + die("Invalid tRP value.\n"); + } + + while (tRP_time < reg8) { + tRP_time += freq_multiplier; + tRP_cycles++; + } + } + + if(tRP_cycles > 6) { + die("DDR-II Module does not support this frequency (tRP error)\n"); + } + + printk_debug("tRP = %d cycles\n", tRP_cycles); + sysinfo->trp = tRP_cycles; +} + +static void sdram_detect_smallest_tRCD(struct sys_info * sysinfo) +{ + int i; + int tRCD_time; + int tRCD_cycles; + int freq_multiplier = 0; + + switch (sysinfo->memory_frequency) { + case 400: freq_multiplier = 0x14; break; /* 5ns */ + case 533: freq_multiplier = 0x0f; break; /* 3.75ns */ + case 667: freq_multiplier = 0x0c; break; /* 3ns */ + } + + tRCD_cycles = 2; + tRCD_time = tRCD_cycles * freq_multiplier; + + for (i=0; i<2*DIMM_SOCKETS; i++) { + u8 reg8; + + if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED) + continue; + + reg8 = spd_read_byte(DIMM_SPD_BASE + i, SPD_MIN_RAS_TO_CAS_DELAY); + if (!reg8) { + die("Invalid tRCD value.\n"); + } + + while (tRCD_time < reg8) { + tRCD_time += freq_multiplier; + tRCD_cycles++; + } + } + if(tRCD_cycles > 6) { + die("DDR-II Module does not support this frequency (tRCD error)\n"); + } + + printk_debug("tRCD = %d cycles\n", tRCD_cycles); + sysinfo->trcd = tRCD_cycles; +} + +static void sdram_detect_smallest_tWR(struct sys_info * sysinfo) +{ + int i; + int tWR_time; + int tWR_cycles; + int freq_multiplier = 0; + + switch (sysinfo->memory_frequency) { + case 400: freq_multiplier = 0x14; break; /* 5ns */ + case 533: freq_multiplier = 0x0f; break; /* 3.75ns */ + case 667: freq_multiplier = 0x0c; break; /* 3ns */ + } + + tWR_cycles = 2; /* 2 clocks minimum */ + tWR_time = tWR_cycles * freq_multiplier; + + for (i=0; i<2*DIMM_SOCKETS; i++) { + u8 reg8; + + if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED) + continue; + + reg8 = spd_read_byte(DIMM_SPD_BASE + i, SPD_WRITE_RECOVERY_TIME); + if (!reg8) { + die("Invalid tWR value.\n"); + } + + while (tWR_time < reg8) { + tWR_time += freq_multiplier; + tWR_cycles++; + } + } + if(tWR_cycles > 5) { + die("DDR-II Module does not support this frequency (tWR error)\n"); + } + + printk_debug("tWR = %d cycles\n", tWR_cycles); + sysinfo->twr = tWR_cycles; +} + +static void sdram_detect_smallest_tRFC(struct sys_info * sysinfo) +{ + int i, index = 0; + + const u8 tRFC_cycles[] = { + /* 75 105 127.5 */ + 15, 21, 26, /* DDR2-400 */ + 20, 28, 34, /* DDR2-533 */ + 25, 35, 43 /* DDR2-667 */ + }; + + for (i=0; i<2*DIMM_SOCKETS; i++) { + u8 reg8; + + if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED) + continue; + + reg8 = sysinfo->banksize[i*2]; + switch (reg8) { + case 0x04: reg8 = 0; break; + case 0x08: reg8 = 1; break; + case 0x10: reg8 = 2; break; + case 0x20: reg8 = 3; break; + } + + if (sysinfo->dimm[i] == SYSINFO_DIMM_X16DS || sysinfo->dimm[i] == SYSINFO_DIMM_X16SS) + reg8++; + + if (reg8 > 3) { + /* Can this happen? Go back to 127.5ns just to be sure + * we don't run out of the array. This may be wrong + */ + printk_debug("DIMM %d is 1Gb x16.. Please report.\n", i); + reg8 = 3; + } + + if (reg8 > index) + index = reg8; + + } + index--; + switch (sysinfo->memory_frequency) { + case 667: index += 3; + case 533: index += 3; + case 400: break; + } + + sysinfo->trfc = tRFC_cycles[index]; + printk_debug("tRFC = %d cycles\n", tRFC_cycles[index]); +} + + +static void sdram_detect_smallest_refresh(struct sys_info * sysinfo) +{ + int i; + + sysinfo->refresh = 0; + + for (i=0; i<2*DIMM_SOCKETS; i++) { + int refresh; + + if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED) + continue; + + refresh = spd_read_byte(DIMM_SPD_BASE + i, SPD_REFRESH) & ~(1 << 7); + + /* 15.6us */ + if (!refresh) + continue; + + /* Refresh is slower than 15.6us, use 15.6us */ + if (refresh > 2) + continue; + + if (refresh == 2) { + sysinfo->refresh = 1; + break; + } + + die("DDR-II module has unsupported refresh value\n"); + } + printk_debug("Refresh: %s\n", sysinfo->refresh?"7.8us":"15.6us"); +} + +static void sdram_verify_burst_length(struct sys_info * sysinfo) +{ + int i; + + for (i=0; i<2*DIMM_SOCKETS; i++) { + if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED) + continue; + + if (!(spd_read_byte(DIMM_SPD_BASE + i, SPD_SUPPORTED_BURST_LENGTHS) & SPD_BURST_LENGTH_8)) + die("Only DDR-II RAM with burst length 8 is supported by this chipset.\n"); + } +} + +static void sdram_program_dram_width(struct sys_info * sysinfo) +{ + u16 c0dramw=0, c1dramw=0; + int idx; + + if (sysinfo->dual_channel) + idx = 2; + else + idx = 1; + + switch (sysinfo->dimm[0]) { + case 0: c0dramw = 0x0000; break; /* x16DS */ + case 1: c0dramw = 0x0001; break; /* x8DS */ + case 2: c0dramw = 0x0000; break; /* x16SS */ + case 3: c0dramw = 0x0005; break; /* x8DDS */ + case 4: c0dramw = 0x0000; break; /* NC */ + } + + switch (sysinfo->dimm[idx]) { + case 0: c1dramw = 0x0000; break; /* x16DS */ + case 1: c1dramw = 0x0010; break; /* x8DS */ + case 2: c1dramw = 0x0000; break; /* x16SS */ + case 3: c1dramw = 0x0050; break; /* x8DDS */ + case 4: c1dramw = 0x0000; break; /* NC */ + } + + if ( !sdram_capabilities_dual_channel() ) { + /* Single Channel */ + c0dramw |= c1dramw; + c1dramw = 0; + } + + MCHBAR16(C0DRAMW) = c0dramw; + MCHBAR16(C1DRAMW) = c1dramw; +} + +static void sdram_write_slew_rates(u32 offset, const u32 *slew_rate_table) +{ + int i; + + for (i=0; i<16; i++) + MCHBAR32(offset+(i*4)) = slew_rate_table[i]; +} + +static void sdram_rcomp_buffer_strength_and_slew(struct sys_info *sysinfo) +{ + static const u32 dq2030[] = { + 0x08070706, 0x0a090908, 0x0d0c0b0a, 0x12100f0e, + 0x1a181614, 0x22201e1c, 0x2a282624, 0x3934302d, + 0x0a090908, 0x0c0b0b0a, 0x0e0d0d0c, 0x1211100f, + 0x19171513, 0x211f1d1b, 0x2d292623, 0x3f393531 + }; + + static const u32 dq2330[] = { + 0x08070706, 0x0a090908, 0x0d0c0b0a, 0x12100f0e, + 0x1a181614, 0x22201e1c, 0x2a282624, 0x3934302d, + 0x0a090908, 0x0c0b0b0a, 0x0e0d0d0c, 0x1211100f, + 0x19171513, 0x211f1d1b, 0x2d292623, 0x3f393531 + }; + + static const u32 cmd2710[] = { + 0x07060605, 0x0f0d0b09, 0x19171411, 0x1f1f1d1b, + 0x1f1f1f1f, 0x1f1f1f1f, 0x1f1f1f1f, 0x1f1f1f1f, + + 0x1110100f, 0x0f0d0b09, 0x19171411, 0x1f1f1d1b, + 0x1f1f1f1f, 0x1f1f1f1f, 0x1f1f1f1f, 0x1f1f1f1f + }; + + static const u32 cmd3210[] = { + 0x0f0d0b0a, 0x17151311, 0x1f1d1b19, 0x1f1f1f1f, + 0x1f1f1f1f, 0x1f1f1f1f, 0x1f1f1f1f, 0x1f1f1f1f, + 0x18171615, 0x1f1f1c1a, 0x1f1f1f1f, 0x1f1f1f1f, + 0x1f1f1f1f, 0x1f1f1f1f, 0x1f1f1f1f, 0x1f1f1f1f + }; + + static const u32 clk2030[] = { + 0x0e0d0d0c, 0x100f0f0e, 0x100f0e0d, 0x15131211, + 0x1d1b1917, 0x2523211f, 0x2a282927, 0x32302e2c, + 0x17161514, 0x1b1a1918, 0x1f1e1d1c, 0x23222120, + 0x27262524, 0x2d2b2928, 0x3533312f, 0x3d3b3937 + }; + + static const u32 ctl3215[] = { + 0x01010000, 0x03020101, 0x07060504, 0x0b0a0908, + 0x100f0e0d, 0x14131211, 0x18171615, 0x1c1b1a19, + 0x05040403, 0x07060605, 0x0a090807, 0x0f0d0c0b, + 0x14131211, 0x18171615, 0x1c1b1a19, 0x201f1e1d + }; + + static const u32 ctl3220[] = { + 0x05040403, 0x07060505, 0x0e0c0a08, 0x1a171411, + 0x2825221f, 0x35322f2b, 0x3e3e3b38, 0x3e3e3e3e, + 0x09080807, 0x0b0a0a09, 0x0f0d0c0b, 0x1b171311, + 0x2825221f, 0x35322f2b, 0x3e3e3b38, 0x3e3e3e3e + }; + + static const u32 nc[] = { + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000 + }; + + static const u32 const * const dual_channel_slew_group_lookup[] = { + dq2030, cmd3210, ctl3215, ctl3215, clk2030, clk2030, dq2030, cmd3210, + dq2030, cmd3210, ctl3215, ctl3215, clk2030, clk2030, dq2030, cmd3210, + dq2030, cmd3210, nc, ctl3215, nc, clk2030, dq2030, cmd3210, + dq2030, cmd3210, ctl3215, ctl3215, clk2030, clk2030, dq2030, cmd2710, + dq2030, cmd3210, nc, ctl3215, nc, clk2030, nc, nc, + + dq2030, cmd3210, ctl3215, ctl3215, clk2030, clk2030, dq2030, cmd3210, + dq2030, cmd3210, ctl3215, nc, clk2030, nc, dq2030, cmd3210, + dq2030, cmd3210, ctl3215, ctl3215, clk2030, clk2030, dq2030, cmd3210, + dq2030, cmd3210, ctl3215, nc, clk2030, nc, dq2030, cmd2710, + dq2030, cmd3210, ctl3215, nc, clk2030, nc, nc, nc, + + dq2030, cmd3210, nc, ctl3215, nc, clk2030, dq2030, cmd3210, + dq2030, cmd3210, ctl3215, ctl3215, clk2030, clk2030, dq2030, cmd3210, + dq2030, cmd3210, nc, ctl3215, nc, clk2030, dq2030, cmd3210, + dq2030, cmd3210, ctl3215, ctl3215, clk2030, clk2030, dq2030, cmd2710, + dq2030, cmd3210, nc, ctl3215, nc, clk2030, nc, nc, + + dq2030, cmd2710, ctl3215, ctl3215, clk2030, clk2030, dq2030, cmd3210, + dq2030, cmd2710, ctl3215, nc, clk2030, nc, dq2030, cmd3210, + dq2030, cmd2710, ctl3215, ctl3215, clk2030, clk2030, dq2030, cmd3210, + dq2030, cmd2710, ctl3215, nc, clk2030, nc, dq2030, cmd2710, + dq2030, cmd2710, ctl3215, nc, clk2030, nc, nc, nc, + + nc, nc, nc, ctl3215, nc, clk2030, dq2030, cmd3210, + nc, nc, ctl3215, nc, clk2030, nc, dq2030, cmd3210, + nc, nc, nc, ctl3215, nc, clk2030, dq2030, cmd3210, + nc, nc, ctl3215, nc, clk2030, clk2030, dq2030, cmd2710 + }; + + static const u32 const * const single_channel_slew_group_lookup[] = { + dq2330, cmd3210, ctl3215, ctl3215, clk2030, clk2030, dq2330, cmd3210, + dq2330, cmd3210, ctl3215, ctl3215, clk2030, clk2030, dq2330, cmd3210, + dq2330, cmd3210, nc, ctl3215, nc, clk2030, dq2330, cmd3210, + dq2330, cmd3210, ctl3215, ctl3215, clk2030, clk2030, dq2330, cmd3210, + dq2330, cmd3210, nc, ctl3215, nc, clk2030, nc, nc, + + dq2330, cmd3210, ctl3215, ctl3215, clk2030, clk2030, dq2330, cmd3210, + dq2330, cmd3210, ctl3215, nc, clk2030, nc, dq2330, cmd3210, + dq2330, cmd3210, ctl3215, ctl3215, clk2030, clk2030, dq2330, cmd3210, + dq2330, cmd3210, ctl3215, nc, clk2030, nc, dq2330, cmd3210, + dq2330, cmd3210, ctl3215, nc, clk2030, nc, nc, nc, + + dq2330, cmd3210, nc, ctl3215, nc, clk2030, dq2330, cmd3210, + dq2330, cmd3210, ctl3215, ctl3215, clk2030, clk2030, dq2330, cmd3210, + dq2330, cmd3210, nc, ctl3215, nc, clk2030, dq2330, cmd3210, + dq2330, cmd3210, ctl3215, ctl3215, clk2030, clk2030, dq2330, cmd3210, + dq2330, cmd3210, nc, ctl3215, nc, clk2030, nc, nc, + + dq2330, cmd3210, ctl3215, ctl3215, clk2030, clk2030, dq2330, cmd3210, + dq2330, cmd3210, ctl3215, nc, clk2030, nc, dq2330, cmd3210, + dq2330, cmd3210, ctl3215, ctl3215, clk2030, clk2030, dq2330, cmd3210, + dq2330, cmd3210, ctl3215, nc, clk2030, nc, dq2330, cmd3210, + dq2330, cmd3210, ctl3215, nc, clk2030, nc, nc, nc, + + dq2330, nc, nc, ctl3215, nc, clk2030, dq2030, cmd3210, + dq2330, nc, ctl3215, nc, clk2030, nc, dq2030, cmd3210, + dq2330, nc, nc, ctl3215, nc, clk2030, dq2030, cmd3210, + dq2330, nc, ctl3215, nc, clk2030, clk2030, dq2030, cmd3210 + }; + + + /* Strength multiplier tables */ + static const u8 dual_channel_strength_multiplier[] = { + 0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11, + 0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11, + 0x44, 0x11, 0x00, 0x11, 0x00, 0x44, 0x44, 0x11, + 0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x22, + 0x44, 0x11, 0x00, 0x11, 0x00, 0x44, 0x00, 0x00, + 0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11, + 0x44, 0x11, 0x11, 0x00, 0x44, 0x00, 0x44, 0x11, + 0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11, + 0x44, 0x11, 0x11, 0x00, 0x44, 0x00, 0x44, 0x22, + 0x44, 0x11, 0x11, 0x00, 0x44, 0x00, 0x00, 0x00, + 0x44, 0x11, 0x00, 0x11, 0x00, 0x44, 0x44, 0x11, + 0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11, + 0x44, 0x11, 0x00, 0x11, 0x00, 0x44, 0x44, 0x11, + 0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x22, + 0x44, 0x11, 0x00, 0x11, 0x00, 0x44, 0x00, 0x00, + 0x44, 0x22, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11, + 0x44, 0x22, 0x11, 0x00, 0x44, 0x00, 0x44, 0x11, + 0x44, 0x22, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11, + 0x44, 0x22, 0x11, 0x00, 0x44, 0x00, 0x44, 0x22, + 0x44, 0x22, 0x11, 0x00, 0x44, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x11, 0x00, 0x44, 0x44, 0x11, + 0x00, 0x00, 0x11, 0x00, 0x44, 0x00, 0x44, 0x11, + 0x00, 0x00, 0x00, 0x11, 0x00, 0x44, 0x44, 0x11, + 0x00, 0x00, 0x11, 0x00, 0x44, 0x44, 0x44, 0x22 + }; + + static const u8 single_channel_strength_multiplier[] = { + 0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11, + 0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11, + 0x33, 0x11, 0x00, 0x11, 0x00, 0x44, 0x33, 0x11, + 0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11, + 0x33, 0x11, 0x00, 0x11, 0x00, 0x44, 0x00, 0x00, + 0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11, + 0x33, 0x11, 0x11, 0x00, 0x44, 0x00, 0x33, 0x11, + 0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11, + 0x33, 0x11, 0x11, 0x00, 0x44, 0x00, 0x33, 0x11, + 0x33, 0x11, 0x11, 0x00, 0x44, 0x00, 0x00, 0x00, + 0x33, 0x11, 0x00, 0x11, 0x00, 0x44, 0x33, 0x11, + 0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11, + 0x33, 0x11, 0x00, 0x11, 0x00, 0x44, 0x33, 0x11, + 0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11, + 0x33, 0x11, 0x00, 0x11, 0x00, 0x44, 0x00, 0x00, + 0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11, + 0x33, 0x11, 0x11, 0x00, 0x44, 0x00, 0x33, 0x11, + 0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11, + 0x33, 0x11, 0x11, 0x00, 0x44, 0x00, 0x33, 0x11, + 0x33, 0x11, 0x11, 0x00, 0x44, 0x00, 0x00, 0x00, + 0x33, 0x00, 0x00, 0x11, 0x00, 0x44, 0x33, 0x11, + 0x33, 0x00, 0x11, 0x00, 0x44, 0x00, 0x33, 0x11, + 0x33, 0x00, 0x00, 0x11, 0x00, 0x44, 0x33, 0x11, + 0x33, 0x00, 0x11, 0x00, 0x44, 0x44, 0x33, 0x11 + }; + + const u8 * strength_multiplier; + const u32* const * slew_group_lookup; + int idx; + + /* Set Strength Multipliers */ + + /* Dual Channel needs different tables. */ + if (sdram_capabilities_dual_channel()) { + printk_debug("Programming Dual Channel RCOMP\r\n"); + strength_multiplier = dual_channel_strength_multiplier; + slew_group_lookup = dual_channel_slew_group_lookup; + idx = 5 * sysinfo->dimm[0] + sysinfo->dimm[2]; + } else { + printk_debug("Programming Single Channel RCOMP\r\n"); + strength_multiplier = single_channel_strength_multiplier; + slew_group_lookup = single_channel_slew_group_lookup; + idx = 5 * sysinfo->dimm[0] + sysinfo->dimm[1]; + } + + printk_debug("Table Index: %d\r\n", idx); + + MCHBAR8(G1SC) = strength_multiplier[idx * 8 + 0]; + MCHBAR8(G2SC) = strength_multiplier[idx * 8 + 1]; + MCHBAR8(G3SC) = strength_multiplier[idx * 8 + 2]; + MCHBAR8(G4SC) = strength_multiplier[idx * 8 + 3]; + MCHBAR8(G5SC) = strength_multiplier[idx * 8 + 4]; + MCHBAR8(G6SC) = strength_multiplier[idx * 8 + 5]; + MCHBAR8(G7SC) = strength_multiplier[idx * 8 + 6]; + MCHBAR8(G8SC) = strength_multiplier[idx * 8 + 7]; + + /* Channel 0 */ + sdram_write_slew_rates(G1SRPUT, slew_group_lookup[idx * 8 + 0]); + sdram_write_slew_rates(G2SRPUT, slew_group_lookup[idx * 8 + 1]); + if ((slew_group_lookup[idx * 8 + 2] != nc) && (sysinfo->package == SYSINFO_PACKAGE_STACKED)) { + + + sdram_write_slew_rates(G3SRPUT, ctl3220); + } else { + sdram_write_slew_rates(G3SRPUT, slew_group_lookup[idx * 8 + 2]); + } + sdram_write_slew_rates(G4SRPUT, slew_group_lookup[idx * 8 + 3]); + sdram_write_slew_rates(G5SRPUT, slew_group_lookup[idx * 8 + 4]); + sdram_write_slew_rates(G6SRPUT, slew_group_lookup[idx * 8 + 5]); + + /* Channel 1 */ + if (sysinfo->dual_channel) { + sdram_write_slew_rates(G7SRPUT, slew_group_lookup[idx * 8 + 6]); + sdram_write_slew_rates(G8SRPUT, slew_group_lookup[idx * 8 + 7]); + } else { + sdram_write_slew_rates(G7SRPUT, nc); + sdram_write_slew_rates(G8SRPUT, nc); + } +} + +static void sdram_enable_rcomp(void) +{ + u32 reg32; + + udelay(300); + reg32 = MCHBAR32(GBRCOMPCTL); + reg32 &= ~(1 << 23); + MCHBAR32(GBRCOMPCTL) = reg32; +} + +static void sdram_program_dll_timings(struct sys_info *sysinfo) +{ + u32 chan0dll = 0, chan1dll = 0; + int i; + + printk_debug ("Programming DLL Timings... \r\n"); + + MCHBAR16(DQSMT) &= ~( (3 << 12) | (1 << 10) | ( 0xf << 0) ); + MCHBAR16(DQSMT) |= (1 << 13) | (0xc << 0); + + /* We drive both channels with the same speed */ + switch (sysinfo->memory_frequency) { + case 400: chan0dll = 0x26262626; chan1dll=0x26262626; break; /* 400MHz */ + case 533: chan0dll = 0x22222222; chan1dll=0x22222222; break; /* 533MHz */ + case 667: chan0dll = 0x11111111; chan1dll=0x11111111; break; /* 667MHz */ + } + + for (i=0; i < 4; i++) { + MCHBAR32(C0R0B00DQST + (i * 0x10) + 0) = chan0dll; + MCHBAR32(C0R0B00DQST + (i * 0x10) + 4) = chan0dll; + MCHBAR32(C1R0B00DQST + (i * 0x10) + 0) = chan1dll; + MCHBAR32(C1R0B00DQST + (i * 0x10) + 4) = chan1dll; + } +} + +static void sdram_force_rcomp(void) +{ + u32 reg32; + u8 reg8; + + reg32 = MCHBAR32(ODTC); + reg32 |= (1 << 28); + MCHBAR32(ODTC) = reg32; + + reg32 = MCHBAR32(SMSRCTL); + reg32 |= (1 << 0); + MCHBAR32(SMSRCTL) = reg32; + + reg32 = MCHBAR32(GBRCOMPCTL); + reg32 |= (1 << 8); + MCHBAR32(GBRCOMPCTL) = reg32; + + reg8 = i945_silicon_revision(); + if ((reg8 == 0 && (MCHBAR32(DCC) & (3 << 0)) == 0) || (reg8 == 1)) { + reg32 = MCHBAR32(GBRCOMPCTL); + reg32 |= (3 << 5); + MCHBAR32(GBRCOMPCTL) = reg32; + } +} + +static void sdram_initialize_system_memory_io(struct sys_info *sysinfo) +{ + u8 reg8; + u32 reg32; + + printk_debug ("Initializing System Memory IO... \r\n"); + + reg8 = MCHBAR8(C0HCTC); + reg8 &= ~0x1f; + reg8 |= ( 1 << 0); + MCHBAR8(C0HCTC) = reg8; + + reg8 = MCHBAR8(C1HCTC); + reg8 &= ~0x1f; + reg8 |= ( 1 << 0); + MCHBAR8(C1HCTC) = reg8; + + + MCHBAR16(WDLLBYPMODE) &= ~( (1 << 9) | (1 << 6) | (1 << 4) | (1 << 3) | (1 << 1) ); + MCHBAR16(WDLLBYPMODE) |= (1 << 8) | (1 << 7) | (1 << 5) | (1 << 2) | (1 << 0); + + MCHBAR8(C0WDLLCMC) = 0; + MCHBAR8(C1WDLLCMC) = 0; + + sdram_program_dram_width(sysinfo); + + sdram_rcomp_buffer_strength_and_slew(sysinfo); + + reg32 = MCHBAR32(GBRCOMPCTL); + reg32 &= ~( (1 << 29) | (1 << 26) | (3 << 21) | (3 << 2) ); + reg32 |= (3 << 27) | (3 << 0); + MCHBAR32(GBRCOMPCTL) = reg32; + + MCHBAR32(GBRCOMPCTL) |= (1 << 10); + + sdram_program_dll_timings(sysinfo); + + sdram_force_rcomp(); +} + +static void sdram_enable_system_memory_io(struct sys_info *sysinfo) +{ + u32 reg32; + + printk_debug ("Enabling System Memory IO... \r\n"); + + reg32 = MCHBAR32(RCVENMT); + reg32 &= ~(0x3f << 6); + MCHBAR32(RCVENMT) = reg32; + + reg32 |= (1 << 11) | (1 << 9); + MCHBAR32(RCVENMT) = reg32; + + reg32 = MCHBAR32(DRTST); + reg32 |= (1 << 3) | (1 << 2); + MCHBAR32(DRTST) = reg32; + + reg32 = MCHBAR32(DRTST); + reg32 |= (1 << 6) | (1 << 4); + MCHBAR32(DRTST) = reg32; + + asm volatile ("nop; nop;"); + + reg32 = MCHBAR32(DRTST); + + /* Is channel 0 populated? */ + if (sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED || + sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED) + reg32 |= (1 << 7) | (1 << 5); + else + reg32 |= (1 << 31); + + /* Is channel 1 populated? */ + if (sysinfo->dimm[2] != SYSINFO_DIMM_NOT_POPULATED || + sysinfo->dimm[3] != SYSINFO_DIMM_NOT_POPULATED) + reg32 |= (1 << 9) | (1 << 8); + else + reg32 |= (1 << 30); + + MCHBAR32(DRTST) = reg32; + + if (sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED || + sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED) { + reg32 = MCHBAR32(C0DRC1); + reg32 |= (1 << 8); + MCHBAR32(C0DRC1) = reg32; + } + if (sysinfo->dimm[2] != SYSINFO_DIMM_NOT_POPULATED || + sysinfo->dimm[3] != SYSINFO_DIMM_NOT_POPULATED) { + reg32 = MCHBAR32(C1DRC1); + reg32 |= (1 << 8); + MCHBAR32(C1DRC1) = reg32; + } +} + +struct dimm_size { + unsigned long side1; + unsigned long side2; +}; + +static struct dimm_size sdram_get_dimm_size(u16 device) +{ + /* Calculate the log base 2 size of a DIMM in bits */ + struct dimm_size sz; + int value, low, rows, columns; + + sz.side1 = 0; + sz.side2 = 0; + + rows = spd_read_byte(device, SPD_NUM_ROWS); /* rows */ + if (rows < 0) goto hw_err; + if ((rows & 0xf) == 0) goto val_err; + sz.side1 += rows & 0xf; + + columns = spd_read_byte(device, SPD_NUM_COLUMNS); /* columns */ + if (columns < 0) goto hw_err; + if ((columns & 0xf) == 0) goto val_err; + sz.side1 += columns & 0xf; + + value = spd_read_byte(device, SPD_NUM_BANKS_PER_SDRAM); /* banks */ + if (value < 0) goto hw_err; + if ((value & 0xff) == 0) goto val_err; + sz.side1 += log2(value & 0xff); + + /* Get the module data width and convert it to a power of two */ + value = spd_read_byte(device, SPD_MODULE_DATA_WIDTH_MSB); /* (high byte) */ + if (value < 0) goto hw_err; + value &= 0xff; + value <<= 8; + + low = spd_read_byte(device, SPD_MODULE_DATA_WIDTH_LSB); /* (low byte) */ + if (low < 0) goto hw_err; + value = value | (low & 0xff); + if ((value != 72) && (value != 64)) goto val_err; + sz.side1 += log2(value); + + /* side 2 */ + value = spd_read_byte(device, SPD_NUM_DIMM_BANKS); /* number of physical banks */ + + if (value < 0) goto hw_err; + value &= 7; + value++; + if (value == 1) goto out; + if (value != 2) goto val_err; + + /* Start with the symmetrical case */ + sz.side2 = sz.side1; + + if ((rows & 0xf0) == 0) goto out; /* If symmetrical we are done */ + + /* Don't die here, I have not come across any of these to test what + * actually happens. + */ + printk_err("Assymetric DIMMs are not supported by this chipset\n"); + + sz.side2 -= (rows & 0x0f); /* Subtract out rows on side 1 */ + sz.side2 += ((rows >> 4) & 0x0f); /* Add in rows on side 2 */ + + sz.side2 -= (columns & 0x0f); /* Subtract out columns on side 1 */ + sz.side2 += ((columns >> 4) & 0x0f); /* Add in columns on side 2 */ + + goto out; + + val_err: + die("Bad SPD value\r\n"); + hw_err: + /* If a hardware error occurs the spd rom probably does not exist. + * In this case report that there is no memory + */ + sz.side1 = 0; + sz.side2 = 0; + out: + return sz; +} + +static void sdram_detect_dimm_size(struct sys_info * sysinfo) +{ + int i; + + for(i = 0; i < 2 * DIMM_SOCKETS; i++) { + struct dimm_size sz; + + sysinfo->banksize[i * 2] = 0; + sysinfo->banksize[(i * 2) + 1] = 0; + + if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED) + continue; + + sz = sdram_get_dimm_size(DIMM_SPD_BASE + i); + + sysinfo->banks[i] = spd_read_byte(DIMM_SPD_BASE + i, SPD_NUM_BANKS_PER_SDRAM); /* banks */ + + if (sz.side1 < 30) + die("DDR-II rank size smaller than 128MB is not supported.\n"); + + sysinfo->banksize[i * 2] = sz.side1 - 30; + + printk_debug("DIMM %d side 0 = %d MB\n", i, (1 << sysinfo->banksize[i * 2]) * 128 ); + + if (!sz.side2) + continue; + + /* If there is a second side, it has to have at least 128M, too */ + if (sz.side2 < 30) + die("DDR-II rank size smaller than 128MB is not supported.\n"); + + sysinfo->banksize[(i * 2) + 1] = sz.side2 - 30; + + printk_debug("DIMM %d side 1 = %d MB\n", i, (1 << sysinfo->banksize[(i * 2) + 1]) * 128); + } +} + +static int sdram_program_row_boundaries(struct sys_info *sysinfo) +{ + int i; + int cum0, cum1, tolud; + + printk_debug ("Setting RAM size... \r\n"); + + cum0 = 0; + for(i = 0; i < 2 * DIMM_SOCKETS; i++) { + cum0 += (sysinfo->banksize[i] << 3); + MCHBAR8(C0DRB0+i) = cum0; + } + + /* Assume we continue in Channel 1 where we stopped in Channel 0 */ + cum1 = cum0; + + /* Exception: Interleaved starts from the beginning */ + if (sysinfo->interleaved) + cum1 = 0; + + /* Exception: Channel 1 is not populated. C1DRB stays zero */ + if (sysinfo->dimm[2] == SYSINFO_DIMM_NOT_POPULATED && + sysinfo->dimm[3] == SYSINFO_DIMM_NOT_POPULATED) + cum1 = 0; + + for(i = 0; i < 2 * DIMM_SOCKETS; i++) { + cum1 += (sysinfo->banksize[i + 4] << 3); + MCHBAR8(C1DRB0+i) = cum1; + } + + /* Set TOLUD Top Of Low Usable DRAM */ + if (sysinfo->interleaved) + tolud = (cum0 + cum1) << 1; + else + tolud = (cum1 ? cum1 : cum0) << 1; + pci_write_config16(PCI_DEV(0,0,0), TOLUD, tolud); + + printk_debug("C0DRB = 0x%08x\r\n", MCHBAR32(C0DRB0)); + printk_debug("C1DRB = 0x%08x\r\n", MCHBAR32(C1DRB0)); + printk_debug("TOLUD = 0x%04x\r\n", tolud); + + pci_write_config16(PCI_DEV(0,0,0), TOM, tolud>>3); + + return 0; +} + + +static int sdram_set_row_attributes(struct sys_info *sysinfo) +{ + int i, value; + u16 dra0=0, dra1=0, dra = 0; + + printk_debug ("Setting row attributes... \r\n"); + for(i=0; i < 2 * DIMM_SOCKETS; i++) { + u16 device; + u8 columnsrows; + + if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED) { + continue; + } + + device = DIMM_SPD_BASE + i; + columnsrows = 0; + + value = spd_read_byte(device, SPD_NUM_ROWS); /* rows */ + columnsrows = (value & 0x0f); + + value = spd_read_byte(device, SPD_NUM_COLUMNS); /* columns */ + columnsrows |= (value & 0xf) << 4; + + switch (columnsrows) { + case 0x9d: dra = 2; break; + case 0xad: dra = 3; break; + case 0xbd: dra = 4; break; + case 0xae: dra = 3; break; + case 0xbe: dra = 4; break; + default: die("Unsupported Rows/Columns. (DRA)"); + } + + /* Double Sided DIMMs? */ + if (sysinfo->banksize[(2 * i) + 1] != 0) { + dra = (dra << 4) | dra; + } + + if (i < DIMM_SOCKETS) + dra0 |= (dra << (i*8)); + else + dra1 |= (dra << ((i - DIMM_SOCKETS)*8)); + } + + MCHBAR16(C0DRA0) = dra0; + MCHBAR16(C1DRA0) = dra1; + + printk_debug("C0DRA = 0x%04x\r\n", dra0); + printk_debug("C1DRA = 0x%04x\r\n", dra1); + + return 0; +} + +static void sdram_set_bank_architecture(struct sys_info *sysinfo) +{ + u32 off32; + int i; + + MCHBAR16(C1BNKARC) &= 0xff00; + MCHBAR16(C0BNKARC) &= 0xff00; + + off32 = C0BNKARC; + for (i=0; i < 2 * DIMM_SOCKETS; i++) { + /* Switch to second channel */ + if (i == DIMM_SOCKETS) + off32 = C1BNKARC; + + if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED) + continue; + + if (sysinfo->banks[i] != 8) + continue; + + printk_spew("DIMM%d has 8 banks.\n"); + + if (i & 1) + MCHBAR16(off32) |= 0x50; + else + MCHBAR16(off32) |= 0x05; + } +} + +#define REFRESH_7_8US 1 +#define REFRESH_15_6US 0 +static void sdram_program_refresh_rate(struct sys_info *sysinfo) +{ + u32 reg32; + + if (sysinfo->refresh == REFRESH_7_8US) { + reg32 = (2 << 8); /* Refresh enabled at 7.8us */ + } else { + reg32 = (1 << 8); /* Refresh enabled at 15.6us */ + } + + MCHBAR32(C0DRC0) &= ~(7 << 8); + MCHBAR32(C0DRC0) |= reg32; + + MCHBAR32(C1DRC0) &= ~(7 << 8); + MCHBAR32(C1DRC0) |= reg32; +} + +static void sdram_program_cke_tristate(struct sys_info *sysinfo) +{ + u32 reg32; + int i; + + reg32 = MCHBAR32(C0DRC1); + + for (i=0; i < 4; i++) { + if (sysinfo->banksize[i] == 0) { + reg32 |= (1 << (16 + i)); + } + } + + reg32 |= (1 << 12); + + reg32 |= (1 << 11); + MCHBAR32(C0DRC1) = reg32; + + /* Do we have to do this if we're in Single Channel Mode? */ + reg32 = MCHBAR32(C1DRC1); + + for (i=4; i < 8; i++) { + if (sysinfo->banksize[i] == 0) { + reg32 |= (1 << (12 + i)); + } + } + + reg32 |= (1 << 12); + + reg32 |= (1 << 11); + MCHBAR32(C1DRC1) = reg32; +} + +static void sdram_program_odt_tristate(struct sys_info *sysinfo) +{ + u32 reg32; + int i; + + reg32 = MCHBAR32(C0DRC2); + + for (i=0; i < 4; i++) { + if (sysinfo->banksize[i] == 0) { + reg32 |= (1 << (24 + i)); + } + } + MCHBAR32(C0DRC2) = reg32; + + reg32 = MCHBAR32(C1DRC2); + + for (i=4; i < 8; i++) { + if (sysinfo->banksize[i] == 0) { + reg32 |= (1 << (20 + i)); + } + } + MCHBAR32(C1DRC2) = reg32; +} + +static void sdram_set_timing_and_control(struct sys_info *sysinfo) +{ + u32 reg32, off32; + u32 tWTR; + u32 temp_drt; + int i, page_size; + + static const u8 const drt0_table[] = { + /* CL 3, 4, 5 */ + 3, 4, 5, /* FSB533/400, DDR533/400 */ + 4, 5, 6, /* FSB667, DDR533/400 */ + 4, 5, 6, /* FSB667, DDR667 */ + }; + + static const u8 const cas_table[] = { + 2, 1, 0, 3 + }; + + reg32 = MCHBAR32(C0DRC0); + reg32 |= (1 << 2); /* Burst Length 8 */ + reg32 &= ~( (1 << 13) | (1 << 12) ); + MCHBAR32(C0DRC0) = reg32; + + reg32 = MCHBAR32(C1DRC0); + reg32 |= (1 << 2); /* Burst Length 8 */ + reg32 &= ~( (1 << 13) | (1 << 12) ); + MCHBAR32(C1DRC0) = reg32; + + if (!sysinfo->dual_channel && sysinfo->dimm[1] != + SYSINFO_DIMM_NOT_POPULATED) { + reg32 = MCHBAR32(C0DRC0); + reg32 |= (1 << 15); + MCHBAR32(C0DRC0) = reg32; + } + + sdram_program_refresh_rate(sysinfo); + + sdram_program_cke_tristate(sysinfo); + + sdram_program_odt_tristate(sysinfo); + + /* Calculate DRT0 */ + + temp_drt = 0; + + /* B2B Write Precharge (same bank) = CL-1 + BL/2 + tWR */ + reg32 = (sysinfo->cas - 1) + (BURSTLENGTH / 2) + sysinfo->twr; + temp_drt |= (reg32 << 28); + + /* Write Auto Precharge (same bank) = CL-1 + BL/2 + tWR + tRP */ + reg32 += sysinfo->trp; + temp_drt |= (reg32 << 4); + + if (sysinfo->memory_frequency == 667) { + tWTR = 3; /* 667MHz */ + } else { + tWTR = 2; /* 400 and 533 */ + } + + /* B2B Write to Read Command Spacing */ + reg32 = (sysinfo->cas - 1) + (BURSTLENGTH / 2) + tWTR; + temp_drt |= (reg32 << 24); + + + temp_drt |= ( (1 << 22) | (3 << 20) | (1 << 18) | (0 << 16) ); + + /* Program Write Auto Precharge to Activate */ + off32 = 0; + if (sysinfo->fsb_frequency == 667) { /* 667MHz FSB */ + off32 += 3; + } + if (sysinfo->memory_frequency == 667) { + off32 += 3; + } + off32 += sysinfo->cas - 3; + reg32 = drt0_table[off32]; + temp_drt |= (reg32 << 11); + + /* Read Auto Precharge to Activate */ + + temp_drt |= (8 << 0); + + MCHBAR32(C0DRT0) = temp_drt; + MCHBAR32(C1DRT0) = temp_drt; + + /* Calculate DRT1 */ + + temp_drt = MCHBAR32(C0DRT1) & 0x00020088; + + /* DRAM RASB Precharge */ + temp_drt |= (sysinfo->trp - 2) << 0; + + /* DRAM RASB to CASB Delay */ + temp_drt |= (sysinfo->trcd - 2) << 4; + + /* CASB Latency */ + temp_drt |= (cas_table[sysinfo->cas - 3]) << 8; + + /* Refresh Cycle Time */ + temp_drt |= (sysinfo->trfc) << 10; + + /* Pre-All to Activate Delay */ + temp_drt |= (0 << 16); + + /* Precharge to Precharge Delay stays at 1 clock */ + temp_drt |= (0 << 18); + + /* Activate to Precharge Delay */ + temp_drt |= (sysinfo->tras << 19); + + /* Read to Precharge (tRTP) */ + if (sysinfo->memory_frequency == 667) { + temp_drt |= (1 << 28); + } else { + temp_drt |= (0 << 28); + } + + /* Determine page size */ + reg32 = 0; + page_size = 1; /* Default: 1k pagesize */ + for (i=0; i< 2*DIMM_SOCKETS; i++) { + if (sysinfo->dimm[i] == SYSINFO_DIMM_X16DS || + sysinfo->dimm[i] == SYSINFO_DIMM_X16SS) + page_size = 2; /* 2k pagesize */ + } + + if (sysinfo->memory_frequency == 533 && page_size == 2) { + reg32 = 1; + } + if (sysinfo->memory_frequency == 667) { + reg32 = page_size; + } + + temp_drt |= (reg32 << 30); + + MCHBAR32(C0DRT1) = temp_drt; + MCHBAR32(C1DRT1) = temp_drt; + + /* Program DRT2 */ + reg32 = MCHBAR32(C0DRT2); + reg32 &= ~(1 << 8); + MCHBAR32(C0DRT2) = reg32; + + reg32 = MCHBAR32(C1DRT2); + reg32 &= ~(1 << 8); + MCHBAR32(C1DRT2) = reg32; + + /* Calculate DRT3 */ + temp_drt = MCHBAR32(C0DRT3) & ~0x07ffffff; + + /* Get old tRFC value */ + reg32 = MCHBAR32(C0DRT1) >> 10; + reg32 &= 0x3f; + + /* 788nS - tRFC */ + switch (sysinfo->memory_frequency) { + case 400: /* 5nS */ + reg32 = ((78800 / 500) - reg32) & 0x1ff; + reg32 |= (0x8c << 16) | (0x0c << 10); /* 1 us */ + break; + case 533: /* 3.75nS */ + reg32 = ((78800 / 375) - reg32) & 0x1ff; + reg32 |= (0xba << 16) | (0x10 << 10); /* 1 us */ + break; + case 667: /* 3nS */ + reg32 = ((78800 / 300) - reg32) & 0x1ff; + reg32 |= (0xe9 << 16) | (0x14 << 10); /* 1 us */ + break; + } + + temp_drt |= reg32; + + MCHBAR32(C0DRT3) = temp_drt; + MCHBAR32(C1DRT3) = temp_drt; +} + +static void sdram_set_channel_mode(struct sys_info *sysinfo) +{ + u32 reg32; + + printk_debug("Setting mode of operation for memory channels..."); + + if (sdram_capabilities_interleave() && + ( ( sysinfo->banksize[0] + sysinfo->banksize[1] + + sysinfo->banksize[2] + sysinfo->banksize[3] ) == + ( sysinfo->banksize[4] + sysinfo->banksize[5] + + sysinfo->banksize[6] + sysinfo->banksize[7] ) ) ) { + /* Both channels equipped with DIMMs of the same size */ + + sysinfo->interleaved = 1; + } else { + sysinfo->interleaved = 0; + } + + reg32 = MCHBAR32(DCC); + reg32 &= ~(7 << 0); + + if(sysinfo->interleaved) { + /* Dual Channel Interleaved */ + printk_debug("Dual Channel Interleaved.\n"); + reg32 |= (1 << 1); + } else if (sysinfo->dimm[0] == SYSINFO_DIMM_NOT_POPULATED && + sysinfo->dimm[1] == SYSINFO_DIMM_NOT_POPULATED) { + /* Channel 1 only */ + printk_debug("Single Channel 1 only.\n"); + reg32 |= (1 << 2); + } else if (sdram_capabilities_dual_channel() && sysinfo->dimm[2] != + SYSINFO_DIMM_NOT_POPULATED) { + /* Dual Channel Assymetric */ + printk_debug("Dual Channel Assymetric.\n"); + reg32 |= (1 << 0); + } else { + /* All bits 0 means Single Channel 0 operation */ + printk_debug("Single Channel 0 only.\n"); + } + + reg32 |= (1 << 10); + + MCHBAR32(DCC) = reg32; + + PRINTK_DEBUG("DCC=0x%08x\r\n", MCHBAR32(DCC)); +} + +static void sdram_program_pll_settings(void) +{ + volatile u16 reg16; + volatile u32 reg32; + + const u8 HPLLGPLLPowerDown[] = { + 0x90, /* 400MHz */ + 0x95, /* 533MHz */ + 0x00, /* --- */ + 0x8d, /* 667MHz */ + }; + + MCHBAR32(PLLMON) = 0x80800000; + + reg32 = MCHBAR32(CLKCFG); + reg32 &= (7 << 0); + + reg16 = MCHBAR16(CPCTL); + reg16 &= 0xff00; + reg16 |= HPLLGPLLPowerDown[reg32]; + MCHBAR16(CPCTL) = reg16; + + reg16 &= ~(1 << 11); + MCHBAR16(CPCTL) = reg16; + + reg16 = MCHBAR16(CPCTL); +} + +static void sdram_program_graphics_frequency(struct sys_info *sysinfo) +{ + u8 reg8; + u16 reg16; + u8 freq, second_vco; + +#define CRCLK_166MHz 0x00 +#define CRCLK_200MHz 0x01 +#define CRCLK_250MHz 0x03 +#define CRCLK_400MHz 0x05 + +#define CDCLK_200MHz 0x00 +#define CDCLK_320MHz 0x40 + + printk_debug ("Setting Graphics Frequency... \r\n"); + + reg16 = pci_read_config16(PCI_DEV(0,2,0), GCFC); + reg16 |= (1<<11) | (1<<9); + pci_write_config16(PCI_DEV(0,2,0), GCFC, reg16); + + /* Program CPCTL according to FSB speed */ + reg16 = MCHBAR16(CPCTL); + reg16 &= 0xff00; + + switch (MCHBAR32(CLKCFG) & 0x7) { + case 0: sysinfo->fsb_frequency = 400; break; /* FSB400 */ + case 1: sysinfo->fsb_frequency = 533; break; /* FSB533 */ + case 3: sysinfo->fsb_frequency = 667; break; /* FSB667 */ + default: die("Unsupported FSB speed"); + } + + switch (sysinfo->fsb_frequency) { + case 533: reg16 |= 0x95; break; /* FSB533 */ + case 667: reg16 |= 0x8d; break; /* FSB667 */ + } + MCHBAR16(CPCTL) = reg16; + + /* Get graphics frequency capabilities */ + reg8 = (pci_read_config8(PCI_DEV(0, 0x00,0), 0xe5) & 0x0e) >> 1; + + freq = CRCLK_250MHz; + switch (reg8) { + case 0: + if (MCHBAR32(DFT_STRAP1) & (1 << 20)) + freq = CRCLK_250MHz; + else + freq = CRCLK_400MHz; + break; + case 2: freq = CRCLK_250MHz; break; + case 3: freq = CRCLK_200MHz; break; + case 4: freq = CRCLK_166MHz; break; + } + + if (freq != CRCLK_400MHz) { + + reg8 = (pci_read_config8(PCI_DEV(0, 0x00,0), 0xe7) & 0x70) >> 4; + if (reg8==2) + freq = CRCLK_166MHz; + } + + if (i945_silicon_revision() == 0) { + sysinfo->mvco4x = 1; + } else { + sysinfo->mvco4x = 0; + } + + + second_vco = 0; + + if (MCHBAR32(DFT_STRAP1) & (1 << 20)) { + second_vco = 1; + } else if ((i945_silicon_revision() > 0) && (freq == CRCLK_250MHz)) { + u16 mem = sysinfo->memory_frequency; + u16 fsb = sysinfo->fsb_frequency; + + if ( (fsb == 667 && mem == 533) || + (fsb == 533 && mem == 533) || + (fsb == 533 && mem == 400)) { + second_vco = 1; + } + + if (fsb == 667 && mem == 533) + sysinfo->mvco4x = 1; + } + + if (second_vco) { + printk_debug("Programming second TCO\r\n"); + sysinfo->clkcfg_bit7=1; + } else { + sysinfo->clkcfg_bit7=0; + } + + reg16 = pci_read_config16(PCI_DEV(0,2,0), GCFC); + reg16 &= ~( (7 << 0) | (1 << 13) ); + reg16 |= freq; + pci_write_config16(PCI_DEV(0,2,0), GCFC, reg16); + + reg16 = pci_read_config16(PCI_DEV(0,2,0), GCFC); + reg16 &= ~( (1<<7) | (7<<4) ); + if (MCHBAR32(DFT_STRAP1) & (1 << 20)) { + reg16 |= CDCLK_200MHz; + } else { + reg16 |= CDCLK_320MHz; + } + pci_write_config16(PCI_DEV(0,2,0), GCFC, reg16); + + reg16 = pci_read_config16(PCI_DEV(0,2,0), GCFC); + reg16 &= ~( (1<<10) | (1<<8) ); + pci_write_config16(PCI_DEV(0,2,0), GCFC, reg16); + reg16 |= (1<<10) | (1<<8); + pci_write_config16(PCI_DEV(0,2,0), GCFC, reg16); + + reg16 &= 0xf0ff; + pci_write_config16(PCI_DEV(0,2,0), GCFC, reg16); +} + +static void sdram_program_memory_frequency(struct sys_info *sysinfo) +{ + u32 clkcfg; + u8 reg8; + + printk_debug ("Setting Memory Frequency... "); + + clkcfg = MCHBAR32(CLKCFG); + + printk_debug("CLKCFG=0x%08x, ", clkcfg); + + clkcfg &= ~( (1 << 12) | (1 << 7) | ( 7 << 4) ); + + if (sysinfo->mvco4x) { + printk_debug("MVCO 4x, "); + clkcfg &= ~(1 << 12); + } + + if (sysinfo->clkcfg_bit7) { + printk_debug("second VCO, "); + + clkcfg |= (1 << 7); + } + + switch (sysinfo->memory_frequency) { + case 400: clkcfg |= (2 << 4); break; + case 533: clkcfg |= (3 << 4); break; + case 667: clkcfg |= (4 << 4); break; + default: die("Target Memory Frequency Error"); + } + + if (MCHBAR32(CLKCFG) == clkcfg) { + printk_debug ("ok (unchanged)\r\n"); + return; + } + + MCHBAR32(CLKCFG) = clkcfg; + + /* Make sure the following code is in the + * cache before we execute it. + */ + goto cache_code; +vco_update: + reg8 = pci_read_config8(PCI_DEV(0,0x1f,0), 0xa2); + reg8 &= ~(1 << 7); + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8); + + + clkcfg &= ~(1 << 10); + MCHBAR32(CLKCFG) = clkcfg; + clkcfg |= (1 << 10); + MCHBAR32(CLKCFG) = clkcfg; + + + __asm__ __volatile__ ( + " movl $0x100, %%ecx\n" + "delay_update:\n" + " nop\n" + " nop\n" + " nop\n" + " nop\n" + " loop delay_update\n" + : /* No outputs */ + : /* No inputs */ + : "%ecx" + ); + + + clkcfg &= ~(1 << 10); + MCHBAR32(CLKCFG) = clkcfg; + + goto out; +cache_code: + goto vco_update; +out: + + printk_debug("CLKCFG=0x%08x, ", MCHBAR32(CLKCFG)); + printk_debug ("ok\r\n"); +} + +static void sdram_program_clock_crossing(void) +{ + u32 reg32; + int idx = 0; + + /** + * The first two lines of each of these tables are for FSB533, + * the following three lines are for FSB667. We ignore FSB400. + * Thus we add the indices according to our clocks from CLKCFG. + */ + + static const u32 data_clock_crossing[] = { + 0x08040120, 0x00000000, /* DDR400 FSB533 */ + 0x00100401, 0x00000000, /* DDR533 FSB533 */ + + 0x04020120, 0x00000010, /* DDR400 FSB667 */ + 0x10040280, 0x00000040, /* DDR533 FSB667 */ + 0x00100401, 0x00000000 /* DDR667 FSB667 */ + }; + + static const u32 command_clock_crossing[] = { + 0x00060108, 0x00000000, /* DDR400 FSB533 */ + 0x04020108, 0x00000000, /* DDR533 FSB533 */ + + 0x00040318, 0x00000000, /* DDR400 FSB667 */ + 0x04020118, 0x00000000, /* DDR533 FSB667 */ + 0x02010804, 0x00000000 /* DDR667 FSB667 */ + }; + + printk_debug("Programming Clock Crossing..."); + reg32 = MCHBAR32(CLKCFG); + + printk_debug("MEM="); + switch ((reg32 >> 4) & 7) { + case 2: printk_debug("400"); idx += 0; break; + case 3: printk_debug("533"); idx += 2; break; + case 4: printk_debug("667"); idx += 4; break; + default: printk_debug("RSVD\r\n"); return; + } + + printk_debug(" FSB="); + switch (reg32 & 7) { + case 0: printk_debug("400\r\n"); return; + case 1: printk_debug("533"); idx += 0; break; + case 3: printk_debug("667"); idx += 4; break; + default: printk_debug("RSVD\r\n"); return; + } + + MCHBAR32(C0DCCFT + 0) = data_clock_crossing[idx]; + MCHBAR32(C0DCCFT + 4) = data_clock_crossing[idx + 1]; + MCHBAR32(C1DCCFT + 0) = data_clock_crossing[idx]; + MCHBAR32(C1DCCFT + 4) = data_clock_crossing[idx + 1]; + + MCHBAR32(CCCFT + 0) = command_clock_crossing[idx]; + MCHBAR32(CCCFT + 4) = command_clock_crossing[idx + 1]; + + printk_debug("... ok\r\n"); +} + +static void sdram_disable_fast_dispatch(void) +{ + u32 reg32; + + reg32 = MCHBAR32(FSBPMC3); + reg32 |= (1 << 1); + MCHBAR32(FSBPMC3) = reg32; + + reg32 = MCHBAR32(SBTEST); + reg32 |= (3 << 1); + MCHBAR32(SBTEST) = reg32; +} + +static void sdram_pre_jedec_initialization(void) +{ + u32 reg32; + + reg32 = MCHBAR32(WCC); + reg32 &= 0x113ff3ff; + reg32 |= (4 << 29) | (3 << 25) | (1 << 10); + MCHBAR32(WCC) = reg32; + + MCHBAR32(SMVREFC) |= (1 << 6); + + MCHBAR32(MMARB0) &= ~(3 << 17); + MCHBAR32(MMARB0) |= (1 << 21) | (1 << 16); + + MCHBAR32(MMARB1) &= ~(7 << 8); + MCHBAR32(MMARB1) |= (3 << 8); + + MCHBAR32(C0AIT) = 0x000006c4; + MCHBAR32(C0AIT+4) = 0x871a066d; + + MCHBAR32(C1AIT) = 0x000006c4; + MCHBAR32(C1AIT+4) = 0x871a066d; +} + +#define EA_DUALCHANNEL_XOR_BANK_RANK_MODE (0xd4 << 24) +#define EA_DUALCHANNEL_XOR_BANK_MODE (0xf4 << 24) +#define EA_DUALCHANNEL_BANK_RANK_MODE (0xc2 << 24) +#define EA_DUALCHANNEL_BANK_MODE (0xe2 << 24) +#define EA_SINGLECHANNEL_XOR_BANK_RANK_MODE (0x91 << 24) +#define EA_SINGLECHANNEL_XOR_BANK_MODE (0xb1 << 24) +#define EA_SINGLECHANNEL_BANK_RANK_MODE (0x80 << 24) +#define EA_SINGLECHANNEL_BANK_MODE (0xa0 << 24) + +static void sdram_enhanced_addressing_mode(struct sys_info *sysinfo) +{ + u32 chan0 = 0, chan1 = 0; + int chan0_dualsided, chan1_dualsided, chan0_populated, chan1_populated; + + chan0_populated = (sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED || + sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED); + chan1_populated = (sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED || + sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED); + chan0_dualsided = (sysinfo->banksize[1] || sysinfo->banksize[3]); + chan1_dualsided = (sysinfo->banksize[5] || sysinfo->banksize[7]); + + if (sdram_capabilities_enhanced_addressing_xor()) { + if (!sysinfo->interleaved) { + /* Single Channel & Dual Channel Assymetric */ + if (chan0_populated) { + if (chan0_dualsided) { + chan0 = EA_SINGLECHANNEL_XOR_BANK_RANK_MODE; + } else { + chan0 = EA_SINGLECHANNEL_XOR_BANK_MODE; + } + } + if (chan1_populated) { + if (chan1_dualsided) { + chan1 = EA_SINGLECHANNEL_XOR_BANK_RANK_MODE; + } else { + chan1 = EA_SINGLECHANNEL_XOR_BANK_MODE; + } + } + } else { + /* Interleaved has always both channels populated */ + if (chan0_dualsided) { + chan0 = EA_DUALCHANNEL_XOR_BANK_RANK_MODE; + } else { + chan0 = EA_DUALCHANNEL_XOR_BANK_MODE; + } + + if (chan1_dualsided) { + chan1 = EA_DUALCHANNEL_XOR_BANK_RANK_MODE; + } else { + chan1 = EA_DUALCHANNEL_XOR_BANK_MODE; + } + } + } else { + if (!sysinfo->interleaved) { + /* Single Channel & Dual Channel Assymetric */ + if (chan0_populated) { + if (chan0_dualsided) { + chan0 = EA_SINGLECHANNEL_BANK_RANK_MODE; + } else { + chan0 = EA_SINGLECHANNEL_BANK_MODE; + } + } + if (chan1_populated) { + if (chan1_dualsided) { + chan1 = EA_SINGLECHANNEL_BANK_RANK_MODE; + } else { + chan1 = EA_SINGLECHANNEL_BANK_MODE; + } + } + } else { + /* Interleaved has always both channels populated */ + if (chan0_dualsided) { + chan0 = EA_DUALCHANNEL_BANK_RANK_MODE; + } else { + chan0 = EA_DUALCHANNEL_BANK_MODE; + } + + if (chan1_dualsided) { + chan1 = EA_DUALCHANNEL_BANK_RANK_MODE; + } else { + chan1 = EA_DUALCHANNEL_BANK_MODE; + } + } + } + + MCHBAR32(C0DRC1) &= 0x00ffffff; + MCHBAR32(C0DRC1) |= chan0; + MCHBAR32(C1DRC1) &= 0x00ffffff; + MCHBAR32(C1DRC1) |= chan1; +} + +static void sdram_post_jedec_initialization(struct sys_info *sysinfo) +{ + u32 reg32; + + /* Enable Channel XORing for Dual Channel Interleave */ + if (sysinfo->interleaved) { + reg32 = MCHBAR32(DCC); +#if CHANNEL_XOR_RANDOMIZATION + reg32 &= ~(1 << 10); +#endif + reg32 &= ~(1 << 9); + MCHBAR32(DCC) = reg32; + } + + /* DRAM mode optimizations */ + sdram_enhanced_addressing_mode(sysinfo); + + reg32 = MCHBAR32(FSBPMC3); + reg32 &= ~(1 << 1); + MCHBAR32(FSBPMC3) = reg32; + + reg32 = MCHBAR32(SBTEST); + reg32 &= ~(1 << 2); + MCHBAR32(SBTEST) = reg32; + + reg32 = MCHBAR32(SBOCC); + reg32 &= 0xffbdb6ff; + reg32 |= (0xbdb6 << 8) | (1 << 0); + MCHBAR32(SBOCC) = reg32; +} + +static void sdram_power_management(struct sys_info *sysinfo) +{ + u8 reg8; + u16 reg16; + u32 reg32; + int integrated_graphics = 1; + int i; + + reg32 = MCHBAR32(C0DRT2); + reg32 &= 0xffffff00; + /* Idle timer = 8 clocks, CKE idle timer = 16 clocks */ + reg32 |= (1 << 5) | (1 << 4); + MCHBAR32(C0DRT2) = reg32; + + reg32 = MCHBAR32(C1DRT2); + reg32 &= 0xffffff00; + /* Idle timer = 8 clocks, CKE idle timer = 16 clocks */ + reg32 |= (1 << 5) | (1 << 4); + MCHBAR32(C1DRT2) = reg32; + + reg32 = MCHBAR32(C0DRC1); + + reg32 |= (1 << 12) | (1 << 11); + MCHBAR32(C0DRC1) = reg32; + + reg32 = MCHBAR32(C1DRC1); + + reg32 |= (1 << 12) | (1 << 11); + MCHBAR32(C1DRC1) = reg32; + + if (i945_silicon_revision()>1) { + MCHBAR16(UPMC1) = 0x1010; + } else { + /* Rev 0 and 1 */ + MCHBAR16(UPMC1) = 0x0010; + } + + reg16 = MCHBAR16(UPMC2); + reg16 &= 0xfc00; + reg16 |= 0x0100; + MCHBAR16(UPMC2) = reg16; + + MCHBAR32(UPMC3) = 0x000f06ff; + + for (i=0; i<5; i++) { + MCHBAR32(UPMC3) &= ~(1 << 16); + MCHBAR32(UPMC3) |= (1 << 16); + } + + MCHBAR32(GIPMC1) = 0x8000000c; + + reg16 = MCHBAR16(CPCTL); + reg16 &= ~(7 << 11); + if (i945_silicon_revision()>2) { + reg16 |= (6 << 11); + } else { + reg16 |= (4 << 11); + } + MCHBAR16(CPCTL) = reg16; + + if ((MCHBAR32(ECO) & (1 << 16)) != 0) { + switch (sysinfo->fsb_frequency) { + case 667: MCHBAR32(HGIPMC2) = 0x0d590d59; break; + case 533: MCHBAR32(HGIPMC2) = 0x155b155b; break; + } + } else { + switch (sysinfo->fsb_frequency) { + case 667: MCHBAR32(HGIPMC2) = 0x09c409c4; break; + case 533: MCHBAR32(HGIPMC2) = 0x0fa00fa0; break; + } + } + + MCHBAR32(FSBPMC1) = 0x8000000c; + + reg32 = MCHBAR32(C2C3TT); + reg32 &= 0xffff0000; + switch (sysinfo->fsb_frequency) { + case 667: reg32 |= 0x0600; break; + case 533: reg32 |= 0x0480; break; + } + MCHBAR32(C2C3TT) = reg32; + + reg32 = MCHBAR32(C3C4TT); + reg32 &= 0xffff0000; + switch (sysinfo->fsb_frequency) { + case 667: reg32 |= 0x0b80; break; + case 533: reg32 |= 0x0980; break; + } + MCHBAR32(C3C4TT) = reg32; + + if (i945_silicon_revision() == 0) { + MCHBAR32(ECO) &= ~(1 << 16); + } else { + MCHBAR32(ECO) |= (1 << 16); + } + +#if 0 + if (i945_silicon_revision() == 0) { + MCHBAR32(FSBPMC3) &= ~(1 << 29); + } else { + MCHBAR32(FSBPMC3) |= (1 << 29); + } +#endif + MCHBAR32(FSBPMC3) &= ~(1 << 29); + + MCHBAR32(FSBPMC3) |= (1 << 21); + + MCHBAR32(FSBPMC3) &= ~(1 << 19); + + MCHBAR32(FSBPMC3) &= ~(1 << 13); + + reg32 = MCHBAR32(FSBPMC4); + reg32 &= ~(3 << 24); + reg32 |= ( 2 << 24); + MCHBAR32(FSBPMC4) = reg32; + + MCHBAR32(FSBPMC4) |= (1 << 21); + + MCHBAR32(FSBPMC4) |= (1 << 5); + + if (i945_silicon_revision() < 2) { + /* stepping 0 and 1 */ + MCHBAR32(FSBPMC4) &= ~(1 << 4); + } else { + MCHBAR32(FSBPMC4) &= ~(1 << 4); + } + + reg8 = pci_read_config8(PCI_DEV(0,0x0,0), 0xfc); + reg8 |= (1 << 4); + pci_write_config8(PCI_DEV(0, 0x0, 0), 0xfc, reg8); + + reg8 = pci_read_config8(PCI_DEV(0,0x2,0), 0xc1); + reg8 |= (1 << 2); + pci_write_config8(PCI_DEV(0, 0x2, 0), 0xc1, reg8); + + if (integrated_graphics) { + MCHBAR16(MIPMC4) = 0x0468; + MCHBAR16(MIPMC5) = 0x046c; + MCHBAR16(MIPMC6) = 0x046c; + } else { + MCHBAR16(MIPMC4) = 0x6468; + MCHBAR16(MIPMC5) = 0x646c; + MCHBAR16(MIPMC6) = 0x646c; + } + + reg32 = MCHBAR32(PMCFG); + reg32 &= ~(3 << 17); + reg32 |= (2 << 17); + reg32 |= (1 << 4); + MCHBAR32(PMCFG) = reg32; + + reg32 = MCHBAR32(0xc30); + reg32 &= 0xffffff00; + reg32 |= 0x01; + MCHBAR32(0xc30) = reg32; + + MCHBAR32(0xb18) &= ~(1 << 21); +} + +static void sdram_thermal_management(void) +{ + /* The Thermal Sensors for DIMMs at 0x50, 0x52 are at I2C addr + * 0x30/0x32. + */ + + /* Explicitly set to 0 */ + MCHBAR8(TCO1) = 0x00; + MCHBAR8(TCO0) = 0x00; +} + +#include "rcven.c" + +static void sdram_program_receive_enable(struct sys_info *sysinfo) +{ + MCHBAR32(REPC) |= (1 << 0); + + receive_enable_adjust(sysinfo); + + MCHBAR32(C0DRC1) |= (1 << 6); + MCHBAR32(C1DRC1) |= (1 << 6); + MCHBAR32(C0DRC1) &= ~(1 << 6); + MCHBAR32(C1DRC1) &= ~(1 << 6); + + MCHBAR32(MIPMC3) |= (0x0f << 0); +} + +/** + * @brief Enable On-Die Termination for DDR2. + * + */ + +static void sdram_on_die_termination(struct sys_info *sysinfo) +{ + static const u32 odt[] = { + 0x00024911, 0xe0010000, + 0x00049211, 0xe0020000, + 0x0006db11, 0xe0030000, + }; + + u32 reg32; + int cas; + + reg32 = MCHBAR32(ODTC); + reg32 &= ~(3 << 16); + reg32 |= (1 << 14) | (1 << 6) | (2 << 16); + MCHBAR32(ODTC) = reg32; + + if ( !(sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED && + sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED) ) { + printk_debug("one dimm per channel config.. \n"); + + reg32 = MCHBAR32(C0ODT); + reg32 &= ~(7 << 28); + MCHBAR32(C0ODT) = reg32; + reg32 = MCHBAR32(C1ODT); + reg32 &= ~(7 << 28); + MCHBAR32(C1ODT) = reg32; + } + + cas = sysinfo->cas; + + reg32 = MCHBAR32(C0ODT) & 0xfff00000; + reg32 |= odt[(cas-3) * 2]; + MCHBAR32(C0ODT) = reg32; + + reg32 = MCHBAR32(C1ODT) & 0xfff00000; + reg32 |= odt[(cas-3) * 2]; + MCHBAR32(C1ODT) = reg32; + + reg32 = MCHBAR32(C0ODT + 4) & 0x1fc8ffff; + reg32 |= odt[((cas-3) * 2) + 1]; + MCHBAR32(C0ODT + 4) = reg32; + + reg32 = MCHBAR32(C1ODT + 4) & 0x1fc8ffff; + reg32 |= odt[((cas-3) * 2) + 1]; + MCHBAR32(C1ODT + 4) = reg32; +} + +/** + * @brief Enable clocks to populated sockets + */ + +static void sdram_enable_memory_clocks(struct sys_info *sysinfo) +{ + u8 clocks[2] = { 0, 0 }; + + if (sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED) + clocks[0] |= (1 << 0) | (1 << 1); + + if (sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED) + clocks[0] |= (1 << 2) | (1 << 3); + + if (sysinfo->dimm[2] != SYSINFO_DIMM_NOT_POPULATED) + clocks[1] |= (1 << 0) | (1 << 1); + + if (sysinfo->dimm[3] != SYSINFO_DIMM_NOT_POPULATED) + clocks[1] |= (1 << 2) | (1 << 3); + +#ifdef OVERRIDE_CLOCK_DISABLE + clocks[0] = 0xf; + clocks[1] = 0xf; +#endif + + MCHBAR8(C0DCLKDIS) = clocks[0]; + MCHBAR8(C1DCLKDIS) = clocks[1]; +} + +#define RTT_ODT_75_OHM (1 << 5) +#define RTT_ODT_150_OHM (1 << 9) + +#define EMRS_OCD_DEFAULT ( (1 << 12) | (1 << 11) | (1 << 10) ) + +#define MRS_CAS_3 (3 << 7) +#define MRS_CAS_4 (4 << 7) +#define MRS_CAS_5 (5 << 7) + +#define MRS_TWR_3 (2 << 12) +#define MRS_TWR_4 (3 << 12) +#define MRS_TWR_5 (4 << 12) + +#define MRS_BT (1 << 6) + +#define MRS_BL4 (2 << 3) +#define MRS_BL8 (3 << 3) + +static void sdram_jedec_enable(struct sys_info *sysinfo) +{ + int i, nonzero; + u32 bankaddr = 0, tmpaddr, mrsaddr = 0; + + for (i = 0, nonzero = -1; i < 8; i++) { + if (sysinfo->banksize[i] == 0) { + continue; + } + + printk_debug("jedec enable sequence: bank %d\n", i); + switch (i) { + case 0: + /* Start at address 0 */ + bankaddr = 0; + break; + case 4: + if (sysinfo->interleaved) { + bankaddr = 0x40; + break; + } + default: + if (nonzero != -1) { + printk_debug("bankaddr from bank size of rank %d\n", nonzero); + bankaddr += (1 << sysinfo->banksize[nonzero]) << (sysinfo->interleaved?28:27); + break; + } + /* No populated bank hit before. Start at address 0 */ + bankaddr = 0; + } + + /* We have a bank with a non-zero size.. Remember it + * for the next offset we have to calculate + */ + nonzero = i; + + /* Get CAS latency set up */ + switch (sysinfo->cas) { + case 5: mrsaddr = MRS_CAS_5; break; + case 4: mrsaddr = MRS_CAS_4; break; + case 3: mrsaddr = MRS_CAS_3; break; + default: die("Jedec Error (CAS).\n"); + } + + /* Get tWR set */ + switch (sysinfo->twr) { + case 5: mrsaddr |= MRS_TWR_5; break; + case 4: mrsaddr |= MRS_TWR_4; break; + case 3: mrsaddr |= MRS_TWR_3; break; + default: die("Jedec Error (tWR).\n"); + } + + /* Interleaved */ + if (sysinfo->interleaved) { + mrsaddr |= MRS_BT; + mrsaddr = mrsaddr << 1; + } + + /* Only burst length 8 supported */ + mrsaddr |= MRS_BL8; + + /* Apply NOP */ + PRINTK_DEBUG("Apply NOP\r\n"); + do_ram_command(RAM_COMMAND_NOP); + ram_read32(bankaddr); + + /* Precharge all banks */ + PRINTK_DEBUG("All Banks Precharge\r\n"); + do_ram_command(RAM_COMMAND_PRECHARGE); + ram_read32(bankaddr); + + /* Extended Mode Register Set (2) */ + PRINTK_DEBUG("Extended Mode Register Set(2)\r\n"); + do_ram_command(RAM_COMMAND_EMRS | RAM_EMRS_2); + ram_read32(bankaddr); + + /* Extended Mode Register Set (3) */ + PRINTK_DEBUG("Extended Mode Register Set(3)\r\n"); + do_ram_command(RAM_COMMAND_EMRS | RAM_EMRS_3); + ram_read32(bankaddr); + + /* Extended Mode Register Set */ + PRINTK_DEBUG("Extended Mode Register Set\r\n"); + do_ram_command(RAM_COMMAND_EMRS | RAM_EMRS_1); + tmpaddr = bankaddr; + if (!sdram_capabilities_dual_channel()) { + tmpaddr |= RTT_ODT_75_OHM; + } else if (sysinfo->interleaved) { + tmpaddr |= (RTT_ODT_150_OHM << 1); + } else { + tmpaddr |= RTT_ODT_150_OHM; + } + ram_read32(tmpaddr); + + /* Mode Register Set: Reset DLLs */ + PRINTK_DEBUG("MRS: Reset DLLs\r\n"); + do_ram_command(RAM_COMMAND_MRS); + tmpaddr = bankaddr; + tmpaddr |= mrsaddr; + /* Set DLL reset bit */ + if (sysinfo->interleaved) + tmpaddr |= (1 << 12); + else + tmpaddr |= (1 << 11); + ram_read32(tmpaddr); + + /* Precharge all banks */ + PRINTK_DEBUG("All Banks Precharge\r\n"); + do_ram_command(RAM_COMMAND_PRECHARGE); + ram_read32(bankaddr); + + /* CAS before RAS Refresh */ + PRINTK_DEBUG("CAS before RAS\r\n"); + do_ram_command(RAM_COMMAND_CBR); + + /* CBR wants two READs */ + ram_read32(bankaddr); + ram_read32(bankaddr); + + /* Mode Register Set: Enable DLLs */ + PRINTK_DEBUG("MRS: Enable DLLs\r\n"); + do_ram_command(RAM_COMMAND_MRS); + + tmpaddr = bankaddr; + tmpaddr |= mrsaddr; + ram_read32(tmpaddr); + + /* Extended Mode Register Set */ + PRINTK_DEBUG("Extended Mode Register Set: ODT/OCD\r\n"); + do_ram_command(RAM_COMMAND_EMRS | RAM_EMRS_1); + + tmpaddr = bankaddr; + if (!sdram_capabilities_dual_channel()) { + + tmpaddr |= RTT_ODT_75_OHM | EMRS_OCD_DEFAULT; + } else if (sysinfo->interleaved) { + tmpaddr |= ((RTT_ODT_150_OHM | EMRS_OCD_DEFAULT) << 1); + } else { + tmpaddr |= RTT_ODT_150_OHM | EMRS_OCD_DEFAULT; + } + ram_read32(tmpaddr); + + /* Extended Mode Register Set */ + PRINTK_DEBUG("Extended Mode Register Set: OCD Exit\r\n"); + do_ram_command(RAM_COMMAND_EMRS | RAM_EMRS_1); + + tmpaddr = bankaddr; + if (!sdram_capabilities_dual_channel()) { + tmpaddr |= RTT_ODT_75_OHM; + } else if (sysinfo->interleaved) { + tmpaddr |= (RTT_ODT_150_OHM << 1); + } else { + tmpaddr |= RTT_ODT_150_OHM; + } + ram_read32(tmpaddr); + } +} + +static void sdram_init_complete(void) +{ + PRINTK_DEBUG("Normal Operation\r\n"); + do_ram_command(RAM_COMMAND_NORMAL); +} + +static void sdram_setup_processor_side(void) +{ + if (i945_silicon_revision() == 0) + MCHBAR32(FSBPMC3) |= (1 << 2); + + MCHBAR8(0xb00) |= 1; + + if (i945_silicon_revision() == 0) + MCHBAR32(SLPCTL) |= (1 << 8); +} + +#define BOOT_MODE_RESUME 1 +#define BOOT_MODE_NORMAL 0 + +/** + * @param boot_mode: 0 = normal, 1 = resume + */ +void sdram_initialize(int boot_mode) +{ + struct sys_info sysinfo; + u8 reg8, cas_mask; + + sdram_detect_errors(); + + printk_debug ("Setting up RAM controller.\r\n"); + + memset(&sysinfo, 0, sizeof(sysinfo)); + + /* Look at the type of DIMMs and verify all DIMMs are x8 or x16 width */ + sdram_get_dram_configuration(&sysinfo); + + /* Check whether we have stacked DIMMs */ + sdram_verify_package_type(&sysinfo); + + /* Determine common CAS */ + cas_mask = sdram_possible_cas_latencies(&sysinfo); + + /* Choose Common Frequency */ + sdram_detect_cas_latency_and_ram_speed(&sysinfo, cas_mask); + + /* Determine smallest common tRAS */ + sdram_detect_smallest_tRAS(&sysinfo); + + /* Determine tRP */ + sdram_detect_smallest_tRP(&sysinfo); + + /* Determine tRCD */ + sdram_detect_smallest_tRCD(&sysinfo); + + /* Determine smallest refresh period */ + sdram_detect_smallest_refresh(&sysinfo); + + /* Verify all DIMMs support burst length 8 */ + sdram_verify_burst_length(&sysinfo); + + /* determine tWR */ + sdram_detect_smallest_tWR(&sysinfo); + + /* Determine DIMM size parameters (rows, columns banks) */ + sdram_detect_dimm_size(&sysinfo); + + /* determine tRFC */ + sdram_detect_smallest_tRFC(&sysinfo); + + /* Program PLL settings */ + sdram_program_pll_settings(); + + /* Program Graphics Frequency */ + sdram_program_graphics_frequency(&sysinfo); + + /* Program System Memory Frequency */ + sdram_program_memory_frequency(&sysinfo); + + /* Determine Mode of Operation (Interleaved etc) */ + sdram_set_channel_mode(&sysinfo); + + /* Program Clock Crossing values */ + sdram_program_clock_crossing(); + + /* Disable fast dispatch */ + sdram_disable_fast_dispatch(); + + /* Enable WIODLL Power Down in ACPI states */ + MCHBAR32(C0DMC) |= (1 << 24); + MCHBAR32(C1DMC) |= (1 << 24); + + /* Program DRAM Row Boundary/Attribute Registers */ + + if (boot_mode != BOOT_MODE_RESUME) { + /* program row size DRB and set TOLUD */ + sdram_program_row_boundaries(&sysinfo); + + /* program page size DRA */ + sdram_set_row_attributes(&sysinfo); + } + + /* Program CxBNKARC */ + sdram_set_bank_architecture(&sysinfo); + + /* Program DRAM Timing and Control registers based on SPD */ + sdram_set_timing_and_control(&sysinfo); + + /* On-Die Termination Adjustment */ + sdram_on_die_termination(&sysinfo); + + /* Pre Jedec Initialization */ + sdram_pre_jedec_initialization(); + + /* Perform System Memory IO Initialization */ + sdram_initialize_system_memory_io(&sysinfo); + + /* Perform System Memory IO Buffer Enable */ + sdram_enable_system_memory_io(&sysinfo); + + /* Enable System Memory Clocks */ + sdram_enable_memory_clocks(&sysinfo); + + if (boot_mode != BOOT_MODE_RESUME) { + /* Jedec Initialization sequence */ + sdram_jedec_enable(&sysinfo); + } + + /* Program Power Management Registers */ + sdram_power_management(&sysinfo); + + /* Post Jedec Init */ + sdram_post_jedec_initialization(&sysinfo); + + /* Program DRAM Throttling */ + sdram_thermal_management(); + + /* Normal Operations */ + sdram_init_complete(); + + /* Program Receive Enable Timings */ + sdram_program_receive_enable(&sysinfo); + + /* Enable Periodic RCOMP */ + sdram_enable_rcomp(); + + /* Tell ICH7 that we're done */ + reg8 = pci_read_config8(PCI_DEV(0,0x1f,0), 0xa2); + reg8 &= ~(1 << 7); + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8); + + printk_debug("RAM initialization finished.\r\n"); + + sdram_setup_processor_side(); +} + Added: trunk/coreboot-v2/src/northbridge/intel/i945/raminit.h =================================================================== --- trunk/coreboot-v2/src/northbridge/intel/i945/raminit.h (rev 0) +++ trunk/coreboot-v2/src/northbridge/intel/i945/raminit.h 2008-10-29 04:51:07 UTC (rev 3703) @@ -0,0 +1,67 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef RAMINIT_H +#define RAMINIT_H + +#define DIMM_SOCKETS 2 + +#define DIMM_SPD_BASE 0x50 +#define DIMM_TCO_BASE 0x30 + +/* Burst length is always 8 */ +#define BURSTLENGTH 8 + +struct sys_info { + u16 memory_frequency; /* 400, 533 or 667 */ + u16 fsb_frequency; /* 400, 533 or 667 */ + + u8 trp; /* calculated by sdram_detect_smallest_tRP() */ + u8 trcd; /* calculated by sdram_detect_smallest_tRCD() */ + u8 tras; /* calculated by sdram_detect_smallest_tRAS() */ + u8 trfc; /* calculated by sdram_detect_smallest_tRFC() */ + u8 twr; /* calculated by sdram_detect_smallest_tWR() */ + + u8 cas; /* 3, 4 or 5 */ + u8 refresh; /* 0 = 15.6us, 1 = 7.8us */ + + u8 dual_channel; /* 0 or 1 */ + u8 interleaved; + + u8 mvco4x; /* 0 (8x) or 1 (4x) */ + u8 clkcfg_bit7; + u8 boot_path; + + u8 package; /* 0 = planar, 1 = stacked */ +#define SYSINFO_PACKAGE_PLANAR 0x00 +#define SYSINFO_PACKAGE_STACKED 0x01 + u8 dimm[2 * DIMM_SOCKETS]; +#define SYSINFO_DIMM_X16DS 0x00 +#define SYSINFO_DIMM_X8DS 0x01 +#define SYSINFO_DIMM_X16SS 0x02 +#define SYSINFO_DIMM_X8DDS 0x03 +#define SYSINFO_DIMM_NOT_POPULATED 0x04 + + u8 banks[2 * DIMM_SOCKETS]; + + u8 banksize[2 * 2 * DIMM_SOCKETS]; + +} __attribute__ ((packed)); + +#endif /* RAMINIT_H */ Added: trunk/coreboot-v2/src/northbridge/intel/i945/rcven.c =================================================================== --- trunk/coreboot-v2/src/northbridge/intel/i945/rcven.c (rev 0) +++ trunk/coreboot-v2/src/northbridge/intel/i945/rcven.c 2008-10-29 04:51:07 UTC (rev 3703) @@ -0,0 +1,338 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "raminit.h" + +/** + * sample the strobes signal + */ +static u32 sample_strobes(int channel_offset, struct sys_info *sysinfo) +{ + u32 reg32, addr; + int i; + + MCHBAR32(C0DRC1 + channel_offset) |= (1 << 6); + + MCHBAR32(C0DRC1 + channel_offset) &= ~(1 << 6); + + addr = 0; + + if (channel_offset != 0) { /* must be dual channel */ + if (sysinfo->interleaved == 1) { + addr |= (1 << 6); + } else { + addr = ((u32)MCHBAR8(C0DRB3)) << 25; + } + } + + for (i = 0; i < 28; i++) { + read32(addr); + read32(addr + 0x80); + } + + reg32 = MCHBAR32(RCVENMT); + if (channel_offset == 0) { + reg32 = reg32 << 2; + } + + /** + * [19] = 1: all bits are high + * [18] = 1: all bits are low + * [19:18] = 00: bits are mixed high, low + */ + return reg32; +} + +/** + * This function sets receive enable coarse and medium timing parameters + */ + +static void set_receive_enable(int channel_offset, u8 medium, u8 coarse) +{ + u32 reg32; + + printk_spew(" set_receive_enable() medium=0x%x, coarse=0x%x\r\n", medium, coarse); + + reg32 = MCHBAR32(C0DRT1 + channel_offset); + reg32 &= 0xf0ffffff; + reg32 |= ((u32)coarse & 0x0f) << 24; + MCHBAR32(C0DRT1 + channel_offset) = reg32; + + if (coarse > 0x0f) + printk_debug("set_receive_enable: coarse overflow: 0x%02x.\n", coarse); + + /* medium control + * + * 00 - 1/4 clock + * 01 - 1/2 clock + * 10 - 3/4 clock + * 11 - 1 clock + */ + + reg32 = MCHBAR32(RCVENMT); + if (!channel_offset) { + + reg32 &= ~(3 << 2); + reg32 |= medium << 2; + } else { + + reg32 &= ~(3 << 0); + reg32 |= medium; + } + MCHBAR32(RCVENMT) = reg32; + +} + +static int normalize(int channel_offset, u8 * mediumcoarse, u8 * fine) +{ + printk_spew(" normalize()\r\n"); + + if (*fine < 0x80) + return 0; + + *fine -= 0x80; + *mediumcoarse += 1; + + if (*mediumcoarse >= 0x40) { + printk_debug("Normalize Error\r\n"); + return -1; + } + + set_receive_enable(channel_offset, *mediumcoarse & 3, + *mediumcoarse >> 2); + + MCHBAR8(C0WL0REOST + channel_offset) = *fine; + + return 0; +} + +static int find_preamble(int channel_offset, u8 * mediumcoarse, + struct sys_info *sysinfo) +{ + /* find start of the data phase */ + u32 reg32; + + printk_spew(" find_preamble()\r\n"); + + do { + if (*mediumcoarse < 4) { + + printk_debug("No Preamble found.\r\n"); + return -1; + } + *mediumcoarse -= 4; + + set_receive_enable(channel_offset, *mediumcoarse & 3, + *mediumcoarse >> 2); + + reg32 = sample_strobes(channel_offset, sysinfo); + + } while (reg32 & (1 << 19)); + + if (!(reg32 & (1 << 18))) { + + printk_debug("No Preamble found (neither high nor low).\r\n"); + return -1; + } + + return 0; +} + +/** + * add a quarter clock to the current receive enable settings + */ + +static int add_quarter_clock(int channel_offset, u8 * mediumcoarse, u8 * fine) +{ + printk_spew(" add_quarter_clock() mediumcoarse=%02x fine=%02x\r\n", + *mediumcoarse, *fine); + if (*fine >= 0x80) { + *fine -= 0x80; + + *mediumcoarse += 2; + if (*mediumcoarse >= 0x40) { + printk_debug("clocks at max.\r\n"); + return -1; + } + + set_receive_enable(channel_offset, *mediumcoarse & 3, + *mediumcoarse >> 2); + } else { + *fine += 0x80; + } + + MCHBAR8(C0WL0REOST + channel_offset) = *fine; + + return 0; +} + +static int find_strobes_low(int channel_offset, u8 * mediumcoarse, u8 * fine, + struct sys_info *sysinfo) +{ + u32 rcvenmt; + + printk_spew(" find_strobes_low()\r\n"); + + for (;;) { + MCHBAR8(C0WL0REOST + channel_offset) = *fine; + + set_receive_enable(channel_offset, *mediumcoarse & 3, + *mediumcoarse >> 2); + + rcvenmt = sample_strobes(channel_offset, sysinfo); + + if (((rcvenmt & (1 << 18)) != 0)) + return 0; + + + *fine -= 0x80; + if (*fine == 0) + continue; + + *mediumcoarse -= 2; + if (*mediumcoarse < 0xfe) + continue; + + break; + + } + + printk_debug("Could not find low strobe\r\n"); + return 0; +} + +static int find_strobes_edge(int channel_offset, u8 * mediumcoarse, u8 * fine, + struct sys_info *sysinfo) +{ + int counter; + u32 rcvenmt; + + printk_spew(" find_strobes_edge()\r\n"); + + counter = 8; + set_receive_enable(channel_offset, *mediumcoarse & 3, + *mediumcoarse >> 2); + + for (;;) { + MCHBAR8(C0WL0REOST + channel_offset) = *fine; + rcvenmt = sample_strobes(channel_offset, sysinfo); + + if ((rcvenmt & (1 << 19)) == 0) { + counter = 8; + } else { + counter--; + if (!counter) + break; + } + + *fine = *fine + 1; + if (*fine < 0xf8) { + if (*fine & (1 << 3)) { + *fine &= ~(1 << 3); + *fine += 0x10; + } + continue; + } + + *fine = 0; + *mediumcoarse += 2; + if (*mediumcoarse <= 0x40) { + set_receive_enable(channel_offset, *mediumcoarse & 3, + *mediumcoarse >> 2); + continue; + } + + printk_debug("could not find rising edge.\r\n"); + return -1; + } + + *fine -= 7; + if (*fine >= 0xf9) { + *mediumcoarse -= 2; + set_receive_enable(channel_offset, *mediumcoarse & 3, + *mediumcoarse >> 2); + } + + *fine &= ~(1 << 3); + MCHBAR8(C0WL0REOST + channel_offset) = *fine; + + return 0; +} + +/** + * Here we use a trick. The RCVEN channel 0 registers are all at an + * offset of 0x80 to the channel 0 registers. We don't want to waste + * a lot of if()s so let's just pass 0 or 0x80 for the channel offset. + */ + +static int receive_enable_autoconfig(int channel_offset, + struct sys_info *sysinfo) +{ + u8 mediumcoarse; + u8 fine; + + printk_spew("receive_enable_autoconfig() for channel %d\r\n", + channel_offset ? 1 : 0); + + /* Set initial values */ + mediumcoarse = (sysinfo->cas << 2) | 3; + fine = 0; + + if (find_strobes_low(channel_offset, &mediumcoarse, &fine, sysinfo)) + return -1; + + if (find_strobes_edge(channel_offset, &mediumcoarse, &fine, sysinfo)) + return -1; + + if (add_quarter_clock(channel_offset, &mediumcoarse, &fine)) + return -1; + + if (find_preamble(channel_offset, &mediumcoarse, sysinfo)) + return -1; + + if (add_quarter_clock(channel_offset, &mediumcoarse, &fine)) + return -1; + + if (normalize(channel_offset, &mediumcoarse, &fine)) + return -1; + + /* This is a debug check to see if the rcven code is fully working. + * It can be removed when the output message is not printed anymore + */ + if (MCHBAR8(C0WL0REOST + channel_offset) == 0) { + printk_debug("Weird. No C%sWL0REOST\n", channel_offset?"1":"0"); + } + + return 0; +} + +void receive_enable_adjust(struct sys_info *sysinfo) +{ + /* Is channel 0 populated? */ + if (sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED + || sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED) + if (receive_enable_autoconfig(0, sysinfo)) + return; + + /* Is channel 1 populated? */ + if (sysinfo->dimm[2] != SYSINFO_DIMM_NOT_POPULATED + || sysinfo->dimm[3] != SYSINFO_DIMM_NOT_POPULATED) + if (receive_enable_autoconfig(0x80, sysinfo)) + return; +} Added: trunk/coreboot-v2/src/northbridge/intel/i945/reset_test.c =================================================================== --- trunk/coreboot-v2/src/northbridge/intel/i945/reset_test.c (rev 0) +++ trunk/coreboot-v2/src/northbridge/intel/i945/reset_test.c 2008-10-29 04:51:07 UTC (rev 3703) @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +static int bios_reset_detected(void) +{ + /* For now ... + * DO NOT, I repeat, DO NOT remove this. If you don't like the + * situation, implement this instead. + */ + return 0; +} + Added: trunk/coreboot-v2/src/northbridge/intel/i945/udelay.c =================================================================== --- trunk/coreboot-v2/src/northbridge/intel/i945/udelay.c (rev 0) +++ trunk/coreboot-v2/src/northbridge/intel/i945/udelay.c 2008-10-29 04:51:07 UTC (rev 3703) @@ -0,0 +1,70 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <cpu/x86/tsc.h> +#include <cpu/x86/msr.h> + +/** + * Intel Core(tm) cpus always run the TSC at the maximum possible CPU clock + */ + +static void udelay(u32 us) +{ + u32 dword; + tsc_t tsc, tsc1, tscd; + msr_t msr; + u32 fsb = 0, divisor; + u32 d; + u32 dn = 0x1000000 / 2; + + msr = rdmsr(0xcd); + switch (msr.lo & 0x07) { + case 5: + fsb = 400; + break; + case 1: + fsb = 533; + break; + case 3: + fsb = 667; + break; + } + + msr = rdmsr(0x198); + divisor = (msr.hi >> 8) & 0x1f; + + d = fsb * divisor; + + tscd.hi = us / dn; + tscd.lo = (us - tscd.hi * dn) * d; + + tsc1 = rdtsc(); + dword = tsc1.lo + tscd.lo; + if ((dword < tsc1.lo) || (dword < tscd.lo)) { + tsc1.hi++; + } + tsc1.lo = dword; + tsc1.hi += tscd.hi; + + do { + tsc = rdtsc(); + } while ((tsc.hi > tsc1.hi) + || ((tsc.hi == tsc1.hi) && (tsc.lo > tsc1.lo))); + +}

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r3702 - in trunk/coreboot-v2/src/cpu: intel intel/model_6ex intel/model_6fx intel/socket_mFCPGA478 intel/socket_mPGA478 x86/car x86/lapic
by svn＠coreboot.org 29 Oct '08

29 Oct '08

Author: stepan Date: 2008-10-29 05:48:44 +0100 (Wed, 29 Oct 2008) New Revision: 3702 Added: trunk/coreboot-v2/src/cpu/intel/model_6ex/ trunk/coreboot-v2/src/cpu/intel/model_6ex/Config.lb trunk/coreboot-v2/src/cpu/intel/model_6ex/cache_as_ram.inc trunk/coreboot-v2/src/cpu/intel/model_6ex/cache_as_ram_disable.c trunk/coreboot-v2/src/cpu/intel/model_6ex/cache_as_ram_post.c trunk/coreboot-v2/src/cpu/intel/model_6ex/microcode_m206e839.h trunk/coreboot-v2/src/cpu/intel/model_6ex/model_6ex_init.c trunk/coreboot-v2/src/cpu/intel/model_6fx/ trunk/coreboot-v2/src/cpu/intel/model_6fx/Config.lb trunk/coreboot-v2/src/cpu/intel/model_6fx/cache_as_ram.inc trunk/coreboot-v2/src/cpu/intel/model_6fx/cache_as_ram_disable.c trunk/coreboot-v2/src/cpu/intel/model_6fx/cache_as_ram_post.c trunk/coreboot-v2/src/cpu/intel/model_6fx/model_6fx_init.c trunk/coreboot-v2/src/cpu/intel/socket_mPGA478/ trunk/coreboot-v2/src/cpu/intel/socket_mPGA478/Config.lb trunk/coreboot-v2/src/cpu/intel/socket_mPGA478/chip.h trunk/coreboot-v2/src/cpu/intel/socket_mPGA478/socket_mPGA478.c Modified: trunk/coreboot-v2/src/cpu/intel/socket_mFCPGA478/Config.lb trunk/coreboot-v2/src/cpu/x86/car/copy_and_run.c trunk/coreboot-v2/src/cpu/x86/lapic/lapic_cpu_init.c Log: Support for Intel Core Duo and Core 2 Duo (tm) CPUs. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Added: trunk/coreboot-v2/src/cpu/intel/model_6ex/Config.lb =================================================================== --- trunk/coreboot-v2/src/cpu/intel/model_6ex/Config.lb (rev 0) +++ trunk/coreboot-v2/src/cpu/intel/model_6ex/Config.lb 2008-10-29 04:48:44 UTC (rev 3702) @@ -0,0 +1,13 @@ +uses HAVE_MOVNTI +default HAVE_MOVNTI=1 + +dir /cpu/x86/tsc +dir /cpu/x86/mtrr +dir /cpu/x86/fpu +dir /cpu/x86/mmx +dir /cpu/x86/sse +dir /cpu/x86/lapic +dir /cpu/x86/cache +dir /cpu/intel/microcode +dir /cpu/intel/hyperthreading +driver model_6ex_init.o Added: trunk/coreboot-v2/src/cpu/intel/model_6ex/cache_as_ram.inc =================================================================== --- trunk/coreboot-v2/src/cpu/intel/model_6ex/cache_as_ram.inc (rev 0) +++ trunk/coreboot-v2/src/cpu/intel/model_6ex/cache_as_ram.inc 2008-10-29 04:48:44 UTC (rev 3702) @@ -0,0 +1,152 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich(a)gmail.com> + * Copyright (C) 2007-2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define CACHE_AS_RAM_SIZE DCACHE_RAM_SIZE +#define CACHE_AS_RAM_BASE DCACHE_RAM_BASE +#define post_code(x) intel_chip_post_macro(x) + +#include <cpu/x86/mtrr.h> +#include <cpu/amd/mtrr.h> + + /* Save the BIST result */ + movl %eax, %ebp + +cache_as_ram: +#if USE_FALLBACK_IMAGE == 1 + + post_code(0x20) + + /* Send INIT IPI to all excluding ourself */ + movl $0x000C4500, %eax + movl $0xFEE00300, %esi + movl %eax, (%esi) + + /* Zero out all Fixed Range and Variable Range MTRRs */ + movl $mtrr_table, %esi + movl $( (mtrr_table_end - mtrr_table) / 2), %edi + xorl %eax, %eax + xorl %edx, %edx +clear_mtrrs: + movw (%esi), %bx + movzx %bx, %ecx + wrmsr + add $2, %esi + dec %edi + jnz clear_mtrrs + + /* Configure the default memory type to uncacheable */ + movl $MTRRdefType_MSR, %ecx + rdmsr + andl $(~0x00000cff), %eax + wrmsr + + /* Set cache as ram base address */ + movl $(MTRRphysBase_MSR(0)), %ecx + movl $(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax + xorl %edx, %edx + wrmsr + + /* Set cache as ram mask */ + movl $(MTRRphysMask_MSR(0)), %ecx + movl $(~((CACHE_AS_RAM_SIZE-1)) | (1 << 11)), %eax + movl $0x0000000f, %edx + wrmsr + + /* Enable MTRR */ + movl $MTRRdefType_MSR, %ecx + rdmsr + orl $(1 << 11), %eax + wrmsr + + /* Enable L2 Cache */ + movl $0x11e, %ecx + rdmsr + orl $(1 << 8), %eax + wrmsr + + /* CR0.CD = 0, CR0.NW = 0 */ + movl %cr0, %eax + andl $( ~( (1 << 30) | (1 << 29) ) ), %eax + invd + movl %eax, %cr0 + + /* Clear the cache memory reagion */ + movl $CACHE_AS_RAM_BASE, %esi + movl %esi, %edi + movl $(CACHE_AS_RAM_SIZE / 4), %ecx + //movl $0x23322332, %eax + xorl %eax, %eax + rep stosl +#endif + + /* Enable Cache As RAM mode by disabling cache */ + movl %cr0, %eax + orl $(1 << 30), %eax + movl %eax, %cr0 + +#if defined(XIP_ROM_SIZE) && defined(XIP_ROM_BASE) + /* Enable cache for our code in Flash because we do XIP here */ + movl $MTRRphysBase_MSR(1), %ecx + xorl %edx, %edx + movl $(XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax + wrmsr + + movl $MTRRphysMask_MSR(1), %ecx + movl $0x0000000f, %edx + movl $(~(XIP_ROM_SIZE - 1) | 0x800), %eax + wrmsr +#endif /* XIP_ROM_SIZE && XIP_ROM_BASE */ + + /* enable cache */ + movl %cr0, %eax + andl $( ~( (1 << 30) | (1 << 29) ) ), %eax + movl %eax, %cr0 + + /* Set up stack pointer */ + movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4), %eax + movl %eax, %esp + + /* Restore the BIST result */ + movl %ebp, %eax + movl %esp, %ebp + pushl %eax + + post_code(0x23) + + call stage1_main + + post_code(0x2f) +error: + hlt + jmp error + +mtrr_table: + /* Fixed MTRRs */ + .word 0x250, 0x258, 0x259 + .word 0x268, 0x269, 0x26A + .word 0x26B, 0x26C, 0x26D + .word 0x26E, 0x26F + /* Variable MTRRs */ + .word 0x200, 0x201, 0x202, 0x203 + .word 0x204, 0x205, 0x206, 0x207 + .word 0x208, 0x209, 0x20A, 0x20B + .word 0x20C, 0x20D, 0x20E, 0x20F +mtrr_table_end: + Added: trunk/coreboot-v2/src/cpu/intel/model_6ex/cache_as_ram_disable.c =================================================================== --- trunk/coreboot-v2/src/cpu/intel/model_6ex/cache_as_ram_disable.c (rev 0) +++ trunk/coreboot-v2/src/cpu/intel/model_6ex/cache_as_ram_disable.c 2008-10-29 04:48:44 UTC (rev 3702) @@ -0,0 +1,111 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include "cpu/x86/car/copy_and_run.c" + +void real_main(unsigned long bist); + +void stage1_main(unsigned long bist) +{ + unsigned int cpu_reset = 0; + +#if USE_FALLBACK_IMAGE == 1 + /* Is this a deliberate reset by the bios */ + if (bios_reset_detected() && last_boot_normal()) { + goto normal_image; + } else { + /* This is the primary cpu how should I boot? */ + check_cmos_failed(); + if (do_normal_boot()) { + goto normal_image; + } + else { + goto fallback_image; + } + } + normal_image: + __asm__ volatile ("jmp __normal_image" + : /* outputs */ + : "a" (bist) /* inputs */ + ); + fallback_image: +#endif + + real_main(bist); + + /* No servicable parts below this line .. */ + + { + /* Check value of esp to verify if we have enough rom for stack in Cache as RAM */ + unsigned v_esp; + __asm__ volatile ( + "movl %%esp, %0\n\t" + : "=a" (v_esp) + ); + printk_spew("v_esp=%08x\r\n", v_esp); + } + +cpu_reset_x: + + printk_spew("cpu_reset = %08x\r\n",cpu_reset); + + if(cpu_reset == 0) { + print_spew("Clearing initial memory region: "); + } + print_spew("No cache as ram now - "); + + /* store cpu_reset to ebx */ + __asm__ volatile ( + "movl %0, %%ebx\n\t" + ::"a" (cpu_reset) + ); + + if(cpu_reset==0) { +#define CLEAR_FIRST_1M_RAM 1 +#include "cache_as_ram_post.c" + } else { +#undef CLEAR_FIRST_1M_RAM +#include "cache_as_ram_post.c" + } + + __asm__ volatile ( + /* set new esp */ /* before _RAMBASE */ + "subl %0, %%ebp\n\t" + "subl %0, %%esp\n\t" + ::"a"( (DCACHE_RAM_BASE + DCACHE_RAM_SIZE)- _RAMBASE ) + ); + + { + unsigned new_cpu_reset; + + /* get back cpu_reset from ebx */ + __asm__ volatile ( + "movl %%ebx, %0\n\t" + :"=a" (new_cpu_reset) + ); + + /* Copy and execute coreboot_ram */ + copy_and_run(new_cpu_reset); + /* We will not return */ + } + + print_debug("sorry. parachute did not open.\r\n"); +} Added: trunk/coreboot-v2/src/cpu/intel/model_6ex/cache_as_ram_post.c =================================================================== --- trunk/coreboot-v2/src/cpu/intel/model_6ex/cache_as_ram_post.c (rev 0) +++ trunk/coreboot-v2/src/cpu/intel/model_6ex/cache_as_ram_post.c 2008-10-29 04:48:44 UTC (rev 3702) @@ -0,0 +1,125 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + + __asm__ volatile ( + + "movb $0x30, %al\noutb %al, $0x80\n" + + /* Disable Cache */ + "movl %cr0, %eax\n" + "orl $(1 << 30), %eax\n" + "movl %eax, %cr0\n" + + "movb $0x31, %al\noutb %al, $0x80\n" + + /* Disable MTRR */ + "movl $MTRRdefType_MSR, %ecx\n" + "rdmsr\n" + "andl $(~(1 << 11)), %eax\n" + "wrmsr\n" + + "movb $0x32, %al\noutb %al, $0x80\n" + + "invd\n" +#if 0 + "xorl %eax, %eax\n" + "xorl %edx, %edx\n" + "movl $MTRRphysBase_MSR(0), %ecx\n" + "wrmsr\n" + "movl $MTRRphysMask_MSR(0), %ecx\n" + "wrmsr\n" + "movl $MTRRphysBase_MSR(1), %ecx\n" + "wrmsr\n" + "movl $MTRRphysMask_MSR(1), %ecx\n" + "wrmsr\n" +#endif + + "movb $0x33, %al\noutb %al, $0x80\n" +#ifdef CLEAR_FIRST_1M_RAM + "movb $0x34, %al\noutb %al, $0x80\n" + /* Enable Write Combining and Speculative Reads for the first 1MB */ + "movl $MTRRphysBase_MSR(0), %ecx\n" + "movl $(0x00000000 | MTRR_TYPE_WRCOMB), %eax\n" + "xorl %edx, %edx\n" + "wrmsr\n" + "movl $MTRRphysMask_MSR(0), %ecx\n" + "movl $(~(1024*1024 -1) | (1 << 11)), %eax\n" + "movl $0x0000000f, %edx\n" // 36bit address space + "wrmsr\n" + "movb $0x35, %al\noutb %al, $0x80\n" +#endif + + /* Enable Cache */ + "movl %cr0, %eax\n" + "andl $~( (1 << 30) | (1 << 29) ), %eax\n" + "movl %eax, %cr0\n" + + "movb $0x36, %al\noutb %al, $0x80\n" +#ifdef CLEAR_FIRST_1M_RAM + + /* Clear first 1MB of RAM */ + "movl $0x00000000, %edi\n" + "cld\n" + "xorl %eax, %eax\n" + "movl $((1024*1024) / 4), %ecx\n" + "rep stosl\n" + + "movb $0x37, %al\noutb %al, $0x80\n" +#endif + + /* Disable Cache */ + "movl %cr0, %eax\n" + "orl $(1 << 30), %eax\n" + "movl %eax, %cr0\n" + + "movb $0x38, %al\noutb %al, $0x80\n" + + /* Enable Write Back and Speculative Reads for the first 1MB */ + "movl $MTRRphysBase_MSR(0), %ecx\n" + "movl $(0x00000000 | MTRR_TYPE_WRBACK), %eax\n" + "xorl %edx, %edx\n" + "wrmsr\n" + "movl $MTRRphysMask_MSR(0), %ecx\n" + "movl $(~(1024*1024 -1) | (1 << 11)), %eax\n" + "movl $0x0000000f, %edx\n" // 36bit address space + "wrmsr\n" + + "movb $0x39, %al\noutb %al, $0x80\n" + + /* And Enable Cache again after setting MTRRs */ + "movl %cr0, %eax\n" + "andl $~( (1 << 30) | (1 << 29) ), %eax\n" + "movl %eax, %cr0\n" + + "movb $0x3a, %al\noutb %al, $0x80\n" + + /* Enable MTRR */ + "movl $MTRRdefType_MSR, %ecx\n" + "rdmsr\n" + "orl $(1 << 11), %eax\n" + "wrmsr\n" + + "movb $0x3b, %al\noutb %al, $0x80\n" + + /* Invalidate the cache again */ + "invd\n" + "movb $0x3c, %al\noutb %al, $0x80\n" + ); Added: trunk/coreboot-v2/src/cpu/intel/model_6ex/microcode_m206e839.h =================================================================== --- trunk/coreboot-v2/src/cpu/intel/model_6ex/microcode_m206e839.h (rev 0) +++ trunk/coreboot-v2/src/cpu/intel/model_6ex/microcode_m206e839.h 2008-10-29 04:48:44 UTC (rev 3702) @@ -0,0 +1,291 @@ +//+++ +// Copyright (c) <1995-2008>, Intel Corporation. +// All rights reserved. +// +// Redistribution. Redistribution and use in binary form, without modification, are +// permitted provided that the following conditions are met: +// .Redistributions must reproduce the above copyright notice and the following +// disclaimer in the documentation and/or other materials provided with the +// distribution. +// .Neither the name of Intel Corporation nor the names of its suppliers may be used +// to endorse or promote products derived from this software without specific prior +// written permission. +// .No reverse engineering, decompilation, or disassembly of this software is +// permitted. +// ."Binary form" includes any format commonly used for electronic conveyance +// which is a reversible, bit-exact translation of binary representation to ASCII or +// ISO text, for example, "uuencode." +// +// DISCLAIMER. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT +// HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED +// WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER +// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +// NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +//--- +/* Tue Apr 1 14:14:15 CST 2008 */ +/* 1624-m206e839.inc */ +0x00000001, 0x00000039, 0x11152005, 0x000006e8, +0x00e9d6a3, 0x00000001, 0x00000020, 0x00000fd0, +0x00001000, 0x00000000, 0x00000000, 0x00000000, +0xc9226026, 0x31d04cc5, 0xeb5e9216, 0x81b9b739, +0xb8187c4d, 0xdb2db5c8, 0xac304dd3, 0x56259185, +0x5cee9dfc, 0xc4c708fc, 0xfbfebb15, 0x4657a346, +0xd5fdfc56, 0x49ccc684, 0xfe2f1980, 0x23e44e95, +0xaf7e0890, 0x0a306ae9, 0x0533035c, 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0x4ee342b0, +0x32b1e444, 0x1c1801a4, 0xc8424702, 0x334a7e35, +0x50cf1543, 0x3b22b495, 0x88683776, 0x8e2e0154, +0x6155c033, 0x4e2fa6ac, 0x42ace700, 0x8d64f97c, +0xaf9ced17, 0xb2a5cb92, 0xa558582d, 0x88705de7, +0x9e528d59, 0x84bd45e4, 0x5cb680c0, 0xcd48fa5c, + Added: trunk/coreboot-v2/src/cpu/intel/model_6ex/model_6ex_init.c =================================================================== --- trunk/coreboot-v2/src/cpu/intel/model_6ex/model_6ex_init.c (rev 0) +++ trunk/coreboot-v2/src/cpu/intel/model_6ex/model_6ex_init.c 2008-10-29 04:48:44 UTC (rev 3702) @@ -0,0 +1,94 @@ +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <string.h> +#include <cpu/cpu.h> +#include <cpu/x86/mtrr.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/lapic.h> +#include <cpu/intel/microcode.h> +#include <cpu/intel/hyperthreading.h> +#include <cpu/x86/cache.h> +#include <cpu/x86/mtrr.h> + +static const uint32_t microcode_updates[] = { + #include "microcode_m206e839.h" + /* Dummy terminator */ + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, +}; + +static inline void strcpy(char *dst, char *src) +{ + while (*src) *dst++ = *src++; +} + +static void fill_processor_name(char *processor_name) +{ + struct cpuid_result regs; + char temp_processor_name[49]; + char *processor_name_start; + unsigned int *name_as_ints = (unsigned int *)temp_processor_name; + int i; + + for (i=0; i<3; i++) { + regs = cpuid(0x80000002 + i); + name_as_ints[i*4 + 0] = regs.eax; + name_as_ints[i*4 + 1] = regs.ebx; + name_as_ints[i*4 + 2] = regs.ecx; + name_as_ints[i*4 + 3] = regs.edx; + } + + temp_processor_name[48] = 0; + + /* Skip leading spaces */ + processor_name_start = temp_processor_name; + while (*processor_name_start == ' ') + processor_name_start++; + + memset(processor_name, 0, 49); + strcpy(processor_name, processor_name_start); +} + +static void model_6ex_init(device_t cpu) +{ + char processor_name[49]; + + /* Turn on caching if we haven't already */ + x86_enable_cache(); + + /* Update the microcode */ + intel_update_microcode(microcode_updates); + + /* Print processor name */ + fill_processor_name(processor_name); + printk_info("CPU: %s.\n", processor_name); + + /* Setup MTRRs */ + x86_setup_mtrrs(36); + x86_mtrr_check(); + + /* Enable the local cpu apics */ + setup_lapic(); + + /* Start up my cpu siblings */ + intel_sibling_init(cpu); +} + +static struct device_operations cpu_dev_ops = { + .init = model_6ex_init, +}; + +static struct cpu_device_id cpu_table[] = { + { X86_VENDOR_INTEL, 0x06e0 }, /* Intel Core Solo/Core Duo */ + { X86_VENDOR_INTEL, 0x06e8 }, /* Intel Core Solo/Core Duo */ + { 0, 0 }, +}; + +static const struct cpu_driver driver __cpu_driver = { + .ops = &cpu_dev_ops, + .id_table = cpu_table, +}; + Added: trunk/coreboot-v2/src/cpu/intel/model_6fx/Config.lb =================================================================== --- trunk/coreboot-v2/src/cpu/intel/model_6fx/Config.lb (rev 0) +++ trunk/coreboot-v2/src/cpu/intel/model_6fx/Config.lb 2008-10-29 04:48:44 UTC (rev 3702) @@ -0,0 +1,13 @@ +uses HAVE_MOVNTI +default HAVE_MOVNTI=1 + +dir /cpu/x86/tsc +dir /cpu/x86/mtrr +dir /cpu/x86/fpu +dir /cpu/x86/mmx +dir /cpu/x86/sse +dir /cpu/x86/lapic +dir /cpu/x86/cache +dir /cpu/intel/microcode +dir /cpu/intel/hyperthreading +driver model_6fx_init.o Added: trunk/coreboot-v2/src/cpu/intel/model_6fx/cache_as_ram.inc =================================================================== --- trunk/coreboot-v2/src/cpu/intel/model_6fx/cache_as_ram.inc (rev 0) +++ trunk/coreboot-v2/src/cpu/intel/model_6fx/cache_as_ram.inc 2008-10-29 04:48:44 UTC (rev 3702) @@ -0,0 +1,159 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich(a)gmail.com> + * Copyright (C) 2007-2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define CACHE_AS_RAM_SIZE DCACHE_RAM_SIZE +#define CACHE_AS_RAM_BASE DCACHE_RAM_BASE +#define post_code(x) intel_chip_post_macro(x) + +#include <cpu/x86/mtrr.h> +#include <cpu/amd/mtrr.h> + + /* Save the BIST result */ + movl %eax, %ebp + +cache_as_ram: +#if USE_FALLBACK_IMAGE == 1 + + post_code(0x20) + + /* Send INIT IPI to all excluding ourself */ + movl $0x000C4500, %eax + movl $0xFEE00300, %esi + movl %eax, (%esi) + + /* Disable prefetchers */ + movl $0x01a0, %eax + rdmsr + orl $((1 << 9) | (1 << 19)), %eax + orl $((1 << 5) | (1 << 7)), %edx + wrmsr + + /* Zero out all Fixed Range and Variable Range MTRRs */ + movl $mtrr_table, %esi + movl $( (mtrr_table_end - mtrr_table) / 2), %edi + xorl %eax, %eax + xorl %edx, %edx +clear_mtrrs: + movw (%esi), %bx + movzx %bx, %ecx + wrmsr + add $2, %esi + dec %edi + jnz clear_mtrrs + + /* Configure the default memory type to uncacheable */ + movl $MTRRdefType_MSR, %ecx + rdmsr + andl $(~0x00000cff), %eax + wrmsr + + /* Set cache as ram base address */ + movl $(MTRRphysBase_MSR(0)), %ecx + movl $(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax + xorl %edx, %edx + wrmsr + + /* Set cache as ram mask */ + movl $(MTRRphysMask_MSR(0)), %ecx + movl $(~((CACHE_AS_RAM_SIZE-1)) | (1 << 11)), %eax + movl $0x0000000f, %edx + wrmsr + + /* Enable MTRR */ + movl $MTRRdefType_MSR, %ecx + rdmsr + orl $(1 << 11), %eax + wrmsr + + /* Enable L2 Cache */ + movl $0x11e, %ecx + rdmsr + orl $(1 << 8), %eax + wrmsr + + /* CR0.CD = 0, CR0.NW = 0 */ + movl %cr0, %eax + andl $( ~( (1 << 30) | (1 << 29) ) ), %eax + invd + movl %eax, %cr0 + + /* Clear the cache memory reagion */ + movl $CACHE_AS_RAM_BASE, %esi + movl %esi, %edi + movl $(CACHE_AS_RAM_SIZE / 4), %ecx + //movl $0x23322332, %eax + xorl %eax, %eax + rep stosl +#endif + + /* Enable Cache As RAM mode by disabling cache */ + movl %cr0, %eax + orl $(1 << 30), %eax + movl %eax, %cr0 + +#if defined(XIP_ROM_SIZE) && defined(XIP_ROM_BASE) + /* Enable cache for our code in Flash because we do XIP here */ + movl $MTRRphysBase_MSR(1), %ecx + xorl %edx, %edx + movl $(XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax + wrmsr + + movl $MTRRphysMask_MSR(1), %ecx + movl $0x0000000f, %edx + movl $(~(XIP_ROM_SIZE - 1) | 0x800), %eax + wrmsr +#endif /* XIP_ROM_SIZE && XIP_ROM_BASE */ + + /* enable cache */ + movl %cr0, %eax + andl $( ~( (1 << 30) | (1 << 29) ) ), %eax + movl %eax, %cr0 + + /* Set up stack pointer */ + movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4), %eax + movl %eax, %esp + + /* Restore the BIST result */ + movl %ebp, %eax + movl %esp, %ebp + pushl %eax + + post_code(0x23) + + call stage1_main + + post_code(0x2f) +error: + hlt + jmp error + +mtrr_table: + /* Fixed MTRRs */ + .word 0x250, 0x258, 0x259 + .word 0x268, 0x269, 0x26A + .word 0x26B, 0x26C, 0x26D + .word 0x26E, 0x26F + /* Variable MTRRs */ + .word 0x200, 0x201, 0x202, 0x203 + .word 0x204, 0x205, 0x206, 0x207 + .word 0x208, 0x209, 0x20A, 0x20B + .word 0x20C, 0x20D, 0x20E, 0x20F +mtrr_table_end: + Added: trunk/coreboot-v2/src/cpu/intel/model_6fx/cache_as_ram_disable.c =================================================================== --- trunk/coreboot-v2/src/cpu/intel/model_6fx/cache_as_ram_disable.c (rev 0) +++ trunk/coreboot-v2/src/cpu/intel/model_6fx/cache_as_ram_disable.c 2008-10-29 04:48:44 UTC (rev 3702) @@ -0,0 +1,111 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include "cpu/x86/car/copy_and_run.c" + +void real_main(unsigned long bist); + +void stage1_main(unsigned long bist) +{ + unsigned int cpu_reset = 0; + +#if USE_FALLBACK_IMAGE == 1 + /* Is this a deliberate reset by the bios */ + if (bios_reset_detected() && last_boot_normal()) { + goto normal_image; + } else { + /* This is the primary cpu how should I boot? */ + check_cmos_failed(); + if (do_normal_boot()) { + goto normal_image; + } + else { + goto fallback_image; + } + } + normal_image: + __asm__ volatile ("jmp __normal_image" + : /* outputs */ + : "a" (bist) /* inputs */ + ); + fallback_image: +#endif + + real_main(bist); + + /* No servicable parts below this line .. */ + + { + /* Check value of esp to verify if we have enough rom for stack in Cache as RAM */ + unsigned v_esp; + __asm__ volatile ( + "movl %%esp, %0\n\t" + : "=a" (v_esp) + ); + printk_spew("v_esp=%08x\r\n", v_esp); + } + +cpu_reset_x: + + printk_spew("cpu_reset = %08x\r\n",cpu_reset); + + if(cpu_reset == 0) { + print_spew("Clearing initial memory region: "); + } + print_spew("No cache as ram now - "); + + /* store cpu_reset to ebx */ + __asm__ volatile ( + "movl %0, %%ebx\n\t" + ::"a" (cpu_reset) + ); + + if(cpu_reset==0) { +#define CLEAR_FIRST_1M_RAM 1 +#include "cache_as_ram_post.c" + } else { +#undef CLEAR_FIRST_1M_RAM +#include "cache_as_ram_post.c" + } + + __asm__ volatile ( + /* set new esp */ /* before _RAMBASE */ + "subl %0, %%ebp\n\t" + "subl %0, %%esp\n\t" + ::"a"( (DCACHE_RAM_BASE + DCACHE_RAM_SIZE)- _RAMBASE ) + ); + + { + unsigned new_cpu_reset; + + /* get back cpu_reset from ebx */ + __asm__ volatile ( + "movl %%ebx, %0\n\t" + :"=a" (new_cpu_reset) + ); + + /* Copy and execute coreboot_ram */ + copy_and_run(new_cpu_reset); + /* We will not return */ + } + + print_debug("sorry. parachute did not open.\r\n"); +} Added: trunk/coreboot-v2/src/cpu/intel/model_6fx/cache_as_ram_post.c =================================================================== --- trunk/coreboot-v2/src/cpu/intel/model_6fx/cache_as_ram_post.c (rev 0) +++ trunk/coreboot-v2/src/cpu/intel/model_6fx/cache_as_ram_post.c 2008-10-29 04:48:44 UTC (rev 3702) @@ -0,0 +1,132 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + + __asm__ volatile ( + + "movb $0x30, %al\noutb %al, $0x80\n" + + /* Disable Cache */ + "movl %cr0, %eax\n" + "orl $(1 << 30), %eax\n" + "movl %eax, %cr0\n" + + "movb $0x31, %al\noutb %al, $0x80\n" + + /* Disable MTRR */ + "movl $MTRRdefType_MSR, %ecx\n" + "rdmsr\n" + "andl $(~(1 << 11)), %eax\n" + "wrmsr\n" + + "movb $0x32, %al\noutb %al, $0x80\n" + + "invd\n" +#if 0 + "xorl %eax, %eax\n" + "xorl %edx, %edx\n" + "movl $MTRRphysBase_MSR(0), %ecx\n" + "wrmsr\n" + "movl $MTRRphysMask_MSR(0), %ecx\n" + "wrmsr\n" + "movl $MTRRphysBase_MSR(1), %ecx\n" + "wrmsr\n" + "movl $MTRRphysMask_MSR(1), %ecx\n" + "wrmsr\n" +#endif + + "movb $0x33, %al\noutb %al, $0x80\n" +#ifdef CLEAR_FIRST_1M_RAM + "movb $0x34, %al\noutb %al, $0x80\n" + /* Enable Write Combining and Speculative Reads for the first 1MB */ + "movl $MTRRphysBase_MSR(0), %ecx\n" + "movl $(0x00000000 | MTRR_TYPE_WRCOMB), %eax\n" + "xorl %edx, %edx\n" + "wrmsr\n" + "movl $MTRRphysMask_MSR(0), %ecx\n" + "movl $(~(1024*1024 -1) | (1 << 11)), %eax\n" + "movl $0x0000000f, %edx\n" // 36bit address space + "wrmsr\n" + "movb $0x35, %al\noutb %al, $0x80\n" +#endif + + /* Enable Cache */ + "movl %cr0, %eax\n" + "andl $~( (1 << 30) | (1 << 29) ), %eax\n" + "movl %eax, %cr0\n" + + "movb $0x36, %al\noutb %al, $0x80\n" +#ifdef CLEAR_FIRST_1M_RAM + + /* Clear first 1MB of RAM */ + "movl $0x00000000, %edi\n" + "cld\n" + "xorl %eax, %eax\n" + "movl $((1024*1024) / 4), %ecx\n" + "rep stosl\n" + + "movb $0x37, %al\noutb %al, $0x80\n" +#endif + + /* Disable Cache */ + "movl %cr0, %eax\n" + "orl $(1 << 30), %eax\n" + "movl %eax, %cr0\n" + + "movb $0x38, %al\noutb %al, $0x80\n" + + /* Enable Write Back and Speculative Reads for the first 1MB */ + "movl $MTRRphysBase_MSR(0), %ecx\n" + "movl $(0x00000000 | MTRR_TYPE_WRBACK), %eax\n" + "xorl %edx, %edx\n" + "wrmsr\n" + "movl $MTRRphysMask_MSR(0), %ecx\n" + "movl $(~(1024*1024 -1) | (1 << 11)), %eax\n" + "movl $0x0000000f, %edx // 36bit address space\n" + "wrmsr\n" + + "movb $0x39, %al\noutb %al, $0x80\n" + + /* And Enable Cache again after setting MTRRs */ + "movl %cr0, %eax\n" + "andl $~( (1 << 30) | (1 << 29) ), %eax\n" + "movl %eax, %cr0\n" + + "movb $0x3a, %al\noutb %al, $0x80\n" + + /* Enable MTRR */ + "movl $MTRRdefType_MSR, %ecx\n" + "rdmsr\n" + "orl $(1 << 11), %eax\n" + "wrmsr\n" + + "movb $0x3b, %al\noutb %al, $0x80\n" + + /* Enable prefetchers */ + "movl $0x01a0, %eax\n" + "rdmsr\n" + "andl $~((1 << 9) | (1 << 19)), %eax\n" + "andl $~((1 << 5) | (1 << 7)), %edx\n" + "wrmsr\n" + + /* Invalidate the cache again */ + "invd\n" + "movb $0x3c, %al\noutb %al, $0x80\n" + ); Added: trunk/coreboot-v2/src/cpu/intel/model_6fx/model_6fx_init.c =================================================================== --- trunk/coreboot-v2/src/cpu/intel/model_6fx/model_6fx_init.c (rev 0) +++ trunk/coreboot-v2/src/cpu/intel/model_6fx/model_6fx_init.c 2008-10-29 04:48:44 UTC (rev 3702) @@ -0,0 +1,94 @@ +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <string.h> +#include <cpu/cpu.h> +#include <cpu/x86/mtrr.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/lapic.h> +#include <cpu/intel/microcode.h> +#include <cpu/intel/hyperthreading.h> +#include <cpu/x86/cache.h> +#include <cpu/x86/mtrr.h> + +static const uint32_t microcode_updates[] = { + // #include "microcode_m206e839.h" + /* Dummy terminator */ + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, +}; + +static inline void strcpy(char *dst, char *src) +{ + while (*src) *dst++ = *src++; +} + +static void fill_processor_name(char *processor_name) +{ + struct cpuid_result regs; + char temp_processor_name[49]; + char *processor_name_start; + unsigned int *name_as_ints = (unsigned int *)temp_processor_name; + int i; + + for (i=0; i<3; i++) { + regs = cpuid(0x80000002 + i); + name_as_ints[i*4 + 0] = regs.eax; + name_as_ints[i*4 + 1] = regs.ebx; + name_as_ints[i*4 + 2] = regs.ecx; + name_as_ints[i*4 + 3] = regs.edx; + } + + temp_processor_name[48] = 0; + + /* Skip leading spaces */ + processor_name_start = temp_processor_name; + while (*processor_name_start == ' ') + processor_name_start++; + + memset(processor_name, 0, 49); + strcpy(processor_name, processor_name_start); +} + +static void model_6ex_init(device_t cpu) +{ + char processor_name[49]; + + /* Turn on caching if we haven't already */ + x86_enable_cache(); + + /* Update the microcode */ + intel_update_microcode(microcode_updates); + + /* Print processor name */ + fill_processor_name(processor_name); + printk_info("CPU: %s.\n", processor_name); + + /* Setup MTRRs */ + x86_setup_mtrrs(36); + x86_mtrr_check(); + + /* Enable the local cpu apics */ + setup_lapic(); + + /* Start up my cpu siblings */ + intel_sibling_init(cpu); +} + +static struct device_operations cpu_dev_ops = { + .init = model_6ex_init, +}; + +static struct cpu_device_id cpu_table[] = { + { X86_VENDOR_INTEL, 0x06f0 }, /* Intel Core 2 Solo/Core Duo */ + { X86_VENDOR_INTEL, 0x06f6 }, /* Intel Core 2 Solo/Core Duo */ + { 0, 0 }, +}; + +static const struct cpu_driver driver __cpu_driver = { + .ops = &cpu_dev_ops, + .id_table = cpu_table, +}; + Modified: trunk/coreboot-v2/src/cpu/intel/socket_mFCPGA478/Config.lb =================================================================== --- trunk/coreboot-v2/src/cpu/intel/socket_mFCPGA478/Config.lb 2008-10-29 04:46:52 UTC (rev 3701) +++ trunk/coreboot-v2/src/cpu/intel/socket_mFCPGA478/Config.lb 2008-10-29 04:48:44 UTC (rev 3702) @@ -2,3 +2,5 @@ object socket_mFCPGA478.o dir /cpu/intel/model_69x dir /cpu/intel/model_6dx +dir /cpu/intel/model_6ex +dir /cpu/intel/model_6fx Added: trunk/coreboot-v2/src/cpu/intel/socket_mPGA478/Config.lb =================================================================== --- trunk/coreboot-v2/src/cpu/intel/socket_mPGA478/Config.lb (rev 0) +++ trunk/coreboot-v2/src/cpu/intel/socket_mPGA478/Config.lb 2008-10-29 04:48:44 UTC (rev 3702) @@ -0,0 +1,4 @@ +config chip.h +object socket_mPGA478.o +dir /cpu/intel/model_69x +dir /cpu/intel/model_6dx Added: trunk/coreboot-v2/src/cpu/intel/socket_mPGA478/chip.h =================================================================== --- trunk/coreboot-v2/src/cpu/intel/socket_mPGA478/chip.h (rev 0) +++ trunk/coreboot-v2/src/cpu/intel/socket_mPGA478/chip.h 2008-10-29 04:48:44 UTC (rev 3702) @@ -0,0 +1,4 @@ +extern struct chip_operations cpu_intel_socket_mPGA478_ops; + +struct cpu_intel_socket_mPGA478_config { +}; Added: trunk/coreboot-v2/src/cpu/intel/socket_mPGA478/socket_mPGA478.c =================================================================== --- trunk/coreboot-v2/src/cpu/intel/socket_mPGA478/socket_mPGA478.c (rev 0) +++ trunk/coreboot-v2/src/cpu/intel/socket_mPGA478/socket_mPGA478.c 2008-10-29 04:48:44 UTC (rev 3702) @@ -0,0 +1,7 @@ +#include <device/device.h> +#include "chip.h" + + +struct chip_operations cpu_intel_socket_mPGA478_ops = { + CHIP_NAME("Socket mPGA478 CPU") +}; Modified: trunk/coreboot-v2/src/cpu/x86/car/copy_and_run.c =================================================================== --- trunk/coreboot-v2/src/cpu/x86/car/copy_and_run.c 2008-10-29 04:46:52 UTC (rev 3701) +++ trunk/coreboot-v2/src/cpu/x86/car/copy_and_run.c 2008-10-29 04:48:44 UTC (rev 3702) @@ -72,7 +72,7 @@ __asm__ volatile ( "cli\n\t" "leal _iseg, %edi\n\t" - "jmp %edi\n\t" + "jmp *%edi\n\t" ); } Modified: trunk/coreboot-v2/src/cpu/x86/lapic/lapic_cpu_init.c =================================================================== --- trunk/coreboot-v2/src/cpu/x86/lapic/lapic_cpu_init.c 2008-10-29 04:46:52 UTC (rev 3701) +++ trunk/coreboot-v2/src/cpu/x86/lapic/lapic_cpu_init.c 2008-10-29 04:48:44 UTC (rev 3702) @@ -437,6 +437,10 @@ #define cpus_ready_for_init() do {} while(0) #endif +#if HAVE_SMI_HANDLER +void smm_init(void); +#endif + void initialize_cpus(struct bus *cpu_bus) { struct device_path cpu_path; @@ -457,14 +461,18 @@ cpu_path.type = DEVICE_PATH_CPU; cpu_path.u.cpu.id = 0; #endif - + /* Find the device structure for the boot cpu */ info->cpu = alloc_find_dev(cpu_bus, &cpu_path); #if CONFIG_SMP == 1 copy_secondary_start_to_1m_below(); // why here? In case some day we can start core1 in amd_sibling_init #endif - + +#if HAVE_SMI_HANDLER + smm_init(); +#endif + cpus_ready_for_init(); #if CONFIG_SMP == 1 @@ -477,7 +485,6 @@ /* Initialize the bootstrap processor */ cpu_initialize(); - #if CONFIG_SMP == 1 #if SERIAL_CPU_INIT == 1 start_other_cpus(cpu_bus, info->cpu); @@ -486,6 +493,5 @@ /* Now wait the rest of the cpus stop*/ wait_other_cpus_stop(cpu_bus); #endif - }

1 0

r3701 - in trunk/coreboot-v2/src: config include/cpu/x86 include/device southbridge/intel southbridge/intel/i82801gx
by svn＠coreboot.org 29 Oct '08

29 Oct '08

Author: stepan Date: 2008-10-29 05:46:52 +0100 (Wed, 29 Oct 2008) New Revision: 3701 Added: trunk/coreboot-v2/src/include/cpu/x86/smm.h trunk/coreboot-v2/src/southbridge/intel/i82801gx/ trunk/coreboot-v2/src/southbridge/intel/i82801gx/Config.lb trunk/coreboot-v2/src/southbridge/intel/i82801gx/IOMAP trunk/coreboot-v2/src/southbridge/intel/i82801gx/chip.h trunk/coreboot-v2/src/southbridge/intel/i82801gx/cmos_failover.c trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx.c trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx.h trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_ac97.c trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_early_smbus.c trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_ide.c trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_lpc.c trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_nic.c trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_nvs.h trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_pci.c trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_pcie.c trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_reset.c trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_sata.c trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_smbus.c trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_smbus.h trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_smi.c trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_usb.c trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_usb_ehci.c trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_watchdog.c trunk/coreboot-v2/src/southbridge/intel/i82801gx/smihandler.c trunk/coreboot-v2/src/southbridge/intel/i82801gx/smm.ld trunk/coreboot-v2/src/southbridge/intel/i82801gx/smmhandler.S trunk/coreboot-v2/src/southbridge/intel/i82801gx/smmrelocate.S Modified: trunk/coreboot-v2/src/config/Options.lb trunk/coreboot-v2/src/include/device/device.h Log: Support for the Intel ICH7 southbridge. This includes an early SMI handler. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Modified: trunk/coreboot-v2/src/config/Options.lb =================================================================== --- trunk/coreboot-v2/src/config/Options.lb 2008-10-29 04:45:28 UTC (rev 3700) +++ trunk/coreboot-v2/src/config/Options.lb 2008-10-29 04:46:52 UTC (rev 3701) @@ -856,6 +856,11 @@ export used comment "Have hard reset" end +define HAVE_SMI_HANDLER + default none + export used + comment "Set, if the board needs an SMI handler" +end define MEMORY_HOLE default none export used Added: trunk/coreboot-v2/src/include/cpu/x86/smm.h =================================================================== --- trunk/coreboot-v2/src/include/cpu/x86/smm.h (rev 0) +++ trunk/coreboot-v2/src/include/cpu/x86/smm.h 2008-10-29 04:46:52 UTC (rev 3701) @@ -0,0 +1,253 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +typedef uint64_t u64; + +/* AMD64 SMM State-Save Area + * starts @ 0x7e00 + */ +typedef struct { + u16 es_selector; + u16 es_attributes; + u32 es_limit; + u64 es_base; + + u16 cs_selector; + u16 cs_attributcs; + u32 cs_limit; + u64 cs_base; + + u16 ss_selector; + u16 ss_attributss; + u32 ss_limit; + u64 ss_base; + + u16 ds_selector; + u16 ds_attributds; + u32 ds_limit; + u64 ds_base; + + u16 fs_selector; + u16 fs_attributfs; + u32 fs_limit; + u64 fs_base; + + u16 gs_selector; + u16 gs_attributgs; + u32 gs_limit; + u64 gs_base; + + u8 reserved0[4]; + u16 gdtr_limit; + u8 reserved1[2]; + u64 gdtr_base; + + u16 ldtr_selector; + u16 ldtr_attributes; + u32 ldtr_limit; + u64 ldtr_base; + + u8 reserved2[4]; + u16 idtr_limit; + u8 reserved3[2]; + u64 idtr_base; + + u16 tr_selector; + u16 tr_attributes; + u32 tr_limit; + u64 tr_base; + + u8 reserved4[40]; + + u8 io_restart; + u8 autohalt_restart; + + u8 reserved5[6]; + + u64 efer; + + u8 reserved6[36]; + + u32 smm_revision; + u32 smbase; + + u8 reserved7[68]; + + u64 cr4; + u64 cr3; + u64 cr0; + u64 dr7; + u64 dr6; + + u64 rflags; + u64 rip; + u64 r15; + u64 r14; + u64 r13; + u64 r12; + u64 r11; + u64 r10; + u64 r9; + u64 r8; + + u64 rdi; + u64 rsi; + u64 rpb; + u64 rsp; + u64 rbx; + u64 rdx; + u64 rcx; + u64 rax; +} __attribute__((packed)) amd64_smm_state_save_area_t; + + +/* Intel Core 2 (EM64T) SMM State-Save Area + * starts @ 0x7d00 + */ +typedef struct { + u8 reserved0[208]; + + u32 gdtr_upper_base; + u32 ldtr_upper_base; + u32 idtr_upper_base; + + u8 reserved1[4]; + + u64 io_rdi; + u64 io_rip; + u64 io_rcx; + u64 io_rsi; + u64 cr4; + + u8 reserved2[68]; + + u64 gdtr_base; + u64 idtr_base; + u64 ldtr_base; + + u8 reserved3[84]; + + u32 smm_revision; + u32 smbase; + + u16 io_restart; + u16 autohalt_restart; + + u8 reserved4[24]; + + u64 r15; + u64 r14; + u64 r13; + u64 r12; + u64 r11; + u64 r10; + u64 r9; + u64 r8; + + u64 rax; + u64 rcx; + u64 rdx; + u64 rbx; + + u64 rsp; + u64 rbp; + u64 rsi; + u64 rdi; + + + u64 io_mem_addr; + u32 io_misc_info; + + u32 es_sel; + u32 cs_sel; + u32 ss_sel; + u32 ds_sel; + u32 fs_sel; + u32 gs_sel; + + u32 ldtr_sel; + u32 tr_sel; + + u64 dr7; + u64 dr6; + u64 rip; + u64 efer; + u64 rflags; + + u64 cr3; + u64 cr0; +} __attribute__((packed)) em64t_smm_state_save_area_t; + + +/* Legacy x86 SMM State-Save Area + * starts @ 0x7e00 + */ + +typedef struct { + u8 reserved0[248]; + u32 smbase; + u32 smm_revision; + u16 io_restart; + u16 autohalt_restart; + u8 reserved1[132]; + u32 gdtbase; + u8 reserved2[8]; + u32 idtbase; + u8 reserved3[16]; + u32 es; + u32 cs; + u32 ss; + u32 ds; + u32 fs; + u32 gs; + u32 ldtbase; + u32 tr; + u32 dr7; + u32 dr6; + u32 eax; + u32 ecx; + u32 edx; + u32 ebx; + u32 esp; + u32 ebp; + u32 esi; + u32 edi; + u32 eip; + u32 eflags; + u32 cr3; + u32 cr0; +} __attribute__((packed)) legacy_smm_state_save_area_t; + +typedef enum { + AMD64, + EM64T, + LEGACY +} save_state_type_t; + + +typedef struct { + save_state_type_t type; + union { + amd64_smm_state_save_area_t *amd64_state_save; + em64t_smm_state_save_area_t *em64t_state_save; + legacy_smm_state_save_area_t *legacy_state_save; + }; +} smm_state_save_area_t; + Modified: trunk/coreboot-v2/src/include/device/device.h =================================================================== --- trunk/coreboot-v2/src/include/device/device.h 2008-10-29 04:45:28 UTC (rev 3700) +++ trunk/coreboot-v2/src/include/device/device.h 2008-10-29 04:46:52 UTC (rev 3701) @@ -71,7 +71,7 @@ struct device_path path; unsigned vendor; unsigned device; - unsigned int class; /* 3 bytes: (base,sub,prog-if) */ + unsigned int class; /* 3 bytes: (base, sub, prog-if) */ unsigned int hdr_type; /* PCI header type */ unsigned int enabled : 1; /* set if we should enable the device */ unsigned int initialized : 1; /* set if we have initialized the device */ @@ -85,7 +85,7 @@ struct resource resource[MAX_RESOURCES]; unsigned int resources; - /* link are (down sream) buses attached to the device, usually a leaf + /* link are (down stream) buses attached to the device, usually a leaf * device with no children have 0 buses attached and a bridge has 1 bus */ struct bus link[MAX_LINKS]; Added: trunk/coreboot-v2/src/southbridge/intel/i82801gx/Config.lb =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/i82801gx/Config.lb (rev 0) +++ trunk/coreboot-v2/src/southbridge/intel/i82801gx/Config.lb 2008-10-29 04:46:52 UTC (rev 3701) @@ -0,0 +1,66 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2008 coresystems GmbH +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +config chip.h +driver i82801gx.o +driver i82801gx_ac97.o +driver i82801gx_ide.o +driver i82801gx_lpc.o +driver i82801gx_nic.o +driver i82801gx_pci.o +driver i82801gx_pcie.o +driver i82801gx_sata.o +driver i82801gx_usb.o +driver i82801gx_usb_ehci.o + +object i82801gx_reset.o +object i82801gx_watchdog.o + +object i82801gx_smi.o +object smmrelocate.S + +makerule smmhandler.o + depends "$(TOP)/src/southbridge/intel/i82801gx/smmhandler.S" + action "@$(CC) -c $(CPU_OPT) $(CPPFLAGS) $(CFLAGS) -o $@ $<" +end + +makerule smihandler.o + depends "$(TOP)/src/southbridge/intel/i82801gx/smihandler.c" + action "@$(CC) -c $(CPU_OPT) $(CPPFLAGS) $(CFLAGS) -o $@ $<" +end + +makerule smm.o + depends "smmhandler.o smihandler.o printk.o vtxprintf.o $(LIBGCC_FILE_NAME)" + action "$(CC) $(DISTRO_LFLAGS) -nostdlib -r -o $@ smmhandler.o smihandler.o printk.o vtxprintf.o $(LIBGCC_FILE_NAME)" +end + +makerule smm + depends "smm.o $(TOP)/src/southbridge/intel/i82801gx/smm.ld ldoptions" + action "$(CC) $(DISTRO_LFLAGS) -nostdlib -nostartfiles -static -o smm.elf -T $(TOP)/src/southbridge/intel/i82801gx/smm.ld smm.o" + action "$(CROSS_COMPILE)nm -n smm.elf | sort > smm.map" + action "$(OBJCOPY) -O binary smm.elf smm" +end + +makerule smm_bin.c + depends "smm" + action "(echo 'unsigned char smm[] = {'; od -vtx1 smm | sed -e 's,^[0-9]* *,,' -e 's:[0-9a-f][0-9a-f] :0x&,:g' -e 's:[0-9a-f][0-9a-f]$$:0x&,:'; echo '}; unsigned int smm_len = '; wc -c smm |awk '{print $$1;}' ; echo ';') > smm_bin.c" +end + +object ./smm_bin.o Added: trunk/coreboot-v2/src/southbridge/intel/i82801gx/IOMAP =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/i82801gx/IOMAP (rev 0) +++ trunk/coreboot-v2/src/southbridge/intel/i82801gx/IOMAP 2008-10-29 04:46:52 UTC (rev 3701) @@ -0,0 +1,35 @@ +Non-automatic IO-Addresses +-------------------------- + +The following dynamic IO BARs are used on the ICH7 for the Kontron Default BIOS: + +GPIOBASE 0x480 (64 bytes) +PMBASE 0x800 (128 bytes) +SMBASE 0x400 (32 bytes) +HWMON 0xa00 (??) + +The following dynamic IO BARs are used on the ICH7 for the Getac Default BIOS: + +GPIOBASE 0x1180 (64 bytes) +PMBASE 0x1000 (128 bytes) +SMBASE 0x18e0 (32 bytes) + +The Getac also needs an IO Trapped area of 0x0C bytes (defaults to 0x800) + +coreboot: +GPIOBASE 0x480 (64 bytes) +PMBASE 0x500 (128 bytes) +SMBASE 0x400 (32 bytes) +HWMON 0xa00 (??) + + + +NOTE: Coreboot sets the SMBASE to 0xf00 in auto.c. But it gets relocated +in stage2 because its a "normal BAR" (to 0x2080 in one case here). + +This is not unhealthy but at least confusing. We should provide a method to +nail down certain resources for stage2. + +For a list of static I/O space allocation look at 6.3.1 of the ICH7 Family +Datasheet. + Added: trunk/coreboot-v2/src/southbridge/intel/i82801gx/chip.h =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/i82801gx/chip.h (rev 0) +++ trunk/coreboot-v2/src/southbridge/intel/i82801gx/chip.h 2008-10-29 04:46:52 UTC (rev 3701) @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef SOUTHBRIDGE_INTEL_I82801GX_CHIP_H +#define SOUTHBRIDGE_INTEL_I82801GX_CHIP_H + +struct southbridge_intel_i82801gx_config { + uint32_t ide_legacy_combined; + uint32_t ide_enable_primary; + uint32_t ide_enable_secondary; + uint32_t sata_ahci; +}; + +extern struct chip_operations southbridge_intel_i82801gx_ops; + +#endif /* SOUTHBRIDGE_INTEL_I82801GX_CHIP_H */ Added: trunk/coreboot-v2/src/southbridge/intel/i82801gx/cmos_failover.c =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/i82801gx/cmos_failover.c (rev 0) +++ trunk/coreboot-v2/src/southbridge/intel/i82801gx/cmos_failover.c 2008-10-29 04:46:52 UTC (rev 3701) @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "i82801gx.h" + +#define RTC_FAILED (1 <<2) +#define GEN_PMCON_3 0xa4 + +static void check_cmos_failed(void) +{ + u8 byte; + byte = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3); + if (byte & RTC_FAILED) { + // clear bit 1 and bit 2 + byte = cmos_read(RTC_BOOT_BYTE); + byte &= 0x0c; + byte |= MAX_REBOOT_CNT << 4; + cmos_write(byte, RTC_BOOT_BYTE); + } +} Added: trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx.c =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx.c (rev 0) +++ trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx.c 2008-10-29 04:46:52 UTC (rev 3701) @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include "i82801gx.h" + +void i82801gx_enable(device_t dev) +{ + +} + +struct chip_operations southbridge_intel_i82801gx_ops = { + CHIP_NAME("Intel ICH7/ICH7-M (82801Gx) Series Southbridge") + .enable_dev = i82801gx_enable, +}; Added: trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx.h =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx.h (rev 0) +++ trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx.h 2008-10-29 04:46:52 UTC (rev 3701) @@ -0,0 +1,122 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef SOUTHBRIDGE_INTEL_I82801GX_I82801GX_H +#define SOUTHBRIDGE_INTEL_I82801GX_I82801GX_H + +#include "chip.h" +extern void i82801gx_enable(device_t dev); + +#define PCI_DMA_CFG 0x90 +#define SERIRQ_CNTL 0x64 +#define GEN_CNTL 0xd0 +#define GEN_STS 0xd4 +#define RTC_CONF 0xd8 +#define GEN_PMCON_1 0xa0 +#define GEN_PMCON_2 0xa2 +#define GEN_PMCON_3 0xa4 + +#define PMBASE 0x40 +#define ACPI_CNTL 0x44 +#define BIOS_CNTL 0x4E +#define GPIO_BASE 0x48 /* LPC GPIO Base Address Register */ +#define GPIO_CNTL 0x4C /* LPC GPIO Control Register */ + +#define PIRQA_ROUT 0x60 +#define PIRQB_ROUT 0x61 +#define PIRQC_ROUT 0x62 +#define PIRQD_ROUT 0x63 +#define PIRQE_ROUT 0x68 +#define PIRQF_ROUT 0x69 +#define PIRQG_ROUT 0x6A +#define PIRQH_ROUT 0x6B + +#define FUNC_DIS 0xF2 + +#define LPC_IO_DEC 0x80 /* IO Decode Ranges Register */ +#define LPC_EN 0x82 /* LPC IF Enables Register */ + +#define SBUS_NUM 0x19 +#define SUB_BUS_NUM 0x1A +#define SMLT 0x1B +#define IOBASE 0x1C +#define IOLIM 0x1D +#define MEMBASE 0x20 +#define MEMLIM 0x22 +#define CNF 0x50 +#define MTT 0x70 +#define PCI_MAST_STS 0x82 + +/* GEN_PMCON_3 bits */ +#define RTC_BATTERY_DEAD (1 << 2) +#define RTC_POWER_FAILED (1 << 1) +#define SLEEP_AFTER_POWER_FAIL (1 << 0) + +/* PCI Configuration Space (D31:F1) */ +#define INTR_LN 0x3c +#define IDE_TIM_PRI 0x40 /* IDE timings, primary */ +#define IDE_DECODE_ENABLE (1 << 15) +#define IDE_SITRE (1 << 14) +#define IDE_TIM_SEC 0x42 /* IDE timings, secondary */ +#define IDE_CONFIG 0x54 /* IDE I/O Configuration Register */ +#define SIG_MODE_NORMAL (0 << 16) +#define SIG_MODE_TRISTATE (1 << 16) +#define SIG_MODE_DRIVELOW (2 << 16) +#define FAST_PCB1 (1 << 13) +#define FAST_PCB0 (1 << 12) +#define PCB1 (1 << 1) +#define PCB0 (1 << 0) + +/* PCI Configuration Space (D31:F3) */ +#define SMB_BASE 0x20 +#define HOSTC 0x40 + +/* HOSTC bits */ +#define I2C_EN (1 << 2) +#define SMB_SMI_EN (1 << 1) +#define HST_EN (1 << 0) + +/* SMBus I/O bits. + * TODO: It does not matter where we put the SMBus IO base, as long as we keep + * consistent and don't interfere with other devices. Stage2 will relocate + * this anyways. But it's a general problem we have not solved in the brightest + * possible way. + */ +/* #define SMBUS_IO_BASE 0x1000 */ +#define SMBUS_IO_BASE 0x0400 + +#define SMBHSTSTAT 0x0 +#define SMBHSTCTL 0x2 +#define SMBHSTCMD 0x3 +#define SMBXMITADD 0x4 +#define SMBHSTDAT0 0x5 +#define SMBHSTDAT1 0x6 +#define SMBBLKDAT 0x7 +#define SMBTRNSADD 0x9 +#define SMBSLVDATA 0xa +#define SMLINK_PIN_CTL 0xe +#define SMBUS_PIN_CTL 0xf + +#define SMBUS_TIMEOUT (10 * 1000 * 100) + +/* HPET, if present */ +#define HPET_ADDR 0xfed0000 + +#endif /* SOUTHBRIDGE_INTEL_I82801GX_I82801GX_H */ Added: trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_ac97.c =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_ac97.c (rev 0) +++ trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_ac97.c 2008-10-29 04:46:52 UTC (rev 3701) @@ -0,0 +1,71 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include "i82801gx.h" + +static void ac97_audio_init(struct device *dev) +{ + // XXX init AC97 codecs. +} + +static void ac97_modem_init(struct device *dev) +{ + // XXX init modem? +} + +static struct device_operations ac97_audio_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = ac97_audio_init, + .scan_bus = 0, + .enable = i82801gx_enable, +}; + +static struct device_operations ac97_modem_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = ac97_modem_init, + .scan_bus = 0, + .enable = i82801gx_enable, +}; + + + +/* 82801GB/GR/GDH/GBM/GHM (ICH7/ICH7R/ICH7DH/ICH7-M/ICH7-M DH) */ +/* Note: 82801GU (ICH7-U) doesn't have AC97 audio/modem. */ + +static const struct pci_driver i82801gb_ac97_audio __pci_driver = { + .ops = &ac97_audio_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82801GB_AC97_AUDIO, +}; + +static const struct pci_driver i82801gb_ac97_modem __pci_driver = { + .ops = &ac97_modem_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82801GB_AC97_MODEM, +}; + Added: trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_early_smbus.c =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_early_smbus.c (rev 0) +++ trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_early_smbus.c 2008-10-29 04:46:52 UTC (rev 3701) @@ -0,0 +1,59 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <device/pci_ids.h> +#include "i82801gx.h" +#include "i82801gx_smbus.h" + +static void enable_smbus(void) +{ + device_t dev; + + /* Set the SMBus device statically. */ + dev = PCI_DEV(0x0, 0x1f, 0x3); + + /* Check to make sure we've got the right device. */ + if (pci_read_config16(dev, 0x2) != 0x27da) { + die("SMBus controller not found!"); + } + + /* Set SMBus I/O base. */ + pci_write_config32(dev, SMB_BASE, + SMBUS_IO_BASE | PCI_BASE_ADDRESS_SPACE_IO); + + /* Set SMBus enable. */ + pci_write_config8(dev, HOSTC, HST_EN); + + /* Set SMBus I/O space enable. */ + pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO); + + /* Disable interrupt generation. */ + outb(0, SMBUS_IO_BASE + SMBHSTCTL); + + /* Clear any lingering errors, so transactions can run. */ + outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); + print_debug("SMBus controller enabled.\r\n"); +} + +static inline int smbus_read_byte(unsigned device, unsigned address) +{ + return do_smbus_read_byte(device, address); +} + Added: trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_ide.c =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_ide.c (rev 0) +++ trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_ide.c 2008-10-29 04:46:52 UTC (rev 3701) @@ -0,0 +1,100 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include "i82801gx.h" + +typedef struct southbridge_intel_i82801gx_config config_t; + +static void ide_init(struct device *dev) +{ + u16 ideTimingConfig; + u32 reg32; + + /* Get the chip configuration */ + config_t *config = dev->chip_info; + + int enable_primary = config->ide_enable_primary; + int enable_secondary = config->ide_enable_secondary; + + reg32 = pci_read_config32(dev, PCI_COMMAND); + pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_IO | PCI_COMMAND_MASTER); + + /* Native Capable, but not enabled. */ + pci_write_config8(dev, 0x09, 0x8a); + + ideTimingConfig = pci_read_config16(dev, IDE_TIM_PRI); + ideTimingConfig &= ~IDE_DECODE_ENABLE; + ideTimingConfig |= IDE_SITRE; + if (enable_primary) { + /* Enable primary IDE interface. */ + ideTimingConfig |= IDE_DECODE_ENABLE; + ideTimingConfig |= (2 << 12); // ISP = 3 clocks + ideTimingConfig |= (3 << 8); // RCT = 1 clock + ideTimingConfig |= (1 << 1); // IE0 + ideTimingConfig |= (1 << 0); // TIME0 + printk_debug("IDE0 "); + } + pci_write_config16(dev, IDE_TIM_PRI, ideTimingConfig); + + ideTimingConfig = pci_read_config16(dev, IDE_TIM_SEC); + ideTimingConfig &= ~IDE_DECODE_ENABLE; + ideTimingConfig |= IDE_SITRE; + if (enable_secondary) { + /* Enable secondary IDE interface. */ + ideTimingConfig |= IDE_DECODE_ENABLE; + ideTimingConfig |= (2 << 12); // ISP = 3 clocks + ideTimingConfig |= (3 << 8); // RCT = 1 clock + ideTimingConfig |= (1 << 1); // IE0 + ideTimingConfig |= (1 << 0); // TIME0 + printk_debug("IDE1 "); + } + pci_write_config16(dev, IDE_TIM_SEC, ideTimingConfig); + + /* Set IDE I/O Configuration */ + if (enable_secondary) + reg32 = SIG_MODE_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0; + else + reg32 = SIG_MODE_NORMAL | FAST_PCB1 | PCB1; + pci_write_config32(dev, IDE_CONFIG, reg32); + + /* Set Interrupt Line */ + /* Interrupt Pin is set by D31IP.PIP */ + pci_write_config32(dev, INTR_LN, 0xff); /* Int 15 */ +} + +static struct device_operations ide_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = ide_init, + .scan_bus = 0, + .enable = i82801gx_enable, +}; + +/* 82801Gx */ +static const struct pci_driver i82801gx_ide __pci_driver = { + .ops = &ide_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x27df, +}; Added: trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_lpc.c =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_lpc.c (rev 0) +++ trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_lpc.c 2008-10-29 04:46:52 UTC (rev 3701) @@ -0,0 +1,361 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <pc80/mc146818rtc.h> +#include <pc80/isa-dma.h> +#include <arch/io.h> +#include "i82801gx.h" + +#include "../../../northbridge/intel/i945/ich7.h" + +#define MAINBOARD_POWER_OFF 0 +#define MAINBOARD_POWER_ON 1 + +#ifndef MAINBOARD_POWER_ON_AFTER_FAIL +#define MAINBOARD_POWER_ON_AFTER_FAIL MAINBOARD_POWER_ON +#endif + +#define NMI_OFF 0 + +/* PIRQ[n]_ROUT[3:0] - PIRQ Routing Control + * 0x00 - 0000 = Reserved + * 0x01 - 0001 = Reserved + * 0x02 - 0010 = Reserved + * 0x03 - 0011 = IRQ3 + * 0x04 - 0100 = IRQ4 + * 0x05 - 0101 = IRQ5 + * 0x06 - 0110 = IRQ6 + * 0x07 - 0111 = IRQ7 + * 0x08 - 1000 = Reserved + * 0x09 - 1001 = IRQ9 + * 0x0A - 1010 = IRQ10 + * 0x0B - 1011 = IRQ11 + * 0x0C - 1100 = IRQ12 + * 0x0D - 1101 = Reserved + * 0x0E - 1110 = IRQ14 + * 0x0F - 1111 = IRQ15 + * PIRQ[n]_ROUT[7] - PIRQ Routing Control + * 0x80 - The PIRQ is not routed. + */ + +#define PIRQA 0x03 +#define PIRQB 0x05 +#define PIRQC 0x06 +#define PIRQD 0x07 +#define PIRQE 0x09 +#define PIRQF 0x0A +#define PIRQG 0x0B +#define PIRQH 0x0C + +static void i82801gx_enable_apic(struct device *dev) +{ + int i; + u32 reg32; + volatile u32 *ioapic_index = (volatile u32 *)0xfec00000; + volatile u32 *ioapic_data = (volatile u32 *)0xfec00010; + + /* Enable ACPI I/O and power management. */ + pci_write_config8(dev, ACPI_CNTL, 0x80); + + *ioapic_index = 0; + *ioapic_data = (1 << 25); + + *ioapic_index = 0; + reg32 = *ioapic_data; + printk_debug("Southbridge APIC ID = %x\n", (reg32 >> 24) & 0x0f); + if (reg32 != (1 << 25)) + die("APIC Error\n"); + + printk_spew("Dumping IOAPIC registers\n"); + for (i=0; i<3; i++) { + *ioapic_index = i; + printk_spew(" reg 0x%04x:", i); + reg32 = *ioapic_data; + printk_spew(" 0x%08x\n", reg32); + } + + *ioapic_index = 3; /* Select Boot Configuration register. */ + *ioapic_data = 1; /* Use Processor System Bus to deliver interrupts. */ +} + +static void i82801gx_enable_serial_irqs(struct device *dev) +{ + /* Set packet length and toggle silent mode bit for one frame. */ + pci_write_config8(dev, SERIRQ_CNTL, + (1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0)); +} + +static void i82801gx_pirq_init(device_t dev) +{ + pci_write_config8(dev, PIRQA_ROUT, 0x85); + pci_write_config8(dev, PIRQB_ROUT, 0x87); + pci_write_config8(dev, PIRQC_ROUT, 0x86); + pci_write_config8(dev, PIRQD_ROUT, 0x87); + + pci_write_config8(dev, PIRQE_ROUT, 0x80); + pci_write_config8(dev, PIRQF_ROUT, 0x80); + pci_write_config8(dev, PIRQG_ROUT, 0x80); + pci_write_config8(dev, PIRQH_ROUT, 0x85); +} + +static void i82801gx_power_options(device_t dev) +{ + u8 reg8; + u16 reg16; + + int pwr_on=MAINBOARD_POWER_ON_AFTER_POWER_FAIL; + int nmi_option; + + /* Which state do we want to goto after g3 (power restored)? + * 0 == S0 Full On + * 1 == S5 Soft Off + */ + get_option(&pwr_on, "power_on_after_fail"); + reg8 = pci_read_config8(dev, GEN_PMCON_3); + reg8 &= 0xfe; + if (pwr_on) { + reg8 &= ~1; + } else { + reg8 |= 1; + } + reg8 |= (3 << 4); /* avoid #S4 assertions */ + + pci_write_config8(dev, GEN_PMCON_3, reg8); + printk_info("Set power %s after power failure.\n", pwr_on ? "on" : "off"); + + /* Set up NMI on errors. */ + reg8 = inb(0x61); + reg8 &= 0x0f; /* Higher Nibble must be 0 */ + reg8 &= ~(1 << 3); /* IOCHK# NMI Enable */ + // reg8 &= ~(1 << 2); /* PCI SERR# Enable */ + reg8 |= (1 << 2); /* PCI SERR# Disable for now */ + outb(reg8, 0x61); + + reg8 = inb(0x70); + nmi_option = NMI_OFF; + get_option(&nmi_option, "nmi"); + if (nmi_option) { + printk_info ("NMI sources enabled.\n"); + reg8 &= ~(1 << 7); /* Set NMI. */ + } else { + printk_info ("NMI sources disabled.\n"); + reg8 |= ( 1 << 7); /* Can't mask NMI from PCI-E and NMI_NOW */ + } + outb(reg8, 0x70); + + // Enable CPU_SLP# and Intel Speedstep, set SMI# rate down + reg16 = pci_read_config16(dev, GEN_PMCON_1); + reg16 &= ~3; + reg16 |= (1 << 3) | (1 << 5) | (1 << 10); + pci_write_config16(dev, GEN_PMCON_1, reg16); + + // Set GPIO13 to SCI (?) + // This might be board specific + pci_write_config32(dev, 0xb8, 0x08000000); +} + +void i82801gx_rtc_init(struct device *dev) +{ + u8 reg8; + u32 reg32; + int rtc_failed; + + reg8 = pci_read_config8(dev, GEN_PMCON_3); + rtc_failed = reg8 & RTC_BATTERY_DEAD; + if (rtc_failed) { + reg8 &= ~RTC_BATTERY_DEAD; + pci_write_config8(dev, GEN_PMCON_3, reg8); + } + printk_debug("rtc_failed = 0x%x\n", rtc_failed); + + rtc_init(rtc_failed); +} + +static void enable_hpet(struct device *dev) +{ + u32 reg32; + u32 code = (0 & 0x3); + + reg32 = pci_read_config32(dev, GEN_CNTL); + reg32 |= (1 << 17); /* Enable HPET. */ + /* + * Bits [16:15] Memory Address Range + * 00 FED0_0000h - FED0_03FFh + * 01 FED0_1000h - FED0_13FFh + * 10 FED0_2000h - FED0_23FFh + * 11 FED0_3000h - FED0_33FFh + */ + reg32 &= ~(3 << 15); /* Clear it */ + reg32 |= (code << 15); + /* TODO: reg32 is never written to anywhere? */ + printk_debug("Enabling HPET @0x%x\n", HPET_ADDR | (code << 12)); +} + +static void i82801gx_lock_smm(struct device *dev) +{ + void smm_lock(void); + u8 reg8; + +#if ENABLE_ACPI_MODE_IN_COREBOOT + printk_debug("Enabling ACPI via APMC:\n"); + outb(0xe1, 0xb2); // Enable ACPI mode + printk_debug("done.\n"); +#else + printk_debug("Disabling ACPI via APMC:\n"); + outb(0x1e, 0xb2); // Disable ACPI mode + printk_debug("done.\n"); +#endif + /* Don't allow evil boot loaders, kernels, or + * userspace applications to deceive us: + */ + smm_lock(); + +#if TEST_SMM_FLASH_LOCKDOWN + /* Now try this: */ + printk_debug("Locking BIOS to RO... "); + reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */ + printk_debug(" BLE: %s; BWE: %s\n", (reg8&2)?"on":"off", + (reg8&1)?"rw":"ro"); + reg8 &= ~(1 << 0); /* clear BIOSWE */ + pci_write_config8(dev, 0xdc, reg8); + reg8 |= (1 << 1); /* set BLE */ + pci_write_config8(dev, 0xdc, reg8); + printk_debug("ok.\n"); + reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */ + printk_debug(" BLE: %s; BWE: %s\n", (reg8&2)?"on":"off", + (reg8&1)?"rw":"ro"); + + printk_debug("Writing:\n"); + *(volatile u8 *)0xfff00000 = 0x00; + printk_debug("Testing:\n"); + reg8 |= (1 << 0); /* set BIOSWE */ + pci_write_config8(dev, 0xdc, reg8); + + reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */ + printk_debug(" BLE: %s; BWE: %s\n", (reg8&2)?"on":"off", + (reg8&1)?"rw":"ro"); + printk_debug("Done.\n"); +#endif +} + +static void lpc_init(struct device *dev) +{ + printk_debug("i82801gx: lpc_init\n"); + + /* Set the value for PCI command register. */ + pci_write_config16(dev, PCI_COMMAND, 0x000f); + + /* IO APIC initialization. */ + i82801gx_enable_apic(dev); + + i82801gx_enable_serial_irqs(dev); + + /* Setup the PIRQ. */ + i82801gx_pirq_init(dev); + + /* Setup power options. */ + i82801gx_power_options(dev); + + /* Set the state of the GPIO lines. */ + //gpio_init(dev); + + /* Initialize the real time clock. */ + i82801gx_rtc_init(dev); + + /* Initialize ISA DMA. */ + isa_dma_init(); + + /* Initialize the High Precision Event Timers, if present. */ + enable_hpet(dev); + + setup_i8259(); + + i82801gx_lock_smm(dev); +} + +static void i82801gx_lpc_read_resources(device_t dev) +{ + struct resource *res; + + /* Get the normal PCI resources of this device. */ + pci_dev_read_resources(dev); + + /* Add an extra subtractive resource for both memory and I/O. */ + res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); + res->flags = + IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; + + res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); + res->flags = + IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; +} + +static void i82801gx_lpc_enable_resources(device_t dev) +{ + pci_dev_enable_resources(dev); + enable_childrens_resources(dev); +} + +static void set_subsystem(device_t dev, unsigned vendor, unsigned device) +{ + printk_debug("Setting LPC bridge subsystem ID\n"); + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, + pci_read_config32(dev, 0)); +} + +static struct pci_operations pci_ops = { + .set_subsystem = set_subsystem, +}; + +static struct device_operations device_ops = { + .read_resources = i82801gx_lpc_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = i82801gx_lpc_enable_resources, + .init = lpc_init, + .scan_bus = scan_static_bus, + .enable = i82801gx_enable, + .ops_pci = &pci_ops, +}; + +/* ICH7 / ICH7R */ +static const struct pci_driver ich7_ich7r_lpc __pci_driver = { + .ops = &device_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x27b8, +}; + +/* ICH7M / ICH7U */ +static const struct pci_driver ich7m_ich7u_lpc __pci_driver = { + .ops = &device_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x27b9, +}; + +/* ICH7M DH */ +static const struct pci_driver ich7m_dh_lpc __pci_driver = { + .ops = &device_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x27bd, +}; + Added: trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_nic.c =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_nic.c (rev 0) +++ trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_nic.c 2008-10-29 04:46:52 UTC (rev 3701) @@ -0,0 +1,50 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* This code should work for all ICH* southbridges with a NIC. */ + +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> + +static void nic_init(struct device *dev) +{ + /* Nothing yet */ +} + +static struct device_operations nic_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = nic_init, + .scan_bus = 0, +}; + +/* 82801GB/GR/GDH/GBM/GHM (ICH7/ICH7R/ICH7DH/ICH7-M/ICH7-M DH) */ +/* Note: 82801GU (ICH7-U) doesn't have a NIC. */ +/* PCI ID loaded from EEPROM. If EEPROM is 0, 0x27dc is used */ +static const struct pci_driver i82801gb_nic __pci_driver = { + .ops = &nic_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82801GB_LAN, +}; + + Added: trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_nvs.h =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_nvs.h (rev 0) +++ trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_nvs.h 2008-10-29 04:46:52 UTC (rev 3701) @@ -0,0 +1,108 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +typedef struct { + u16 osys; + u8 smif; + u8 prm0; + u8 prm1; + u8 scif; + u8 prm2; + u8 prm3; + u8 lckf; + u8 prm4; + u8 prm5; + u32 p80d; + u8 lids; + u8 pwrs; + u8 dbgs; + u8 linxs; + u8 rsvd; + u8 actt; + u8 psvt; + u8 tc1v; + u8 tc2v; + u8 tspv; + u8 crtt; + u8 dtse; + u8 dts1; + u8 dts2; + u8 rsvd2; + u8 bnum; + u8 b0sc, b1sc, b2sc; + u8 b0ss, b1ss, b2ss; + u8 rsvd3[3]; + u8 apic; + u8 mpen; + u8 bten; + u8 ppcm; + u8 pcp0; + u8 pcp1; + u8 rsvd4[4]; + u8 natp; + u8 cmap; + u8 cmbp; + u8 lptp; + u8 fdcp; + u8 rfdv; + u8 hotk; + u8 rtcf; + u8 util; + u8 acin; + u8 igds; + u8 tlst; + u8 cadl; + u8 padl; + u16 cste; + u16 pste; + u16 nste; + u16 sste; + u8 ndid; + u32 did1; + u32 did2; + u32 did3; + u32 did4; + u32 did5; + u8 rsvd5[0xb]; + u8 brtl; + u8 odds; + u8 alse; + u8 alaf; + u8 llow; + u8 lhih; + u8 rsvd6; + u8 emae; + u16 emap; + u16 emal; + u8 rsvd7; + u8 mefe; + u8 igps; + u8 rsvd8[2]; + u8 tpmp; + u8 tpme; + u8 rsvd9[8]; + u8 gtf0[7]; + u8 gtf2[7]; + u8 idem; + u8 idet; + u8 dock; +} global_nvs_t; + Added: trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_pci.c =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_pci.c (rev 0) +++ trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_pci.c 2008-10-29 04:46:52 UTC (rev 3701) @@ -0,0 +1,141 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> + +static void pci_init(struct device *dev) +{ + u16 reg16; + +#if 0 + /* Commented out for now because it will break on some machines. */ + /* Set latency timer to 32. */ + pci_write_config16(dev, 0x1b, 0x20); +#endif + + /* disable parity error response */ + reg16 = pci_read_config16(dev, 0x3e); + reg16 &= ~(1 << 0); + pci_write_config16(dev, 0x3e, reg16); + + /* Clear errors in status registers */ + reg16 = pci_read_config16(dev, 0x06); + reg16 |= 0xf900; + pci_write_config16(dev, 0x06, reg16); + + reg16 = pci_read_config16(dev, 0x1e); + reg16 |= 0xf900; + pci_write_config16(dev, 0x1e, reg16); +} + +static void ich_pci_dev_enable_resources(struct device *dev) +{ + const struct pci_operations *ops; + uint16_t command; + + /* Set the subsystem vendor and device id for mainboard devices */ + ops = ops_pci(dev); + if (dev->on_mainboard && ops && ops->set_subsystem) { + printk_debug("%s subsystem <- %02x/%02x\n", + dev_path(dev), + MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID, + MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID); + ops->set_subsystem(dev, + MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID, + MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID); + } + +#if 0 + /* If we write to PCI_COMMAND, on some systems + * this will cause the ROM and APICs not being visible + * anymore. + */ + command = pci_read_config16(dev, PCI_COMMAND); + command |= dev->command; + printk_debug("%s cmd <- %02x\n", dev_path(dev), command); + pci_write_config16(dev, PCI_COMMAND, command); +#endif +} + +static void ich_pci_bus_enable_resources(struct device *dev) +{ + uint16_t ctrl; + /* enable IO in command register if there is VGA card + * connected with (even it does not claim IO resource) + */ + if (dev->link[0].bridge_ctrl & PCI_BRIDGE_CTL_VGA) + dev->command |= PCI_COMMAND_IO; + ctrl = pci_read_config16(dev, PCI_BRIDGE_CONTROL); + ctrl |= dev->link[0].bridge_ctrl; + ctrl |= (PCI_BRIDGE_CTL_PARITY + PCI_BRIDGE_CTL_SERR); /* error check */ + printk_debug("%s bridge ctrl <- %04x\n", dev_path(dev), ctrl); + pci_write_config16(dev, PCI_BRIDGE_CONTROL, ctrl); + + /* This is the reason we need our own pci_bus_enable_resources */ + ich_pci_dev_enable_resources(dev); + + enable_childrens_resources(dev); +} + +static void set_subsystem(device_t dev, unsigned vendor, unsigned device) +{ +#if 0 + /* Currently disabled because it causes a "BAR 9" memory resource + * conflict: + */ + u32 pci_id; + + printk_debug("Setting PCI bridge subsystem ID\n"); + pci_id = pci_read_config32(dev, 0); + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, pci_id ); +#endif +} + +static struct pci_operations pci_ops = { + .set_subsystem = set_subsystem, +}; + +static struct device_operations device_ops = { + .read_resources = pci_bus_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = ich_pci_bus_enable_resources, + .init = pci_init, + .scan_bus = pci_scan_bridge, + .ops_pci = &pci_ops, +}; + + +/* Desktop */ +static const struct pci_driver i82801g_pci __pci_driver = { + .ops = &device_ops, + .vendor = 0x8086, + .device = 0x244e, +}; + +/* Mobile / Ultra Mobile */ +static const struct pci_driver i82801gmu_pci __pci_driver = { + .ops = &device_ops, + .vendor = 0x8086, + .device = 0x2448, +}; + Added: trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_pcie.c =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_pcie.c (rev 0) +++ trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_pcie.c 2008-10-29 04:46:52 UTC (rev 3701) @@ -0,0 +1,126 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> + +static void pci_init(struct device *dev) +{ + u16 reg16; + u32 reg32; + + printk_debug("Initializing ICH7 PCIe bridge.\n"); +#if 0 + // When the latency of the PCIe(!) bridge is set to 0x20 + // all devices on the secondary bus of the PCI(!) bridge + // suddenly vanish. If you know why, please explain here. + + /* Set latency timer to 32. */ + pci_write_config16(dev, 0x1b, 0x20); +#endif + + /* disable parity error response */ + reg16 = pci_read_config16(dev, 0x3e); + reg16 &= ~(1 << 0); + pci_write_config16(dev, 0x3e, reg16); + + /* Clear errors in status registers */ + reg16 = pci_read_config16(dev, 0x06); + reg16 |= 0xf900; + pci_write_config16(dev, 0x06, reg16); + + reg16 = pci_read_config16(dev, 0x1e); + reg16 |= 0xf900; + pci_write_config16(dev, 0x1e, reg16); + + reg32 = pci_read_config32(dev, 0x20); + printk_debug(" MBL = 0x%08x\n", reg32); + reg32 = pci_read_config32(dev, 0x24); + printk_debug(" PMBL = 0x%08x\n", reg32); + reg32 = pci_read_config32(dev, 0x28); + printk_debug(" PMBU32 = 0x%08x\n", reg32); + reg32 = pci_read_config32(dev, 0x2c); + printk_debug(" PMLU32 = 0x%08x\n", reg32); +} + +static void set_subsystem(device_t dev, unsigned vendor, unsigned device) +{ + u32 pci_id; + + printk_debug("Setting PCIe bridge subsystem ID.\n"); + pci_id = pci_read_config32(dev, 0); + pci_write_config32(dev, 0x94, pci_id ); +} + +static struct pci_operations pci_ops = { + .set_subsystem = set_subsystem, +}; + +static struct device_operations device_ops = { + .read_resources = pci_bus_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_bus_enable_resources, + .init = pci_init, + .scan_bus = pci_scan_bridge, + .ops_pci = &pci_ops, +}; + +static const struct pci_driver i82801gx_pcie_port1 __pci_driver = { + .ops = &device_ops, + .vendor = 0x8086, + .device = 0x27d0, +}; + +static const struct pci_driver i82801gx_pcie_port2 __pci_driver = { + .ops = &device_ops, + .vendor = 0x8086, + .device = 0x27d2, +}; + +static const struct pci_driver i82801gx_pcie_port3 __pci_driver = { + .ops = &device_ops, + .vendor = 0x8086, + .device = 0x27d4, +}; + +static const struct pci_driver i82801gx_pcie_port4 __pci_driver = { + .ops = &device_ops, + .vendor = 0x8086, + .device = 0x27d6, +}; + +static const struct pci_driver i82801gx_pcie_port5 __pci_driver = { + .ops = &device_ops, + .vendor = 0x8086, + .device = 0x27e0, +}; + +static const struct pci_driver i82801gx_pcie_port6 __pci_driver = { + .ops = &device_ops, + .vendor = 0x8086, + .device = 0x27e2, +}; + + + + + Added: trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_reset.c =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_reset.c (rev 0) +++ trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_reset.c 2008-10-29 04:46:52 UTC (rev 3701) @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> + +void hard_reset(void) +{ + /* Try rebooting through port 0xcf9. */ + outb((1 << 2) | (1 << 1), 0xcf9); +} Added: trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_sata.c =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_sata.c (rev 0) +++ trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_sata.c 2008-10-29 04:46:52 UTC (rev 3701) @@ -0,0 +1,190 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include "i82801gx.h" + +typedef struct southbridge_intel_i82801gx_config config_t; + +static void sata_init(struct device *dev) +{ + u32 reg32; + /* Get the chip configuration */ + config_t *config = dev->chip_info; + + printk_debug("i82801gx_sata: initializing...\n"); + /* SATA configuration */ + + /* Enable BARs */ + pci_write_config16(dev, 0x04, 0x0007); + + if (config->ide_legacy_combined) { + pci_write_config8(dev, 0x09, 0x80); + + /* Set timings */ + pci_write_config16(dev, IDE_TIM_PRI, 0x8000); + pci_write_config16(dev, IDE_TIM_SEC, 0xa307); + + /* Sync DMA */ + pci_write_config16(dev, 0x48, 0x0004); + pci_write_config16(dev, 0x4a, 0x0200); + + /* Combine IDE - SATA configuration */ + pci_write_config8(dev, 0x90, 0x02); + + /* Port 0 & 1 enable */ + pci_write_config8(dev, 0x92, 0x0f); + + /* SATA Initialization register */ + pci_write_config32(dev, 0x94, 0x40000180); + } else if(config->sata_ahci) { + /* Allow both Legacy and Native mode */ + pci_write_config8(dev, 0x09, 0x8f); + + /* Set Interrupt Line */ + /* Interrupt Pin is set by D31IP.PIP */ + pci_write_config8(dev, INTR_LN, 0x0a); + + /* Set timings */ + pci_write_config16(dev, IDE_TIM_PRI, 0xa307); + pci_write_config16(dev, IDE_TIM_SEC, 0x8000); + + /* Sync DMA */ + pci_write_config16(dev, 0x48, 0x0001); + pci_write_config16(dev, 0x4a, 0x0001); + + /* Set IDE I/O Configuration */ + reg32 = SIG_MODE_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0; + pci_write_config32(dev, IDE_CONFIG, reg32); + + /* Set Sata Controller Mode. */ + pci_write_config8(dev, 0x90, 0xc0); // WTF - Reserved? + + /* Port 0 & 1 enable */ + pci_write_config8(dev, 0x92, 0x0f); + + /* SATA Initialization register */ + pci_write_config32(dev, 0x94, 0x1a000180); + } else { + /* Native mode capable on both primary and secondary (0xa) + * or'ed with enabled (0x50) = 0xf + */ + pci_write_config8(dev, 0x09, 0x8f); + + /* Set Interrupt Line */ + /* Interrupt Pin is set by D31IP.PIP */ + pci_write_config8(dev, INTR_LN, 0xff); + + /* Set timings */ + pci_write_config16(dev, IDE_TIM_PRI, 0xa307); + pci_write_config16(dev, IDE_TIM_SEC, 0xe303); + + /* Sync DMA */ + pci_write_config16(dev, 0x48, 0x0005); + pci_write_config16(dev, 0x4a, 0x0201); + + /* Set IDE I/O Configuration */ + reg32 = SIG_MODE_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0; + pci_write_config32(dev, IDE_CONFIG, reg32); + + /* Set Sata Controller Mode. */ + pci_write_config8(dev, 0x90, 0x02); + + /* Port 0 & 1 enable XXX */ + pci_write_config8(dev, 0x92, 0x15); + + /* SATA Initialization register */ + pci_write_config32(dev, 0x94, 0x1a000180); + } + + /* All configurations need this SATA initialization sequence */ + pci_write_config8(dev, 0xa0, 0x40); + pci_write_config8(dev, 0xa6, 0x22); + pci_write_config8(dev, 0xa0, 0x78); + pci_write_config8(dev, 0xa6, 0x22); + pci_write_config8(dev, 0xa0, 0x88); + reg32 = pci_read_config32(dev, 0xa4); + reg32 &= 0xc0c0c0c0; + reg32 |= 0x1b1b1212; + pci_write_config32(dev, 0xa4, reg32); + pci_write_config8(dev, 0xa0, 0x8c); + reg32 = pci_read_config32(dev, 0xa4); + reg32 &= 0xc0c0ff00; + reg32 |= 0x121200aa; + pci_write_config32(dev, 0xa4, reg32); + pci_write_config8(dev, 0xa0, 0x00); +} + +static struct device_operations sata_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = sata_init, + .scan_bus = 0, + .enable = i82801gx_enable, +}; + +/* Desktop Non-AHCI and Non-RAID Mode */ +static const struct pci_driver i82801gx_sata_normal_driver __pci_driver = { + .ops = &sata_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x27c0, +}; + +/* NOTE: Any of the below are not properly supported yet */ + +/* Desktop AHCI Mode */ +static const struct pci_driver i82801gx_sata_ahci_driver __pci_driver = { + .ops = &sata_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x27c1, +}; + +/* Desktop RAID mode */ +static const struct pci_driver i82801gx_sata_raid_driver __pci_driver = { + .ops = &sata_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x27c3, +}; + +/* Mobile Non-AHCI and Non-RAID Mode */ +static const struct pci_driver i82801gx_sata_mobile_normal_driver __pci_driver = { + .ops = &sata_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x27c4, +}; + +/* Mobile AHCI Mode */ +static const struct pci_driver i82801gx_sata_mobile_ahci_driver __pci_driver = { + .ops = &sata_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x27c5, +}; + +/* ICH7M DH Raid Mode */ +static const struct pci_driver i82801gx_sata_ich7dh_raid_driver __pci_driver = { + .ops = &sata_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x27c6, +}; + Added: trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_smbus.c =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_smbus.c (rev 0) +++ trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_smbus.c 2008-10-29 04:46:52 UTC (rev 3701) @@ -0,0 +1,59 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include <smbus.h> +#include <pci.h> +#include <arch/io.h> +#include "i82801gx.h" +#include "i82801_smbus.h" + +static int smbus_read_byte(struct bus *bus, device_t dev, u8 address) +{ + u16 device; + struct resource *res; + + device = dev->path.u.i2c.device; + res = find_resource(bus->dev, 0x20); + + return do_smbus_read_byte(res->base, device, address); +} + +static struct smbus_bus_operations lops_smbus_bus = { + .read_byte = smbus_read_byte, +}; + +static struct device_operations smbus_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = 0, + .scan_bus = scan_static_bus, + .enable = i82801gx_enable, + .ops_smbus_bus = &lops_smbus_bus, +}; + +/* 82801GB/GR/GDH/GBM/GHM/GU (ICH7/ICH7R/ICH7DH/ICH7-M/ICH7-M DH/ICH7-U) */ +static const struct pci_driver i82801gx_smbus __pci_driver = { + .ops = &smbus_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82801GB_SMB, +}; + Added: trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_smbus.h =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_smbus.h (rev 0) +++ trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_smbus.h 2008-10-29 04:46:52 UTC (rev 3701) @@ -0,0 +1,187 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2005 Yinghai Lu <yinghailu(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <device/smbus_def.h> + +static void smbus_delay(void) +{ + inb(0x80); +} + +static int smbus_wait_until_ready(void) +{ + unsigned loops = SMBUS_TIMEOUT; + unsigned char byte; + do { + smbus_delay(); + if (--loops == 0) + break; + byte = inb(SMBUS_IO_BASE + SMBHSTSTAT); + } while (byte & 1); + return loops ? 0 : -1; +} + +static int smbus_wait_until_done(void) +{ + unsigned loops = SMBUS_TIMEOUT; + unsigned char byte; + do { + smbus_delay(); + if (--loops == 0) + break; + byte = inb(SMBUS_IO_BASE + SMBHSTSTAT); + } while ((byte & 1) || (byte & ~((1 << 6) | (1 << 0))) == 0); + return loops ? 0 : -1; +} + +static int smbus_wait_until_blk_done(void) +{ + unsigned loops = SMBUS_TIMEOUT; + unsigned char byte; + do { + smbus_delay(); + if (--loops == 0) + break; + byte = inb(SMBUS_IO_BASE + SMBHSTSTAT); + } while ((byte & (1 << 7)) == 0); + return loops ? 0 : -1; +} + +static int do_smbus_read_byte(unsigned device, unsigned address) +{ + unsigned char global_status_register; + unsigned char byte; + + if (smbus_wait_until_ready() < 0) { + return SMBUS_WAIT_UNTIL_READY_TIMEOUT; + } + /* Setup transaction */ + /* Disable interrupts */ + outb(inb(SMBUS_IO_BASE + SMBHSTCTL) & (~1), SMBUS_IO_BASE + SMBHSTCTL); + /* Set the device I'm talking too */ + outb(((device & 0x7f) << 1) | 1, SMBUS_IO_BASE + SMBXMITADD); + /* Set the command/address... */ + outb(address & 0xff, SMBUS_IO_BASE + SMBHSTCMD); + /* Set up for a byte data read */ + outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xe3) | (0x2 << 2), + (SMBUS_IO_BASE + SMBHSTCTL)); + /* Clear any lingering errors, so the transaction will run */ + outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); + + /* Clear the data byte... */ + outb(0, SMBUS_IO_BASE + SMBHSTDAT0); + + /* Start the command */ + outb((inb(SMBUS_IO_BASE + SMBHSTCTL) | 0x40), + SMBUS_IO_BASE + SMBHSTCTL); + + /* Poll for transaction completion */ + if (smbus_wait_until_done() < 0) { + return SMBUS_WAIT_UNTIL_DONE_TIMEOUT; + } + + global_status_register = inb(SMBUS_IO_BASE + SMBHSTSTAT); + + /* Ignore the "In Use" status... */ + global_status_register &= ~(3 << 5); + + /* Read results of transaction */ + byte = inb(SMBUS_IO_BASE + SMBHSTDAT0); + if (global_status_register != (1 << 1)) { + return SMBUS_ERROR; + } + return byte; +} + +/* This function is neither used nor tested by me (Corey Osgood), the author +(Yinghai) probably tested/used it on i82801er */ +static int do_smbus_write_block(unsigned device, unsigned length, unsigned cmd, + unsigned data1, unsigned data2) +{ + unsigned char byte; + unsigned char stat; + int i; + +#if CONFIG_USE_PRINTK_IN_CAR + printk_err("Untested smbus_write_block called\r\n"); +#else + print_err("Untested smbus_write_block called\r\n"); +#endif + + /* Clear the PM timeout flags, SECOND_TO_STS */ + outw(inw(0x0400 + 0x66), 0x0400 + 0x66); + + if (smbus_wait_until_ready() < 0) { + return -2; + } + + /* Setup transaction */ + /* Obtain ownership */ + outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); + for (stat = 0; (stat & 0x40) == 0;) { + stat = inb(SMBUS_IO_BASE + SMBHSTSTAT); + } + /* Clear the done bit */ + outb(0x80, SMBUS_IO_BASE + SMBHSTSTAT); + /* Disable interrupts */ + outb(inb(SMBUS_IO_BASE + SMBHSTCTL) & (~1), SMBUS_IO_BASE + SMBHSTCTL); + + /* Set the device I'm talking too */ + outb(((device & 0x7f) << 1), SMBUS_IO_BASE + SMBXMITADD); + + /* Set the command address */ + outb(cmd & 0xff, SMBUS_IO_BASE + SMBHSTCMD); + + /* Set the block length */ + outb(length & 0xff, SMBUS_IO_BASE + SMBHSTDAT0); + + /* Try sending out the first byte of data here */ + byte = (data1 >> (0)) & 0x0ff; + outb(byte, SMBUS_IO_BASE + SMBBLKDAT); + /* Issue a block write command */ + outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xe3) | (0x5 << 2) | 0x40, + SMBUS_IO_BASE + SMBHSTCTL); + + for (i = 0; i < length; i++) { + + /* Poll for transaction completion */ + if (smbus_wait_until_blk_done() < 0) { + return -3; + } + + /* Load the next byte */ + if (i > 3) + byte = (data2 >> (i % 4)) & 0x0ff; + else + byte = (data1 >> (i)) & 0x0ff; + outb(byte, SMBUS_IO_BASE + SMBBLKDAT); + + /* Clear the done bit */ + outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), + SMBUS_IO_BASE + SMBHSTSTAT); + } + +#if CONFIG_USE_PRINTK_IN_CAR + printk_debug("SMBUS Block complete\r\n"); +#else + print_debug("SMBUS Block complete\r\n"); +#endif + return 0; +} Added: trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_smi.c =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_smi.c (rev 0) +++ trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_smi.c 2008-10-29 04:46:52 UTC (rev 3701) @@ -0,0 +1,335 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + + +#include <device/device.h> +#include <device/pci.h> +#include <console/console.h> +#include <arch/io.h> +#include <cpu/x86/cache.h> +#include <cpu/x86/smm.h> +#include <string.h> +#include "chip.h" + +// Future TODO: Move to i82801gx directory +#include "../../../northbridge/intel/i945/ich7.h" + +extern unsigned char smm[]; +extern unsigned int smm_len; + +/* I945 */ +#define SMRAM 0x9d +#define D_OPEN (1 << 6) +#define D_CLS (1 << 5) +#define D_LCK (1 << 4) +#define G_SMRAME (1 << 3) +#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0)) + +/* ICH7 */ +#define PM1_STS 0x00 +#define PM1_EN 0x02 +#define PM1_CNT 0x04 +#define PM1_TMR 0x08 +#define PROC_CNT 0x10 +#define LV2 0x14 +#define LV3 0x15 +#define LV4 0x16 +#define PM2_CNT 0x20 // mobile only +#define GPE0_STS 0x28 +#define GPE0_EN 0x2c +#define SMI_EN 0x30 +#define EL_SMI_EN (1 << 25) // Intel Quick Resume Technology +#define INTEL_USB2_EN (1 << 18) // Intel-Specific USB2 SMI logic +#define LEGACY_USB2_EN (1 << 17) // Legacy USB2 SMI logic +#define PERIODIC_EN (1 << 14) // SMI on PERIODIC_STS in SMI_STS +#define TCO_EN (1 << 13) // Enable TCO Logic (BIOSWE et al) +#define MCSMI_EN (1 << 11) // Trap microcontroller range access +#define BIOS_RLS (1 << 7) // asserts SCI on bit set +#define SWSMI_TMR_EN (1 << 6) // start software smi timer on bit set +#define APMC_EN (1 << 5) // Writes to APM_CNT cause SMI# +#define SLP_SMI_EN (1 << 4) // Write to SLP_EN in PM1_CNT asserts SMI# +#define LEGACY_USB_EN (1 << 3) // Legacy USB circuit SMI logic +#define BIOS_EN (1 << 2) // Assert SMI# on setting GBL_RLS bit +#define EOS (1 << 1) // End of SMI (deassert SMI#) +#define GBL_SMI_EN (1 << 0) // SMI# generation at all? +#define SMI_STS 0x34 +#define ALT_GP_SMI_EN 0x38 +#define ALT_GP_SMI_STS 0x3a +#define GPE_CNTL 0x42 +#define DEVACT_STS 0x44 +#define SS_CNT 0x50 +#define C3_RES 0x54 + +/* While we read PMBASE dynamically in case it changed, let's + * initialize it with a sane value + */ +static u16 pmbase = DEFAULT_PMBASE; + +/** + * @brief read and clear PM1_STS + * @return PM1_STS register + */ +static u16 reset_pm1_status(void) +{ + u16 reg16; + + reg16 = inw(pmbase + PM1_STS); + /* set status bits are cleared by writing 1 to them */ + outw(reg16, pmbase + PM1_STS); + + return reg16; +} + +static void dump_pm1_status(u16 pm1_sts) +{ + printk_debug("PM1_STS: "); + if (pm1_sts & (1 << 15)) printk_debug("WAK "); + if (pm1_sts & (1 << 14)) printk_debug("PCIEXPWAK "); + if (pm1_sts & (1 << 11)) printk_debug("PRBTNOR "); + if (pm1_sts & (1 << 10)) printk_debug("RTC "); + if (pm1_sts & (1 << 8)) printk_debug("PWRBTN "); + if (pm1_sts & (1 << 5)) printk_debug("GBL "); + if (pm1_sts & (1 << 4)) printk_debug("BM "); + if (pm1_sts & (1 << 0)) printk_debug("TMROF "); + printk_debug("\n"); +} + +/** + * @brief read and clear SMI_STS + * @return SMI_STS register + */ +static u32 reset_smi_status(void) +{ + u32 reg32; + + reg32 = inl(pmbase + SMI_STS); + /* set status bits are cleared by writing 1 to them */ + outl(reg32, pmbase + SMI_STS); + + return reg32; +} + +static void dump_smi_status(u32 smi_sts) +{ + printk_debug("SMI_STS: "); + if (smi_sts & (1 << 26)) printk_debug("SPI "); + if (smi_sts & (1 << 25)) printk_debug("EL_SMI "); + if (smi_sts & (1 << 21)) printk_debug("MONITOR "); + if (smi_sts & (1 << 20)) printk_debug("PCI_EXP_SMI "); + if (smi_sts & (1 << 18)) printk_debug("INTEL_USB2 "); + if (smi_sts & (1 << 17)) printk_debug("LEGACY_USB2 "); + if (smi_sts & (1 << 16)) printk_debug("SMBUS_SMI "); + if (smi_sts & (1 << 15)) printk_debug("SERIRQ_SMI "); + if (smi_sts & (1 << 14)) printk_debug("PERIODIC "); + if (smi_sts & (1 << 13)) printk_debug("TCO "); + if (smi_sts & (1 << 12)) printk_debug("DEVMON "); + if (smi_sts & (1 << 11)) printk_debug("MCSMI "); + if (smi_sts & (1 << 10)) printk_debug("GPI "); + if (smi_sts & (1 << 9)) printk_debug("GPE0 "); + if (smi_sts & (1 << 8)) printk_debug("PM1 "); + if (smi_sts & (1 << 6)) printk_debug("SWSMI_TMR "); + if (smi_sts & (1 << 5)) printk_debug("APM "); + if (smi_sts & (1 << 4)) printk_debug("SLP_SMI "); + if (smi_sts & (1 << 3)) printk_debug("LEGACY_USB "); + if (smi_sts & (1 << 2)) printk_debug("BIOS "); + printk_debug("\n"); +} + + +/** + * @brief read and clear GPE0_STS + * @return GPE0_STS register + */ +static u32 reset_gpe0_status(void) +{ + u32 reg32; + + reg32 = inl(pmbase + GPE0_STS); + /* set status bits are cleared by writing 1 to them */ + outl(reg32, pmbase + GPE0_STS); + + return reg32; +} + +static void dump_gpe0_status(u32 gpe0_sts) +{ + int i; + printk_debug("GPE0_STS: "); + for (i=31; i<= 16; i--) { + if (gpe0_sts & (1 << i)) printk_debug("GPIO%d ", (i-16)); + } + if (gpe0_sts & (1 << 14)) printk_debug("USB4 "); + if (gpe0_sts & (1 << 13)) printk_debug("PME_B0 "); + if (gpe0_sts & (1 << 12)) printk_debug("USB3 "); + if (gpe0_sts & (1 << 11)) printk_debug("PME "); + if (gpe0_sts & (1 << 10)) printk_debug("EL_SCI/BATLOW "); + if (gpe0_sts & (1 << 9)) printk_debug("PCI_EXP "); + if (gpe0_sts & (1 << 8)) printk_debug("RI "); + if (gpe0_sts & (1 << 7)) printk_debug("SMB_WAK "); + if (gpe0_sts & (1 << 6)) printk_debug("TCO_SCI "); + if (gpe0_sts & (1 << 5)) printk_debug("AC97 "); + if (gpe0_sts & (1 << 4)) printk_debug("USB2 "); + if (gpe0_sts & (1 << 3)) printk_debug("USB1 "); + if (gpe0_sts & (1 << 2)) printk_debug("HOT_PLUG "); + if (gpe0_sts & (1 << 0)) printk_debug("THRM "); + printk_debug("\n"); +} + +/** + * @brief read and clear TCOx_STS + * @return TCOx_STS registers + */ +static u32 reset_tco_status(void) +{ + u32 tcobase = pmbase + 0x60; + u32 reg32; + + reg32 = inl(tcobase + 0x04); + /* set status bits are cleared by writing 1 to them */ + outl(reg32 & ~(1<<18), tcobase + 0x04); // Don't clear BOOT_STS before SECOND_TO_STS + if (reg32 & (1 << 18)) + outl(reg32 & (1<<18), tcobase + 0x04); // clear BOOT_STS + + return reg32; +} + + +static void dump_tco_status(u32 tco_sts) +{ + printk_debug("TCO_STS: "); + if (tco_sts & (1 << 20)) printk_debug("SMLINK_SLV "); + if (tco_sts & (1 << 18)) printk_debug("BOOT "); + if (tco_sts & (1 << 17)) printk_debug("SECOND_TO "); + if (tco_sts & (1 << 16)) printk_debug("INTRD_DET "); + if (tco_sts & (1 << 12)) printk_debug("DMISERR "); + if (tco_sts & (1 << 10)) printk_debug("DMISMI "); + if (tco_sts & (1 << 9)) printk_debug("DMISCI "); + if (tco_sts & (1 << 8)) printk_debug("BIOSWR "); + if (tco_sts & (1 << 7)) printk_debug("NEWCENTURY "); + if (tco_sts & (1 << 3)) printk_debug("TIMEOUT "); + if (tco_sts & (1 << 2)) printk_debug("TCO_INT "); + if (tco_sts & (1 << 1)) printk_debug("SW_TCO "); + if (tco_sts & (1 << 0)) printk_debug("NMI2SMI "); + printk_debug("\n"); +} + + + +/** + * @brief Set the EOS bit + */ +static void smi_set_eos(void) +{ + u8 reg8; + + reg8 = inb(pmbase + SMI_EN); + reg8 |= EOS; + outb(reg8, pmbase + SMI_EN); +} + +extern uint8_t smm_relocation_start, smm_relocation_end; + +void smm_relocate(void) +{ + u32 smi_en; + + printk_debug("Initializing SMM handler..."); + + pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f, 0)), 0x40) & 0xfffc; + printk_spew(" ... pmbase = 0x%04x\n", pmbase); + + smi_en = inl(pmbase + SMI_EN); + if (smi_en & APMC_EN) { + printk_info("SMI# handler already enabled?\n"); + return; + } + + /* copy the SMM relocation code */ + memcpy((void *)0x38000, &smm_relocation_start, + &smm_relocation_end - &smm_relocation_start); + + printk_debug("\n"); + dump_smi_status(reset_smi_status()); + dump_pm1_status(reset_pm1_status()); + dump_gpe0_status(reset_gpe0_status()); + dump_tco_status(reset_tco_status()); + + /* Enable SMI generation: + * - on TCO events + * - on APMC writes (io 0xb2) + * - on writes to SLP_EN (sleep states) + * - on writes to GBL_RLS (bios commands) + * No SMIs: + * - on microcontroller writes (io 0x62/0x66) + */ + outl(smi_en | (TCO_EN | APMC_EN | SLP_SMI_EN | BIOS_EN | + EOS | GBL_SMI_EN), pmbase + SMI_EN); + + /** + * There are several methods of raising a controlled SMI# via + * software, among them: + * - Writes to io 0xb2 (APMC) + * - Writes to the Local Apic ICR with Delivery mode SMI. + * + * Using the local apic is a bit more tricky. According to + * AMD Family 11 Processor BKDG no destination shorthand must be + * used. + * The whole SMM initialization is quite a bit hardware specific, so + * I'm not too worried about the better of the methods at the moment + */ + + /* raise an SMI interrupt */ + printk_spew(" ... raise SMI#\n"); + outb(0x00, 0xb2); +} + +void smm_install(void) +{ + /* enable the SMM memory window */ + pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), SMRAM, + D_OPEN | G_SMRAME | C_BASE_SEG); + + /* copy the real SMM handler */ + memcpy((void *)0xa0000, smm, smm_len); + wbinvd(); + + /* close the SMM memory window and enable normal SMM */ + pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), SMRAM, + G_SMRAME | C_BASE_SEG); +} + +void smm_init(void) +{ + smm_relocate(); + smm_install(); +} + +void smm_lock(void) +{ + /* LOCK the SMM memory window and enable normal SMM. + * After running this function, only a full reset can + * make the SMM registers writable again. + */ + printk_debug("Locking SMM.\n"); + pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), SMRAM, + D_LCK | G_SMRAME | C_BASE_SEG); +} + Added: trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_usb.c =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_usb.c (rev 0) +++ trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_usb.c 2008-10-29 04:46:52 UTC (rev 3701) @@ -0,0 +1,79 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include "i82801gx.h" + +static void usb_init(struct device *dev) +{ + u32 reg32; + u8 reg8; + + /* USB Specification says the device must be Bus Master */ + printk_debug("UHCI: Setting up controller.. "); + + reg32 = pci_read_config32(dev, PCI_COMMAND); + pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER); + + reg8 = pci_read_config8(dev, 0xca); + reg8 |= (1 << 0); + pci_write_config8(dev, 0xca, reg8); + + printk_debug("done.\n"); +} + +static struct device_operations usb_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = usb_init, + .scan_bus = 0, + .enable = i82801gx_enable, +}; + +/* 82801GB/GR/GDH/GBM/GHM/GU (ICH7/ICH7R/ICH7DH/ICH7-M/ICH7-M DH/ICH7-U) */ +static const struct pci_driver i82801gb_usb1 __pci_driver = { + .ops = &usb_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82801GB_USB1, +}; + +static const struct pci_driver i82801gb_usb2 __pci_driver = { + .ops = &usb_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82801GB_USB2, +}; + +static const struct pci_driver i82801gb_usb3 __pci_driver = { + .ops = &usb_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82801GB_USB3, +}; + +static const struct pci_driver i82801gb_usb4 __pci_driver = { + .ops = &usb_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82801GB_USB4, +}; + + Added: trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_usb_ehci.c =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_usb_ehci.c (rev 0) +++ trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_usb_ehci.c 2008-10-29 04:46:52 UTC (rev 3701) @@ -0,0 +1,84 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include "i82801gx.h" + +static void usb_ehci_init(struct device *dev) +{ + u32 reg32; + + printk_debug("EHCI: Setting up controller.. "); + reg32 = pci_read_config32(dev, PCI_COMMAND); + pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER); + + reg32 = pci_read_config32(dev, 0xdc); + reg32 |= (1 << 31) | (1 << 27); + pci_write_config32(dev, 0xdc, reg32); + + reg32 = pci_read_config32(dev, 0xfc); + reg32 &= ~(3 << 2); + reg32 |= (2 << 2) | (1 << 29) | (1 << 17); + pci_write_config32(dev, 0xfc, reg32); + + printk_debug("done.\n"); +} + +static void usb_ehci_set_subsystem(device_t dev, unsigned vendor, + unsigned device) +{ + u8 access_cntl; + + access_cntl = pci_read_config8(dev, 0x80); + + /* Enable writes to protected registers. */ + pci_write_config8(dev, 0x80, access_cntl | 1); + + /* Write the subsystem vendor and device ID. */ + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, + ((device & 0xffff) << 16) | (vendor & 0xffff)); + + /* Restore protection. */ + pci_write_config8(dev, 0x80, access_cntl); +} + +static struct pci_operations lops_pci = { + .set_subsystem = &usb_ehci_set_subsystem, +}; + +static struct device_operations usb_ehci_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = usb_ehci_init, + .scan_bus = 0, + .enable = i82801gx_enable, + .ops_pci = &lops_pci, +}; + +/* 82801Gx */ +static const struct pci_driver i82801ex_usb_ehci __pci_driver = { + .ops = &usb_ehci_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x27cc, +}; Added: trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_watchdog.c =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_watchdog.c (rev 0) +++ trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_watchdog.c 2008-10-29 04:46:52 UTC (rev 3701) @@ -0,0 +1,52 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <arch/io.h> +#include <device/device.h> +#include <device/pci.h> + +void watchdog_off(void) +{ + device_t dev; + unsigned long value, base; + + /* Turn off the ICH7 watchdog. */ + dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0)); + + /* Enable I/O space. */ + value = pci_read_config16(dev, 0x04); + value |= (1 << 10); + pci_write_config16(dev, 0x04, value); + + /* Get TCO base. */ + base = (pci_read_config32(dev, 0x40) & 0x0fffe) + 0x60; + + /* Disable the watchdog timer. */ + value = inw(base + 0x08); + value |= 1 << 11; + outw(value, base + 0x08); + + /* Clear TCO timeout status. */ + outw(0x0008, base + 0x04); + outw(0x0002, base + 0x06); + + printk_debug("ICH7 watchdog disabled\r\n"); +} Added: trunk/coreboot-v2/src/southbridge/intel/i82801gx/smihandler.c =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/i82801gx/smihandler.c (rev 0) +++ trunk/coreboot-v2/src/southbridge/intel/i82801gx/smihandler.c 2008-10-29 04:46:52 UTC (rev 3701) @@ -0,0 +1,551 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <arch/romcc_io.h> +#include <console/console.h> +#include <cpu/x86/cache.h> +#include <cpu/x86/smm.h> +#include "chip.h" + +// Future TODO: Move to i82801gx directory +#include "../../../northbridge/intel/i945/ich7.h" + +#define DEBUG_SMI + +#define ACPI_DISABLE 0x1e +#define ACPI_ENABLE 0xe1 + +/* I945 */ +#define SMRAM 0x9d +#define D_OPEN (1 << 6) +#define D_CLS (1 << 5) +#define D_LCK (1 << 4) +#define G_SMRANE (1 << 3) +#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0)) + +/* ICH7 */ +#define PM1_STS 0x00 +#define PM1_EN 0x02 +#define PM1_CNT 0x04 +#define PM1_TMR 0x08 +#define PROC_CNT 0x10 +#define LV2 0x14 +#define LV3 0x15 +#define LV4 0x16 +#define PM2_CNT 0x20 // mobile only +#define GPE0_STS 0x28 +#define GPE0_EN 0x2c +#define SMI_EN 0x30 +#define EL_SMI_EN (1 << 25) // Intel Quick Resume Technology +#define INTEL_USB2_EN (1 << 18) // Intel-Specific USB2 SMI logic +#define LEGACY_USB2_EN (1 << 17) // Legacy USB2 SMI logic +#define PERIODIC_EN (1 << 14) // SMI on PERIODIC_STS in SMI_STS +#define TCO_EN (1 << 13) // Enable TCO Logic (BIOSWE et al) +#define MCSMI_EN (1 << 11) // Trap microcontroller range access +#define BIOS_RLS (1 << 7) // asserts SCI on bit set +#define SWSMI_TMR_EN (1 << 6) // start software smi timer on bit set +#define APMC_EN (1 << 5) // Writes to APM_CNT cause SMI# +#define SLP_SMI_EN (1 << 4) // Write to SLP_EN in PM1_CNT asserts SMI# +#define LEGACY_USB_EN (1 << 3) // Legacy USB circuit SMI logic +#define BIOS_EN (1 << 2) // Assert SMI# on setting GBL_RLS bit +#define EOS (1 << 1) // End of SMI (deassert SMI#) +#define GBL_SMI_EN (1 << 0) // SMI# generation at all? +#define SMI_STS 0x34 +#define ALT_GP_SMI_EN 0x38 +#define ALT_GP_SMI_STS 0x3a +#define GPE_CNTL 0x42 +#define DEVACT_STS 0x44 +#define SS_CNT 0x50 +#define C3_RES 0x54 + +#include "i82801gx_nvs.h" + +/* While we read PMBASE dynamically in case it changed, let's + * initialize it with a sane value + */ +static u16 pmbase = DEFAULT_PMBASE; + +typedef enum { SMI_LOCKED, SMI_UNLOCKED } smi_semaphore; + +/* SMI multiprocessing semaphore */ +static volatile smi_semaphore smi_handler_status = SMI_UNLOCKED; + +static int smi_obtain_lock(void) +{ + u8 ret = SMI_LOCKED; + + asm volatile ( + "movb %2, %%al\n" + "xchgb %%al, %1\n" + "movb %%al, %0\n" + : "=g" (ret), "=m" (smi_handler_status) + : "g" (SMI_LOCKED) + : "eax" + ); + + return (ret == SMI_UNLOCKED); +} + +static void smi_release_lock(void) +{ + asm volatile ( + "movb %1, %%al\n" + "xchgb %%al, %0\n" + : "=m" (smi_handler_status) + : "g" (SMI_UNLOCKED) + : "eax" + ); +} + +#define LAPIC_ID 0xfee00020 +static inline __attribute__((always_inline)) unsigned long nodeid(void) +{ + return (*((volatile unsigned long *)(LAPIC_ID)) >> 24); +} + + +/** + * @brief read and clear PM1_STS + * @return PM1_STS register + */ +static u16 reset_pm1_status(void) +{ + u16 reg16; + + reg16 = inw(pmbase + PM1_STS); + /* set status bits are cleared by writing 1 to them */ + outw(reg16, pmbase + PM1_STS); + + return reg16; +} + +static void dump_pm1_status(u16 pm1_sts) +{ + printk_debug("PM1_STS: "); + if (pm1_sts & (1 << 15)) printk_debug("WAK "); + if (pm1_sts & (1 << 14)) printk_debug("PCIEXPWAK "); + if (pm1_sts & (1 << 11)) printk_debug("PRBTNOR "); + if (pm1_sts & (1 << 10)) printk_debug("RTC "); + if (pm1_sts & (1 << 8)) printk_debug("PWRBTN "); + if (pm1_sts & (1 << 5)) printk_debug("GBL "); + if (pm1_sts & (1 << 4)) printk_debug("BM "); + if (pm1_sts & (1 << 0)) printk_debug("TMROF "); + printk_debug("\n"); +} + +/** + * @brief read and clear SMI_STS + * @return SMI_STS register + */ +static u32 reset_smi_status(void) +{ + u32 reg32; + + reg32 = inl(pmbase + SMI_STS); + /* set status bits are cleared by writing 1 to them */ + outl(reg32, pmbase + SMI_STS); + + return reg32; +} + +static void dump_smi_status(u32 smi_sts) +{ + printk_debug("SMI_STS: "); + if (smi_sts & (1 << 26)) printk_debug("SPI "); + if (smi_sts & (1 << 25)) printk_debug("EL_SMI "); + if (smi_sts & (1 << 21)) printk_debug("MONITOR "); + if (smi_sts & (1 << 20)) printk_debug("PCI_EXP_SMI "); + if (smi_sts & (1 << 18)) printk_debug("INTEL_USB2 "); + if (smi_sts & (1 << 17)) printk_debug("LEGACY_USB2 "); + if (smi_sts & (1 << 16)) printk_debug("SMBUS_SMI "); + if (smi_sts & (1 << 15)) printk_debug("SERIRQ_SMI "); + if (smi_sts & (1 << 14)) printk_debug("PERIODIC "); + if (smi_sts & (1 << 13)) printk_debug("TCO "); + if (smi_sts & (1 << 12)) printk_debug("DEVMON "); + if (smi_sts & (1 << 11)) printk_debug("MCSMI "); + if (smi_sts & (1 << 10)) printk_debug("GPI "); + if (smi_sts & (1 << 9)) printk_debug("GPE0 "); + if (smi_sts & (1 << 8)) printk_debug("PM1 "); + if (smi_sts & (1 << 6)) printk_debug("SWSMI_TMR "); + if (smi_sts & (1 << 5)) printk_debug("APM "); + if (smi_sts & (1 << 4)) printk_debug("SLP_SMI "); + if (smi_sts & (1 << 3)) printk_debug("LEGACY_USB "); + if (smi_sts & (1 << 2)) printk_debug("BIOS "); + printk_debug("\n"); +} + + +/** + * @brief read and clear GPE0_STS + * @return GPE0_STS register + */ +static u32 reset_gpe0_status(void) +{ + u32 reg32; + + reg32 = inl(pmbase + GPE0_STS); + /* set status bits are cleared by writing 1 to them */ + outl(reg32, pmbase + GPE0_STS); + + return reg32; +} + +static void dump_gpe0_status(u32 gpe0_sts) +{ + int i; + printk_debug("GPE0_STS: "); + for (i=31; i<= 16; i--) { + if (gpe0_sts & (1 << i)) printk_debug("GPIO%d ", (i-16)); + } + if (gpe0_sts & (1 << 14)) printk_debug("USB4 "); + if (gpe0_sts & (1 << 13)) printk_debug("PME_B0 "); + if (gpe0_sts & (1 << 12)) printk_debug("USB3 "); + if (gpe0_sts & (1 << 11)) printk_debug("PME "); + if (gpe0_sts & (1 << 10)) printk_debug("EL_SCI/BATLOW "); + if (gpe0_sts & (1 << 9)) printk_debug("PCI_EXP "); + if (gpe0_sts & (1 << 8)) printk_debug("RI "); + if (gpe0_sts & (1 << 7)) printk_debug("SMB_WAK "); + if (gpe0_sts & (1 << 6)) printk_debug("TCO_SCI "); + if (gpe0_sts & (1 << 5)) printk_debug("AC97 "); + if (gpe0_sts & (1 << 4)) printk_debug("USB2 "); + if (gpe0_sts & (1 << 3)) printk_debug("USB1 "); + if (gpe0_sts & (1 << 2)) printk_debug("HOT_PLUG "); + if (gpe0_sts & (1 << 0)) printk_debug("THRM "); + printk_debug("\n"); +} + + +/** + * @brief read and clear TCOx_STS + * @return TCOx_STS registers + */ +static u32 reset_tco_status(void) +{ + u32 tcobase = pmbase + 0x60; + u32 reg32; + + reg32 = inl(tcobase + 0x04); + /* set status bits are cleared by writing 1 to them */ + outl(reg32 & ~(1<<18), tcobase + 0x04); // Don't clear BOOT_STS before SECOND_TO_STS + if (reg32 & (1 << 18)) + outl(reg32 & (1<<18), tcobase + 0x04); // clear BOOT_STS + + return reg32; +} + + +static void dump_tco_status(u32 tco_sts) +{ + printk_debug("TCO_STS: "); + if (tco_sts & (1 << 20)) printk_debug("SMLINK_SLV "); + if (tco_sts & (1 << 18)) printk_debug("BOOT "); + if (tco_sts & (1 << 17)) printk_debug("SECOND_TO "); + if (tco_sts & (1 << 16)) printk_debug("INTRD_DET "); + if (tco_sts & (1 << 12)) printk_debug("DMISERR "); + if (tco_sts & (1 << 10)) printk_debug("DMISMI "); + if (tco_sts & (1 << 9)) printk_debug("DMISCI "); + if (tco_sts & (1 << 8)) printk_debug("BIOSWR "); + if (tco_sts & (1 << 7)) printk_debug("NEWCENTURY "); + if (tco_sts & (1 << 3)) printk_debug("TIMEOUT "); + if (tco_sts & (1 << 2)) printk_debug("TCO_INT "); + if (tco_sts & (1 << 1)) printk_debug("SW_TCO "); + if (tco_sts & (1 << 0)) printk_debug("NMI2SMI "); + printk_debug("\n"); +} + + +/* ********************* smi_util ************************* */ + +/* Data */ +#define UART_RBR 0x00 +#define UART_TBR 0x00 + +/* Control */ +#define UART_IER 0x01 +#define UART_IIR 0x02 +#define UART_FCR 0x02 +#define UART_LCR 0x03 +#define UART_MCR 0x04 +#define UART_DLL 0x00 +#define UART_DLM 0x01 + +/* Status */ +#define UART_LSR 0x05 +#define UART_MSR 0x06 +#define UART_SCR 0x07 + +static int uart_can_tx_byte(void) +{ + return inb(TTYS0_BASE + UART_LSR) & 0x20; +} + +static void uart_wait_to_tx_byte(void) +{ + while(!uart_can_tx_byte()) + ; +} + +static void uart_wait_until_sent(void) +{ + while(!(inb(TTYS0_BASE + UART_LSR) & 0x40)) + ; +} + +static void uart_tx_byte(unsigned char data) +{ + uart_wait_to_tx_byte(); + outb(data, TTYS0_BASE + UART_TBR); + /* Make certain the data clears the fifos */ + uart_wait_until_sent(); +} + +void console_tx_flush(void) +{ + uart_wait_to_tx_byte(); +} + +void console_tx_byte(unsigned char byte) +{ + if (byte == '\n') + uart_tx_byte('\r'); + uart_tx_byte(byte); +} + +/* We are using PCIe accesses for now + * 1. the chipset can do it + * 2. we don't need to worry about how we leave 0xcf8/0xcfc behind + */ +#include "../../../northbridge/intel/i945/pcie_config.c" + +/* ********************* smi_util ************************* */ + + +void io_trap_handler(int smif) +{ + u8 reg8; + global_nvs_t *gnvs = (global_nvs_t *)0xc00; + + printk_debug("SMI function trap 0x%x: ", smif); + + + switch (smif) { + case 0x32: + printk_debug("OS Init\n"); + break; + case 0xd6: + printk_debug("Get Brightness\n"); + outb(0x17, 0x66); + reg8 = inb(0x62); + gnvs->brtl = reg8; + break; + default: + printk_debug("Unknown function\n"); + break; + } + + /* On success, the IO Trap Handler returns 0 + * On failure, the IO Trap Handler returns a value != 0 + * + * For now, we force the return value to 0 and log all traps to + * see what's going on. + */ + //gnvs->smif = 0; +} + +/** + * @brief Set the EOS bit + */ +static void smi_set_eos(void) +{ + u8 reg8; + + reg8 = inb(pmbase + SMI_EN); + reg8 |= EOS; + outb(reg8, pmbase + SMI_EN); +} + +/** + * @brief Interrupt handler for SMI# + * + * @param smm_revision revision of the smm state save map + */ + +void smi_handler(u32 smm_revision) +{ + u8 reg8; + u16 pmctrl; + u16 pm1_sts; + u32 smi_sts, gpe0_sts, tco_sts; + unsigned int node; + smm_state_save_area_t state_save; + + /* Are we ok to execute the handler? */ + if (!smi_obtain_lock()) + return; + + node=nodeid(); + +#ifdef DEBUG_SMI + console_loglevel = DEFAULT_CONSOLE_LOGLEVEL; +#else + console_loglevel = 1; +#endif + + printk_debug("\nSMI# #%d\n", node); + + switch (smm_revision) { + case 0x00030007: + state_save.type = LEGACY; + state_save.legacy_state_save = (legacy_smm_state_save_area_t *) + (0xa8000 + 0x7e00 - (node * 0x400)); + break; + case 0x00030100: + state_save.type = EM64T; + state_save.em64t_state_save = (em64t_smm_state_save_area_t *) + (0xa8000 + 0x7d00 - (node * 0x400)); + break; + default: + printk_debug("smm_revision: 0x%08x\n", smm_revision); + printk_debug("SMI# not supported on your CPU\n"); + /* Don't release lock, so no further SMI will happen, + * if we don't handle it anyways. + */ + return; + } + + pmbase = pcie_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc; + printk_spew("SMI#: pmbase = 0x%04x\n", pmbase); + + /* We need to clear the SMI status registers, or we won't see what's + * happening in the following calls. + */ + smi_sts = reset_smi_status(); + dump_smi_status(smi_sts); + + if (smi_sts & (1 << 21)) { // MONITOR + global_nvs_t *gnvs = (global_nvs_t *)0xc00; + int i; + u32 reg32; + + reg32 = RCBA32(0x1e00); // TRSR - Trap Status Register +#if 0 + /* Comment in for some useful debug */ + for (i=0; i<4; i++) { + if (reg32 & (1 << i)) { + printk_debug(" io trap #%d\n", i); + } + } +#endif + RCBA32(0x1e00) = reg32; // TRSR + + reg32 = RCBA32(0x1e10); + + if ((reg32 & 0xfffc) != 0x808) { + printk_debug(" trapped io address = 0x%x\n", reg32 & 0xfffc); + printk_debug(" AHBE = %x\n", (reg32 >> 16) & 0xf); + printk_debug(" read/write: %s\n", (reg32 & (1 << 24)) ? "read" : + "write"); + } + + if (!(reg32 & (1 << 24))) { + /* Write Cycle */ + reg32 = RCBA32(0x1e18); + printk_debug(" iotrap written data = 0x%08x\n", reg32); + + } + + if (gnvs->smif) + io_trap_handler(gnvs->smif); // call function smif + } + + if (smi_sts & (1 << 13)) { // TCO + tco_sts = reset_tco_status(); + dump_tco_status(tco_sts); + + if (tco_sts & (1 << 8)) { // BIOSWR + u8 bios_cntl; + + bios_cntl = pcie_read_config16(PCI_DEV(0, 0x1f, 0), 0xdc); + + if (bios_cntl & 1) { + /* BWE is RW, so the SMI was caused by a + * write to BWE, not by a write to the BIOS + */ + + /* This is the place where we notice someone + * is trying to tinker with the BIOS. We are + * trying to be nice and just ignore it. A more + * resolute answer would be to power down the + * box. + */ + printk_debug("Switching back to RO\n"); + pcie_write_config32(PCI_DEV(0, 0x1f, 0), 0xdc, (bios_cntl & ~1)); + } /* No else for now? */ + } + } + + if (smi_sts & (1 << 8)) { // PM1 + pm1_sts = reset_pm1_status(); + dump_pm1_status(pm1_sts); + } + + if (smi_sts & (1 << 9)) { // GPE0 + gpe0_sts = reset_gpe0_status(); + dump_gpe0_status(gpe0_sts); + } + + if (smi_sts & (1 << 5)) { // APM + /* Emulate B2 register as the FADT / Linux expects it */ + + reg8 = inb(0xb2); + switch (reg8) { + case ACPI_DISABLE: + pmctrl = inw(pmbase + 0x04); + pmctrl |= (1 << 0); + outw(pmctrl, pmbase + 0x04); + printk_debug("SMI#: ACPI disabled.\n"); + break; + case ACPI_ENABLE: + pmctrl = inw(pmbase + 0x04); + pmctrl &= ~(1 << 0); + outw(pmctrl, pmbase + 0x04); + printk_debug("SMI#: ACPI enabled.\n"); + break; + } + } + + if (smi_sts & (1 << 4)) { // SLP_SMI + u32 reg32; + reg32 = inl(pmbase + 0x04); + printk_debug("SMI#: SLP = 0x%08x\n"); + printk_debug("SMI#: Powering off.\n"); + outl((6 << 10), pmbase + 0x04); + outl((1 << 13) | (6 << 10), pmbase + 0x04); + printk_debug("....\n"); + } + + + smi_release_lock(); + + /* De-assert SMI# signal to allow another SMI */ + smi_set_eos(); +} Added: trunk/coreboot-v2/src/southbridge/intel/i82801gx/smm.ld =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/i82801gx/smm.ld (rev 0) +++ trunk/coreboot-v2/src/southbridge/intel/i82801gx/smm.ld 2008-10-29 04:46:52 UTC (rev 3701) @@ -0,0 +1,53 @@ + +/* Maximum number of CPUs/cores */ +CPUS = 4; + +SECTIONS +{ + /* This is the actual SMM handler. + * + * We just put code, rodata, data and bss all in a row. + */ + . = 0xa0000; + .handler (.): { + /* Assembler stub */ + *(.handler) + + /* C code of the SMM handler */ + *(.text); + *(.text.*); + + /* C read-only data of the SMM handler */ + . = ALIGN(16); + *(.rodata) + *(.rodata.*) + + /* C read-write data of the SMM handler */ + . = ALIGN(4); + *(.data) + + /* C uninitialized data of the SMM handler */ + . = ALIGN(4); + *(.bss) + *(.sbss) + + /* What is this? */ + *(COMMON) + . = ALIGN(4); + } + + /* We are using the ASEG interleaved to stuff the SMM handlers + * for all CPU cores in there. The jump table redirects the execution + * to the actual SMM handler + */ + . = 0xa8000 - (( CPUS - 1) * 0x400); + .jumptable : { + *(.jumptable) + } + + /DISCARD/ : { + *(.comment) + *(.note) + *(.note.*) + } +} Added: trunk/coreboot-v2/src/southbridge/intel/i82801gx/smmhandler.S =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/i82801gx/smmhandler.S (rev 0) +++ trunk/coreboot-v2/src/southbridge/intel/i82801gx/smmhandler.S 2008-10-29 04:46:52 UTC (rev 3701) @@ -0,0 +1,201 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +/* NOTE: This handler assumes the SMM window goes from 0xa0000 + * to 0xaffff. In fact, at least on Intel Core CPUs (i945 chipset) + * the SMM window is 128K big, covering 0xa0000 to 0xbffff. + * So there is a lot of potential for growth in here. Let's stick + * to 64k if we can though. + */ + +/* + * +--------------------------------+ 0xaffff + * | Save State Map Node 0 | + * | Save State Map Node 1 | + * | Save State Map Node 2 | + * | Save State Map Node 3 | + * | ... | + * +--------------------------------+ 0xaf000 + * | | + * | | + * | | + * +--------------------------------+ 0xa8400 + * | SMM Entry Node 0 (+ stack) | + * +--------------------------------+ 0xa8000 + * | SMM Entry Node 1 (+ stack) | + * | SMM Entry Node 2 (+ stack) | + * | SMM Entry Node 3 (+ stack) | + * | ... | + * +--------------------------------+ 0xa7400 + * | | + * | SMM Handler | + * | | + * +--------------------------------+ 0xa0000 + * + */ + +#include <arch/asm.h> + +#define LAPIC_ID 0xfee00020 + +/* SMM_HANDLER_OFFSET is the 16bit offset within the ASEG + * at which smm_handler_start lives. At the moment the handler + * lives right at 0xa0000, so the offset is 0. + */ + +#define SMM_HANDLER_OFFSET 0x0000 + +/* initially SMM is some sort of real mode. Let gcc know + * how to treat the SMM handler stub + */ + +.section ".handler", "a", @progbits + +.code16 + +/** + * SMM code to enable protected mode and jump to the + * C-written function void smi_handler(u32 smm_revision) + * + * All the bad magic is not all that bad after all. + */ +smm_handler_start: + movw $(smm_gdtptr16 - smm_handler_start + SMM_HANDLER_OFFSET), %bx + data32 lgdt %cs:(%bx) + + movl %cr0, %eax + andl $0x7FFAFFD1, %eax /* PG,AM,WP,NE,TS,EM,MP = 0 */ + orl $0x60000001, %eax /* CD, NW, PE = 1 */ + movl %eax, %cr0 + + /* Enable protected mode */ + data32 ljmp $0x08, $1f + +.code32 +1: + /* Use flat data segment */ + movw $0x10, %ax + movw %ax, %ds + movw %ax, %es + movw %ax, %ss + movw %ax, %fs + movw %ax, %gs + + /* Get this CPU's LAPIC ID */ + movl $LAPIC_ID, %esi + movl (%esi), %ecx + shr $24, %ecx + + /* calculate stack offset by multiplying the APIC ID + * by 1024 (0x400), and save that offset in ebp. + */ + shl $10, %ecx + movl %ecx, %ebp + + /* We put the stack for each core right above + * its SMM entry point. Core 0 starts at 0xa8000, + * we spare 0x10 bytes for the jump to be sure. + */ + movl $0xa8010, %eax + subl %ecx, %eax /* subtract offset, see above */ + movl %eax, %ebx /* Save bottom of stack in ebx */ + +#define SMM_STACK_SIZE (0x400 - 0x10) + /* clear stack */ + cld + movl %eax, %edi + movl $(SMM_STACK_SIZE >> 2), %ecx + xorl %eax, %eax + rep stosl + + /* set new stack */ + addl $SMM_STACK_SIZE, %ebx + movl %ebx, %esp + + /* Get SMM revision */ + movl $0xa8000 + 0x7efc, %ebx /* core 0 address */ + subl %ebp, %ebx /* subtract core X offset */ + movl (%ebx), %eax + pushl %eax + + /* Call 32bit C handler */ + call smi_handler + + /* To return, just do rsm. It will "clean up" protected mode */ + rsm + +.code16 + +.align 4, 0xff + +smm_gdtptr16: + .word smm_gdt_end - smm_gdt - 1 + .long smm_gdt - smm_handler_start + 0xa0000 + SMM_HANDLER_OFFSET + +.code32 + +smm_gdt: + /* The first GDT entry can not be used. Keep it zero */ + .long 0x00000000, 0x00000000 + + /* gdt selector 0x08, flat code segment */ + .word 0xffff, 0x0000 + .byte 0x00, 0x9b, 0xcf, 0x00 /* G=1 and 0x0f, 4GB limit */ + + /* gdt selector 0x10, flat data segment */ + .word 0xffff, 0x0000 + .byte 0x00, 0x93, 0xcf, 0x00 + +smm_gdt_end: + + +.section ".jumptable", "a", @progbits + +/* This is the SMM jump table. All cores use the same SMM handler + * for simplicity. But SMM Entry needs to be different due to the + * save state area. The jump table makes sure all CPUs jump into the + * real handler on SMM entry. + */ + +/* This code currently supports up to 4 CPU cores. If more than 4 CPU cores + * shall be used, below table has to be updated, as well as smm.ld + */ + +/* GNU AS/LD will always generate code that assumes CS is 0xa000. In reality + * CS will be set to SMM_BASE[19:4] though. Knowing that the smm handler is the + * first thing in the ASEG, we do a far jump here, to set CS to 0xa000. + */ + +.code16 +jumptable: + /* core 3 */ + ljmp $0xa000, $SMM_HANDLER_OFFSET +.align 1024, 0x00 + /* core 2 */ + ljmp $0xa000, $SMM_HANDLER_OFFSET +.align 1024, 0x00 + /* core 1 */ + ljmp $0xa000, $SMM_HANDLER_OFFSET +.align 1024, 0x00 + /* core 0 */ + ljmp $0xa000, $SMM_HANDLER_OFFSET +.align 1024, 0x00 + Added: trunk/coreboot-v2/src/southbridge/intel/i82801gx/smmrelocate.S =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/i82801gx/smmrelocate.S (rev 0) +++ trunk/coreboot-v2/src/southbridge/intel/i82801gx/smmrelocate.S 2008-10-29 04:46:52 UTC (rev 3701) @@ -0,0 +1,168 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <arch/asm.h> +#include "../../../../src/northbridge/intel/i945/ich7.h" + +#undef DEBUG_SMM_RELOCATION +//#define DEBUG_SMM_RELOCATION + +#define LAPIC_ID 0xfee00020 + +.global smm_relocation_start +.global smm_relocation_end + +/* initially SMM is some sort of real mode. */ +.code16 + +/** + * This trampoline code relocates SMBASE to 0xa0000 - ( lapicid * 0x400 ) + * + * Why 0x400? It is a safe value to cover the save state area per CPU. On + * current AMD CPUs this area is _documented_ to be 0x200 bytes. On Intel + * Core 2 CPUs the _documented_ parts of the save state area is 48 bytes + * bigger, effectively sizing our data structures 0x300 bytes. + * + * LAPICID SMBASE SMM Entry SAVE STATE + * 0 0xa0000 0xa8000 0xafd00 + * 1 0x9fc00 0xa7c00 0xaf900 + * 2 0x9f800 0xa7800 0xaf500 + * 3 0x9f400 0xa7400 0xaf100 + * 4 0x9f000 0xa7000 0xaed00 + * 5 0x9ec00 0xa6c00 0xae900 + * 6 0x9e800 0xa6800 0xae500 + * 7 0x9e400 0xa6400 0xae100 + * 8 0x9e000 0xa6000 0xadd00 + * 9 0x9dc00 0xa5c00 0xad900 + * 10 0x9d800 0xa5800 0xad500 + * 11 0x9d400 0xa5400 0xad100 + * 12 0x9d000 0xa5000 0xacd00 + * 13 0x9cc00 0xa4c00 0xac900 + * 14 0x9c800 0xa4800 0xac500 + * 15 0x9c400 0xa4400 0xac100 + * . . . . + * . . . . + * . . . . + * 31 0x98400 0xa0400 0xa8100 + * + * With 32 cores, the SMM handler would need to fit between + * 0xa0000-0xa0400 and the stub plus stack would need to go + * at 0xa8000-0xa8100 (example for core 0). That is not enough. + * + * This means we're basically limited to 16 cpu cores before + * we need to use the TSEG/HSEG for the actual SMM handler plus stack. + * When we exceed 32 cores, we also need to put SMBASE to TSEG/HSEG. + * + * If we figure out the documented values above are safe to use, + * we could pack the structure above even more, so we could use the + * scheme to pack save state areas for 63 AMD CPUs or 58 Intel CPUs + * in the ASEG. + * + * Note: Some versions of Pentium M need their SMBASE aligned to 32k. + * On those the above only works for up to 2 cores. But for now we only + * care fore Core (2) Duo/Solo + * + */ + +smm_relocation_start: + /* Check revision to see if AMD64 style SMM_BASE + * Intel Core Solo/Duo: 0x30007 + * Intel Core2 Solo/Duo: 0x30100 + * AMD64: 0x3XX64 + * This check does not make much sense, unless someone ports + * SMI handling to AMD64 CPUs. + */ + + mov $0x38000 + 0x7efc, %ebx + addr32 mov (%ebx), %al + cmp $0x64, %al + je 1f + + mov $0x38000 + 0x7ef8, %ebx + jmp smm_relocate +1: + mov $0x38000 + 0x7f00, %ebx + +smm_relocate: + /* Get this CPU's LAPIC ID */ + movl $LAPIC_ID, %esi + addr32 movl (%esi), %ecx + shr $24, %ecx + + /* calculate offset by multiplying the + * apic ID by 1024 (0x400) + */ + movl %ecx, %edx + shl $10, %edx + + movl $0xa0000, %eax + subl %edx, %eax /* subtract offset, see above */ + + addr32 movl %eax, (%ebx) + + + /* The next section of code is hardware specific */ + + /* Clear SMI status */ + movw $(DEFAULT_PMBASE + 0x34), %dx + inw %dx, %ax + outw %ax, %dx + + /* Clear PM1 status */ + movw $(DEFAULT_PMBASE + 0x00), %dx + inw %dx, %ax + outw %ax, %dx + + /* Set EOS bit so other SMIs can occur */ + movw $(DEFAULT_PMBASE + 0x30), %dx + inl %dx, %eax + orl $(1 << 1), %eax + outl %eax, %dx + + /* End of hardware specific section. */ +#ifdef DEBUG_SMM_RELOCATION + /* print [SMM-x] so we can determine if CPUx went to SMM */ + movw $TTYS0_BASE, %dx + mov $'[', %al + outb %al, %dx + mov $'S', %al + outb %al, %dx + mov $'M', %al + outb %al, %dx + outb %al, %dx + movb $'-', %al + outb %al, %dx + /* calculate ascii of cpu number. More than 9 cores? -> FIXME */ + movb %cl, %al + addb $'0', %al + outb %al, %dx + mov $']', %al + outb %al, %dx + mov $'\r', %al + outb %al, %dx + mov $'\n', %al + outb %al, %dx +#endif + + /* That's it. return */ + rsm +smm_relocation_end: +

1 0

r3700 - in trunk/coreboot-v2/src/superio/winbond: . w83627thg
by svn＠coreboot.org 29 Oct '08

29 Oct '08

Author: stepan Date: 2008-10-29 05:45:28 +0100 (Wed, 29 Oct 2008) New Revision: 3700 Added: trunk/coreboot-v2/src/superio/winbond/w83627thg/ trunk/coreboot-v2/src/superio/winbond/w83627thg/Config.lb trunk/coreboot-v2/src/superio/winbond/w83627thg/chip.h trunk/coreboot-v2/src/superio/winbond/w83627thg/superio.c trunk/coreboot-v2/src/superio/winbond/w83627thg/w83627thg.h trunk/coreboot-v2/src/superio/winbond/w83627thg/w83627thg_early_serial.c Log: Implement support for the Winbond W83627THG. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Added: trunk/coreboot-v2/src/superio/winbond/w83627thg/Config.lb =================================================================== --- trunk/coreboot-v2/src/superio/winbond/w83627thg/Config.lb (rev 0) +++ trunk/coreboot-v2/src/superio/winbond/w83627thg/Config.lb 2008-10-29 04:45:28 UTC (rev 3700) @@ -0,0 +1,2 @@ +config chip.h +object superio.o Added: trunk/coreboot-v2/src/superio/winbond/w83627thg/chip.h =================================================================== --- trunk/coreboot-v2/src/superio/winbond/w83627thg/chip.h (rev 0) +++ trunk/coreboot-v2/src/superio/winbond/w83627thg/chip.h 2008-10-29 04:45:28 UTC (rev 3700) @@ -0,0 +1,9 @@ +#include <pc80/keyboard.h> +#include <uart8250.h> + +extern struct chip_operations superio_winbond_w83627thg_ops; + +struct superio_winbond_w83627thg_config { + struct uart8250 com1, com2; + struct pc_keyboard keyboard; +}; Added: trunk/coreboot-v2/src/superio/winbond/w83627thg/superio.c =================================================================== --- trunk/coreboot-v2/src/superio/winbond/w83627thg/superio.c (rev 0) +++ trunk/coreboot-v2/src/superio/winbond/w83627thg/superio.c 2008-10-29 04:45:28 UTC (rev 3700) @@ -0,0 +1,109 @@ +/* Copyright 2000 AG Electronics Ltd. */ +/* Copyright 2003-2004 Linux Networx */ +/* Copyright 2004 Tyan + By LYH change from PC87360 */ +/* This code is distributed without warranty under the GPL v2 (see COPYING) */ + +#include <arch/io.h> +#include <device/device.h> +#include <device/pnp.h> +#include <console/console.h> +#include <string.h> +#include <bitops.h> +#include <uart8250.h> +#include <pc80/keyboard.h> +#include "chip.h" +#include "w83627thg.h" + +static void w83627thg_enter_ext_func_mode(device_t dev) +{ + outb(0x87, dev->path.u.pnp.port); + outb(0x87, dev->path.u.pnp.port); +} +static void w83627thg_exit_ext_func_mode(device_t dev) +{ + outb(0xaa, dev->path.u.pnp.port); +} + +static void w83627thg_init(device_t dev) +{ + struct superio_winbond_w83627thg_config *conf; + struct resource *res0, *res1; + /* Wishlist handle well known programming interfaces more + * generically. + */ + if (!dev->enabled) { + return; + } + conf = dev->chip_info; + switch(dev->path.u.pnp.device) { + case W83627THG_SP1: + res0 = find_resource(dev, PNP_IDX_IO0); + init_uart8250(res0->base, &conf->com1); + break; + case W83627THG_SP2: + res0 = find_resource(dev, PNP_IDX_IO0); + init_uart8250(res0->base, &conf->com2); + break; + case W83627THG_KBC: + res0 = find_resource(dev, PNP_IDX_IO0); + res1 = find_resource(dev, PNP_IDX_IO1); + init_pc_keyboard(res0->base, res1->base, &conf->keyboard); + break; + } +} + +static void w83627thg_set_resources(device_t dev) +{ + w83627thg_enter_ext_func_mode(dev); + pnp_set_resources(dev); + w83627thg_exit_ext_func_mode(dev); +} + +static void w83627thg_enable_resources(device_t dev) +{ + w83627thg_enter_ext_func_mode(dev); + pnp_enable_resources(dev); + w83627thg_exit_ext_func_mode(dev); +} + +static void w83627thg_enable(device_t dev) +{ + w83627thg_enter_ext_func_mode(dev); + pnp_enable(dev); + w83627thg_exit_ext_func_mode(dev); +} + + +static struct device_operations ops = { + .read_resources = pnp_read_resources, + .set_resources = w83627thg_set_resources, + .enable_resources = w83627thg_enable_resources, + .enable = w83627thg_enable, + .init = w83627thg_init, +}; + +static struct pnp_info pnp_dev_info[] = { + { &ops, W83627THG_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, }, + { &ops, W83627THG_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, }, + { &ops, W83627THG_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, + { &ops, W83627THG_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, + // No 4 { 0,}, + { &ops, W83627THG_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, { 0x7ff, 0x4}, }, + { &ops, W83627THG_GAME_MIDI_GPIO1, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x7ff, 0 }, {0x7fe, 4} }, + { &ops, W83627THG_GPIO2,}, + { &ops, W83627THG_GPIO3,}, + { &ops, W83627THG_ACPI, PNP_IRQ0, }, + { &ops, W83627THG_HWM, PNP_IO0 | PNP_IRQ0, { 0xff8, 0 } }, +}; + +static void enable_dev(device_t dev) +{ + pnp_enable_devices(dev, &ops, + sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]), pnp_dev_info); +} + +struct chip_operations superio_winbond_w83627thg_ops = { + CHIP_NAME("Winbond W83627THG Super I/O") + .enable_dev = enable_dev, +}; Added: trunk/coreboot-v2/src/superio/winbond/w83627thg/w83627thg.h =================================================================== --- trunk/coreboot-v2/src/superio/winbond/w83627thg/w83627thg.h (rev 0) +++ trunk/coreboot-v2/src/superio/winbond/w83627thg/w83627thg.h 2008-10-29 04:45:28 UTC (rev 3700) @@ -0,0 +1,10 @@ +#define W83627THG_FDC 0 /* Floppy */ +#define W83627THG_PP 1 /* Parallel Port */ +#define W83627THG_SP1 2 /* Com1 */ +#define W83627THG_SP2 3 /* Com2 */ +#define W83627THG_KBC 5 /* Keyboard & Mouse */ +#define W83627THG_GAME_MIDI_GPIO1 7 +#define W83627THG_GPIO2 8 +#define W83627THG_GPIO3 9 +#define W83627THG_ACPI 10 +#define W83627THG_HWM 11 /* Hardware Monitor */ Added: trunk/coreboot-v2/src/superio/winbond/w83627thg/w83627thg_early_serial.c =================================================================== --- trunk/coreboot-v2/src/superio/winbond/w83627thg/w83627thg_early_serial.c (rev 0) +++ trunk/coreboot-v2/src/superio/winbond/w83627thg/w83627thg_early_serial.c 2008-10-29 04:45:28 UTC (rev 3700) @@ -0,0 +1,25 @@ +#include <arch/romcc_io.h> +#include "w83627thg.h" + +static inline void pnp_enter_ext_func_mode(device_t dev) +{ + unsigned int port = dev >> 8; + outb(0x87, port); + outb(0x87, port); +} + +static void pnp_exit_ext_func_mode(device_t dev) +{ + unsigned int port = dev >> 8; + outb(0xaa, port); +} + +static void w83627thg_enable_serial(device_t dev, unsigned int iobase) +{ + pnp_enter_ext_func_mode(dev); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, iobase); + pnp_set_enable(dev, 1); + pnp_exit_ext_func_mode(dev); +}

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coreboot October 2008