r3702 - in trunk/coreboot-v2/src/cpu: intel intel/model_6ex intel/model_6fx intel/socket_mFCPGA478 intel/socket_mPGA478 x86/car x86/lapic
Author: stepan Date: 2008-10-29 05:48:44 +0100 (Wed, 29 Oct 2008) New Revision: 3702
Added: trunk/coreboot-v2/src/cpu/intel/model_6ex/ trunk/coreboot-v2/src/cpu/intel/model_6ex/Config.lb trunk/coreboot-v2/src/cpu/intel/model_6ex/cache_as_ram.inc trunk/coreboot-v2/src/cpu/intel/model_6ex/cache_as_ram_disable.c trunk/coreboot-v2/src/cpu/intel/model_6ex/cache_as_ram_post.c trunk/coreboot-v2/src/cpu/intel/model_6ex/microcode_m206e839.h trunk/coreboot-v2/src/cpu/intel/model_6ex/model_6ex_init.c trunk/coreboot-v2/src/cpu/intel/model_6fx/ trunk/coreboot-v2/src/cpu/intel/model_6fx/Config.lb trunk/coreboot-v2/src/cpu/intel/model_6fx/cache_as_ram.inc trunk/coreboot-v2/src/cpu/intel/model_6fx/cache_as_ram_disable.c trunk/coreboot-v2/src/cpu/intel/model_6fx/cache_as_ram_post.c trunk/coreboot-v2/src/cpu/intel/model_6fx/model_6fx_init.c trunk/coreboot-v2/src/cpu/intel/socket_mPGA478/ trunk/coreboot-v2/src/cpu/intel/socket_mPGA478/Config.lb trunk/coreboot-v2/src/cpu/intel/socket_mPGA478/chip.h trunk/coreboot-v2/src/cpu/intel/socket_mPGA478/socket_mPGA478.c Modified: trunk/coreboot-v2/src/cpu/intel/socket_mFCPGA478/Config.lb trunk/coreboot-v2/src/cpu/x86/car/copy_and_run.c trunk/coreboot-v2/src/cpu/x86/lapic/lapic_cpu_init.c Log: Support for Intel Core Duo and Core 2 Duo (tm) CPUs.
Signed-off-by: Stefan Reinauer stepan@coresystems.de Acked-by: Ronald G. Minnich rminnich@gmail.com
Added: trunk/coreboot-v2/src/cpu/intel/model_6ex/Config.lb =================================================================== --- trunk/coreboot-v2/src/cpu/intel/model_6ex/Config.lb (rev 0) +++ trunk/coreboot-v2/src/cpu/intel/model_6ex/Config.lb 2008-10-29 04:48:44 UTC (rev 3702) @@ -0,0 +1,13 @@ +uses HAVE_MOVNTI +default HAVE_MOVNTI=1 + +dir /cpu/x86/tsc +dir /cpu/x86/mtrr +dir /cpu/x86/fpu +dir /cpu/x86/mmx +dir /cpu/x86/sse +dir /cpu/x86/lapic +dir /cpu/x86/cache +dir /cpu/intel/microcode +dir /cpu/intel/hyperthreading +driver model_6ex_init.o
Added: trunk/coreboot-v2/src/cpu/intel/model_6ex/cache_as_ram.inc =================================================================== --- trunk/coreboot-v2/src/cpu/intel/model_6ex/cache_as_ram.inc (rev 0) +++ trunk/coreboot-v2/src/cpu/intel/model_6ex/cache_as_ram.inc 2008-10-29 04:48:44 UTC (rev 3702) @@ -0,0 +1,152 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2000,2007 Ronald G. Minnich rminnich@gmail.com + * Copyright (C) 2007-2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define CACHE_AS_RAM_SIZE DCACHE_RAM_SIZE +#define CACHE_AS_RAM_BASE DCACHE_RAM_BASE +#define post_code(x) intel_chip_post_macro(x) + +#include <cpu/x86/mtrr.h> +#include <cpu/amd/mtrr.h> + + /* Save the BIST result */ + movl %eax, %ebp + +cache_as_ram: +#if USE_FALLBACK_IMAGE == 1 + + post_code(0x20) + + /* Send INIT IPI to all excluding ourself */ + movl $0x000C4500, %eax + movl $0xFEE00300, %esi + movl %eax, (%esi) + + /* Zero out all Fixed Range and Variable Range MTRRs */ + movl $mtrr_table, %esi + movl $( (mtrr_table_end - mtrr_table) / 2), %edi + xorl %eax, %eax + xorl %edx, %edx +clear_mtrrs: + movw (%esi), %bx + movzx %bx, %ecx + wrmsr + add $2, %esi + dec %edi + jnz clear_mtrrs + + /* Configure the default memory type to uncacheable */ + movl $MTRRdefType_MSR, %ecx + rdmsr + andl $(~0x00000cff), %eax + wrmsr + + /* Set cache as ram base address */ + movl $(MTRRphysBase_MSR(0)), %ecx + movl $(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax + xorl %edx, %edx + wrmsr + + /* Set cache as ram mask */ + movl $(MTRRphysMask_MSR(0)), %ecx + movl $(~((CACHE_AS_RAM_SIZE-1)) | (1 << 11)), %eax + movl $0x0000000f, %edx + wrmsr + + /* Enable MTRR */ + movl $MTRRdefType_MSR, %ecx + rdmsr + orl $(1 << 11), %eax + wrmsr + + /* Enable L2 Cache */ + movl $0x11e, %ecx + rdmsr + orl $(1 << 8), %eax + wrmsr + + /* CR0.CD = 0, CR0.NW = 0 */ + movl %cr0, %eax + andl $( ~( (1 << 30) | (1 << 29) ) ), %eax + invd + movl %eax, %cr0 + + /* Clear the cache memory reagion */ + movl $CACHE_AS_RAM_BASE, %esi + movl %esi, %edi + movl $(CACHE_AS_RAM_SIZE / 4), %ecx + //movl $0x23322332, %eax + xorl %eax, %eax + rep stosl +#endif + + /* Enable Cache As RAM mode by disabling cache */ + movl %cr0, %eax + orl $(1 << 30), %eax + movl %eax, %cr0 + +#if defined(XIP_ROM_SIZE) && defined(XIP_ROM_BASE) + /* Enable cache for our code in Flash because we do XIP here */ + movl $MTRRphysBase_MSR(1), %ecx + xorl %edx, %edx + movl $(XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax + wrmsr + + movl $MTRRphysMask_MSR(1), %ecx + movl $0x0000000f, %edx + movl $(~(XIP_ROM_SIZE - 1) | 0x800), %eax + wrmsr +#endif /* XIP_ROM_SIZE && XIP_ROM_BASE */ + + /* enable cache */ + movl %cr0, %eax + andl $( ~( (1 << 30) | (1 << 29) ) ), %eax + movl %eax, %cr0 + + /* Set up stack pointer */ + movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4), %eax + movl %eax, %esp + + /* Restore the BIST result */ + movl %ebp, %eax + movl %esp, %ebp + pushl %eax + + post_code(0x23) + + call stage1_main + + post_code(0x2f) +error: + hlt + jmp error + +mtrr_table: + /* Fixed MTRRs */ + .word 0x250, 0x258, 0x259 + .word 0x268, 0x269, 0x26A + .word 0x26B, 0x26C, 0x26D + .word 0x26E, 0x26F + /* Variable MTRRs */ + .word 0x200, 0x201, 0x202, 0x203 + .word 0x204, 0x205, 0x206, 0x207 + .word 0x208, 0x209, 0x20A, 0x20B + .word 0x20C, 0x20D, 0x20E, 0x20F +mtrr_table_end: +
Added: trunk/coreboot-v2/src/cpu/intel/model_6ex/cache_as_ram_disable.c =================================================================== --- trunk/coreboot-v2/src/cpu/intel/model_6ex/cache_as_ram_disable.c (rev 0) +++ trunk/coreboot-v2/src/cpu/intel/model_6ex/cache_as_ram_disable.c 2008-10-29 04:48:44 UTC (rev 3702) @@ -0,0 +1,111 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include "cpu/x86/car/copy_and_run.c" + +void real_main(unsigned long bist); + +void stage1_main(unsigned long bist) +{ + unsigned int cpu_reset = 0; + +#if USE_FALLBACK_IMAGE == 1 + /* Is this a deliberate reset by the bios */ + if (bios_reset_detected() && last_boot_normal()) { + goto normal_image; + } else { + /* This is the primary cpu how should I boot? */ + check_cmos_failed(); + if (do_normal_boot()) { + goto normal_image; + } + else { + goto fallback_image; + } + } + normal_image: + __asm__ volatile ("jmp __normal_image" + : /* outputs */ + : "a" (bist) /* inputs */ + ); + fallback_image: +#endif + + real_main(bist); + + /* No servicable parts below this line .. */ + + { + /* Check value of esp to verify if we have enough rom for stack in Cache as RAM */ + unsigned v_esp; + __asm__ volatile ( + "movl %%esp, %0\n\t" + : "=a" (v_esp) + ); + printk_spew("v_esp=%08x\r\n", v_esp); + } + +cpu_reset_x: + + printk_spew("cpu_reset = %08x\r\n",cpu_reset); + + if(cpu_reset == 0) { + print_spew("Clearing initial memory region: "); + } + print_spew("No cache as ram now - "); + + /* store cpu_reset to ebx */ + __asm__ volatile ( + "movl %0, %%ebx\n\t" + ::"a" (cpu_reset) + ); + + if(cpu_reset==0) { +#define CLEAR_FIRST_1M_RAM 1 +#include "cache_as_ram_post.c" + } else { +#undef CLEAR_FIRST_1M_RAM +#include "cache_as_ram_post.c" + } + + __asm__ volatile ( + /* set new esp */ /* before _RAMBASE */ + "subl %0, %%ebp\n\t" + "subl %0, %%esp\n\t" + ::"a"( (DCACHE_RAM_BASE + DCACHE_RAM_SIZE)- _RAMBASE ) + ); + + { + unsigned new_cpu_reset; + + /* get back cpu_reset from ebx */ + __asm__ volatile ( + "movl %%ebx, %0\n\t" + :"=a" (new_cpu_reset) + ); + + /* Copy and execute coreboot_ram */ + copy_and_run(new_cpu_reset); + /* We will not return */ + } + + print_debug("sorry. parachute did not open.\r\n"); +}
Added: trunk/coreboot-v2/src/cpu/intel/model_6ex/cache_as_ram_post.c =================================================================== --- trunk/coreboot-v2/src/cpu/intel/model_6ex/cache_as_ram_post.c (rev 0) +++ trunk/coreboot-v2/src/cpu/intel/model_6ex/cache_as_ram_post.c 2008-10-29 04:48:44 UTC (rev 3702) @@ -0,0 +1,125 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + + __asm__ volatile ( + + "movb $0x30, %al\noutb %al, $0x80\n" + + /* Disable Cache */ + "movl %cr0, %eax\n" + "orl $(1 << 30), %eax\n" + "movl %eax, %cr0\n" + + "movb $0x31, %al\noutb %al, $0x80\n" + + /* Disable MTRR */ + "movl $MTRRdefType_MSR, %ecx\n" + "rdmsr\n" + "andl $(~(1 << 11)), %eax\n" + "wrmsr\n" + + "movb $0x32, %al\noutb %al, $0x80\n" + + "invd\n" +#if 0 + "xorl %eax, %eax\n" + "xorl %edx, %edx\n" + "movl $MTRRphysBase_MSR(0), %ecx\n" + "wrmsr\n" + "movl $MTRRphysMask_MSR(0), %ecx\n" + "wrmsr\n" + "movl $MTRRphysBase_MSR(1), %ecx\n" + "wrmsr\n" + "movl $MTRRphysMask_MSR(1), %ecx\n" + "wrmsr\n" +#endif + + "movb $0x33, %al\noutb %al, $0x80\n" +#ifdef CLEAR_FIRST_1M_RAM + "movb $0x34, %al\noutb %al, $0x80\n" + /* Enable Write Combining and Speculative Reads for the first 1MB */ + "movl $MTRRphysBase_MSR(0), %ecx\n" + "movl $(0x00000000 | MTRR_TYPE_WRCOMB), %eax\n" + "xorl %edx, %edx\n" + "wrmsr\n" + "movl $MTRRphysMask_MSR(0), %ecx\n" + "movl $(~(1024*1024 -1) | (1 << 11)), %eax\n" + "movl $0x0000000f, %edx\n" // 36bit address space + "wrmsr\n" + "movb $0x35, %al\noutb %al, $0x80\n" +#endif + + /* Enable Cache */ + "movl %cr0, %eax\n" + "andl $~( (1 << 30) | (1 << 29) ), %eax\n" + "movl %eax, %cr0\n" + + "movb $0x36, %al\noutb %al, $0x80\n" +#ifdef CLEAR_FIRST_1M_RAM + + /* Clear first 1MB of RAM */ + "movl $0x00000000, %edi\n" + "cld\n" + "xorl %eax, %eax\n" + "movl $((1024*1024) / 4), %ecx\n" + "rep stosl\n" + + "movb $0x37, %al\noutb %al, $0x80\n" +#endif + + /* Disable Cache */ + "movl %cr0, %eax\n" + "orl $(1 << 30), %eax\n" + "movl %eax, %cr0\n" + + "movb $0x38, %al\noutb %al, $0x80\n" + + /* Enable Write Back and Speculative Reads for the first 1MB */ + "movl $MTRRphysBase_MSR(0), %ecx\n" + "movl $(0x00000000 | MTRR_TYPE_WRBACK), %eax\n" + "xorl %edx, %edx\n" + "wrmsr\n" + "movl $MTRRphysMask_MSR(0), %ecx\n" + "movl $(~(1024*1024 -1) | (1 << 11)), %eax\n" + "movl $0x0000000f, %edx\n" // 36bit address space + "wrmsr\n" + + "movb $0x39, %al\noutb %al, $0x80\n" + + /* And Enable Cache again after setting MTRRs */ + "movl %cr0, %eax\n" + "andl $~( (1 << 30) | (1 << 29) ), %eax\n" + "movl %eax, %cr0\n" + + "movb $0x3a, %al\noutb %al, $0x80\n" + + /* Enable MTRR */ + "movl $MTRRdefType_MSR, %ecx\n" + "rdmsr\n" + "orl $(1 << 11), %eax\n" + "wrmsr\n" + + "movb $0x3b, %al\noutb %al, $0x80\n" + + /* Invalidate the cache again */ + "invd\n" + "movb $0x3c, %al\noutb %al, $0x80\n" + );
Added: trunk/coreboot-v2/src/cpu/intel/model_6ex/microcode_m206e839.h =================================================================== --- trunk/coreboot-v2/src/cpu/intel/model_6ex/microcode_m206e839.h (rev 0) +++ trunk/coreboot-v2/src/cpu/intel/model_6ex/microcode_m206e839.h 2008-10-29 04:48:44 UTC (rev 3702) @@ -0,0 +1,291 @@ +//+++ +// Copyright (c) <1995-2008>, Intel Corporation. +// All rights reserved. +// +// Redistribution. Redistribution and use in binary form, without modification, are +// permitted provided that the following conditions are met: +// .Redistributions must reproduce the above copyright notice and the following +// disclaimer in the documentation and/or other materials provided with the +// distribution. +// .Neither the name of Intel Corporation nor the names of its suppliers may be used +// to endorse or promote products derived from this software without specific prior +// written permission. +// .No reverse engineering, decompilation, or disassembly of this software is +// permitted. +// ."Binary form" includes any format commonly used for electronic conveyance +// which is a reversible, bit-exact translation of binary representation to ASCII or +// ISO text, for example, "uuencode." +// +// DISCLAIMER. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT +// HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED +// WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER +// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +// NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +//--- +/* Tue Apr 1 14:14:15 CST 2008 */ +/* 1624-m206e839.inc */ +0x00000001, 0x00000039, 0x11152005, 0x000006e8, +0x00e9d6a3, 0x00000001, 0x00000020, 0x00000fd0, +0x00001000, 0x00000000, 0x00000000, 0x00000000, +0xc9226026, 0x31d04cc5, 0xeb5e9216, 0x81b9b739, +0xb8187c4d, 0xdb2db5c8, 0xac304dd3, 0x56259185, +0x5cee9dfc, 0xc4c708fc, 0xfbfebb15, 0x4657a346, +0xd5fdfc56, 0x49ccc684, 0xfe2f1980, 0x23e44e95, +0xaf7e0890, 0x0a306ae9, 0x0533035c, 0xf747f6c4, +0xbb7a6356, 0x07415037, 0xb9cd0d46, 0x4dc69422, +0x19ed8dba, 0x61955793, 0x2c69260d, 0x0e23b80f, +0xce2c111e, 0x94c5acb3, 0xf2050f28, 0xc4348718, +0x4496d9b0, 0xec1eb627, 0x8f6d3916, 0xa67909c6, +0x37bdb9ce, 0x4d7393bc, 0x9b7027a4, 0xc1bfa4b4, +0x671fb655, 0x447f72ea, 0xf96b0311, 0xbfa5989d, +0xffa59b41, 0x4af95bb9, 0xeebc0d4e, 0xce0d8017, +0xad35c182, 0x9fa068f0, 0xcdafa471, 0x5459e6da, +0x9bb88256, 0xc593800c, 0x327a1e3f, 0x714bfb6f, +0x8b02e7cd, 0x16020ebb, 0xb0598f84, 0xd021f373, +0x07d55d88, 0x90774676, 0x6cd1f7ca, 0x99e1bfa7, +0x3c67877c, 0xdbd380ab, 0x5eb38db2, 0xe0edbfd0, +0xc5534984, 0x411b21df, 0x16771220, 0x4a8a60f1, +0xd80ab95f, 0x93090a73, 0x12135fa7, 0xbf0fde89, +0x50cb4bc6, 0x508ea81f, 0x8f567bbc, 0xecd02b7f, +0x2b0ceb7b, 0x6fe0367e, 0xce928c01, 0x69589c6f, +0x0c28f0f7, 0xd9ac3fa8, 0xd6a23e1d, 0x19613ebb, +0xe455b950, 0xa58b7cf7, 0xeeab2947, 0x1e588aa8, +0xbb634862, 0x5b6421b2, 0x6297ae0b, 0xbf63b1e9, +0x530e7f14, 0x5c2c0f79, 0x9cdeebc4, 0xf6d7037e, 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Added: trunk/coreboot-v2/src/cpu/intel/model_6ex/model_6ex_init.c =================================================================== --- trunk/coreboot-v2/src/cpu/intel/model_6ex/model_6ex_init.c (rev 0) +++ trunk/coreboot-v2/src/cpu/intel/model_6ex/model_6ex_init.c 2008-10-29 04:48:44 UTC (rev 3702) @@ -0,0 +1,94 @@ +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <string.h> +#include <cpu/cpu.h> +#include <cpu/x86/mtrr.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/lapic.h> +#include <cpu/intel/microcode.h> +#include <cpu/intel/hyperthreading.h> +#include <cpu/x86/cache.h> +#include <cpu/x86/mtrr.h> + +static const uint32_t microcode_updates[] = { + #include "microcode_m206e839.h" + /* Dummy terminator */ + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, +}; + +static inline void strcpy(char *dst, char *src) +{ + while (*src) *dst++ = *src++; +} + +static void fill_processor_name(char *processor_name) +{ + struct cpuid_result regs; + char temp_processor_name[49]; + char *processor_name_start; + unsigned int *name_as_ints = (unsigned int *)temp_processor_name; + int i; + + for (i=0; i<3; i++) { + regs = cpuid(0x80000002 + i); + name_as_ints[i*4 + 0] = regs.eax; + name_as_ints[i*4 + 1] = regs.ebx; + name_as_ints[i*4 + 2] = regs.ecx; + name_as_ints[i*4 + 3] = regs.edx; + } + + temp_processor_name[48] = 0; + + /* Skip leading spaces */ + processor_name_start = temp_processor_name; + while (*processor_name_start == ' ') + processor_name_start++; + + memset(processor_name, 0, 49); + strcpy(processor_name, processor_name_start); +} + +static void model_6ex_init(device_t cpu) +{ + char processor_name[49]; + + /* Turn on caching if we haven't already */ + x86_enable_cache(); + + /* Update the microcode */ + intel_update_microcode(microcode_updates); + + /* Print processor name */ + fill_processor_name(processor_name); + printk_info("CPU: %s.\n", processor_name); + + /* Setup MTRRs */ + x86_setup_mtrrs(36); + x86_mtrr_check(); + + /* Enable the local cpu apics */ + setup_lapic(); + + /* Start up my cpu siblings */ + intel_sibling_init(cpu); +} + +static struct device_operations cpu_dev_ops = { + .init = model_6ex_init, +}; + +static struct cpu_device_id cpu_table[] = { + { X86_VENDOR_INTEL, 0x06e0 }, /* Intel Core Solo/Core Duo */ + { X86_VENDOR_INTEL, 0x06e8 }, /* Intel Core Solo/Core Duo */ + { 0, 0 }, +}; + +static const struct cpu_driver driver __cpu_driver = { + .ops = &cpu_dev_ops, + .id_table = cpu_table, +}; +
Added: trunk/coreboot-v2/src/cpu/intel/model_6fx/Config.lb =================================================================== --- trunk/coreboot-v2/src/cpu/intel/model_6fx/Config.lb (rev 0) +++ trunk/coreboot-v2/src/cpu/intel/model_6fx/Config.lb 2008-10-29 04:48:44 UTC (rev 3702) @@ -0,0 +1,13 @@ +uses HAVE_MOVNTI +default HAVE_MOVNTI=1 + +dir /cpu/x86/tsc +dir /cpu/x86/mtrr +dir /cpu/x86/fpu +dir /cpu/x86/mmx +dir /cpu/x86/sse +dir /cpu/x86/lapic +dir /cpu/x86/cache +dir /cpu/intel/microcode +dir /cpu/intel/hyperthreading +driver model_6fx_init.o
Added: trunk/coreboot-v2/src/cpu/intel/model_6fx/cache_as_ram.inc =================================================================== --- trunk/coreboot-v2/src/cpu/intel/model_6fx/cache_as_ram.inc (rev 0) +++ trunk/coreboot-v2/src/cpu/intel/model_6fx/cache_as_ram.inc 2008-10-29 04:48:44 UTC (rev 3702) @@ -0,0 +1,159 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2000,2007 Ronald G. Minnich rminnich@gmail.com + * Copyright (C) 2007-2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define CACHE_AS_RAM_SIZE DCACHE_RAM_SIZE +#define CACHE_AS_RAM_BASE DCACHE_RAM_BASE +#define post_code(x) intel_chip_post_macro(x) + +#include <cpu/x86/mtrr.h> +#include <cpu/amd/mtrr.h> + + /* Save the BIST result */ + movl %eax, %ebp + +cache_as_ram: +#if USE_FALLBACK_IMAGE == 1 + + post_code(0x20) + + /* Send INIT IPI to all excluding ourself */ + movl $0x000C4500, %eax + movl $0xFEE00300, %esi + movl %eax, (%esi) + + /* Disable prefetchers */ + movl $0x01a0, %eax + rdmsr + orl $((1 << 9) | (1 << 19)), %eax + orl $((1 << 5) | (1 << 7)), %edx + wrmsr + + /* Zero out all Fixed Range and Variable Range MTRRs */ + movl $mtrr_table, %esi + movl $( (mtrr_table_end - mtrr_table) / 2), %edi + xorl %eax, %eax + xorl %edx, %edx +clear_mtrrs: + movw (%esi), %bx + movzx %bx, %ecx + wrmsr + add $2, %esi + dec %edi + jnz clear_mtrrs + + /* Configure the default memory type to uncacheable */ + movl $MTRRdefType_MSR, %ecx + rdmsr + andl $(~0x00000cff), %eax + wrmsr + + /* Set cache as ram base address */ + movl $(MTRRphysBase_MSR(0)), %ecx + movl $(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax + xorl %edx, %edx + wrmsr + + /* Set cache as ram mask */ + movl $(MTRRphysMask_MSR(0)), %ecx + movl $(~((CACHE_AS_RAM_SIZE-1)) | (1 << 11)), %eax + movl $0x0000000f, %edx + wrmsr + + /* Enable MTRR */ + movl $MTRRdefType_MSR, %ecx + rdmsr + orl $(1 << 11), %eax + wrmsr + + /* Enable L2 Cache */ + movl $0x11e, %ecx + rdmsr + orl $(1 << 8), %eax + wrmsr + + /* CR0.CD = 0, CR0.NW = 0 */ + movl %cr0, %eax + andl $( ~( (1 << 30) | (1 << 29) ) ), %eax + invd + movl %eax, %cr0 + + /* Clear the cache memory reagion */ + movl $CACHE_AS_RAM_BASE, %esi + movl %esi, %edi + movl $(CACHE_AS_RAM_SIZE / 4), %ecx + //movl $0x23322332, %eax + xorl %eax, %eax + rep stosl +#endif + + /* Enable Cache As RAM mode by disabling cache */ + movl %cr0, %eax + orl $(1 << 30), %eax + movl %eax, %cr0 + +#if defined(XIP_ROM_SIZE) && defined(XIP_ROM_BASE) + /* Enable cache for our code in Flash because we do XIP here */ + movl $MTRRphysBase_MSR(1), %ecx + xorl %edx, %edx + movl $(XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax + wrmsr + + movl $MTRRphysMask_MSR(1), %ecx + movl $0x0000000f, %edx + movl $(~(XIP_ROM_SIZE - 1) | 0x800), %eax + wrmsr +#endif /* XIP_ROM_SIZE && XIP_ROM_BASE */ + + /* enable cache */ + movl %cr0, %eax + andl $( ~( (1 << 30) | (1 << 29) ) ), %eax + movl %eax, %cr0 + + /* Set up stack pointer */ + movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4), %eax + movl %eax, %esp + + /* Restore the BIST result */ + movl %ebp, %eax + movl %esp, %ebp + pushl %eax + + post_code(0x23) + + call stage1_main + + post_code(0x2f) +error: + hlt + jmp error + +mtrr_table: + /* Fixed MTRRs */ + .word 0x250, 0x258, 0x259 + .word 0x268, 0x269, 0x26A + .word 0x26B, 0x26C, 0x26D + .word 0x26E, 0x26F + /* Variable MTRRs */ + .word 0x200, 0x201, 0x202, 0x203 + .word 0x204, 0x205, 0x206, 0x207 + .word 0x208, 0x209, 0x20A, 0x20B + .word 0x20C, 0x20D, 0x20E, 0x20F +mtrr_table_end: +
Added: trunk/coreboot-v2/src/cpu/intel/model_6fx/cache_as_ram_disable.c =================================================================== --- trunk/coreboot-v2/src/cpu/intel/model_6fx/cache_as_ram_disable.c (rev 0) +++ trunk/coreboot-v2/src/cpu/intel/model_6fx/cache_as_ram_disable.c 2008-10-29 04:48:44 UTC (rev 3702) @@ -0,0 +1,111 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include "cpu/x86/car/copy_and_run.c" + +void real_main(unsigned long bist); + +void stage1_main(unsigned long bist) +{ + unsigned int cpu_reset = 0; + +#if USE_FALLBACK_IMAGE == 1 + /* Is this a deliberate reset by the bios */ + if (bios_reset_detected() && last_boot_normal()) { + goto normal_image; + } else { + /* This is the primary cpu how should I boot? */ + check_cmos_failed(); + if (do_normal_boot()) { + goto normal_image; + } + else { + goto fallback_image; + } + } + normal_image: + __asm__ volatile ("jmp __normal_image" + : /* outputs */ + : "a" (bist) /* inputs */ + ); + fallback_image: +#endif + + real_main(bist); + + /* No servicable parts below this line .. */ + + { + /* Check value of esp to verify if we have enough rom for stack in Cache as RAM */ + unsigned v_esp; + __asm__ volatile ( + "movl %%esp, %0\n\t" + : "=a" (v_esp) + ); + printk_spew("v_esp=%08x\r\n", v_esp); + } + +cpu_reset_x: + + printk_spew("cpu_reset = %08x\r\n",cpu_reset); + + if(cpu_reset == 0) { + print_spew("Clearing initial memory region: "); + } + print_spew("No cache as ram now - "); + + /* store cpu_reset to ebx */ + __asm__ volatile ( + "movl %0, %%ebx\n\t" + ::"a" (cpu_reset) + ); + + if(cpu_reset==0) { +#define CLEAR_FIRST_1M_RAM 1 +#include "cache_as_ram_post.c" + } else { +#undef CLEAR_FIRST_1M_RAM +#include "cache_as_ram_post.c" + } + + __asm__ volatile ( + /* set new esp */ /* before _RAMBASE */ + "subl %0, %%ebp\n\t" + "subl %0, %%esp\n\t" + ::"a"( (DCACHE_RAM_BASE + DCACHE_RAM_SIZE)- _RAMBASE ) + ); + + { + unsigned new_cpu_reset; + + /* get back cpu_reset from ebx */ + __asm__ volatile ( + "movl %%ebx, %0\n\t" + :"=a" (new_cpu_reset) + ); + + /* Copy and execute coreboot_ram */ + copy_and_run(new_cpu_reset); + /* We will not return */ + } + + print_debug("sorry. parachute did not open.\r\n"); +}
Added: trunk/coreboot-v2/src/cpu/intel/model_6fx/cache_as_ram_post.c =================================================================== --- trunk/coreboot-v2/src/cpu/intel/model_6fx/cache_as_ram_post.c (rev 0) +++ trunk/coreboot-v2/src/cpu/intel/model_6fx/cache_as_ram_post.c 2008-10-29 04:48:44 UTC (rev 3702) @@ -0,0 +1,132 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + + __asm__ volatile ( + + "movb $0x30, %al\noutb %al, $0x80\n" + + /* Disable Cache */ + "movl %cr0, %eax\n" + "orl $(1 << 30), %eax\n" + "movl %eax, %cr0\n" + + "movb $0x31, %al\noutb %al, $0x80\n" + + /* Disable MTRR */ + "movl $MTRRdefType_MSR, %ecx\n" + "rdmsr\n" + "andl $(~(1 << 11)), %eax\n" + "wrmsr\n" + + "movb $0x32, %al\noutb %al, $0x80\n" + + "invd\n" +#if 0 + "xorl %eax, %eax\n" + "xorl %edx, %edx\n" + "movl $MTRRphysBase_MSR(0), %ecx\n" + "wrmsr\n" + "movl $MTRRphysMask_MSR(0), %ecx\n" + "wrmsr\n" + "movl $MTRRphysBase_MSR(1), %ecx\n" + "wrmsr\n" + "movl $MTRRphysMask_MSR(1), %ecx\n" + "wrmsr\n" +#endif + + "movb $0x33, %al\noutb %al, $0x80\n" +#ifdef CLEAR_FIRST_1M_RAM + "movb $0x34, %al\noutb %al, $0x80\n" + /* Enable Write Combining and Speculative Reads for the first 1MB */ + "movl $MTRRphysBase_MSR(0), %ecx\n" + "movl $(0x00000000 | MTRR_TYPE_WRCOMB), %eax\n" + "xorl %edx, %edx\n" + "wrmsr\n" + "movl $MTRRphysMask_MSR(0), %ecx\n" + "movl $(~(1024*1024 -1) | (1 << 11)), %eax\n" + "movl $0x0000000f, %edx\n" // 36bit address space + "wrmsr\n" + "movb $0x35, %al\noutb %al, $0x80\n" +#endif + + /* Enable Cache */ + "movl %cr0, %eax\n" + "andl $~( (1 << 30) | (1 << 29) ), %eax\n" + "movl %eax, %cr0\n" + + "movb $0x36, %al\noutb %al, $0x80\n" +#ifdef CLEAR_FIRST_1M_RAM + + /* Clear first 1MB of RAM */ + "movl $0x00000000, %edi\n" + "cld\n" + "xorl %eax, %eax\n" + "movl $((1024*1024) / 4), %ecx\n" + "rep stosl\n" + + "movb $0x37, %al\noutb %al, $0x80\n" +#endif + + /* Disable Cache */ + "movl %cr0, %eax\n" + "orl $(1 << 30), %eax\n" + "movl %eax, %cr0\n" + + "movb $0x38, %al\noutb %al, $0x80\n" + + /* Enable Write Back and Speculative Reads for the first 1MB */ + "movl $MTRRphysBase_MSR(0), %ecx\n" + "movl $(0x00000000 | MTRR_TYPE_WRBACK), %eax\n" + "xorl %edx, %edx\n" + "wrmsr\n" + "movl $MTRRphysMask_MSR(0), %ecx\n" + "movl $(~(1024*1024 -1) | (1 << 11)), %eax\n" + "movl $0x0000000f, %edx // 36bit address space\n" + "wrmsr\n" + + "movb $0x39, %al\noutb %al, $0x80\n" + + /* And Enable Cache again after setting MTRRs */ + "movl %cr0, %eax\n" + "andl $~( (1 << 30) | (1 << 29) ), %eax\n" + "movl %eax, %cr0\n" + + "movb $0x3a, %al\noutb %al, $0x80\n" + + /* Enable MTRR */ + "movl $MTRRdefType_MSR, %ecx\n" + "rdmsr\n" + "orl $(1 << 11), %eax\n" + "wrmsr\n" + + "movb $0x3b, %al\noutb %al, $0x80\n" + + /* Enable prefetchers */ + "movl $0x01a0, %eax\n" + "rdmsr\n" + "andl $~((1 << 9) | (1 << 19)), %eax\n" + "andl $~((1 << 5) | (1 << 7)), %edx\n" + "wrmsr\n" + + /* Invalidate the cache again */ + "invd\n" + "movb $0x3c, %al\noutb %al, $0x80\n" + );
Added: trunk/coreboot-v2/src/cpu/intel/model_6fx/model_6fx_init.c =================================================================== --- trunk/coreboot-v2/src/cpu/intel/model_6fx/model_6fx_init.c (rev 0) +++ trunk/coreboot-v2/src/cpu/intel/model_6fx/model_6fx_init.c 2008-10-29 04:48:44 UTC (rev 3702) @@ -0,0 +1,94 @@ +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <string.h> +#include <cpu/cpu.h> +#include <cpu/x86/mtrr.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/lapic.h> +#include <cpu/intel/microcode.h> +#include <cpu/intel/hyperthreading.h> +#include <cpu/x86/cache.h> +#include <cpu/x86/mtrr.h> + +static const uint32_t microcode_updates[] = { + // #include "microcode_m206e839.h" + /* Dummy terminator */ + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, +}; + +static inline void strcpy(char *dst, char *src) +{ + while (*src) *dst++ = *src++; +} + +static void fill_processor_name(char *processor_name) +{ + struct cpuid_result regs; + char temp_processor_name[49]; + char *processor_name_start; + unsigned int *name_as_ints = (unsigned int *)temp_processor_name; + int i; + + for (i=0; i<3; i++) { + regs = cpuid(0x80000002 + i); + name_as_ints[i*4 + 0] = regs.eax; + name_as_ints[i*4 + 1] = regs.ebx; + name_as_ints[i*4 + 2] = regs.ecx; + name_as_ints[i*4 + 3] = regs.edx; + } + + temp_processor_name[48] = 0; + + /* Skip leading spaces */ + processor_name_start = temp_processor_name; + while (*processor_name_start == ' ') + processor_name_start++; + + memset(processor_name, 0, 49); + strcpy(processor_name, processor_name_start); +} + +static void model_6ex_init(device_t cpu) +{ + char processor_name[49]; + + /* Turn on caching if we haven't already */ + x86_enable_cache(); + + /* Update the microcode */ + intel_update_microcode(microcode_updates); + + /* Print processor name */ + fill_processor_name(processor_name); + printk_info("CPU: %s.\n", processor_name); + + /* Setup MTRRs */ + x86_setup_mtrrs(36); + x86_mtrr_check(); + + /* Enable the local cpu apics */ + setup_lapic(); + + /* Start up my cpu siblings */ + intel_sibling_init(cpu); +} + +static struct device_operations cpu_dev_ops = { + .init = model_6ex_init, +}; + +static struct cpu_device_id cpu_table[] = { + { X86_VENDOR_INTEL, 0x06f0 }, /* Intel Core 2 Solo/Core Duo */ + { X86_VENDOR_INTEL, 0x06f6 }, /* Intel Core 2 Solo/Core Duo */ + { 0, 0 }, +}; + +static const struct cpu_driver driver __cpu_driver = { + .ops = &cpu_dev_ops, + .id_table = cpu_table, +}; +
Modified: trunk/coreboot-v2/src/cpu/intel/socket_mFCPGA478/Config.lb =================================================================== --- trunk/coreboot-v2/src/cpu/intel/socket_mFCPGA478/Config.lb 2008-10-29 04:46:52 UTC (rev 3701) +++ trunk/coreboot-v2/src/cpu/intel/socket_mFCPGA478/Config.lb 2008-10-29 04:48:44 UTC (rev 3702) @@ -2,3 +2,5 @@ object socket_mFCPGA478.o dir /cpu/intel/model_69x dir /cpu/intel/model_6dx +dir /cpu/intel/model_6ex +dir /cpu/intel/model_6fx
Added: trunk/coreboot-v2/src/cpu/intel/socket_mPGA478/Config.lb =================================================================== --- trunk/coreboot-v2/src/cpu/intel/socket_mPGA478/Config.lb (rev 0) +++ trunk/coreboot-v2/src/cpu/intel/socket_mPGA478/Config.lb 2008-10-29 04:48:44 UTC (rev 3702) @@ -0,0 +1,4 @@ +config chip.h +object socket_mPGA478.o +dir /cpu/intel/model_69x +dir /cpu/intel/model_6dx
Added: trunk/coreboot-v2/src/cpu/intel/socket_mPGA478/chip.h =================================================================== --- trunk/coreboot-v2/src/cpu/intel/socket_mPGA478/chip.h (rev 0) +++ trunk/coreboot-v2/src/cpu/intel/socket_mPGA478/chip.h 2008-10-29 04:48:44 UTC (rev 3702) @@ -0,0 +1,4 @@ +extern struct chip_operations cpu_intel_socket_mPGA478_ops; + +struct cpu_intel_socket_mPGA478_config { +};
Added: trunk/coreboot-v2/src/cpu/intel/socket_mPGA478/socket_mPGA478.c =================================================================== --- trunk/coreboot-v2/src/cpu/intel/socket_mPGA478/socket_mPGA478.c (rev 0) +++ trunk/coreboot-v2/src/cpu/intel/socket_mPGA478/socket_mPGA478.c 2008-10-29 04:48:44 UTC (rev 3702) @@ -0,0 +1,7 @@ +#include <device/device.h> +#include "chip.h" + + +struct chip_operations cpu_intel_socket_mPGA478_ops = { + CHIP_NAME("Socket mPGA478 CPU") +};
Modified: trunk/coreboot-v2/src/cpu/x86/car/copy_and_run.c =================================================================== --- trunk/coreboot-v2/src/cpu/x86/car/copy_and_run.c 2008-10-29 04:46:52 UTC (rev 3701) +++ trunk/coreboot-v2/src/cpu/x86/car/copy_and_run.c 2008-10-29 04:48:44 UTC (rev 3702) @@ -72,7 +72,7 @@ __asm__ volatile ( "cli\n\t" "leal _iseg, %edi\n\t" - "jmp %edi\n\t" + "jmp *%edi\n\t" );
}
Modified: trunk/coreboot-v2/src/cpu/x86/lapic/lapic_cpu_init.c =================================================================== --- trunk/coreboot-v2/src/cpu/x86/lapic/lapic_cpu_init.c 2008-10-29 04:46:52 UTC (rev 3701) +++ trunk/coreboot-v2/src/cpu/x86/lapic/lapic_cpu_init.c 2008-10-29 04:48:44 UTC (rev 3702) @@ -437,6 +437,10 @@ #define cpus_ready_for_init() do {} while(0) #endif
+#if HAVE_SMI_HANDLER +void smm_init(void); +#endif + void initialize_cpus(struct bus *cpu_bus) { struct device_path cpu_path; @@ -457,14 +461,18 @@ cpu_path.type = DEVICE_PATH_CPU; cpu_path.u.cpu.id = 0; #endif - + /* Find the device structure for the boot cpu */ info->cpu = alloc_find_dev(cpu_bus, &cpu_path);
#if CONFIG_SMP == 1 copy_secondary_start_to_1m_below(); // why here? In case some day we can start core1 in amd_sibling_init #endif - + +#if HAVE_SMI_HANDLER + smm_init(); +#endif + cpus_ready_for_init();
#if CONFIG_SMP == 1 @@ -477,7 +485,6 @@ /* Initialize the bootstrap processor */ cpu_initialize();
- #if CONFIG_SMP == 1 #if SERIAL_CPU_INIT == 1 start_other_cpus(cpu_bus, info->cpu); @@ -486,6 +493,5 @@ /* Now wait the rest of the cpus stop*/ wait_other_cpus_stop(cpu_bus); #endif - }
-
svn＠coreboot.org