coreboot October 2016

coreboot@coreboot.org

55 participants
148 discussions

Re: [coreboot] Microcode question ?
by Riko Ho 19 Oct '16

19 Oct '16

Ok, it means, I need to use microcode for LGA775 otherwise it will not work, please correct me ? On 20/10/2016 1:51 AM, ron minnich wrote: > > > On Wed, Oct 19, 2016 at 9:36 AM Vasilief <vazopadry(a)gmail.com > <mailto:vazopadry@gmail.com>> wrote: > > On 10/18/2016 10:31 AM, Stefan Reinauer wrote: > > * Riko Ho <antonius.riko(a)gmail.com > <mailto:antonius.riko@gmail.com>> [161017 02:18]: > >> Is it ok if I'm not including microcode updates ? > > > > It might, or might not. On the i945/946 it probably is ok. A lot of > > modern CPUs can't boot successfully anymore without loading > microcode. > > Most modern ARM, MIPS, and AVR CPUs can. > > > > OK, then, although Stefan's meaning is pretty obvious, we can say it > this way: For those CPUs that have microcode, many can not boot > successfully without loading up to date microcode. For those CPUs that > don't have microcode, this question won't appear in the menuconfig. > > Therefore, if you see this question, you have a CPU with microcode. In > many cases, if you say no, you may see troubles with your hardware. In > some rare cases the CPU can't even configure memory correctly. > > I hope that's sufficiently clear? > > ron > >

2 1

[Broadwell-DE] camelbackmountain_fsp project hang 7a/95
by James_Lee 19 Oct '16

19 Oct '16

Hello All, My platform is Intel camelback CRB, I use coreboot +intel FSP, But hang on 7a or 95, please see below log, and attach .config, I have enable serial irq conutine mode, have some guys know the root cause? Thanks. Best Regards -James Hide devices in Bus:255 Notify: PPI Guid: 30CFE3E7-3DE1-4586-BE20-DEABA1B3B793, Peim notify entry point: 7F7417E7 FSP Notification Handler Returns : 0x00000000 FSP Got Notification. Notification Value : 0x00000040 FSP Ready To Boot ... Install PPI: 7CE88FB3-4BD7-4679-87A8-A8D8DEE50D2B Notify: PPI Guid: 7CE88FB3-4BD7-4679-87A8-A8D8DEE50D2B, Peim notify entry point: 7F7966F7 Notify: PPI Guid: 7CE88FB3-4BD7-4679-87A8-A8D8DEE50D2B, Peim notify entry point: 7F79991A IioLateInitialize ReadyToBoot Callback OnExitBootServices.. IioInit Late Secure the Platform (TXT).. Notify: PPI Guid: 7CE88FB3-4BD7-4679-87A8-A8D8DEE50D2B, Peim notify entry point: 7F766B1E Hiding ME Devices Notify: PPI Guid: 7CE88FB3-4BD7-4679-87A8-A8D8DEE50D2B, Peim notify entry point: 7F7727C4 MP ReadyToBootEvent() :: Set LOCK bit in PACKAGE_RAPL_LIMIT with value = 80078150 :: Set LOCK bit in CSR_SAPMCTL with value = B8002024 :: Set LOCK bit in CSR_DRAM_PLANE_POWER_LIMIT with value = 80000000 :: Set LOCK bit in P_STATE_LIMITS_PCU_FUN0_REG with value = 800000FF :: Set LOCK bit in CSR_DESIRED_CORES_PCU_FUN1_REG with value = 80000000 Done Write MAILBOX_BIOS_CMD_WRITE_PCU_MISC_CONFIG, data = 800002, SETUP Pl2SafetyNetEnable = 1 :: Read BIOS_MAILBOX_DATA_PCU_FUN1_REG back, data = 800002 :: Debug PpmSetBiosInitDone Read Data: 00000606 Detected 16 CPU threads Notify: PPI Guid: 7CE88FB3-4BD7-4679-87A8-A8D8DEE50D2B, Peim notify entry point: 7F7190F5 PciERWORegInit() Start PciERWORegInit() End ThermalLockDown() Start ThermalLockdown() - ThermalBaseB = 00000004 ThermalBaseB not set!! BDX-DE MCP PMSYNC enable = 1 InstallPchThermalLevelsProtocol() ASSERT DUMP: -> EBP:0x7F0FDE60 EIP:0x7F719305 -> EBP:0x7F0FDEBC EIP:0x7F718D2D -> EBP:0x7F0FDEF4 EIP:0x7F7190FD -> EBP:0x7F0FDF30 EIP:0x7F7FA29B -> EBP:0x7F0FDF5C EIP:0x7F7F309B -> EBP:0x7F0FDF84 EIP:0x7F7F2DC9 -> EBP:0x7F0FE8EC EIP:0xFFEB2239 -> EBP:0x7F0FF24C EIP:0xFFEB5584

2 1

Re: [coreboot] Disassemble i946 BIOS
by Sergej Ivanov 19 Oct '16

19 Oct '16

Hello, Try to begin with these two articles: 1) https://sites.google.com/site/pinczakko/pinczakko-s-guide-to-award-bios-rev… 2) https://sites.google.com/site/pinczakko/pinczakko-s-guide-to-ami-bios-rever… But keep in mind, that disassembly may take a lot of time (several years in worst case scenario). On Wed, Oct 19, 2016 at 10:54 AM, Riko Ho <antonius.riko(a)gmail.com> wrote: > Everyone, > > I've tested i945 code on i946 board and I can hear tuck tuck on its > buzzard, got FC 00 on serial...an repeat tuck tuck and nothing on serial.... > > I'm thinking on diassembling the code on i946 bios, I've downloaded a copy > on my computer as a *.bin. > and make a copy on another chip W39V040FCPZ....originaly from W39V040FB.. > now it's running with W39V040FCPZ (backup chip) I keep the original > chip.... > > Does anyone of you have a guide on disassemble this BIOS and retrieve the > init code of > i82946 ? > > Cheers > > -- > coreboot mailing list: coreboot(a)coreboot.org > https://www.coreboot.org/mailman/listinfo/coreboot >

1 0

Disassemble i946 BIOS
by Riko Ho 19 Oct '16

19 Oct '16

Everyone, I've tested i945 code on i946 board and I can hear tuck tuck on its buzzard, got FC 00 on serial...an repeat tuck tuck and nothing on serial.... I'm thinking on diassembling the code on i946 bios, I've downloaded a copy on my computer as a *.bin. and make a copy on another chip W39V040FCPZ....originaly from W39V040FB.. now it's running with W39V040FCPZ (backup chip) I keep the original chip.... Does anyone of you have a guide on disassemble this BIOS and retrieve the init code of i82946 ? Cheers

1 0

i946GZ test
by Riko Ho 18 Oct '16

18 Oct '16

Hello everyone.. I've put W39F040FCPZ on the board...but I can not see any messages on serial... I can hear tuck tuck on motherboard buzzard....repeatedly command : sudo putty /dev/ttyUSB0 -serial -sercfg 115200,8,n,1,N on the host What should I do next to debug ? Cheers

1 0

Re: [coreboot] WY1200LE with coreboot
by Stefan Reinauer 18 Oct '16

18 Oct '16

* Riko Ho <antonius.riko(a)gmail.com> [161018 09:31]: > Everyone, > > Does coreboot suport WY1200LE? it's using AMD geode, and I can't access its > BIOS...directly to windows and no BIOS key access .. AMD Geode GX support has been dropped a while ago. Older versions of coreboot will support the chip, but the mainboard was never supported. > Anyone has ported it ? No. > Cheers Stefan

1 0

Re: [coreboot] ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); ?
by Stefan Reinauer 18 Oct '16

18 Oct '16

* Riko Ho <antonius.riko(a)gmail.com> [161018 14:29]: > Everyone, > Does this line use port on 0x3F8 ? It uses whatever you configured for CONFIG_TTYS0_BASE in your .config. Stefan

1 0

ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); ?
by Riko Ho 18 Oct '16

18 Oct '16

Everyone, Does this line use port on 0x3F8 ? Cheers

1 0

WY1200LE with coreboot
by Riko Ho 18 Oct '16

18 Oct '16

Everyone, Does coreboot suport WY1200LE? it's using AMD geode, and I can't access its BIOS...directly to windows and no BIOS key access .. Anyone has ported it ? Cheers

1 0

Re: [coreboot] W39V040FB and W39V040FC?
by Stefan Reinauer 17 Oct '16

17 Oct '16

* Antonius Riko <antonius.riko(a)gmail.com> [161016 07:38]: > Everyone, > > Is W39V040FB compatible with W39V040FC ? > Cheers That depends on your uyse case. They have different erase block sizes. >From the data sheets: The W39V040FC is a 4-megabit, 3.3-volt only CMOS flash memory organized as 512K x 8 bits. For flexible erase capability, the 4Mbits of data are divided into 16 x 8 Kbytes pages and 6 x 64 Kbytes sectors or 8 x 64 Kbytes sectors. The W39V040FB is a 4-megabit, 3.3-volt only CMOS flash memory organized as 512K x 8 bits. For flexible erase capability, the 4Mbits of data are divided into 8 uniform sectors of 64 Kbytes Stefan

1 0

← Newer
1
2
3
4
5
6
7
8
9
...
15
Older →

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

2009

2008

2007

2006

2005

2004

2003

2002

coreboot October 2016