coreboot October 2016

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Virtualization Support X220
by Philipp Stanner 22 Oct '16

22 Oct '16

Is it possible to activate virtualization in the CPU somewhere? greetings

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Re: [coreboot] coreboot 4.5 release notes
by Riko Ho 22 Oct '16

22 Oct '16

Congratulation, Does qemu support i946 and ICH 7 simulation ? I have *.bin file, can I run on Qemu to see how it runs ? Or it must be physically run and tap via SerialICE ? Cheers On 21/10/2016 2:21 AM, Mike Banon wrote: > Coreboot 4.5 has been released quietly two days ago > (http://www.coreboot.org/downloads.html) , but we haven't seen the > release notes yet - either at http://blogs.coreboot.org/ or > elsewhere... > > According to http://www.coreboot.org/Supported_Motherboards page, so > far the following systems have been successfully tested with this > release: > > * Lenovo G505S - http://www.coreboot.org/Supported_Motherboards#lenovo.2Fg505s > * Lenovo X201 - http://www.coreboot.org/Supported_Motherboards#lenovo.2Fx201 > * Lenovo X220 - http://www.coreboot.org/Supported_Motherboards#lenovo.2Fx220 > * ASUS KFSN4-DRE - > http://www.coreboot.org/Supported_Motherboards#asus.2Fkfsn4-dre > * ASUS KGPE-D16 - http://www.coreboot.org/Supported_Motherboards#asus.2Fkgpe-d16 > * GIGABYTE GA-B75M-D3V - > http://www.coreboot.org/Supported_Motherboards#gigabyte.2Fga-b75m-d3v > * ASROCK E350M1 - http://www.coreboot.org/Supported_Motherboards#asrock.2Fe350m1 > * Google ( Acer ) C720 Chromebook - > http://www.coreboot.org/Supported_Motherboards#google.2Fpeppy > * Emulation QEMU x86 q35/ich9 - > http://www.coreboot.org/Supported_Motherboards#emulation.2Fqemu-q35 > > These successful test reports have been submitted after the quoted > Martin Roth's message below. Cheers! > > On Thu, Sep 29, 2016 at 6:44 PM, Martin Roth <gaumless at gmail.com> wrote: > >> Hi Everyone, >> We're coming up on our next coreboot release. We'd like to get the >> release done around the middle of October, but if there are issues in >> flight, we can delay it a bit. The release will absolutely happen before >> end of the month. >> >> If anyone is working on major changes that will affect all of coreboot, I'd >> request that they hold off until after the release so we have time to >> stabilize before the release. >> >> Please test platforms that you're interested in now, and as we get closer >> to the release. I'll create a list of validated platforms to include in >> the release notes, so if you want your favorite platform listed as having >> been tested in the release notes, please test it now, and post it to the >> board_status tracker. I'll release updated documentation for running >> board_status in the next few days. >> >> We've got a number of outstanding issues right now, both on the coreboot >> issue tracker, and in coverity. Please take a moment to look over these >> issues and if there are any in an area that you think you can fix, please >> take a swing at them. >>

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New on blogs.coreboot.org: Announcing coreboot 4.5
by WordPress 21 Oct '16

21 Oct '16

1 0

coreboot 4.5 release notes
by Mike Banon 20 Oct '16

20 Oct '16

Coreboot 4.5 has been released quietly two days ago (http://www.coreboot.org/downloads.html) , but we haven't seen the release notes yet - either at http://blogs.coreboot.org/ or elsewhere... According to http://www.coreboot.org/Supported_Motherboards page, so far the following systems have been successfully tested with this release: * Lenovo G505S - http://www.coreboot.org/Supported_Motherboards#lenovo.2Fg505s * Lenovo X201 - http://www.coreboot.org/Supported_Motherboards#lenovo.2Fx201 * Lenovo X220 - http://www.coreboot.org/Supported_Motherboards#lenovo.2Fx220 * ASUS KFSN4-DRE - http://www.coreboot.org/Supported_Motherboards#asus.2Fkfsn4-dre * ASUS KGPE-D16 - http://www.coreboot.org/Supported_Motherboards#asus.2Fkgpe-d16 * GIGABYTE GA-B75M-D3V - http://www.coreboot.org/Supported_Motherboards#gigabyte.2Fga-b75m-d3v * ASROCK E350M1 - http://www.coreboot.org/Supported_Motherboards#asrock.2Fe350m1 * Google ( Acer ) C720 Chromebook - http://www.coreboot.org/Supported_Motherboards#google.2Fpeppy * Emulation QEMU x86 q35/ich9 - http://www.coreboot.org/Supported_Motherboards#emulation.2Fqemu-q35 These successful test reports have been submitted after the quoted Martin Roth's message below. Cheers! On Thu, Sep 29, 2016 at 6:44 PM, Martin Roth <gaumless at gmail.com> wrote: > > Hi Everyone, > We're coming up on our next coreboot release. We'd like to get the > release done around the middle of October, but if there are issues in > flight, we can delay it a bit. The release will absolutely happen before > end of the month. > > If anyone is working on major changes that will affect all of coreboot, I'd > request that they hold off until after the release so we have time to > stabilize before the release. > > Please test platforms that you're interested in now, and as we get closer > to the release. I'll create a list of validated platforms to include in > the release notes, so if you want your favorite platform listed as having > been tested in the release notes, please test it now, and post it to the > board_status tracker. I'll release updated documentation for running > board_status in the next few days. > > We've got a number of outstanding issues right now, both on the coreboot > issue tracker, and in coverity. Please take a moment to look over these > issues and if there are any in an area that you think you can fix, please > take a swing at them. >

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Noob-questions
by Philipp Stanner 20 Oct '16

20 Oct '16

Hi cb-community, as everyone who owns a computer can subscribe to the list and there is no coreboot-forum, I presume that I'm allowed to ask a few primitive questions about the topic :) 1. Coreboot+Payload are only used to initialize the hardware and then give the complete control over the system to the OS, right? So once the OS booted no Coreboot or Payload-code is executed anymore? 2. Bios calls were used decades ago (so the OS hadn't to bring all the drivers) but aren't used by modern OS anymore, right? So why does Windows need seaBIOS to work? 3. If [1] is true, does that mean it's not important (for the user) if coreboot supports 100% of the boards hardware? Example: If I install coreboot on a machine and the wiki says "VGA not supported" this means that the monitor won't show anything - until the OS boots which uses it's own driver to address the monitor. Right? To be sure: As long as the OS boots successfully I don't really have to care if all system components work during the boot process? 4. In the traditional BIOS I can adjust lots of settings - overclock my CPU for example or enable Virtualization for KVM. How do I do this in coreboot? Beside of that: Great work guys, take care. Greetings Philipp

3 2

Re: [coreboot] [Broadwell-DE] camelbackmountain_fsp project hang 7a/95
by James_Lee 20 Oct '16

20 Oct '16

Hi York, This issue already fixed, the issue root cause is on Intel ME Setting need fine tune, Thanks. Best Regards -James From: James_Lee [mailto:james_lee@lannerinc.com] Sent: Thursday, October 20, 2016 9:06 AM To: 'Yang, York'; 'coreboot(a)coreboot.org' Subject: Re: [coreboot] [Broadwell-DE] camelbackmountain_fsp project hang 7a/95 Hi York, Thanks your respond; the FSP version is golden ver1.0 1/15/16, CPU SKU U0/Y0/V2 test result is same, and enable or not "Configure defaults for the Intel FSP package" item the test result also same, have other thing I can to try? Best Regards -James From: Yang, York [mailto:york.yang@intel.com] Sent: Thursday, October 20, 2016 4:38 AM To: James_Lee; coreboot(a)coreboot.org Subject: Re: [coreboot] [Broadwell-DE] camelbackmountain_fsp project hang 7a/95 >From the log, it looks like hang in FSP. What version of FSP did you use. Are you using U-0 stepping CPU? You may want to enable the "Configure defaults for the Intel FSP package" in menuconfig\Mainboard menu. / YoRK From: coreboot [mailto:coreboot-bounces@coreboot.org] On Behalf Of James_Lee Sent: Wednesday, October 19, 2016 3:59 AM To: coreboot(a)coreboot.org Subject: [coreboot] [Broadwell-DE] camelbackmountain_fsp project hang 7a/95 Hello All, My platform is Intel camelback CRB, I use coreboot +intel FSP, But hang on 7a or 95, please see below log, and attach .config, I have enable serial irq conutine mode, have some guys know the root cause? Thanks. Best Regards -James Hide devices in Bus:255 Notify: PPI Guid: 30CFE3E7-3DE1-4586-BE20-DEABA1B3B793, Peim notify entry point: 7F7417E7 FSP Notification Handler Returns : 0x00000000 FSP Got Notification. Notification Value : 0x00000040 FSP Ready To Boot ... Install PPI: 7CE88FB3-4BD7-4679-87A8-A8D8DEE50D2B Notify: PPI Guid: 7CE88FB3-4BD7-4679-87A8-A8D8DEE50D2B, Peim notify entry point: 7F7966F7 Notify: PPI Guid: 7CE88FB3-4BD7-4679-87A8-A8D8DEE50D2B, Peim notify entry point: 7F79991A IioLateInitialize ReadyToBoot Callback OnExitBootServices.. IioInit Late Secure the Platform (TXT).. Notify: PPI Guid: 7CE88FB3-4BD7-4679-87A8-A8D8DEE50D2B, Peim notify entry point: 7F766B1E Hiding ME Devices Notify: PPI Guid: 7CE88FB3-4BD7-4679-87A8-A8D8DEE50D2B, Peim notify entry point: 7F7727C4 MP ReadyToBootEvent() :: Set LOCK bit in PACKAGE_RAPL_LIMIT with value = 80078150 :: Set LOCK bit in CSR_SAPMCTL with value = B8002024 :: Set LOCK bit in CSR_DRAM_PLANE_POWER_LIMIT with value = 80000000 :: Set LOCK bit in P_STATE_LIMITS_PCU_FUN0_REG with value = 800000FF :: Set LOCK bit in CSR_DESIRED_CORES_PCU_FUN1_REG with value = 80000000 Done Write MAILBOX_BIOS_CMD_WRITE_PCU_MISC_CONFIG, data = 800002, SETUP Pl2SafetyNetEnable = 1 :: Read BIOS_MAILBOX_DATA_PCU_FUN1_REG back, data = 800002 :: Debug PpmSetBiosInitDone Read Data: 00000606 Detected 16 CPU threads Notify: PPI Guid: 7CE88FB3-4BD7-4679-87A8-A8D8DEE50D2B, Peim notify entry point: 7F7190F5 PciERWORegInit() Start PciERWORegInit() End ThermalLockDown() Start ThermalLockdown() - ThermalBaseB = 00000004 ThermalBaseB not set!! BDX-DE MCP PMSYNC enable = 1 InstallPchThermalLevelsProtocol() ASSERT DUMP: -> EBP:0x7F0FDE60 EIP:0x7F719305 -> EBP:0x7F0FDEBC EIP:0x7F718D2D -> EBP:0x7F0FDEF4 EIP:0x7F7190FD -> EBP:0x7F0FDF30 EIP:0x7F7FA29B -> EBP:0x7F0FDF5C EIP:0x7F7F309B -> EBP:0x7F0FDF84 EIP:0x7F7F2DC9 -> EBP:0x7F0FE8EC EIP:0xFFEB2239 -> EBP:0x7F0FF24C EIP:0xFFEB5584

1 0

Microcode question ?
by Riko Ho 20 Oct '16

20 Oct '16

Everyone, Is it ok if I'm not including microcode updates ? Please see the capture... I have done compiling for i946GZ, but not yet tested on the board....I have my spare flash chip only different type....on board is FB series, my spare chip is FC... Cheers Rick

5 6

MSI K9A2VM question?
by Riko Ho 20 Oct '16

20 Oct '16

Everyone, Does coreboot support MSI K9A2VM? It has AMD 780V northbridge and SB700 southbridge, Spec : https://www.msi.com/Motherboard/K9A2VMFD.html#hero-specification I need to find 8 pin SOIC socket for it... Cheers,

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Re: [coreboot] [Broadwell-DE] camelbackmountain_fsp project hang 7a/95
by James_Lee 20 Oct '16

20 Oct '16

Hi York, Thanks your respond; the FSP version is golden ver1.0 1/15/16, CPU SKU U0/Y0/V2 test result is same, and enable or not "Configure defaults for the Intel FSP package" item the test result also same, have other thing I can to try? Best Regards -James From: Yang, York [mailto:york.yang@intel.com] Sent: Thursday, October 20, 2016 4:38 AM To: James_Lee; coreboot(a)coreboot.org Subject: Re: [coreboot] [Broadwell-DE] camelbackmountain_fsp project hang 7a/95 >From the log, it looks like hang in FSP. What version of FSP did you use. Are you using U-0 stepping CPU? You may want to enable the "Configure defaults for the Intel FSP package" in menuconfig\Mainboard menu. / YoRK From: coreboot [mailto:coreboot-bounces@coreboot.org] On Behalf Of James_Lee Sent: Wednesday, October 19, 2016 3:59 AM To: coreboot(a)coreboot.org Subject: [coreboot] [Broadwell-DE] camelbackmountain_fsp project hang 7a/95 Hello All, My platform is Intel camelback CRB, I use coreboot +intel FSP, But hang on 7a or 95, please see below log, and attach .config, I have enable serial irq conutine mode, have some guys know the root cause? Thanks. Best Regards -James Hide devices in Bus:255 Notify: PPI Guid: 30CFE3E7-3DE1-4586-BE20-DEABA1B3B793, Peim notify entry point: 7F7417E7 FSP Notification Handler Returns : 0x00000000 FSP Got Notification. Notification Value : 0x00000040 FSP Ready To Boot ... Install PPI: 7CE88FB3-4BD7-4679-87A8-A8D8DEE50D2B Notify: PPI Guid: 7CE88FB3-4BD7-4679-87A8-A8D8DEE50D2B, Peim notify entry point: 7F7966F7 Notify: PPI Guid: 7CE88FB3-4BD7-4679-87A8-A8D8DEE50D2B, Peim notify entry point: 7F79991A IioLateInitialize ReadyToBoot Callback OnExitBootServices.. IioInit Late Secure the Platform (TXT).. Notify: PPI Guid: 7CE88FB3-4BD7-4679-87A8-A8D8DEE50D2B, Peim notify entry point: 7F766B1E Hiding ME Devices Notify: PPI Guid: 7CE88FB3-4BD7-4679-87A8-A8D8DEE50D2B, Peim notify entry point: 7F7727C4 MP ReadyToBootEvent() :: Set LOCK bit in PACKAGE_RAPL_LIMIT with value = 80078150 :: Set LOCK bit in CSR_SAPMCTL with value = B8002024 :: Set LOCK bit in CSR_DRAM_PLANE_POWER_LIMIT with value = 80000000 :: Set LOCK bit in P_STATE_LIMITS_PCU_FUN0_REG with value = 800000FF :: Set LOCK bit in CSR_DESIRED_CORES_PCU_FUN1_REG with value = 80000000 Done Write MAILBOX_BIOS_CMD_WRITE_PCU_MISC_CONFIG, data = 800002, SETUP Pl2SafetyNetEnable = 1 :: Read BIOS_MAILBOX_DATA_PCU_FUN1_REG back, data = 800002 :: Debug PpmSetBiosInitDone Read Data: 00000606 Detected 16 CPU threads Notify: PPI Guid: 7CE88FB3-4BD7-4679-87A8-A8D8DEE50D2B, Peim notify entry point: 7F7190F5 PciERWORegInit() Start PciERWORegInit() End ThermalLockDown() Start ThermalLockdown() - ThermalBaseB = 00000004 ThermalBaseB not set!! BDX-DE MCP PMSYNC enable = 1 InstallPchThermalLevelsProtocol() ASSERT DUMP: -> EBP:0x7F0FDE60 EIP:0x7F719305 -> EBP:0x7F0FDEBC EIP:0x7F718D2D -> EBP:0x7F0FDEF4 EIP:0x7F7190FD -> EBP:0x7F0FDF30 EIP:0x7F7FA29B -> EBP:0x7F0FDF5C EIP:0x7F7F309B -> EBP:0x7F0FDF84 EIP:0x7F7F2DC9 -> EBP:0x7F0FE8EC EIP:0xFFEB2239 -> EBP:0x7F0FF24C EIP:0xFFEB5584

1 0

Re: [coreboot] Microcode question ?
by ron minnich 20 Oct '16

20 Oct '16

On Wed, Oct 19, 2016 at 5:53 PM ron minnich <rminnich(a)gmail.com> wrote: > On Wed, Oct 19, 2016 at 4:50 PM Riko Ho <antonius.riko(a)gmail.com> wrote: > > Ok, it means, I need to use microcode for LGA775 otherwise it will not > work, please correct me ? > > > I can't honestly say. I talked to an expert about this yesterday and > THE EXPERT, NOT ME > pointed out that early sandybridge required the microcode update to work > at all, later ones did not. > sorry, I'm not the expert. Typo. ron

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coreboot October 2016