coreboot October 2016

coreboot@coreboot.org

55 participants
148 discussions

Re: [coreboot] Stops at 0xD2
by Stefan Reinauer 29 Oct '16

29 Oct '16

* Riko Ho <antonius.riko(a)gmail.com> [161026 03:36]: > Everyone, > > I tried to initialize UART on IT8718F and it stopped at 0xD2... > Here's the complete function, any clues ? Yes, there is a halt() right after the post_code(0xd2); so that is where your last post code is coming from. use superiotool (from coreboot/util) to dump the superio registers on a running system and compare them with what you write in there and the data sheet. Are you sure you are using the correct SuperIO driver? Stefan > > Cheers > =============== > void mainboard_romstage_entry(unsigned long bist) > { > int s3resume = 0, boot_mode = 0; > > if (bist == 0) > enable_lapic(); > > ich7_enable_lpc(); > post_code(0xD1); > /* Enable SuperIO PM */ > //lpc47m15x_enable_serial(PME_DEV, 0x680); > //lpc47m15x_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); /* 0x3f8 */ > //enable_dev(SERIAL_DEV); > //ite_conf_clkin();//needs a parameter, what is it ? > > /* > 04:24:31 AM) idwer: 24 or 48 MHz? > > (04:25:18 AM) idwer: how do you find out? run superiotool when > having booted with the vendor bios, and look at register > CR23 > */ > //ite_conf_clkin(CLKIN_DEV, ITE_UART_CLK_PREDIVIDE_24); > ite_conf_clkin(CLKIN_DEV, ITE_UART_CLK_PREDIVIDE_48); > > > ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); /* 0x3f8 */ > //printk(BIOS_DEBUG,"HELLO WORLD FROM COREBOOT BY RIKO HO...\n"); > //it8716f_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE); > it8718f_disable_reboot(GPIO_DEV); > /* Set up the console */ > console_init(); > post_code(0xD2); > printk(BIOS_DEBUG,"HELLO WORLD FROM COREBOOT ...\n"); > halt(); > post_code(0xD3); > > > > /* Halt if there was a built in self test failure */ > report_bist_failure(bist); > > if (MCHBAR16(SSKPD) == 0xCAFE) { > printk(BIOS_DEBUG, "soft reset detected.\n"); > boot_mode = 1; > } > > /* Perform some early chipset initialization required > * before RAM initialization can work > */ > i945_early_initialization(); > post_code(0xD4); > s3resume = southbridge_detect_s3_resume(); > > /* Enable SPD ROMs and DDR-II DRAM */ > enable_smbus(); > > #if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 > dump_spd_registers(); > #endif > > sdram_initialize(s3resume ? 2 : boot_mode, NULL); > > /* Perform some initialization that must run before stage2 */ > early_ich7_init(); > > /* This should probably go away. Until now it is required > * and mainboard specific > */ > rcba_config(); > > /* Chipset Errata! */ > fixup_i945_errata(); > > /* Initialize the internal PCIe links before we go into stage2 */ > i945_late_initialization(s3resume); > } > > -- > coreboot mailing list: coreboot(a)coreboot.org > https://www.coreboot.org/mailman/listinfo/coreboot >

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PSA: abandoning old patches (again)
by Stefan Reinauer 29 Oct '16

29 Oct '16

Hi, we're planning (as we have done in the past), to abandon patches that have been crowding up gerrit without any update in the last 18 months. The list of patches in question is https://review.coreboot.org/#/q/status:open+age:18months If you want to preserve any of those patches, please rebase them against current ToT, take them over, maintain them, or whatever, because I plan to abandon everything that is still in this list at the end of next week (November 4th) Stefan

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Re: [coreboot] i946GZ test
by Stefan Reinauer 29 Oct '16

29 Oct '16

* Riko Ho <antonius.riko(a)gmail.com> [161019 06:29]: > Hello everyone.. > > I've put W39F040FCPZ on the board...but I can not see any messages on > serial... > I can hear tuck tuck on motherboard buzzard....repeatedly > > command : sudo putty /dev/ttyUSB0 -serial -sercfg 115200,8,n,1,N on the host > > What should I do next to debug ? > > Cheers Use a scope or a bus analyzer to figure out whether you are executing code, and where you die. Check your SuperIO init code to see if you are doing the right thing. Stefan

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Global changing of IOT Power Ballance
by Zoran Stojsavljevic 27 Oct '16

27 Oct '16

Could not resist! https://www.qualcomm.com/news/releases/2016/10/27/qualcomm-acquire-nxp Tough (extremely) call for INTEL IOTG. Good Luck, INTEL IOTG! ;-) This will change IOT balance across The World. Coreboot folks, be prepared! Zoran

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Change-sets for AMD Stoney Ridge, unifying PI directories
by Paul Menzel 27 Oct '16

27 Oct '16

Dear coreboot folks, If you haven’t seen it yet, Marc uploaded change-sets for review adding support for AMD Stoney Ridge (if I am not mistaken) [1][2], he and Marshall worked on. Are the different AMD PI using devices different enough, to have one directory for each of them, or would it make sense to unify it? Thanks, Paul [1] https://review.coreboot.org/17139 [2] https://review.coreboot.org/#/q/owner:%22Marc+Jones%22+status:open

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[ANNOUNCE] SeaBIOS 1.10.0
by Kevin O'Connor 26 Oct '16

26 Oct '16

The 1.10.0 version of SeaBIOS has now been released. For more information on the release, please see: http://seabios.org/Releases New in this release: * Initial support for Trusted Platform Module (TPM) version 2.0 * Several USB XHCI timing fixes on real hardware * Support for "LSI MPT Fusion" scsi controllers on QEMU * Support for virtio devices mapped above 4GB * Several bug fixes and code cleanups For information on obtaining SeaBIOS, please see: http://seabios.org/Download ===== git shortlog -n rel-1.9.0..rel-1.10.0 ===== Kevin O'Connor (124): usb: Allow configuration of sigatt time (in etc/usb-time-sigatt) xhci: Check for device disconnects during USB2 reset polling sdcard: Only enable error_irq_enable for bits defined in SDHCI v1 spec sdcard: fix typo causing 32bit write to 16bit block_size field sdcard: Enable extra debugging on sdcard_waitw() timeout acpi_extract: Move main code to new function main() acpi_extract: Make the generated .hex files more human readable acpi_extract: Don't generate unused (and empty) q35-acpi-dsdt.hex file acpi: Don't build SSDT files on every build; store them in git acpi: Remove build check for iasl tpm: Move standard definitions from tcgbios.h to new file std/tcg.h util.h: Minor - HaveRunPost is in misc.c not resume.c tpm: Add "static" declaration to functions not used outside tcgbios.c tpm: Move code around in tcgbios.c tpm: Move error recovery from tpm_extend_acpi_log() to only caller tpm: Open code tpm_ipl() into callers tpm: Change tpm_add_measurement() to tpm_add_action() tpm: Move tpm_add_bootdevice() into callers tpm: Move tpm_start_option_rom_scan() and tpm_calling_int19h() into callers tpm: pcpes->event is a variable length array tpm: Don't pass entry_count around in parameters to/from tpm_extend_acpi_log() tpm: There is no need to pass pcrindex to hash_log_extend_event() tpm: Perform hashing separately from logging tpm: There is no need to pass event_length to hash/extend functions tpm: Avoid scatter-gather copying in build_and_send_cmd() tpm: Don't implement scatter-gather in transmit() tpm: Merge tpm_log_event() and tpm_extend_acpi_log() tpm: Merge tpm_log_extend_event() and tpm_extend(); extend before logging xhci: Wait for port enable even for USB3 devices xhci: Improve port status change debugging xhci: Disable slot on failed set_address command nmi: Don't try to switch onto extra stack in NMI handler scsi: Do not call printf() from scsi_is_ready() block: Report drive->sectors using "%u" instead of "%d" tpm: Add banner separating the TCG bios interface code from TCG menu code tpm: Avoid macro expansion of tpm request / response structs tpm: Simplify hardware probe and detection checks tpm: Add wrapper function tpmhw_set_timeouts() tpm: Move TPM hardware functions from tcgbios.c to hw/tpm_drivers.c tpm: Rework TPM interface shutdown support tpm: Simplify tcpa probe tpm: Introduce tpm_get_capability() helper function tpm: Eliminate response buffer parameter from build_and_send_cmd() tpm: Don't return a status from external bios measurement functions tpm: No need to check the return status of measurements tpm: Don't call tpm_set_failure() from tpm_log_extend_event() tpm: Don't use 16bit BIOS return codes in build_and_send_cmd() tpm: Don't use 16bit BIOS return codes in tpm_log_event() tpm: Don't use 16bit BIOS return codes in tpmhw_* functions tpm: Don't use 16bit BIOS return codes in TPM menu functions usb: Remove usbdev->slotid field coreboot: Check for unaligned cbfs header resume: Make KVM soft reboot loop detection more flexible post: Always set HaveRunPost prior to setting any other global variable kbd: Don't treat scancode and asciicode as separate values kbd: Refactor capslock and numlock handling ehci: Only delay UHCI/OHCI port scan until after EHCI setup completes usb: Eliminate USB controller setup thread pci: Add helper functions for internal driver BAR handling ahci: Convert to new PCI BAR helper functions ata: Convert to new PCI BAR helper functions esp-scsi: Convert to new PCI BAR helper functions lsi-scsi: Convert to new PCI BAR helper functions megasas: Convert to new PCI BAR helper functions pvscsi: Convert to new PCI BAR helper functions sdcard: Convert to new PCI BAR helper functions ehci: Convert to new PCI BAR helper functions ohci: Convert to new PCI BAR helper functions uhci: Convert to new PCI BAR helper functions xhci: Convert to new PCI BAR helper functions virtio: Convert to new PCI BAR helper functions pci: Consistently set pci->have_drivers for devices with internal drivers pci: Implement '%pP' printf handler for 'struct pci_device' pointers pci: Move code in pci.c that is specific to pciinit.c to pciinit.c pci: Split low-level pci code from higher-level 'struct pci_device' code scsi: Always use MAXDESCSIZE when building drive description block: Move drive setup to new function block_setup() tpm: Unify tpm_fill_hash()/tpm_log_extend_event() and use in BIOS interface docs: Note release date of 1.9.1 build: fix .text section address alignment tpm: Write logs in TPM 2 format mpt-scsi: Declare 'int i' outside of for loop for older compilers block: Move send_disk_op() from block.c to disk.c disk: Avoid stack_hop() path if already on the extra stack optionroms: Drop support for CONFIG_OPTIONROMS_DEPLOYED shadow: Batch PCI config writes virtio: Use threads when scanning for virtio devices scsi: Launch a thread when scanning for drives in the scsi drivers docs: Note release date of 1.9.2 usb-xhci: Remove unused const variables tcgbios: Remove unused const variable vgabios: Remove special case of dh==0xff in handle_1013() vgabios: Don't check for special case of page==0xff on external calls vgabios: Simplify set_cursor_pos() docs: Note release date of 1.9.3 vgabios: Simplify scroll logic blockcmd: CMD_SCSI op is only used in 32bit mode swcursor: Move swcursor code from vgafb.c to new file swcursor.c swcursor: Concentrate swcursor logic in swcursor.c vgafb: Move header definitions from vgabios.h to new file vgafb.h vgainit: Move video param setup to stdvga_build_video_param() vgautil: Add new header file with misc function and variable definitions vgautil: Move generic definitions from stdvga.h to vgautil.h vgautil: Move definitions from cbvga.h and clext.h to vgautil.h version: Update header files now that version.c is not auto generated checkstack: Handle conditional checks at start of functions tpm: Append to TPM2 log the hashes used for PCR extension ps2: Remove stale check for timeout warning on reset pic: The default hardware interrupt handlers should not take a parameter kbd: Implement 101-key keyboard keycode mapping kbd: Implement extended keycode mappings for keypad-enter and keypad-/ kbd: Suppress keys without mappings kbd: Merge bda->kbd_flag0 and bda->kbd_flag1 kbd: Extract out shift flag setting into new function kbd: Move checking for special keys in __process_keys() into switch kbd: Ignore fake shift keys usb-hid: Generate Ctrl+Break and Alt+SysReq keys kbd: Generate interrupt events for SysReq, PrtScr, and Break post: Map int 0x05 to entry point kbd: Move extended and release events out of special key detection switch build: Be sure to also include out/*.d in Makefile smp: consolidate CPU APIC ID detection and accounting build: Add -fno-pie to the gcc flags when available docs: Note v1.10.0 release Stefan Berger (34): tpm: Temporarily deactivate the TPM in case of failure tpm: Refactor function building TPM commands tpm: Refactor the parameters being passed to tpm_extend_acpi_log tpm: Refactor hash_log_event BIOS interface function tpm: Refactor hash_log_extend_event tpm: fix compiler warning with older gcc versions tpm: Drop code using the TPM for sha1 tpm: Set timeouts and durations to microsecond values tpm: Cache all log related pointers in tpm_state tpm: Refactor pass_through_to_tpm tpm: Rename remaining interrupt functions tpm: Remove check for working TPM from TPM interrupt handler tpm: Check length parameter of the array tpm: Add a menu for TPM configuration tpm: Copy digest into HashLogExentEvent response tpm: Move assert_physical_presence and dependencies tpm: Add support for harware physical presence tpm: Rework the assertion of physical presence tpm: Remove usage of PP_CMD_ENABLE from all but one place tpm: Do not set TPM in failure mode if menu command fails tpm: Extend TPM TIS with TPM 2 support. tpm: Factor out tpm_extend tpm: Prepare code for TPM 2 functions tpm: Implement tpm20_startup and tpm20_s3_resume tpm: Implement tpm20_set_timeouts tpm: Implement tpm20_prepboot tpm: Implement tpm20_extend tpm: Implement tpm20_menu tpm: Implement TPM 2's tpm_set_failure part tpm: Filter TPM commands in passthrough API tpm: Retrieve the PCR Bank configuration tpm: Restructure tpm20_extend to use buffer and take hash as parameter tpm: Refactor tpml_digest_values_sha1 structure tpm: Extend tpm20_extend to support extending to multiple PCR banks Gerd Hoffmann (4): ahci: set transfer mode according to the capabilities of connected drive virtio: uninline _vp_{read,write} virtio: pci cfg access virtio: fix virtio-pci Igor Mammedov (3): paravirt: disable legacy bios tables in case of more than 255 CPUs add helpers to read etc/boot-cpus at resume time support booting with more than 255 CPUs Dana Rubin (2): pvscsi: Fix incorrect arguments order in call to memalign_low pvscsi: Use high memory for rings Marcel Apfelbaum (2): fw/pci: do not automatically allocate IO region for PCIe bridges fw/pci: add Q35 S3 support Alex Williamson (1): fw/pci: Add support for mapping Intel IGD via QEMU Cao jin (1): Fix comment typo Cole Robinson (1): biostables: Support SMBIOS 2.6+ UUID format Don Slutz (1): Support for booting from LSI Logic LSI53C1030, SAS1068, SAS1068e Haozhong Zhang (1): fw/msr_feature_control: add support to set MSR_IA32_FEATURE_CONTROL Matt DeVillier (1): sdcard: skip detection of PCI sdhci controllers if etc/sdcard used Paolo Bonzini (1): smp: restore MSRs on S3 resume Piotr Król (1): docs: fix various typos and inconsistency Roger Pau Monne (1): build: fix typo in buildversion.py Zheng Bao (1): splash: Skip the RGB555 mode

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KGPE-D16 SR-IOV support?
by Taiidan＠gmx.com 26 Oct '16

26 Oct '16

Hello I am wondering if this motherboard supports with coreboot SR-IOV and PCI-e Access Control Services (needed for secure sr-iov apparently) Information: http://kb.vmware.com/selfservice/microsites/search.do?language=en_US&cmd=di… http://www.intel.com/content/www/us/en/pci-express/pci-sig-sr-iov-primer-sr… ACS Spec: http://www.pcisig.com/specifications/pciexpress/specifications/ECN_access_c… It would be nice if information like this was added to the supported motherboards page as these days sr-iov is a pretty basic server feature.

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Building of payloads fails, SeaBIOS fails in qemu
by Philipp Stanner 26 Oct '16

26 Oct '16

Hi, according the first problem I've already created a ticket. I (and others in IRC) failed building rom-images using nconfig+make with other payloads than seabios. See the txt-files in the ticket system; make reports something like: "Rule for filo unkown". The second problem is that a self-build seabios doesn't boot in qemu (again for me and people in IRC). While the default-qemu-bios boots any diskimage just fine, -boot build/coreboot.rom causes seabios to start fine (at first), too. But when it actually tries to boot from an image, the errors: "Graphic initalization failed. Error setting up gfxboot. boot: Could not allocate memory." If I build a new virtual harddrive, install Ubuntu there (using qemu's default bios) then I'm able to start the new image using my self-build bios.

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Update AMD microcode
by Loic 26 Oct '16

26 Oct '16

-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Hi, Looking in debian, I look that AMD microcode are outdated in coreboot: https://packages.debian.org/sid/amd64-microcode microcode_amd_fam15h.bin (md5sum: ee3f0f46936aa1788dc31ca3487e0ff3) November 2014 in coreboot. microcode_amd_fam15h.bin (md5sum: 2384ef1d8ec8ca3930b62d82ea5a3813) March 2016 in "amd64-microcode_3.20160316.2_amd64.deb". Description: For AMD Family 15h Processors to fix bugs in prior microcode patch Example? If only AMD was willing to give the code to the versions that are no longer sold... - -- Best regards, Loic -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQYcBAEBAgAGBQJYEF9BAAoJEOU2PAjT6toDlqkwAIwilXii2rSBcu0iwz/GqR/T qUBJlb8GNl0vZRvQWAa2Yshl+ctFAuu/iVeBFtmRGD6A+wvK1Wg70aMOynEq2BKt lHWwbO8DNNsHcORiVWFb/F0iuhxXVYb9zHRX8WErpxWw4uw1Zcx9Slho+RckVvWg FH0T7x0+fNjDovt/elTHKVrumV8hJGWcbBJ2QoO0SYqTa3EFO9K9RDjY2ejucuBC 4Dp7/Q+FnwXMhi5SRmeIv6eLBkDM1BnPWSM8I38tsTlLgd6OSsxjk0dmPQ03LK1Q sGVOQAIZdDrzClQzkS96gIPT8cBgftdAul1PEEvuwESBSwVdsFUTmL9um9frRlM2 +UU9j1i2n3xW0Pb6jKCX5s0mFiwX/8GYdH5lH18rdh2VBGoeLxHWHnzbmjf8Kz2I 4xe+FNc/whAkdUqYgitxV7XUjBcsM/6LS9PpvtpLlQK09lzBuRBBSkGCorcU7KQE 68xCbzqgEZa7P71olwvkGJt5RQIVtJlMd/Yy0xkM++tzW+2wt4XjP5qx8sDNsZZI 1HVdJMeU3ZwSWEIe3bXOjl7xYuXnJ4rLgQ2sYhwGlQUHrgFSuINpX3QQw8tbgY1t /hnpxP/vpzLCmTAR6lc9Z8IxzhSJ4fkVPwIvdwAuLFf6ICoZ9YYiDT/gOmuopTot N6grR3IeimwGhZCQ/ImubXf347fzROFHD32sHAYkKPhDdRXAonTBB/OiLMkck8lH rZ+Ne5VPhjf5PxFTUjz/mn3IoTWOEHb72a2o0+1Hwzn12cOcXVnpXXBUcmzfmQhH GksZCcjUy6H9xYG2XocSH1p2bRba+Nv+LhylzsDafh5YTxGJLW54aPU/ojsqwVKD grNugQdy+DZBllJ6P6UocWyjDrUyR7WOW2QfkQ4ku9WrgHbMI3W3e7yyVfL1TdOw l3DmaUsx+p0ZSpyJrFwvHBZgI09w7q9PTym/qZFqcI+5yOi0pg7UdFhj/77U1a7t N2ust5D9215nNe8Ci+OeqHzXA1I74E3R2yEjG4u5HAaz5TVE65/vW/HSxVNy8OMC Y//zw6Ei2Cbrg+xkBxagZ0bpyhMffTc4i0sOio7BW1dmzfBZ7HHNCU1MNByn36y0 nMlby6uKZOq9pGOtq9J4rjGeuZGat4ET2LSWYtEPVzjEmBrwzZzJclEFmxYsOPGU sL9L3sGK4VbGbDGuaa/kD9du0lJ/cA1MaEzcDdJLOpMAoQnMxpzTey4pPUgErS7c 0v/7P35T7Mdq8723Gy585a40Q469Q/h3/gySbgSzwa3fF58nePIeTBtDRGKLOtkD v3aTXJPvs9Cz7TU+2drinniSETkUB7H2iqytcAfR1zAkP5bw2NtrwOlqt4JrDGwb tL3WQ8/vy2Ck0mzsUQfnapkX7pDvv2PXX29LQK95I3tAFFQRioZD/9J+HMfxwJMs pKWb/M2bbzUaUprWMBCqdm6n3asbdQoGU1e797j1f0/hhkeVeekDf0BNnjuV5kJv Sf7SKhlndYrZu4OBvG6/lTmA2h79wyynQPQ1TmrhB08yuzB59kb56us+sFBhXn2B 3l9HkHGi77AMuh9Hat3TwH2guF+r8SNAy0hBLEDNOgvuinErV+xL6ZIEX7FqgHlT +xyaKCK8UaENSPHjaz6JYy1aY41HxDmwpcqTp0T8+fOAucOKCIOPjyW3KD6JoBfK 3uTemwvdAIkF/KqxOXLTtACR5pm9ZGehIqdY3RBi/TCkgbn1d0Wph6BceP9vZM6j RwFEVIewpCmwRX/QMsaCTi9shkZjKMnLwAl0yrvy5q5mL658L7cKiJxM0lRx+iHJ oXvunWyKb1H3hXCsNZN9BoZFWjSaznMf1u35Famg8FXmLgC8VweIxGHc3pShWZd5 xBgJvbYAIV59RqeGDkHXS+CZVdYaR6d4cM5j05r3ibUn5kREXwCQPTmrAJPSvVto akglAMSSL1hFbvM9Us93h5wcIfzefoZoi1OwuPMZNqR+YKaTsvEj2msSIemzT8cI mV7YA4FY4yjAkDv2Ayh99M1CsJDS3MpawbuhW7BF2Q== =NGBF -----END PGP SIGNATURE-----

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Re: [coreboot] Stops at 0xD2
by Riko Ho 26 Oct '16

26 Oct '16

Which superIO register should we read to make sure LPC bus communication to superio works? On Wed, Oct 26, 2016 at 9:58 AM, Kyösti Mälkki <kyosti.malkki(a)gmail.com> wrote: > The information missing from the mail is I requested to have that halt() > added after console_init(). > > Also at least it was previously reported system was in a periodic reset-loop > regardless of the halt() there, so sn active watchdog may be involved here. > Looks like other boards > with same superio use call ite_kill_watchdog(), I don't know what > it8718f_disable_reboot() does. > > There was also suggestion to dump superio ID register on POST display to > make sure LPC bus communication to superio works, but I did not hear back > from that experiment. > > Kyösti > > On Wed, Oct 26, 2016 at 4:36 AM, Riko Ho <antonius.riko(a)gmail.com> wrote: >> >> Everyone, >> >> I tried to initialize UART on IT8718F and it stopped at 0xD2... >> Here's the complete function, any clues ? >> >> Cheers >> =============== >> void mainboard_romstage_entry(unsigned long bist) >> { >> int s3resume = 0, boot_mode = 0; >> >> if (bist == 0) >> enable_lapic(); >> >> ich7_enable_lpc(); >> post_code(0xD1); >> /* Enable SuperIO PM */ >> //lpc47m15x_enable_serial(PME_DEV, 0x680); >> //lpc47m15x_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); /* 0x3f8 */ >> //enable_dev(SERIAL_DEV); >> //ite_conf_clkin();//needs a parameter, what is it ? >> >> /* >> 04:24:31 AM) idwer: 24 or 48 MHz? >> >> (04:25:18 AM) idwer: how do you find out? run superiotool when >> having booted with the vendor bios, and look at register >> CR23 >> */ >> //ite_conf_clkin(CLKIN_DEV, ITE_UART_CLK_PREDIVIDE_24); >> ite_conf_clkin(CLKIN_DEV, ITE_UART_CLK_PREDIVIDE_48); >> >> >> ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); /* 0x3f8 */ >> //printk(BIOS_DEBUG,"HELLO WORLD FROM COREBOOT BY RIKO HO...\n"); >> //it8716f_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE); >> it8718f_disable_reboot(GPIO_DEV); >> /* Set up the console */ >> console_init(); >> post_code(0xD2); >> printk(BIOS_DEBUG,"HELLO WORLD FROM COREBOOT ...\n"); >> halt(); >> post_code(0xD3); >> >> >> >> /* Halt if there was a built in self test failure */ >> report_bist_failure(bist); >> >> if (MCHBAR16(SSKPD) == 0xCAFE) { >> printk(BIOS_DEBUG, "soft reset detected.\n"); >> boot_mode = 1; >> } >> >> /* Perform some early chipset initialization required >> * before RAM initialization can work >> */ >> i945_early_initialization(); >> post_code(0xD4); >> s3resume = southbridge_detect_s3_resume(); >> >> /* Enable SPD ROMs and DDR-II DRAM */ >> enable_smbus(); >> >> #if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 >> dump_spd_registers(); >> #endif >> >> sdram_initialize(s3resume ? 2 : boot_mode, NULL); >> >> /* Perform some initialization that must run before stage2 */ >> early_ich7_init(); >> >> /* This should probably go away. Until now it is required >> * and mainboard specific >> */ >> rcba_config(); >> >> /* Chipset Errata! */ >> fixup_i945_errata(); >> >> /* Initialize the internal PCIe links before we go into stage2 */ >> i945_late_initialization(s3resume); >> } >> >> -- >> coreboot mailing list: coreboot(a)coreboot.org >> https://www.coreboot.org/mailman/listinfo/coreboot > >

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coreboot October 2016