Hi, I have acer es1-131 that as I see like some Google Chromebooks, it
motherboard based on intel braswell, and as I found support for this soc
added by intel.
Does current coreboot master support my motherboard and laptop?
In wiki I can't find many braswell supported platforms and acer in vendor
of laptop too (only Chromebooks).
I'm working with a fairly large Linux payload in my coreboot image
and one of my targets (the x230) has two separate ROM chips. I'd like
to have the top 4 MB SPI flash reserved for coreboot (bootblock,
romstage, ramstage, mrc, etc) and the bottom 8 MB chip just for
Most of my changes now are in the payload, not in the coreboot
components, so ideally I would not need to touch the top 4 MB
chip at all. I can't figure out a way to ask CBFS to create
two sections like this for me. Is it possible?
As a secondary improvement, I'd like to have an even more minimal
Linux payload in the top 4 MB that has spiflash tools to re-write
the bottom 8 MB. Is there an easy way to select which payload
will be executed?
Idwer, thanks for the info,
How come it's different with:
80 81 82 83
80: 10 00*07 34 *01 08 3c 00 91 02 1c 00 00 00 00 00
change this to pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x*3407*);
It's reversing backward,
On 31/10/2016 7:35 AM, Idwer Vollering wrote:
> 2016-10-31 0:18 GMT+01:00 Riko Ho <antonius.riko(a)gmail.com>:
>> Hi Idwer,
>> 80 81 82 83 84
>> 80: 10 00 07 34*01 08 3c 00* 91 02 1c 00 00 00 00 00
> 0x84 starts here: ^^
it's going forward, which way is the right one ? I'll have a read
of that link may be 32bits and 16bits causing it...? I misunderstand it
>> isn't it :
>> pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x00073401);
> The byte ordering has to do with endianness, see this webpage:
>> (correct me if I'm wrong)
>> change this to pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84,*0x003c0801*);
>> Kind regards,
>> Riko Ho