coreboot October 2016

coreboot@coreboot.org

55 participants
148 discussions

Newbie question about motherboard support
by Vasiliy Tolstov 31 Oct '16

31 Oct '16

Hi, I have acer es1-131 that as I see like some Google Chromebooks, it motherboard based on intel braswell, and as I found support for this soc added by intel. Does current coreboot master support my motherboard and laptop? In wiki I can't find many braswell supported platforms and acer in vendor of laptop too (only Chromebooks).

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Fixing payload address
by Trammell Hudson 31 Oct '16

31 Oct '16

I'm working with a fairly large Linux payload in my coreboot image and one of my targets (the x230) has two separate ROM chips. I'd like to have the top 4 MB SPI flash reserved for coreboot (bootblock, romstage, ramstage, mrc, etc) and the bottom 8 MB chip just for Linux. Most of my changes now are in the payload, not in the coreboot components, so ideally I would not need to touch the top 4 MB chip at all. I can't figure out a way to ask CBFS to create two sections like this for me. Is it possible? As a secondary improvement, I'd like to have an even more minimal Linux payload in the top 4 MB that has spiflash tools to re-write the bottom 8 MB. Is there an easy way to select which payload will be executed? -- Trammell

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POST 0xFFFF
by Riko Ho 31 Oct '16

31 Oct '16

Everyone, I got POST 0xFFFF then loop, and UART = 00 I have rewritten the ich7_enable_lpc function, and the complete romstage.c attached, what do I miss here ? Does enable_lapic(); function depend to the board or it can run on 946 even it's written for 945? static void ich7_enable_lpc(void) { // Enable Serial IRQ pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0); // Set COM1/COM2 decode range pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010); // Enable COM1 //pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x140d); pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3407); //from sudo lspci -xxx -s 0:1F.0 // Enable SuperIO Power Management Events //pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x007c0681); //pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x01340700); pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x003C0801);//from sudo lspci -xxx -s 0:1F.0, Idwer suggestion } bianchi@bianchi-AcerPower-SK50:~$ sudo lspci -xxx -s 0:1F.0 >> [sudo] password for bianchi: >> 00:1f.0 ISA bridge: Intel Corporation 82801GB/GR (ICH7 Family) LPC >> Interface Bridge (rev 01) >> 00: 86 80 b8 27 07 01 10 02 01 00 01 06 00 00 80 00 >> 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 >> 20: 00 00 00 00 00 00 00 00 00 00 00 00 19 10 96 21 >> 30: 00 00 00 00 e0 00 00 00 00 00 00 00 00 00 00 00 >> 40: 01 04 00 00 80 00 00 00 81 04 00 00 10 00 00 00 >> 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 >> 60: 8a 89 89 8f d0 00 00 00 89 80 80 8f 00 00 00 00 >> 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 >> 80: 10 00 07 34 01 08 3c 00 91 02 1c 00 00 00 00 00 >> 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 >> a0: 23 02 00 00 38 00 00 00 13 00 00 00 00 03 00 00 >> b0: 00 00 f0 00 00 00 00 00 55 55 55 59 00 00 00 00 >> c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 >> d0: 33 22 11 00 67 45 00 00 c0 c0 00 00 00 00 00 00 >> e0: 09 00 0c 10 a8 00 24 00 00 00 00 00 00 00 00 00 >> f0: 01 c0 d1 fe 00 00 00 00 86 0f 01 00 00 00 00 00

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Re: [coreboot] lspci -xxx -s 0:1F.0 ?
by Riko Ho 31 Oct '16

31 Oct '16

Idwer, thanks for the info, How come it's different with: 80 81 82 83 80: 10 00*07 34 *01 08 3c 00 91 02 1c 00 00 00 00 00 change this to pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x*3407*); It's reversing backward, On 31/10/2016 7:35 AM, Idwer Vollering wrote: > 2016-10-31 0:18 GMT+01:00 Riko Ho <antonius.riko(a)gmail.com>: >> Hi Idwer, >> 80 81 82 83 84 >> 80: 10 00 07 34*01 08 3c 00* 91 02 1c 00 00 00 00 00 > 0x84 starts here: ^^ it's going forward, which way is the right one ? I'll have a read of that link may be 32bits and 16bits causing it...? I misunderstand it I reckon... > >> isn't it : >> >> pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x00073401); >> ? > The byte ordering has to do with endianness, see this webpage: > https://docs.oracle.com/cd/E26505_01/html/E27000/hwovr-66.html > >> (correct me if I'm wrong) >> change this to pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84,*0x003c0801*); >> >> >> >> -- >> /*=== >> Kind regards, >> Riko Ho >> ===*/ -- */*=== Kind regards, Riko Ho ===*/ *

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Re: [coreboot] lspci -xxx -s 0:1F.0 ?
by Riko Ho 31 Oct '16

31 Oct '16

Hi Idwer, *80 81 82 83 84* 80: 10*00 07 34 01* 08 3c 00 91 02 1c 00 00 00 00 00 isn't it :**pci_write_config32(PCI_DEV(0, 0x1f, 0),*0x84, 0x00073401); * ? > (correct me if I'm wrong) > change this to pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x003c0801); > -- */*=== Kind regards, Riko Ho ===*/ *

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Re: [coreboot] lspci -xxx -s 0:1F.0 ?
by Riko Ho 30 Oct '16

30 Oct '16

I have compiled this function, hopefully it will work... http://dpaste.com/195R18B On 30/10/2016 7:21 AM, Idwer Vollering wrote: > 2016-10-30 1:18 GMT+02:00 Idwer Vollering <vidwer(a)gmail.com>: >> 2016-10-30 1:04 GMT+02:00 Riko Ho <antonius.riko(a)gmail.com>: >>> Everyone, >>> >>> How can I use the result from >>> >>> sudo lspci -xxx -s 0:1F.0 >>> >>> inside this function ? >>> >>> static void ich7_enable_lpc(void) >>> { >>> // Enable Serial IRQ >>> pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0); >> This looks good, because lspci tells you this: 60: 8a 89 89 8f d0 00 >> 00 00 89 80 80 8f 00 00 00 00 >> >>> // Set COM1/COM2 decode range >>> pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010); >> This looks good, because lspci tells you this: 60: 8a 89 89 8f d0 00 >> 00 00 89 80 80 8f 00 00 00 00 > mea culpa, the above should have been 80: 10 00 07 34 01 08 3c 00 91 > 02 1c 00 00 00 00 00 > >>> // Enable COM1 >>> pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x140d); >> lspci's output: 80: 10 00 07 34 01 08 3c 00 91 02 1c 00 00 00 00 00 >> change this to pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3407); >> >>> // Enable SuperIO Power Management Events >>> pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x007c0681); >> lspci's output: 80: 01 08 3c 00 > ^ this was me, stripping the whole line to the value that should be > written.. whole line: > 80: 10 00 07 34 01 08 3c 00 91 02 1c 00 00 00 00 00 > >> (correct me if I'm wrong) >> change this to pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x003c0801); >> >>> } >>> >>> >>> are they correctly defined or something not right ? >>> >>> >>> >>> >>> >>> >>> >>> >>> >>> >>> bianchi@bianchi-AcerPower-SK50:~$ sudo lspci -xxx -s 0:1F.0 >>> [sudo] password for bianchi: >>> 00:1f.0 ISA bridge: Intel Corporation 82801GB/GR (ICH7 Family) LPC >>> Interface Bridge (rev 01) >>> 00: 86 80 b8 27 07 01 10 02 01 00 01 06 00 00 80 00 >>> 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 >>> 20: 00 00 00 00 00 00 00 00 00 00 00 00 19 10 96 21 >>> 30: 00 00 00 00 e0 00 00 00 00 00 00 00 00 00 00 00 >>> 40: 01 04 00 00 80 00 00 00 81 04 00 00 10 00 00 00 >>> 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 >>> 60: 8a 89 89 8f d0 00 00 00 89 80 80 8f 00 00 00 00 >>> 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 >>> 80: 10 00 07 34 01 08 3c 00 91 02 1c 00 00 00 00 00 >>> 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 >>> a0: 23 02 00 00 38 00 00 00 13 00 00 00 00 03 00 00 >>> b0: 00 00 f0 00 00 00 00 00 55 55 55 59 00 00 00 00 >>> c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 >>> d0: 33 22 11 00 67 45 00 00 c0 c0 00 00 00 00 00 00 >>> e0: 09 00 0c 10 a8 00 24 00 00 00 00 00 00 00 00 00 >>> f0: 01 c0 d1 fe 00 00 00 00 86 0f 01 00 00 00 00 00 >>> >>> Cheers >>> >>> >>> -- >>> /*=== >>> Kind regards, >>> Riko Ho >>> ===*/ >>> >>> -- >>> coreboot mailing list: coreboot(a)coreboot.org >>> https://www.coreboot.org/mailman/listinfo/coreboot -- */*=== Kind regards, Riko Ho ===*/ *

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Re: [coreboot] lspci -xxx -s 0:1F.0 ?
by Riko Ho 30 Oct '16

30 Oct '16

On 30/10/2016 7:21 AM, Idwer Vollering wrote: > 2016-10-30 1:18 GMT+02:00 Idwer Vollering <vidwer(a)gmail.com>: >> 2016-10-30 1:04 GMT+02:00 Riko Ho <antonius.riko(a)gmail.com>: >>> Everyone, >>> >>> How can I use the result from >>> >>> sudo lspci -xxx -s 0:1F.0 >>> >>> inside this function ? >>> >>> static void ich7_enable_lpc(void) >>> { >>> // Enable Serial IRQ >>> pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0); >> This looks good, because lspci tells you this: 60: 8a 89 89 8f d0 00 >> 00 00 89 80 80 8f 00 00 00 00 >> >>> // Set COM1/COM2 decode range >>> pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010); >> This looks good, because lspci tells you this: 60: 8a 89 89 8f d0 00 >> 00 00 89 80 80 8f 00 00 00 00 > mea culpa, the above should have been 80: 10 00 07 34 01 08 3c 00 91 > 02 1c 00 00 00 00 00 > >>> // Enable COM1 >>> pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x140d); >> lspci's output: 80: 10 00 07 34 01 08 3c 00 91 02 1c 00 00 00 00 00 >> change this to pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3407); >> >>> // Enable SuperIO Power Management Events >>> pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x007c0681); >> lspci's output: 80: 01 08 3c 00 > ^ this was me, stripping the whole line to the value that should be > written.. whole line: > 80: 10 00 07 34 01 08 3c 00 91 02 1c 00 00 00 00 00 > >> (correct me if I'm wrong) >> change this to pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x003c0801); >> >>> } if we cut from 84 and following the logic from change this to pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3407); pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x01340700); ...or ? >>> >>> >>> are they correctly defined or something not right ? >>> >>> >>> >>> >>> >>> >>> >>> >>> >>> >>> bianchi@bianchi-AcerPower-SK50:~$ sudo lspci -xxx -s 0:1F.0 >>> [sudo] password for bianchi: >>> 00:1f.0 ISA bridge: Intel Corporation 82801GB/GR (ICH7 Family) LPC >>> Interface Bridge (rev 01) >>> 00: 86 80 b8 27 07 01 10 02 01 00 01 06 00 00 80 00 >>> 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 >>> 20: 00 00 00 00 00 00 00 00 00 00 00 00 19 10 96 21 >>> 30: 00 00 00 00 e0 00 00 00 00 00 00 00 00 00 00 00 >>> 40: 01 04 00 00 80 00 00 00 81 04 00 00 10 00 00 00 >>> 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 >>> 60: 8a 89 89 8f d0 00 00 00 89 80 80 8f 00 00 00 00 >>> 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 >>> 80: 10 00 07 34 01 08 3c 00 91 02 1c 00 00 00 00 00 >>> 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 >>> a0: 23 02 00 00 38 00 00 00 13 00 00 00 00 03 00 00 >>> b0: 00 00 f0 00 00 00 00 00 55 55 55 59 00 00 00 00 >>> c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 >>> d0: 33 22 11 00 67 45 00 00 c0 c0 00 00 00 00 00 00 >>> e0: 09 00 0c 10 a8 00 24 00 00 00 00 00 00 00 00 00 >>> f0: 01 c0 d1 fe 00 00 00 00 86 0f 01 00 00 00 00 00 >>> >>> Cheers >>> >>> >>> -- >>> /*=== >>> Kind regards, >>> Riko Ho >>> ===*/ >>> >>> -- >>> coreboot mailing list: coreboot(a)coreboot.org >>> https://www.coreboot.org/mailman/listinfo/coreboot -- */*=== Kind regards, Riko Ho ===*/ *

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Re: [coreboot] lspci -xxx -s 0:1F.0 ?
by Riko Ho 30 Oct '16

30 Oct '16

Thanks Idwer, that's what I've been thinking something is not the same between lspci and the function, I'll give a try, perhaps it will answer our puzzle... On 30/10/2016 7:18 AM, Idwer Vollering wrote: > 2016-10-30 1:04 GMT+02:00 Riko Ho <antonius.riko(a)gmail.com>: >> Everyone, >> >> How can I use the result from >> >> sudo lspci -xxx -s 0:1F.0 >> >> inside this function ? >> >> static void ich7_enable_lpc(void) >> { >> // Enable Serial IRQ >> pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0); > This looks good, because lspci tells you this: 60: 8a 89 89 8f d0 00 > 00 00 89 80 80 8f 00 00 00 00 > >> // Set COM1/COM2 decode range >> pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010); > This looks good, because lspci tells you this: 60: 8a 89 89 8f d0 00 > 00 00 89 80 80 8f 00 00 00 00 > >> // Enable COM1 >> pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x140d); > lspci's output: 80: 10 00 07 34 01 08 3c 00 91 02 1c 00 00 00 00 00 > change this to pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3407); > >> // Enable SuperIO Power Management Events >> pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x007c0681); > lspci's output: 80: 01 08 3c 00 > > (correct me if I'm wrong) > change this to pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x003c0801); > >> } >> >> >> are they correctly defined or something not right ? >> >> >> >> >> >> >> >> >> >> >> bianchi@bianchi-AcerPower-SK50:~$ sudo lspci -xxx -s 0:1F.0 >> [sudo] password for bianchi: >> 00:1f.0 ISA bridge: Intel Corporation 82801GB/GR (ICH7 Family) LPC >> Interface Bridge (rev 01) >> 00: 86 80 b8 27 07 01 10 02 01 00 01 06 00 00 80 00 >> 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 >> 20: 00 00 00 00 00 00 00 00 00 00 00 00 19 10 96 21 >> 30: 00 00 00 00 e0 00 00 00 00 00 00 00 00 00 00 00 >> 40: 01 04 00 00 80 00 00 00 81 04 00 00 10 00 00 00 >> 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 >> 60: 8a 89 89 8f d0 00 00 00 89 80 80 8f 00 00 00 00 >> 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 >> 80: 10 00 07 34 01 08 3c 00 91 02 1c 00 00 00 00 00 >> 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 >> a0: 23 02 00 00 38 00 00 00 13 00 00 00 00 03 00 00 >> b0: 00 00 f0 00 00 00 00 00 55 55 55 59 00 00 00 00 >> c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 >> d0: 33 22 11 00 67 45 00 00 c0 c0 00 00 00 00 00 00 >> e0: 09 00 0c 10 a8 00 24 00 00 00 00 00 00 00 00 00 >> f0: 01 c0 d1 fe 00 00 00 00 86 0f 01 00 00 00 00 00 >> >> Cheers >> >> >> -- >> /*=== >> Kind regards, >> Riko Ho >> ===*/ >> >> -- >> coreboot mailing list: coreboot(a)coreboot.org >> https://www.coreboot.org/mailman/listinfo/coreboot > . > -- */*=== Kind regards, Riko Ho ===*/ *

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Re: [coreboot] lspci -xxx -s 0:1F.0 ?
by Idwer Vollering 30 Oct '16

30 Oct '16

2016-10-30 1:18 GMT+02:00 Idwer Vollering <vidwer(a)gmail.com>: > 2016-10-30 1:04 GMT+02:00 Riko Ho <antonius.riko(a)gmail.com>: >> >> Everyone, >> >> How can I use the result from >> >> sudo lspci -xxx -s 0:1F.0 >> >> inside this function ? >> >> static void ich7_enable_lpc(void) >> { >> // Enable Serial IRQ >> pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0); > > This looks good, because lspci tells you this: 60: 8a 89 89 8f d0 00 > 00 00 89 80 80 8f 00 00 00 00 > >> // Set COM1/COM2 decode range >> pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010); > > This looks good, because lspci tells you this: 60: 8a 89 89 8f d0 00 > 00 00 89 80 80 8f 00 00 00 00 mea culpa, the above should have been 80: 10 00 07 34 01 08 3c 00 91 02 1c 00 00 00 00 00 > >> // Enable COM1 >> pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x140d); > > lspci's output: 80: 10 00 07 34 01 08 3c 00 91 02 1c 00 00 00 00 00 > change this to pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3407); > >> // Enable SuperIO Power Management Events >> pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x007c0681); > > lspci's output: 80: 01 08 3c 00 ^ this was me, stripping the whole line to the value that should be written.. whole line: 80: 10 00 07 34 01 08 3c 00 91 02 1c 00 00 00 00 00 > > (correct me if I'm wrong) > change this to pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x003c0801); > >> } >> >> >> are they correctly defined or something not right ? >> >> >> >> >> >> >> >> >> >> >> bianchi@bianchi-AcerPower-SK50:~$ sudo lspci -xxx -s 0:1F.0 >> [sudo] password for bianchi: >> 00:1f.0 ISA bridge: Intel Corporation 82801GB/GR (ICH7 Family) LPC >> Interface Bridge (rev 01) >> 00: 86 80 b8 27 07 01 10 02 01 00 01 06 00 00 80 00 >> 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 >> 20: 00 00 00 00 00 00 00 00 00 00 00 00 19 10 96 21 >> 30: 00 00 00 00 e0 00 00 00 00 00 00 00 00 00 00 00 >> 40: 01 04 00 00 80 00 00 00 81 04 00 00 10 00 00 00 >> 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 >> 60: 8a 89 89 8f d0 00 00 00 89 80 80 8f 00 00 00 00 >> 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 >> 80: 10 00 07 34 01 08 3c 00 91 02 1c 00 00 00 00 00 >> 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 >> a0: 23 02 00 00 38 00 00 00 13 00 00 00 00 03 00 00 >> b0: 00 00 f0 00 00 00 00 00 55 55 55 59 00 00 00 00 >> c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 >> d0: 33 22 11 00 67 45 00 00 c0 c0 00 00 00 00 00 00 >> e0: 09 00 0c 10 a8 00 24 00 00 00 00 00 00 00 00 00 >> f0: 01 c0 d1 fe 00 00 00 00 86 0f 01 00 00 00 00 00 >> >> Cheers >> >> >> -- >> /*=== >> Kind regards, >> Riko Ho >> ===*/ >> >> -- >> coreboot mailing list: coreboot(a)coreboot.org >> https://www.coreboot.org/mailman/listinfo/coreboot

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lspci -xxx -s 0:1F.0 ?
by Riko Ho 30 Oct '16

30 Oct '16

Everyone, How can I use the result from sudo lspci -xxx -s 0:1F.0 inside this function ? static void ich7_enable_lpc(void) { // Enable Serial IRQ pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0); // Set COM1/COM2 decode range pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010); // Enable COM1 pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x140d); // Enable SuperIO Power Management Events pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x007c0681); } are they correctly defined or something not right ? bianchi@bianchi-AcerPower-SK50:~$ sudo lspci -xxx -s 0:1F.0 [sudo] password for bianchi: 00:1f.0 ISA bridge: Intel Corporation 82801GB/GR (ICH7 Family) LPC Interface Bridge (rev 01) 00: 86 80 b8 27 07 01 10 02 01 00 01 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 19 10 96 21 30: 00 00 00 00 e0 00 00 00 00 00 00 00 00 00 00 00 40: 01 04 00 00 80 00 00 00 81 04 00 00 10 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 8a 89 89 8f d0 00 00 00 89 80 80 8f 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 10 00 07 34 01 08 3c 00 91 02 1c 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 23 02 00 00 38 00 00 00 13 00 00 00 00 03 00 00 b0: 00 00 f0 00 00 00 00 00 55 55 55 59 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 33 22 11 00 67 45 00 00 c0 c0 00 00 00 00 00 00 e0: 09 00 0c 10 a8 00 24 00 00 00 00 00 00 00 00 00 f0: 01 c0 d1 fe 00 00 00 00 86 0f 01 00 00 00 00 00 Cheers -- */*=== Kind regards, Riko Ho ===*/ *

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coreboot October 2016