coreboot October 2016

coreboot@coreboot.org

55 participants
148 discussions

Re: [coreboot] ARMv8 prototype in simulator failing at payload_load()
by tmiket 15 Oct '16

15 Oct '16

Julius, I appreciate the background on the API change and the pointer to what to fix in the code. I have stubbed out the soc chip operations and now am letting coreboot know that there is a region of dram. The simulation train continues. Cheers, T.mike On 2016-10-13 14:30, Julius Werner wrote: > You need a call like ram_resource(<any device node>, 0, <start of DRAM > in KB>, <size of DRAM in KB>); somewhere in ramstage... e.g. as in > src/soc/rockchip/rk3288/soc.c. Even if you're running on an emulator, > you'll still have to decide on a memory range that you want to be your > emulated DRAM so that coreboot knows where it can put stuff. > >> Can anybody comment on this suspicion, as well as why the check is >> enabled >> for payload load but disabled for bl31 load? > > This was a recent change that became necessary to support a special > case... before that, the check was always mandatory. The memory > allocator situation is a little ugly on non-x86 devices since they > usually have separate SRAM and DRAM areas. The resource allocator was > written for x86 and only meant to dynamically track DRAM (and > non-memory) resources in ramstage. On non-x86 devices it became > necessary to handle SRAM allocations in earlier stages and we invented > the static memlayout.ld mechanism. The two don't really talk much, and > thus the ramstage resource allocator doesn't know about SRAM (we > should probably try to improve that, but as usual, it's a little > tricky in the details and nobody has the time right now). We needed > BL31 to be loaded through the same mechanism as the payload, but some > platforms want to place (parts of) it in SRAM... so we had to hack out > the usable memory check for it to get it to work. You can see some of > the original discussion in > https://chromium-review.googlesource.com/c/376849/.

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Attempt to porting coreboot to Gigabyte ga-945gcm-s2l
by Arthur Heymans 15 Oct '16

15 Oct '16

Hi I'm trying to port coreboot to the gigabyte ga-945gcm-s2l, which has a 945gc northbridge, a ich7 southbridge and a ite it8718f sio. I'm trying all this with a 1067fsb cpu, so in that last aspect there is no precedent in coreboot. I encountered some raminit issues where the MCHBAR(CLKCFG) was incorrectly written, but this was fixed in https://review.coreboot.org/#/c/16940/. Right now I'm stuck in smm_init in southbridge/intel/i82801gx/smi.c. The boot process completely hangs when wbinvd() is called which supposed to "Write Back and Invalidate Cache" according to http://x86.renejeschke.de/html/file_module_x86_id_325.html. What does this mean? Did the raminit not work? -- Kind regards Arthur Heymans

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Re: [coreboot] southbridge/intel/i82801gx/i82801gx.h
by Antonius Riko 15 Oct '16

15 Oct '16

I did rm .config and did make again : bianchi@ubuntu:~/coreboot$ make clean bianchi@ubuntu:~/coreboot$ make # # configuration written to /home/bianchi/coreboot/.config # HOSTCC util/sconfig/lex.yy.o HOSTCC util/sconfig/sconfig.tab.o HOSTCC util/sconfig/main.o HOSTCC util/sconfig/sconfig (link) SCONFIG mainboard/intel/i946gz/devicetree.cb HOSTCC nvramtool/cli/nvramtool.o HOSTCC nvramtool/cli/opts.o HOSTCC nvramtool/cmos_lowlevel.o HOSTCC nvramtool/cmos_ops.o HOSTCC nvramtool/common.o HOSTCC nvramtool/compute_ip_checksum.o HOSTCC nvramtool/hexdump.o HOSTCC nvramtool/input_file.o HOSTCC nvramtool/layout.o HOSTCC nvramtool/accessors/layout-common.o HOSTCC nvramtool/accessors/layout-text.o HOSTCC nvramtool/accessors/layout-bin.o HOSTCC nvramtool/lbtable.o HOSTCC nvramtool/reg_expr.o HOSTCC nvramtool/cbfs.o HOSTCC nvramtool/accessors/cmos-mem.o HOSTCC nvramtool/nvramtool (link) OPTION option_table.h CC bootblock/mainboard/intel/i946gz/static.o CC bootblock/arch/x86/boot.o GEN generated/bootblock.ld CP bootblock/arch/x86/bootblock.ld HOSTCC util/romcc/romcc (this may take a while) ROMCC generated/bootblock.inc CC bootblock/arch/x86/bootblock_romcc.o CC bootblock/arch/x86/cpu_common.o GEN build.h CC bootblock/arch/x86/id.o CC bootblock/arch/x86/memcpy.o CC bootblock/arch/x86/memset.o CC bootblock/arch/x86/mmap_boot.o CC bootblock/arch/x86/timestamp.o CC bootblock/arch/x86/walkcbfs.o CC bootblock/commonlib/cbfs.o CC bootblock/commonlib/lz4_wrapper.o CC bootblock/commonlib/mem_pool.o CC bootblock/commonlib/region.o CC bootblock/console/die.o CC bootblock/console/post.o CC bootblock/cpu/x86/lapic/boot_cpu.o CC bootblock/cpu/x86/mtrr/earlymtrr.o CC bootblock/device/device_simple.o CC bootblock/device/i2c.o CC bootblock/drivers/uart/uart8250io.o CC bootblock/drivers/uart/util.o CC bootblock/lib/boot_device.o CC bootblock/lib/bootmode.o HOSTCC cbfstool/fmaptool.o HOSTCC cbfstool/cbfs_sections.o HOSTCC cbfstool/fmap_from_fmd.o HOSTCC cbfstool/fmd.o HOSTCC cbfstool/fmd_parser.o HOSTCC cbfstool/fmd_scanner.o HOSTCC cbfstool/fmap.o HOSTCC cbfstool/kv_pair.o HOSTCC cbfstool/valstr.o HOSTCC cbfstool/fmaptool (link) FMAP build/util/cbfstool/fmaptool -h build/fmap_config.h build/fmap.fmd build/fmap.fmap SUCCESS: Wrote 182 bytes to file 'build/fmap.fmap' (and generated header) The sections containing CBFSes are: COREBOOT CC bootblock/lib/cbfs.o CC bootblock/lib/cbmem_console.o CC bootblock/lib/delay.o CC bootblock/lib/fmap.o CC bootblock/lib/gcc.o CC bootblock/lib/halt.o CC bootblock/lib/hexdump.o CC bootblock/lib/libgcc.o CC bootblock/lib/memchr.o CC bootblock/lib/memcmp.o CC bootblock/lib/prog_loaders.o CC bootblock/lib/prog_ops.o CC bootblock/lib/timestamp.o CC bootblock/lib/version.o CC bootblock/vboot/bootmode.o LINK cbfs/fallback/bootblock.debug OBJCOPY cbfs/fallback/bootblock.elf OBJCOPY bootblock.raw.bin CC romstage/mainboard/intel/i946gz/static.o CC romstage/arch/x86/acpi_s3.o GEN generated/assembly.inc CC romstage/arch/x86/assembly_entry.o CC romstage/arch/x86/boot.o CC romstage/arch/x86/cbfs_and_run.o CC romstage/arch/x86/cbmem.o CC romstage/arch/x86/cpu_common.o CC romstage/arch/x86/memcpy.o CP romstage/arch/x86/memlayout.ld CC romstage/arch/x86/memmove.o CC romstage/arch/x86/memset.o CC romstage/arch/x86/mmap_boot.o CC romstage/arch/x86/postcar_loader.o CC romstage/arch/x86/timestamp.o CC romstage/commonlib/cbfs.o CC romstage/commonlib/lz4_wrapper.o CC romstage/commonlib/mem_pool.o CC romstage/commonlib/region.o CC romstage/console/console.o CC romstage/console/die.o CC romstage/console/init.o CC romstage/console/post.o CC romstage/console/printk.o CC romstage/console/vtxprintf.o CC romstage/cpu/intel/car/romstage.o CC romstage/cpu/intel/microcode/microcode.o CC romstage/cpu/x86/car.o CC romstage/cpu/x86/lapic/apic_timer.o CC romstage/cpu/x86/lapic/boot_cpu.o CC romstage/cpu/x86/mtrr/earlymtrr.o CC romstage/device/device_simple.o CC romstage/device/i2c.o CC romstage/device/pci_early.o CC romstage/drivers/pc80/rtc/mc146818rtc.o CC romstage/drivers/pc80/rtc/mc146818rtc_early.o CC romstage/drivers/uart/uart8250io.o CC romstage/drivers/uart/util.o CC romstage/lib/boot_device.o CC romstage/lib/bootmode.o CC romstage/lib/cbfs.o CC romstage/lib/cbmem_common.o CC romstage/lib/cbmem_console.o CC romstage/lib/compute_ip_checksum.o CC romstage/lib/delay.o CC romstage/lib/ext_stage_cache.o CC romstage/lib/fmap.o CC romstage/lib/gcc.o CC romstage/lib/halt.o CC romstage/lib/hexdump.o CC romstage/lib/imd.o CC romstage/lib/imd_cbmem.o CC romstage/lib/libgcc.o CC romstage/lib/lzma.o CC romstage/lib/lzmadecode.o CC romstage/lib/memchr.o CC romstage/lib/memcmp.o CC romstage/lib/memrange.o CC romstage/lib/prog_loaders.o CC romstage/lib/prog_ops.o CP romstage/lib/program.ld CC romstage/lib/ramtest.o CC romstage/lib/rmodule.o CC romstage/lib/romstage_stack.o CC romstage/lib/stack.o CC romstage/lib/timestamp.o CC romstage/lib/version.o CC romstage/mainboard/intel/i946gz/romstage.o CC romstage/northbridge/intel/i945/debug.o CC romstage/northbridge/intel/i945/early_init.o CC romstage/northbridge/intel/i945/errata.o CC romstage/northbridge/intel/i945/ram_calc.o CC romstage/northbridge/intel/i945/raminit.o CC romstage/southbridge/intel/i82801gx/early_lpc.o CC romstage/southbridge/intel/i82801gx/early_smbus.o CC romstage/superio/ite/common/early_serial.o CC romstage/superio/ite/it8718f/early_serial.o CC romstage/vboot/bootmode.o LINK cbfs/fallback/romstage.debug build/romstage/lib/ext_stage_cache.o: In function `stage_cache_recover': /home/bianchi/coreboot/src/lib/ext_stage_cache.c:55: undefined reference to `stage_cache_external_region' build/romstage/lib/ext_stage_cache.o: In function `stage_cache_create_empty': /home/bianchi/coreboot/src/lib/ext_stage_cache.c:39: undefined reference to `stage_cache_external_region' src/arch/x86/Makefile.inc:264: recipe for target 'build/cbfs/fallback/romstage.debug' failed make: *** [build/cbfs/fallback/romstage.debug] Error 1 bianchi@ubuntu:~/coreboot$ What do I miss here ?

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Re: [coreboot] southbridge/intel/i82801gx/i82801gx.h
by Antonius Riko 15 Oct '16

15 Oct '16

Hi, make clean, did help....thanks now in the next stage, I got this error : Include CPU microcode in CBFS > 1. Generate from tree (CPU_MICROCODE_CBFS_GENERATE) 2. Include external microcode header files (CPU_MICROCODE_CBFS_EXTERNAL_HEADER) 3. Do not include microcode updates (CPU_MICROCODE_CBFS_NONE) choice[1-3]: 1 Microcode binary path and filename (CPU_UCODE_BINARIES) [] * * Northbridge * * * Southbridge * * * Super I/O * * * Embedded Controllers * Vboot non-volatile storage in CMOS. (VBOOT_VBNV_CMOS) [N/y/?] n Vboot non-volatile storage in EC. (VBOOT_VBNV_EC) [N/y/?] n Verify firmware with vboot. (VBOOT) [N/y/?] (NEW) y * * Generic Drivers * AS3722 RTC support (DRIVERS_AS3722_RTC) [N/y] n Realtek 8168 reset (REALTEK_8168_RESET) [N/y/?] n Serial port on SuperIO (DRIVERS_UART_8250IO) [Y/n] y Oxford OXPCIe952 (DRIVERS_UART_OXPCIE) [N/y/?] n UART's PCI bus, device, function address (UART_PCI_ADDR) [0x0] 0x0 USB 2.0 EHCI debug dongle support (USBDEBUG) [N/y/?] (NEW) y Enable early (pre-RAM) usbdebug (USBDEBUG_IN_ROMSTAGE) [Y/n/?] (NEW) y Type of dongle > 1. Net20DC or compatible (USBDEBUG_DONGLE_STD) (NEW) 2. BeagleBone (USBDEBUG_DONGLE_BEAGLEBONE) (NEW) 3. BeagleBone Black (USBDEBUG_DONGLE_BEAGLEBONE_BLACK) (NEW) 4. FTDI FT232H UART (USBDEBUG_DONGLE_FTDI_FT232H) (NEW) choice[1-4]: 1 I2C TPM (I2C_TPM) [Y] (NEW) y I2C TPM Driver > 1. Generic I2C TPM Driver (I2C_TPM_GENERIC) (NEW) 2. CR50 I2C TPM Driver (I2C_TPM_CR50) (NEW) choice[1-2]: 1 I2C TPM chip bus (DRIVER_TPM_I2C_BUS) [0x9] (NEW) 1 I2C TPM chip address (DRIVER_TPM_I2C_ADDR) [0x2] (NEW) 0x2 IRQ or GPE to use for TPM interrupt (DRIVER_TPM_I2C_IRQ) [-1] (NEW) 18 Generate I2C TPM ACPI device (DRIVER_I2C_TPM_ACPI) [N/y] n Support Intel PCI-e WiFi adapters (DRIVERS_INTEL_WIFI) [Y/n/?] y PS/2 keyboard init (DRIVERS_PS2_KEYBOARD) [N/y/?] n Silicon Image SIL3114 (DRIVERS_SIL_3114) [N/y/?] n TI TPS65913 support (DRIVERS_TI_TPS65913) [N/y] n TI TPS65913 RTC support (DRIVERS_TI_TPS65913_RTC) [N/y] n * * Console * Squelch AP CPUs from early console. (SQUELCH_EARLY_SMP) [Y/n/?] y Serial port console output (CONSOLE_SERIAL) [Y/n/?] y * * I/O mapped, 8250-compatible * Index for UART port to use for console (UART_FOR_CONSOLE) [0] 0 * * Serial port base address = 0x3f8 * Baud rate 1. 921600 (CONSOLE_SERIAL_921600) 2. 460800 (CONSOLE_SERIAL_460800) 3. 230400 (CONSOLE_SERIAL_230400) > 4. 115200 (CONSOLE_SERIAL_115200) 5. 57600 (CONSOLE_SERIAL_57600) 6. 38400 (CONSOLE_SERIAL_38400) 7. 19200 (CONSOLE_SERIAL_19200) 8. 9600 (CONSOLE_SERIAL_9600) choice[1-8]: 4 spkmodem (console on speaker) console output (SPKMODEM) [N/y/?] n USB dongle console output (CONSOLE_USB) [N/y/?] (NEW) y Use onboard VGA as primary video device (ONBOARD_VGA_IS_PRIMARY) [N/y/?] n Network console over NE2000 compatible Ethernet adapter (CONSOLE_NE2K) [N/y/?] n Send console output to a CBMEM buffer (CONSOLE_CBMEM) [Y/n/?] y Room allocated for console output in CBMEM (CONSOLE_CBMEM_BUFFER_SIZE) [0x20000] 0x20000 Default console log level > 1. 8: SPEW (DEFAULT_CONSOLE_LOGLEVEL_8) 2. 7: DEBUG (DEFAULT_CONSOLE_LOGLEVEL_7) 3. 6: INFO (DEFAULT_CONSOLE_LOGLEVEL_6) 4. 5: NOTICE (DEFAULT_CONSOLE_LOGLEVEL_5) 5. 4: WARNING (DEFAULT_CONSOLE_LOGLEVEL_4) 6. 3: ERR (DEFAULT_CONSOLE_LOGLEVEL_3) 7. 2: CRIT (DEFAULT_CONSOLE_LOGLEVEL_2) 8. 1: ALERT (DEFAULT_CONSOLE_LOGLEVEL_1) 9. 0: EMERG (DEFAULT_CONSOLE_LOGLEVEL_0) choice[1-9]: 1 Don't show any POST codes (NO_POST) [N/y] n Store post codes in CMOS for debugging (CMOS_POST) [N/y/?] n Show POST codes on the debug console (CONSOLE_POST) [N/y/?] n Send POST codes to an external device (POST_DEVICE) [Y/n] y Device to send POST codes to > 1. None (POST_DEVICE_NONE) 2. LPC (POST_DEVICE_LPC) 3. PCI/PCIe (POST_DEVICE_PCI_PCIE) choice[1-3]: 1 Send POST codes to an IO port (POST_IO) [Y/n/?] y IO port for POST codes (POST_IO_PORT) [0x80] 0x80 * * Debugging * GDB debugging support (GDB_STUB) [Y/n/?] y Wait for a GDB connection (GDB_WAIT) [N/y/?] n Halt when hitting a BUG() or assertion error (FATAL_ASSERTS) [N/y/?] n Output verbose CBFS debug messages (DEBUG_CBFS) [Y/n/?] y Output verbose RAM init debug messages (DEBUG_RAM_SETUP) [N/y/?] n Check PIRQ table consistency (DEBUG_PIRQ) [Y/n/?] y Output verbose SMI debug messages (DEBUG_SMI) [N/y/?] (NEW) y Debug SMM relocation code (DEBUG_SMM_RELOCATION) [N/y/?] (NEW) y Output verbose malloc debug messages (DEBUG_MALLOC) [Y/n/?] y Output verbose ACPI debug messages (DEBUG_ACPI) [Y/n/?] y Output verbose TPM debug messages (DEBUG_TPM) [N/y/?] (NEW) y Output verbose USB 2.0 EHCI debug dongle messages (DEBUG_USBDEBUG) [N/y/?] (NEW) y Trace function calls (TRACE) [Y/n/?] y Debug boot state machine (DEBUG_BOOT_STATE) [Y/n/?] y * * Restart config... * * * Chipset * * * SoC * * * CPU * Include CPU microcode in CBFS > 1. Generate from tree (CPU_MICROCODE_CBFS_GENERATE) 2. Include external microcode header files (CPU_MICROCODE_CBFS_EXTERNAL_HEADER) 3. Do not include microcode updates (CPU_MICROCODE_CBFS_NONE) choice[1-3]: 1 Microcode binary path and filename (CPU_UCODE_BINARIES) [] * * Northbridge * * * Southbridge * * * Super I/O * * * Embedded Controllers * Vboot non-volatile storage in CMOS. (VBOOT_VBNV_CMOS) [N/y/?] n Vboot non-volatile storage in EC. (VBOOT_VBNV_EC) [N/y/?] n Vboot starts verifying in bootblock (VBOOT_STARTS_IN_BOOTBLOCK) [N/y/?] (NEW) y Mock secdata for firmware verification (VBOOT_MOCK_SECDATA) [N/y/?] (NEW) y Disable dev mode on recovery requests (VBOOT_DISABLE_DEV_ON_RECOVERY) [N/y/?] (NEW) y Vboot verification is built into a separate stage (SEPARATE_VERSTAGE) [N/y] (NEW) y The separate verification stage returns to its caller (RETURN_FROM_VERSTAGE) [N/y/?] (NEW) y The chipset provides the main() entry point for verstage (CHIPSET_PROVIDES_VERSTAGE_MAIN_SYMBOL) [N/y/?] (NEW) y Vboot's work buffer is dynamically allocated. (VBOOT_DYNAMIC_WORK_BUFFER) [N/y/?] (NEW) y Video option ROM matters (= can skip display init) (VBOOT_OPROM_MATTERS) [N/y/?] (NEW) y Verify firmware with vboot. (VBOOT) [Y/n/?] y # # configuration written to /home/bianchi/coreboot/.config # HOSTCC util/sconfig/lex.yy.o HOSTCC util/sconfig/sconfig.tab.o HOSTCC util/sconfig/main.o HOSTCC util/sconfig/sconfig (link) SCONFIG mainboard/intel/i946gz/devicetree.cb HOSTCC nvramtool/cli/nvramtool.o HOSTCC nvramtool/cli/opts.o HOSTCC nvramtool/cmos_lowlevel.o HOSTCC nvramtool/cmos_ops.o HOSTCC nvramtool/common.o HOSTCC nvramtool/compute_ip_checksum.o HOSTCC nvramtool/hexdump.o HOSTCC nvramtool/input_file.o HOSTCC nvramtool/layout.o HOSTCC nvramtool/accessors/layout-common.o HOSTCC nvramtool/accessors/layout-text.o HOSTCC nvramtool/accessors/layout-bin.o HOSTCC nvramtool/lbtable.o HOSTCC nvramtool/reg_expr.o HOSTCC nvramtool/cbfs.o HOSTCC nvramtool/accessors/cmos-mem.o HOSTCC nvramtool/nvramtool (link) OPTION option_table.h CC bootblock/mainboard/intel/i946gz/static.o CC bootblock/arch/x86/boot.o GEN generated/bootblock.ld CP bootblock/arch/x86/bootblock.ld HOSTCC util/romcc/romcc (this may take a while) ROMCC generated/bootblock.inc CC bootblock/arch/x86/bootblock_romcc.o CC bootblock/arch/x86/cpu_common.o GEN build.h CC bootblock/arch/x86/id.o CC bootblock/arch/x86/memcpy.o CC bootblock/arch/x86/memset.o CC bootblock/arch/x86/mmap_boot.o CC bootblock/arch/x86/walkcbfs.o CC bootblock/commonlib/cbfs.o CC bootblock/commonlib/lz4_wrapper.o CC bootblock/commonlib/mem_pool.o CC bootblock/commonlib/region.o CC bootblock/console/die.o CC bootblock/console/post.o CC bootblock/cpu/x86/lapic/boot_cpu.o CC bootblock/cpu/x86/mtrr/earlymtrr.o CC bootblock/device/device_simple.o CC bootblock/device/i2c.o CC bootblock/drivers/uart/uart8250io.o CC bootblock/drivers/uart/util.o CC bootblock/lib/boot_device.o CC bootblock/lib/bootmode.o HOSTCC cbfstool/fmaptool.o HOSTCC cbfstool/cbfs_sections.o HOSTCC cbfstool/fmap_from_fmd.o HOSTCC cbfstool/fmd.o HOSTCC cbfstool/fmd_parser.o HOSTCC cbfstool/fmd_scanner.o HOSTCC cbfstool/fmap.o HOSTCC cbfstool/kv_pair.o HOSTCC cbfstool/valstr.o HOSTCC cbfstool/fmaptool (link) FMAP build/util/cbfstool/fmaptool -h build/fmap_config.h build/fmap.fmd build/fmap.fmap SUCCESS: Wrote 182 bytes to file 'build/fmap.fmap' (and generated header) The sections containing CBFSes are: COREBOOT CC bootblock/lib/cbfs.o CC bootblock/lib/cbmem_console.o CC bootblock/lib/delay.o CC bootblock/lib/fmap.o CC bootblock/lib/gcc.o CC bootblock/lib/halt.o CC bootblock/lib/hexdump.o CC bootblock/lib/libgcc.o CC bootblock/lib/memchr.o CC bootblock/lib/memcmp.o CC bootblock/lib/prog_loaders.o CC bootblock/lib/prog_ops.o CC bootblock/lib/version.o CC bootblock/vboot/bootmode.o LINK cbfs/fallback/bootblock.debug OBJCOPY cbfs/fallback/bootblock.elf OBJCOPY bootblock.raw.bin CC romstage/mainboard/intel/i946gz/static.o CC romstage/arch/x86/acpi_s3.o GEN generated/assembly.inc CC romstage/arch/x86/assembly_entry.o CC romstage/arch/x86/boot.o CC romstage/arch/x86/cbfs_and_run.o CC romstage/arch/x86/cbmem.o CC romstage/arch/x86/cpu_common.o CC romstage/arch/x86/memcpy.o CP romstage/arch/x86/memlayout.ld CC romstage/arch/x86/memmove.o CC romstage/arch/x86/memset.o CC romstage/arch/x86/mmap_boot.o CC romstage/arch/x86/postcar_loader.o CC romstage/commonlib/cbfs.o CC romstage/commonlib/lz4_wrapper.o CC romstage/commonlib/mem_pool.o CC romstage/commonlib/region.o CC romstage/console/console.o CC romstage/console/die.o CC romstage/console/init.o CC romstage/console/post.o CC romstage/console/printk.o CC romstage/console/vtxprintf.o CC romstage/cpu/intel/car/romstage.o CC romstage/cpu/intel/microcode/microcode.o CC romstage/cpu/x86/car.o CC romstage/cpu/x86/lapic/apic_timer.o CC romstage/cpu/x86/lapic/boot_cpu.o CC romstage/cpu/x86/mtrr/earlymtrr.o CC romstage/device/device_simple.o CC romstage/device/i2c.o CC romstage/device/pci_early.o CC romstage/drivers/pc80/rtc/mc146818rtc.o CC romstage/drivers/pc80/rtc/mc146818rtc_early.o CC romstage/drivers/uart/uart8250io.o CC romstage/drivers/uart/util.o CC romstage/lib/boot_device.o CC romstage/lib/bootmode.o CC romstage/lib/cbfs.o CC romstage/lib/cbmem_common.o CC romstage/lib/cbmem_console.o CC romstage/lib/compute_ip_checksum.o CC romstage/lib/delay.o CC romstage/lib/fmap.o CC romstage/lib/gcc.o CC romstage/lib/halt.o CC romstage/lib/hexdump.o CC romstage/lib/imd.o CC romstage/lib/imd_cbmem.o CC romstage/lib/libgcc.o CC romstage/lib/lzma.o CC romstage/lib/lzmadecode.o CC romstage/lib/memchr.o CC romstage/lib/memcmp.o CC romstage/lib/memrange.o CC romstage/lib/prog_loaders.o CC romstage/lib/prog_ops.o CP romstage/lib/program.ld CC romstage/lib/ramtest.o CC romstage/lib/romstage_stack.o CC romstage/lib/stack.o CC romstage/lib/version.o CC romstage/mainboard/intel/i946gz/romstage.o CC romstage/northbridge/intel/i945/debug.o CC romstage/northbridge/intel/i945/early_init.o CC romstage/northbridge/intel/i945/errata.o CC romstage/northbridge/intel/i945/ram_calc.o CC romstage/northbridge/intel/i945/raminit.o CC romstage/superio/ite/common/early_serial.o CC romstage/superio/ite/it8718f/early_serial.o CC romstage/vboot/bootmode.o LINK cbfs/fallback/romstage.debug /home/bianchi/coreboot/util/crossgcc/xgcc/bin/i386-elf-ld.bfd: Cache as RAM area is too full build/romstage/console/console.o: In function `__usb_tx_byte': /home/bianchi/coreboot/src/include/console/usb.h:38: undefined reference to `usb_tx_byte' /home/bianchi/coreboot/src/include/console/usb.h:38: undefined reference to `usb_tx_byte' build/romstage/console/console.o: In function `__usb_tx_flush': /home/bianchi/coreboot/src/include/console/usb.h:39: undefined reference to `usb_tx_flush' src/arch/x86/Makefile.inc:264: recipe for target 'build/cbfs/fallback/romstage.debug' failed make: *** [build/cbfs/fallback/romstage.debug] Error 1 bianchi@ubuntu:~/coreboot$ How can I fix that ? I can give you the complete code on i946gz if you want to reproduce in your computer...I'm changing only romstage.c so far I attached with this email... Regards, Riko

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Re: [coreboot] southbridge/intel/i82801gx/i82801gx.h
by Nico Huber 15 Oct '16

15 Oct '16

Hi, On 15.10.2016 13:26, Antonius Riko wrote: > I closed the patch > > //#include <southbridge/intel/i82801gx/early_lpc.c> > //#include <southbridge/intel/i82801gx/early_smbus.c> > //#include <southbridge/intel/i82801gx/lpc.c> > > and I got error : > > bianchi@ubuntu:~/coreboot$ make > GEN generated/bootblock.ld > CP bootblock/arch/x86/bootblock.ld > LINK cbfs/fallback/bootblock.debug > OBJCOPY cbfs/fallback/bootblock.elf > OBJCOPY bootblock.raw.bin > CC romstage/mainboard/intel/i946gz/romstage.o > LINK cbfs/fallback/romstage.debug > build/romstage/mainboard/intel/i946gz/romstage.o: In function > `mainboard_romstage_entry': > /home/bianchi/coreboot/src/mainboard/intel/i946gz/romstage.c:214: > undefined reference to `southbridge_detect_s3_resume' > /home/bianchi/coreboot/src/mainboard/intel/i946gz/romstage.c:217: > undefined reference to `enable_smbus' > build/romstage/northbridge/intel/i945/raminit.o: In function `spd_read_byte': > /home/bianchi/coreboot/src/northbridge/intel/i945/raminit.c:62: > undefined reference to `smbus_read_byte' > /home/bianchi/coreboot/src/northbridge/intel/i945/raminit.c:62: > undefined reference to `smbus_read_byte' > /home/bianchi/coreboot/src/northbridge/intel/i945/raminit.c:62: > undefined reference to `smbus_read_byte' > /home/bianchi/coreboot/src/northbridge/intel/i945/raminit.c:62: > undefined reference to `smbus_read_byte' > /home/bianchi/coreboot/src/northbridge/intel/i945/raminit.c:62: > undefined reference to `smbus_read_byte' > build/romstage/northbridge/intel/i945/raminit.o:/home/bianchi/coreboot/src/northbridge/intel/i945/raminit.c:62: > more undefined references to `smbus_read_byte' follow > src/arch/x86/Makefile.inc:264: recipe for target > 'build/cbfs/fallback/romstage.debug' failed > make: *** [build/cbfs/fallback/romstage.debug] Error 1 it's hard to reproduce with only the Kconfig snippet. Here's what I've tried: copied src/mainboard/intel/d945gclf to i946gz, used your Kconfig below and the following Kconfig.name: config BOARD_INTEL_I946GZ bool "I946GZ" Then I got: build/romstage/mainboard/intel/i946gz/romstage.o: In function `mainboard_romstage_entry': /home/icon/coreboot/src/mainboard/intel/i946gz/romstage.c:162: undefined reference to `lpc47m15x_enable_serial' /home/icon/coreboot/src/mainboard/intel/i946gz/romstage.c:163: undefined reference to `lpc47m15x_enable_serial' which is ok, given that I mixed the d945gclf/romstage.c with your Kconfig. Maybe it's just a leftover from your previous try; did you do a `make clean`? If that doesn't help, maybe your .config is just messed up because of the Kconfig changes. You should try with a fresh .config (i.e. `rm .config` then `make menuconfig` again and select intel/i945gz). Nico PS. Please use the "reply" function of your mail client, if it has any. That way mails can be sorted in one thread correctly which makes the mailing list life a lot easier. > > my Kconfig at /src/mainboard/intel/i946gz : > > ## > ## This file is part of the coreboot project. > ## > ## Copyright (C) 2009 coresystems GmbH > ## > ## This program is free software; you can redistribute it and/or modify > ## it under the terms of the GNU General Public License as published by > ## the Free Software Foundation; version 2 of the License. > ## > ## This program is distributed in the hope that it will be useful, > ## but WITHOUT ANY WARRANTY; without even the implied warranty of > ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > ## GNU General Public License for more details. > ## > if BOARD_INTEL_I946GZ > > config BOARD_SPECIFIC_OPTIONS # dummy > def_bool y > select CPU_INTEL_SOCKET_LGA775 > select NORTHBRIDGE_INTEL_I945 > select NORTHBRIDGE_INTEL_SUBTYPE_I945GC > ##select NORTHBRIDGE_INTEL_I946GZ > ##select NORTHBRIDGE_INTEL_SUBTYPE_I946GZ > select CHECK_SLFRCS_ON_RESUME > select SOUTHBRIDGE_INTEL_I82801GX > select SUPERIO_ITE_IT8718F > select HAVE_OPTION_TABLE > select HAVE_PIRQ_TABLE > select HAVE_MP_TABLE > select HAVE_ACPI_TABLES > select HAVE_ACPI_RESUME > select BOARD_ROMSIZE_KB_512 > select CHANNEL_XOR_RANDOMIZATION > select MAINBOARD_HAS_NATIVE_VGA_INIT > select INTEL_EDID > > config MAINBOARD_DIR > string > default intel/i946gz > > config MAINBOARD_PART_NUMBER > string > default "I946GZ" > > config MMCONF_BASE_ADDRESS > hex > default 0xf0000000 > > config IRQ_SLOT_COUNT > int > default 18 > > config MAX_CPUS > int > default 1 > > endif # BOARD_INTEL_I946GZ > > > ==== > Including .c files is a bad idea. We did that before and still do in > some places, but will get rid of it in the future hopefully. Also you > are mixing romstage (early_*.c) and ramstage (lpc.c) code here. > > I guess the remaining errors are caused by the mixing. > > Hope that helps, > Nico > > ====== > > >

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Re: [coreboot] Official builds for EoL Chromebooks
by John Lewis 15 Oct '16

15 Oct '16

Yes, I think in this case you're mixing your alternate realities. No, no direct association. On 15/10/16 11:44, Zoran Stojsavljevic wrote: > Hello John, > > I'll investigate this in depth... Somehow, I remember, you were > connected with them (anyhow - as free lancer, or in different way), > aren't you? ;-) > > Maybe I am just too old dummy cat, and I mix virtual realities... > Everything is possible! I admit. > > Thank you, > Zoran > > On 10/15/16, John Lewis <jlewis(a)johnlewis.ie> wrote: >> On 13/10/16 20:45, Zoran Stojsavljevic wrote: >>>> John Lewis has some upstream firmware for the older >>> SandyBridge/IvyBridge models, >>>> but his Haswell firmware is build from Google's tree/branches not >>> upstream. >>>> He also has no plans for any future upstream firmware. >>> Once upon a time when John worked for SAGE Electronics. I remember >>> this time, about 3 and more years ago. ;-) >>> >> I never worked for Sage. >>> SAGE was the first company (FSP echo system partner) to accept and >>> adopt INTEL FSP (midst of 2013, IVB was the first child). Since then, >>> lot of things have changed. Lot of... SAGE is not anymore in this >>> business, and, and... .. . (you all fill in the dots). :-) >>> >>> Zoran >>> >>> On Thu, Oct 13, 2016 at 4:53 PM, Matt DeVillier >>> <matt.devillier(a)gmail.com <mailto:matt.devillier@gmail.com>> wrote: >>> >>> Emi, >>> >>> I think this is what you're looking >>> for: https://www.coreboot.org/Supported_Motherboards >>> <https://www.coreboot.org/Supported_Motherboards> >>> It contains the commit hash, build config, and a few other logs >>> for each device/commit. It is user submitted though, since there >>> doesn't exist a test setup for every supported device. >>> >>> Right now, I'm the main builder/distributor of upstream coreboot >>> firmware for ChromeOS devices; I support all Haswell, Broadwell, >>> and some Baytrail devices, the former with both UEFI and Legacy >>> Boot variants. When time permits, I'll expand that to cover the >>> rest of the Baytrail devices, then move on to adding support for >>> Skylake. No plans for Braswell support unless I acquire a device >>> on which to test. >>> >>> John Lewis has some upstream firmware for the older >>> SandyBridge/IvyBridge models, but his Haswell firmware is build >>> from Google's tree/branches not upstream. He also has no plans >>> for any future upstream firmware. >>> >>> cheers, >>> Matt >>> >>> On Thu, Oct 13, 2016 at 6:49 AM, Emilian Bold >>> <emilian.bold(a)gmail.com <mailto:emilian.bold@gmail.com>> wrote: >>> >>> Hello, >>> >>> Now that Coreboot has reproducible builds, could you provide a >>> list of build hashes for Chromebooks that are or will soon >>> reach End of Life? >>> >>> I see >>> on https://support.google.com/chrome/a/answer/6220366?hl=en >>> <https://support.google.com/chrome/a/answer/6220366?hl=en> that >>> 2 Chromebooks will reach End of Life in 2016 and 3 more in >>> 2017 then 7 in 2018. I assume the number will increase each year. >>> >>> I know that Coreboot does not distribute builds, but the >>> little Custom roms section >>> on https://www.coreboot.org/users.html >>> <https://www.coreboot.org/users.html> seems insufficient. >>> >>> It's easy making a build, you just need to have the certainty >>> you did it well. Or that the one you are downloading is correct. >>> >>> Posting an official SHA-256 hash for a ROM would solve this. >>> >>> --emi >>> >>> -- >>> coreboot mailing list: coreboot(a)coreboot.org >>> <mailto:coreboot@coreboot.org> >>> https://www.coreboot.org/mailman/listinfo/coreboot >>> <https://www.coreboot.org/mailman/listinfo/coreboot> >>> >>> >>> >>> -- >>> coreboot mailing list: coreboot(a)coreboot.org >>> <mailto:coreboot@coreboot.org> >>> https://www.coreboot.org/mailman/listinfo/coreboot >>> <https://www.coreboot.org/mailman/listinfo/coreboot> >>> >>> >>> >>> >>

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Re: [coreboot] southbridge/intel/i82801gx/i82801gx.h
by Antonius Riko 15 Oct '16

15 Oct '16

Thanks, for the response.... Here's what I've got, what else do I miss here ? I closed the patch //#include <southbridge/intel/i82801gx/early_lpc.c> //#include <southbridge/intel/i82801gx/early_smbus.c> //#include <southbridge/intel/i82801gx/lpc.c> and I got error : bianchi at ubuntu <https://www.coreboot.org/mailman/listinfo/coreboot>:~/coreboot$ make GEN generated/bootblock.ld CP bootblock/arch/x86/bootblock.ld LINK cbfs/fallback/bootblock.debug OBJCOPY cbfs/fallback/bootblock.elf OBJCOPY bootblock.raw.bin CC romstage/mainboard/intel/i946gz/romstage.o LINK cbfs/fallback/romstage.debug build/romstage/mainboard/intel/i946gz/romstage.o: In function `mainboard_romstage_entry': /home/bianchi/coreboot/src/mainboard/intel/i946gz/romstage.c:214: undefined reference to `southbridge_detect_s3_resume' /home/bianchi/coreboot/src/mainboard/intel/i946gz/romstage.c:217: undefined reference to `enable_smbus' build/romstage/northbridge/intel/i945/raminit.o: In function `spd_read_byte': /home/bianchi/coreboot/src/northbridge/intel/i945/raminit.c:62: undefined reference to `smbus_read_byte' /home/bianchi/coreboot/src/northbridge/intel/i945/raminit.c:62: undefined reference to `smbus_read_byte' /home/bianchi/coreboot/src/northbridge/intel/i945/raminit.c:62: undefined reference to `smbus_read_byte' /home/bianchi/coreboot/src/northbridge/intel/i945/raminit.c:62: undefined reference to `smbus_read_byte' /home/bianchi/coreboot/src/northbridge/intel/i945/raminit.c:62: undefined reference to `smbus_read_byte' build/romstage/northbridge/intel/i945/raminit.o:/home/bianchi/coreboot/src/northbridge/intel/i945/raminit.c:62: more undefined references to `smbus_read_byte' follow src/arch/x86/Makefile.inc:264: recipe for target 'build/cbfs/fallback/romstage.debug' failed make: *** [build/cbfs/fallback/romstage.debug] Error 1 my Kconfig at /src/mainboard/intel/i946gz : ## ## This file is part of the coreboot project. ## ## Copyright (C) 2009 coresystems GmbH ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by ## the Free Software Foundation; version 2 of the License. ## ## This program is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ## GNU General Public License for more details. ## if BOARD_INTEL_I946GZ config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select CPU_INTEL_SOCKET_LGA775 select NORTHBRIDGE_INTEL_I945 select NORTHBRIDGE_INTEL_SUBTYPE_I945GC ##select NORTHBRIDGE_INTEL_I946GZ ##select NORTHBRIDGE_INTEL_SUBTYPE_I946GZ select CHECK_SLFRCS_ON_RESUME select SOUTHBRIDGE_INTEL_I82801GX select SUPERIO_ITE_IT8718F select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select HAVE_ACPI_TABLES select HAVE_ACPI_RESUME select BOARD_ROMSIZE_KB_512 select CHANNEL_XOR_RANDOMIZATION select MAINBOARD_HAS_NATIVE_VGA_INIT select INTEL_EDID config MAINBOARD_DIR string default intel/i946gz config MAINBOARD_PART_NUMBER string default "I946GZ" config MMCONF_BASE_ADDRESS hex default 0xf0000000 config IRQ_SLOT_COUNT int default 18 config MAX_CPUS int default 1 endif # BOARD_INTEL_I946GZ ==== Including .c files is a bad idea. We did that before and still do in some places, but will get rid of it in the future hopefully. Also you are mixing romstage (early_*.c) and ramstage (lpc.c) code here. I guess the remaining errors are caused by the mixing. Hope that helps, Nico

1 0

Re: [coreboot] southbridge/intel/i82801gx/i82801gx.h
by Antonius Riko 15 Oct '16

15 Oct '16

I closed the patch //#include <southbridge/intel/i82801gx/early_lpc.c> //#include <southbridge/intel/i82801gx/early_smbus.c> //#include <southbridge/intel/i82801gx/lpc.c> and I got error : bianchi@ubuntu:~/coreboot$ make GEN generated/bootblock.ld CP bootblock/arch/x86/bootblock.ld LINK cbfs/fallback/bootblock.debug OBJCOPY cbfs/fallback/bootblock.elf OBJCOPY bootblock.raw.bin CC romstage/mainboard/intel/i946gz/romstage.o LINK cbfs/fallback/romstage.debug build/romstage/mainboard/intel/i946gz/romstage.o: In function `mainboard_romstage_entry': /home/bianchi/coreboot/src/mainboard/intel/i946gz/romstage.c:214: undefined reference to `southbridge_detect_s3_resume' /home/bianchi/coreboot/src/mainboard/intel/i946gz/romstage.c:217: undefined reference to `enable_smbus' build/romstage/northbridge/intel/i945/raminit.o: In function `spd_read_byte': /home/bianchi/coreboot/src/northbridge/intel/i945/raminit.c:62: undefined reference to `smbus_read_byte' /home/bianchi/coreboot/src/northbridge/intel/i945/raminit.c:62: undefined reference to `smbus_read_byte' /home/bianchi/coreboot/src/northbridge/intel/i945/raminit.c:62: undefined reference to `smbus_read_byte' /home/bianchi/coreboot/src/northbridge/intel/i945/raminit.c:62: undefined reference to `smbus_read_byte' /home/bianchi/coreboot/src/northbridge/intel/i945/raminit.c:62: undefined reference to `smbus_read_byte' build/romstage/northbridge/intel/i945/raminit.o:/home/bianchi/coreboot/src/northbridge/intel/i945/raminit.c:62: more undefined references to `smbus_read_byte' follow src/arch/x86/Makefile.inc:264: recipe for target 'build/cbfs/fallback/romstage.debug' failed make: *** [build/cbfs/fallback/romstage.debug] Error 1 my Kconfig at /src/mainboard/intel/i946gz : ## ## This file is part of the coreboot project. ## ## Copyright (C) 2009 coresystems GmbH ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by ## the Free Software Foundation; version 2 of the License. ## ## This program is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ## GNU General Public License for more details. ## if BOARD_INTEL_I946GZ config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select CPU_INTEL_SOCKET_LGA775 select NORTHBRIDGE_INTEL_I945 select NORTHBRIDGE_INTEL_SUBTYPE_I945GC ##select NORTHBRIDGE_INTEL_I946GZ ##select NORTHBRIDGE_INTEL_SUBTYPE_I946GZ select CHECK_SLFRCS_ON_RESUME select SOUTHBRIDGE_INTEL_I82801GX select SUPERIO_ITE_IT8718F select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select HAVE_ACPI_TABLES select HAVE_ACPI_RESUME select BOARD_ROMSIZE_KB_512 select CHANNEL_XOR_RANDOMIZATION select MAINBOARD_HAS_NATIVE_VGA_INIT select INTEL_EDID config MAINBOARD_DIR string default intel/i946gz config MAINBOARD_PART_NUMBER string default "I946GZ" config MMCONF_BASE_ADDRESS hex default 0xf0000000 config IRQ_SLOT_COUNT int default 18 config MAX_CPUS int default 1 endif # BOARD_INTEL_I946GZ ==== Including .c files is a bad idea. We did that before and still do in some places, but will get rid of it in the future hopefully. Also you are mixing romstage (early_*.c) and ramstage (lpc.c) code here. I guess the remaining errors are caused by the mixing. Hope that helps, Nico ======

1 0

Re: [coreboot] Official builds for EoL Chromebooks
by John Lewis 15 Oct '16

15 Oct '16

On 13/10/16 20:45, Zoran Stojsavljevic wrote: > > John Lewis has some upstream firmware for the older > SandyBridge/IvyBridge models, > > but his Haswell firmware is build from Google's tree/branches not > upstream. > > He also has no plans for any future upstream firmware. > > Once upon a time when John worked for SAGE Electronics. I remember > this time, about 3 and more years ago. ;-) > I never worked for Sage. > SAGE was the first company (FSP echo system partner) to accept and > adopt INTEL FSP (midst of 2013, IVB was the first child). Since then, > lot of things have changed. Lot of... SAGE is not anymore in this > business, and, and... .. . (you all fill in the dots). :-) > > Zoran > > On Thu, Oct 13, 2016 at 4:53 PM, Matt DeVillier > <matt.devillier(a)gmail.com <mailto:matt.devillier@gmail.com>> wrote: > > Emi, > > I think this is what you're looking > for: https://www.coreboot.org/Supported_Motherboards > <https://www.coreboot.org/Supported_Motherboards> > It contains the commit hash, build config, and a few other logs > for each device/commit. It is user submitted though, since there > doesn't exist a test setup for every supported device. > > Right now, I'm the main builder/distributor of upstream coreboot > firmware for ChromeOS devices; I support all Haswell, Broadwell, > and some Baytrail devices, the former with both UEFI and Legacy > Boot variants. When time permits, I'll expand that to cover the > rest of the Baytrail devices, then move on to adding support for > Skylake. No plans for Braswell support unless I acquire a device > on which to test. > > John Lewis has some upstream firmware for the older > SandyBridge/IvyBridge models, but his Haswell firmware is build > from Google's tree/branches not upstream. He also has no plans > for any future upstream firmware. > > cheers, > Matt > > On Thu, Oct 13, 2016 at 6:49 AM, Emilian Bold > <emilian.bold(a)gmail.com <mailto:emilian.bold@gmail.com>> wrote: > > Hello, > > Now that Coreboot has reproducible builds, could you provide a > list of build hashes for Chromebooks that are or will soon > reach End of Life? > > I see > on https://support.google.com/chrome/a/answer/6220366?hl=en > <https://support.google.com/chrome/a/answer/6220366?hl=en> that > 2 Chromebooks will reach End of Life in 2016 and 3 more in > 2017 then 7 in 2018. I assume the number will increase each year. > > I know that Coreboot does not distribute builds, but the > little Custom roms section > on https://www.coreboot.org/users.html > <https://www.coreboot.org/users.html> seems insufficient. > > It's easy making a build, you just need to have the certainty > you did it well. Or that the one you are downloading is correct. > > Posting an official SHA-256 hash for a ROM would solve this. > > --emi > > -- > coreboot mailing list: coreboot(a)coreboot.org > <mailto:coreboot@coreboot.org> > https://www.coreboot.org/mailman/listinfo/coreboot > <https://www.coreboot.org/mailman/listinfo/coreboot> > > > > -- > coreboot mailing list: coreboot(a)coreboot.org > <mailto:coreboot@coreboot.org> > https://www.coreboot.org/mailman/listinfo/coreboot > <https://www.coreboot.org/mailman/listinfo/coreboot> > > > >

2 1

TALOS secure workstation campaign has launched
by Leah Rowe 15 Oct '16

15 Oct '16

-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA256 Hello everyone, Here: https://www.crowdsupply.com/raptor-computing-systems/talos-secure-workst ation This is a high-end desktop/workstation, on par with Intel in terms of performance, and it's going to ship with entirely libre software on it, including the boot firmware. From the factory, brand new. Libreboot is going to support it, once it starts shipping (I'll be working with Timothy Pearson, the engineer behind the TALOS project, in my capacity as leader of the libreboot project). Spread the word! This campaign needs to succeed. - -- Leah Rowe Libreboot developer Use free software. Free as in freedom. https://en.wikipedia.org/wiki/Free_software Use a free operating system, GNU/Linux. https://libreboot.org/docs/distros/ Or BSD: https://libreboot.org/docs/bsd/ Use a free BIOS. https://libreboot.org/ Support computer user freedom. https://peers.community/ Minifree Ltd, trading as Ministry of Freedom | Registered in England, No. 9361826 | VAT No. GB202190462 Registered Office: 19 Hilton Road, Canvey Island, Essex SS8 9QA, UK | Web: http://minifree.org/ -----BEGIN PGP SIGNATURE----- iQEcBAEBCAAGBQJYAgPKAAoJEP9Ft0z50c+Uv0UH/iWZt7ZZAMyiFjwv4y7Xa8zM jENqT3Q86PV0f45pB0262/ABtA1loBTmJ4ag7Y9WB4fg6BlgK0BV4snwoUKazMB7 j9CCzHfAPpkTKjY4t+rTu5fH8Yx2EdinhgjQi0SW8pYYn8bu+XlheLKDvflOcaIc TXRWhU8D/x77FbKWNePuG9xQCoOIPaQ+JKwrKmk1Q4iepaFhzRh7edoFpVBhnJeV vMS5myX7oJgTwuLEsh41CT0wc8vmZEW8APcCsYYzmzi6STE5uqzoKoPWw+Jst5Av agD7X/N0nNjcLnk0q3FTMOolC4Tk1+G7E6eSnukZq3q/RZUmkvZ3YefEZOtnHjs= =VW6q -----END PGP SIGNATURE-----

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coreboot October 2016