coreboot January 2013

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Patch set updated for coreboot: 59a8e96 Omit a lot of pinmux code in __PRE_RAM__ stage
by David Hendricks 11 Jan '13

11 Jan '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2061 -gerrit commit 59a8e968e27e4e15cb52d5e2f0a753be735114d5 Author: David Hendricks <dhendrix(a)chromium.org> Date: Thu Jan 10 12:00:21 2013 -0800 Omit a lot of pinmux code in __PRE_RAM__ stage This omits a lot of pinmux code to save space. It is no longer needed. Change-Id: I970d2111855ee5e2d960d38f99100b31b2b39eb5 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> --- src/cpu/samsung/exynos5250/pinmux.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/src/cpu/samsung/exynos5250/pinmux.c b/src/cpu/samsung/exynos5250/pinmux.c index becced2..ffdd182 100644 --- a/src/cpu/samsung/exynos5250/pinmux.c +++ b/src/cpu/samsung/exynos5250/pinmux.c @@ -30,7 +30,12 @@ int exynos_pinmux_config(enum periph_id peripheral, int flags) { - int i, start, count, start_ext, pin_ext, pin, drv; + int i, start, count; + +#ifndef __PRE_RAM__ + /* Variables only in RAM stage. */ + int start_ext, pin_ext, pin, drv; +#endif switch (peripheral) { case PERIPH_ID_UART0: @@ -57,6 +62,8 @@ int exynos_pinmux_config(enum periph_id peripheral, int flags) gpio_cfg_pin(i, EXYNOS_GPIO_FUNC(0x2)); } break; + +#ifndef __PRE_RAM__ case PERIPH_ID_SDMMC0: case PERIPH_ID_SDMMC1: case PERIPH_ID_SDMMC2: @@ -294,6 +301,8 @@ int exynos_pinmux_config(enum periph_id peripheral, int flags) for (i = 0; i < 5; i++) gpio_cfg_pin(GPIO_B00 + i, EXYNOS_GPIO_FUNC(0x02)); break; +#endif // __PRE_RAM__ + default: debug("%s: invalid peripheral %d", __func__, peripheral); return -1;

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New patch to review for coreboot: 81c9624 Omit extra clock timing table entries to save some space
by David Hendricks 11 Jan '13

11 Jan '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2088 -gerrit commit 81c9624ff1fa79b7feeaa0bacaf314be63f3c764 Author: David Hendricks <dhendrix(a)chromium.org> Date: Mon Dec 31 16:34:21 2012 -0800 Omit extra clock timing table entries to save some space This is just a temporary hack to give us some more room to breathe while developing proper bootblock and romstage code... Change-Id: I0d114b6e69187bf4d0dce6ab2ac538c3e112bd7f Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/cpu/samsung/exynos5250/clock.c | 9 +++++++++ src/cpu/samsung/exynos5250/clock_init.c | 15 +++++++++++++-- 2 files changed, 22 insertions(+), 2 deletions(-) diff --git a/src/cpu/samsung/exynos5250/clock.c b/src/cpu/samsung/exynos5250/clock.c index 0250d77..41a653e 100644 --- a/src/cpu/samsung/exynos5250/clock.c +++ b/src/cpu/samsung/exynos5250/clock.c @@ -169,6 +169,8 @@ unsigned long clock_get_periph_rate(enum periph_id peripheral) src = readl(&clk->src_peric0); div = readl(&clk->div_peric0); break; + /* FIXME (dhendrix): temporarily omitted for space */ +#ifndef __PRE_RAM__ case PERIPH_ID_PWM0: case PERIPH_ID_PWM1: case PERIPH_ID_PWM2: @@ -202,6 +204,7 @@ unsigned long clock_get_periph_rate(enum periph_id peripheral) src = readl(&clk->src_fsys); div = readl(&clk->div_fsys1); break; +#endif /* __PRE_RAM__ */ case PERIPH_ID_I2C0: case PERIPH_ID_I2C1: case PERIPH_ID_I2C2: @@ -239,10 +242,13 @@ unsigned long clock_get_periph_rate(enum periph_id peripheral) sub_div = (div >> bit_info->div_bit) & 0xf; sub_clk = sclk / (sub_div + 1); + /* FIXME (dhendrix): temporarily omitted for space */ +#ifndef __PRE_RAM__ if (peripheral == PERIPH_ID_SDMMC0 || peripheral == PERIPH_ID_SDMMC2) { div = (div >> bit_info->prediv_bit) & 0xff; return sub_clk / (div + 1); } +#endif /* __PRE_RAM__ */ return sub_clk; } @@ -466,6 +472,8 @@ int clock_set_rate(enum periph_id periph_id, unsigned int rate) return 0; } +/* FIXME(dhendrix): temporarily omitted for space */ +#if 0 int clock_set_mshci(enum periph_id peripheral) { struct exynos5_clock *clk = @@ -504,6 +512,7 @@ int clock_set_mshci(enum periph_id peripheral) } return 0; } +#endif #ifdef CONFIG_OF_CONTROL int clock_decode_periph_id(const void *blob, int node) diff --git a/src/cpu/samsung/exynos5250/clock_init.c b/src/cpu/samsung/exynos5250/clock_init.c index d2abfa9..a8a50ea 100644 --- a/src/cpu/samsung/exynos5250/clock_init.c +++ b/src/cpu/samsung/exynos5250/clock_init.c @@ -40,6 +40,9 @@ #include "setup.h" struct arm_clk_ratios arm_clk_ratios[] = { + /* FIXME(dhendrix): this is just a stop-gap measure to reduce image + size while we implement bootblock and romstage functionality */ +#if 0 { .arm_freq_mhz = 600, @@ -116,6 +119,8 @@ struct arm_clk_ratios arm_clk_ratios[] = { .cpud_ratio = 0x3, .arm_ratio = 0x0, }, { +#endif + { .arm_freq_mhz = 1700, .apll_mdiv = 0x1a9, @@ -238,6 +243,10 @@ struct mem_timings mem_timings[] = { .send_zq_init = 1, .impedance = IMP_OUTPUT_DRV_30_OHM, .gate_leveling_enable = 0, + /* FIXME(dhendrix): this is just a stop-gap measure to reduce image + size while we implement bootblock and romstage functionality */ + } +#if 0 }, { .mem_manuf = MEM_MANUF_SAMSUNG, .mem_type = DDR_MODE_DDR3, @@ -552,6 +561,7 @@ struct mem_timings mem_timings[] = { .impedance = IMP_OUTPUT_DRV_40_OHM, .gate_leveling_enable = 1, } +#endif }; /** @@ -723,6 +733,8 @@ struct arm_clk_ratios *get_arm_ratios(void) struct mem_timings *clock_get_mem_timings(void) { + return &mem_timings[0]; +#if 0 struct mem_timings *mem; enum ddr_mode mem_type; enum mem_manuf mem_manuf; @@ -741,6 +753,7 @@ struct mem_timings *clock_get_mem_timings(void) } } return NULL; +#endif } void system_clock_init() @@ -855,7 +868,6 @@ void system_clock_init() setbits_le32(&clk->pll_div2_sel, MUX_BPLL_FOUT_SEL); } - /* Set CPLL */ writel(CPLL_CON1_VAL, &clk->cpll_con1); val = set_pll(mem->cpll_mdiv, mem->cpll_pdiv, mem->cpll_sdiv); @@ -979,7 +991,6 @@ void system_clock_init() writel(CLK_REG_DISABLE, &clk->clkout_cmu_r0x); writel(CLK_REG_DISABLE, &clk->clkout_cmu_r1x); writel(CLK_REG_DISABLE, &clk->clkout_cmu_cdrex); - writel(CLK_SRC_PERIC0_VAL, &clk->src_peric0); writel(CLK_DIV_PERIC0_VAL, &clk->div_peric0); writel(CLK_SRC_PERIC1_VAL, &clk->src_peric1);

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Patch set updated for coreboot: 9a1451c omit code that touches PWM to save some space
by David Hendricks 11 Jan '13

11 Jan '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2087 -gerrit commit 9a1451c8e25f26c547c56b3a5ebf276cbd31b3db Author: David Hendricks <dhendrix(a)chromium.org> Date: Mon Dec 31 16:30:46 2012 -0800 omit code that touches PWM to save some space This is just a temporary hack to give us some more space while developing proper bootblock and romstage code... Change-Id: I50b92e89b920cbc455d1da5be9afcffbf49f5000 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/cpu/samsung/exynos5250/lowlevel_init_c.c | 2 +- src/cpu/samsung/s5p-common/Makefile.inc | 2 +- src/cpu/samsung/s5p-common/timer.c | 54 ++++++++++++++-------------- 3 files changed, 30 insertions(+), 28 deletions(-) diff --git a/src/cpu/samsung/exynos5250/lowlevel_init_c.c b/src/cpu/samsung/exynos5250/lowlevel_init_c.c index 848ebee..6c1940f 100644 --- a/src/cpu/samsung/exynos5250/lowlevel_init_c.c +++ b/src/cpu/samsung/exynos5250/lowlevel_init_c.c @@ -113,7 +113,7 @@ int lowlevel_init_subsystems(void) console_tx_byte('C'); } } - init_timer(); /* FIXME(dhendrix): was timer_init() */ +// init_timer(); /* FIXME(dhendrix): was timer_init() */ #if 0 if (actions & DO_CLOCKS) { diff --git a/src/cpu/samsung/s5p-common/Makefile.inc b/src/cpu/samsung/s5p-common/Makefile.inc index 7de3c28..9557b85 100644 --- a/src/cpu/samsung/s5p-common/Makefile.inc +++ b/src/cpu/samsung/s5p-common/Makefile.inc @@ -1,5 +1,5 @@ romstage-y += cpu_info.c -romstage-y += pwm.c # needed by timer.c +#romstage-y += pwm.c # needed by timer.c romstage-y += s5p_gpio.c romstage-y += timer.c romstage-y += s3c24x0_i2c.c diff --git a/src/cpu/samsung/s5p-common/timer.c b/src/cpu/samsung/s5p-common/timer.c index 373c374..c10ce87 100644 --- a/src/cpu/samsung/s5p-common/timer.c +++ b/src/cpu/samsung/s5p-common/timer.c @@ -25,16 +25,13 @@ #include <common.h> #include <arch/io.h> -//#include <cpu/samsung/exynos5250/pwm.h> -//#include <cpu/samsung/exynos5250/clk.h> + #include <cpu/samsung/s5p-common/pwm.h> #include <cpu/samsung/s5p-common/clk.h> #include <cpu/samsung/exynos5250/cpu.h> #include <cpu/samsung/exynos5-common/exynos5-common.h> -//#include <pwm.h> -//DECLARE_GLOBAL_DATA_PTR; static unsigned long long timer_reset_value; static unsigned long lastinc; @@ -59,28 +56,6 @@ static unsigned long timer_get_us_down(void) return readl(&timer->tcnto4); } -int init_timer(void) -{ - /* Timer may have been enabled in SPL */ - if (!pwm_check_enabled(4)) { - /* PWM Timer 4 */ - pwm_init(4, MUX_DIV_4, 0); - pwm_config(4, 100000, 100000); - pwm_enable(4); -#ifndef CONFIG_SPL_BUILD - /* Use this as the current monotonic time in us */ - //gd->timer_reset_value = 0; - timer_reset_value = 0; - - /* Use this as the last timer value we saw */ - //gd->lastinc = timer_get_us_down(); - lastinc = timer_get_us_down(); -#endif - } - - return 0; -} - /* * timer without interrupts */ @@ -107,6 +82,32 @@ unsigned long get_timer(unsigned long base) return timer_reset_value / 1000 - base; } +/* FIXME(dhendrix): We should probably do init_timer() in romstage. This + * is just a stop-gap to reduce image size until we have the proper + * bootblock code implemented. */ +#ifndef __PRE_RAM__ +int init_timer(void) +{ + /* Timer may have been enabled in SPL */ + if (!pwm_check_enabled(4)) { + /* PWM Timer 4 */ + pwm_init(4, MUX_DIV_4, 0); + pwm_config(4, 100000, 100000); + pwm_enable(4); +#ifndef CONFIG_SPL_BUILD + /* Use this as the current monotonic time in us */ + //gd->timer_reset_value = 0; + timer_reset_value = 0; + + /* Use this as the last timer value we saw */ + //gd->lastinc = timer_get_us_down(); + lastinc = timer_get_us_down(); +#endif + } + + return 0; +} + unsigned long timer_get_us(void) { struct s5p_timer *const timer = s5p_get_base_timer(); @@ -151,3 +152,4 @@ unsigned long timer_get_boot_us(void) { return timer_get_us(); } +#endif /* __PRE_RAM__ */

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Patch merged into coreboot/master: ea22796 armv7: Add temporary build script for CrOS devs
by gerrit＠coreboot.org 11 Jan '13

11 Jan '13

the following patch was just integrated into master: commit ea22796edaa5c51271ea98590d22eea3976cadba Author: David Hendricks <dhendrix(a)chromium.org> Date: Thu Jan 10 15:07:59 2013 -0800 armv7: Add temporary build script for CrOS devs This build script will: - Build coreboot.rom - Download BL1, extract and place it if necessary - Do a partial flash via Servo, using some flashrom trickery to make the process fast. This probably should not be submitted, unless the intention is to back it out eventually. Credit goes to Hung-Te for writing the original version. Change-Id: Ia7a4bea6077416fc06768a5de5ee07edc973ede2 Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Reviewed-on: http://review.coreboot.org/2134 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Build-Tested: build bot (Jenkins) at Fri Jan 11 00:32:42 2013, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Fri Jan 11 01:45:48 2013, giving +2 See http://review.coreboot.org/2134 for details. -gerrit

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Patch merged into coreboot/master: eb5e252 exynos5250: Hacked up lowlevel_init_c
by gerrit＠coreboot.org 11 Jan '13

11 Jan '13

the following patch was just integrated into master: commit eb5e252ce16acd80e5374a351d49e9d90cfed982 Author: David Hendricks <dhendrix(a)chromium.org> Date: Thu Jan 10 15:05:22 2013 -0800 exynos5250: Hacked up lowlevel_init_c This is the first lowlevel init routine that gets called in romstage. It's fugly and needs a lot of clean-up, but does the job for now. Change-Id: Id54bf4f1c3753bcbed5f6b5eeb4b48bc3b41ce93 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Reviewed-on: http://review.coreboot.org/2133 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Build-Tested: build bot (Jenkins) at Fri Jan 11 00:25:57 2013, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Fri Jan 11 01:45:12 2013, giving +2 See http://review.coreboot.org/2133 for details. -gerrit

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Patch merged into coreboot/master: b9fb213 exynos5250: Temporarily remove intermediate rule in Makefile
by gerrit＠coreboot.org 11 Jan '13

11 Jan '13

the following patch was just integrated into master: commit b9fb213f85b9a6c76253c21504c6bfe838670de7 Author: David Hendricks <dhendrix(a)chromium.org> Date: Thu Jan 10 15:00:23 2013 -0800 exynos5250: Temporarily remove intermediate rule in Makefile This cannot be used until we get the BL1 mess sorted out. Change-Id: I2490addb31256e27caa89ebb5b1501296e6903bd Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Reviewed-on: http://review.coreboot.org/2132 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Build-Tested: build bot (Jenkins) at Fri Jan 11 00:19:33 2013, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Fri Jan 11 00:44:03 2013, giving +2 See http://review.coreboot.org/2132 for details. -gerrit

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Patch merged into coreboot/master: 105da50 AMD: Set the mask of MTRR according to CONFIG_CPU_ADDR_BITS
by gerrit＠coreboot.org 11 Jan '13

11 Jan '13

the following patch was just integrated into master: commit 105da50df4fe6073575a2eb6247d916746b6143e Author: Zheng Bao <fishbaozi(a)gmail.com> Date: Sat Jan 5 12:17:46 2013 +0800 AMD: Set the mask of MTRR according to CONFIG_CPU_ADDR_BITS The high bits of mtrr mask are MBZ (Must be zero). Writing 1 to these bits will cause exception. So be carefull when spread this change. The supermicro/h8scm needs more work. Currently it is set as it was. We need to check if the F10 and F15 have different value. Change-Id: I2dd8bf07ecee2fe4d1721cec6b21623556e68947 Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: zbao <fishbaozi(a)gmail.com> Reviewed-on: http://review.coreboot.org/1661 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303(a)gmail.com> Build-Tested: build bot (Jenkins) at Sat Jan 5 03:52:46 2013, giving +1 Reviewed-By: Marc Jones <marcj303(a)gmail.com> at Fri Jan 11 00:42:07 2013, giving +2 See http://review.coreboot.org/1661 for details. -gerrit

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Patch set updated for coreboot: 8b0ae4f armv7: invoke intermediate build rules
by David Hendricks 11 Jan '13

11 Jan '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2095 -gerrit commit 8b0ae4fef9d230a8ea79b052f58be380c9deff7d Author: David Hendricks <dhendrix(a)chromium.org> Date: Wed Jan 2 17:48:49 2013 -0800 armv7: invoke intermediate build rules This adds $$(INTERMEDIATE) as a pre-requisite for coreboot.rom on armv7. It is modeled after the $(obj)/coreboot.rom rule for x86. Change-Id: I483a88035fa2288829b6e042e51ef932c8c4f23c Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/arch/armv7/Makefile.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/arch/armv7/Makefile.inc b/src/arch/armv7/Makefile.inc index d7fbbdf..8176f9a 100644 --- a/src/arch/armv7/Makefile.inc +++ b/src/arch/armv7/Makefile.inc @@ -58,7 +58,7 @@ $(obj)/coreboot.pre1: $(CBFSTOOL) mv $(obj)/coreboot.rom $@ endif -$(obj)/coreboot.rom: $(obj)/coreboot.pre $(objcbfs)/coreboot_ram.elf $(CBFSTOOL) $(call strip_quotes,$(COREBOOT_ROM_DEPENDENCIES)) +$(obj)/coreboot.rom: $(obj)/coreboot.pre $(objcbfs)/coreboot_ram.elf $(CBFSTOOL) $(call strip_quotes,$(COREBOOT_ROM_DEPENDENCIES)) $$(INTERMEDIATE) @printf " CBFS $(subst $(obj)/,,$(@))\n" cp $(obj)/coreboot.pre $@.tmp if [ -f $(objcbfs)/coreboot_ap.elf ]; \

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New patch to review for coreboot: 41b3717 armv7: Add temporary build script for CrOS devs
by David Hendricks 11 Jan '13

11 Jan '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2134 -gerrit commit 41b3717b980ca7ba480dbf7019389e64a7280ecb Author: David Hendricks <dhendrix(a)chromium.org> Date: Thu Jan 10 15:07:59 2013 -0800 armv7: Add temporary build script for CrOS devs This build script will: - Build coreboot.rom - Download BL1, extract and place it if necessary - Do a partial flash via Servo, using some flashrom trickery to make the process fast. This probably should not be submitted, unless the intention is to back it out eventually. Credit goes to Hung-Te for writing the original version. Change-Id: Ia7a4bea6077416fc06768a5de5ee07edc973ede2 Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- cros/build | 82 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 82 insertions(+) diff --git a/cros/build b/cros/build new file mode 100755 index 0000000..13f7d92 --- /dev/null +++ b/cros/build @@ -0,0 +1,82 @@ +#!/bin/sh + +SCRIPT="$0" +SCRIPT_DIR="$(dirname "$(readlink -f "$0")")" + +OUTPUT="build/coreboot.rom" +TMP_DIFF="$SCRIPT_DIR/.image-diff.bin" +FLASHROM="/usr/local/sbin/flashrom" + +BL1_NAME="E5250.nbl1.bin" +BL1_PATH="3rdparty/cpu/samsung/exynos5250/" +BL1_URL="http://commondatastorage.googleapis.com/chromeos-localmirror/distfiles/exyn…" + +die() { + echo "$*" >&2 + exit 1 +} + +create_diff_128k() { + local image_file="$1" + local diff_file="$2" + cp -f "$image_file" "$diff_file" + dd if=/dev/zero of=$diff_file bs=1 count=$((128*1024)) conv=notrunc +} + +fast_flash_image() { + local image_file="$1" + local diff_file="$2" + dut-control spi2_buf_en:on spi2_buf_on_flex_en:on spi2_vref:pp1800 + sudo ${FLASHROM} -p ft2232_spi:type=servo-v2,port=a -w "$image_file" -V \ + --noverify --ignore-fmap --diff "$diff_file" + dut-control spi2_buf_en:off spi2_buf_on_flex_en:off spi2_vref:off +} + +get_bl1() { + wget "${BL1_URL}" -O /tmp/bl1.tbz2 + tar jxvf /tmp/bl1.tbz2 + mkdir -p "${BL1_PATH}" + mv "exynos-pre-boot/firmware/${BL1_NAME}" "${BL1_PATH}" + rm -rf exynos-pre-boot + if [ ! -e "${BL1_PATH}/${BL1_NAME}" ]; then + echo "Error getting BL1" + exit 1 + fi +} + +merge_bl1() { + local outfile="$1" + local bl1="${BL1_PATH}/${BL1_NAME}" + + if [ ! -e "$bl1" ]; then + get_bl1 + fi + + # use the new BL1 which supports 30KB BL2/SPL/Coreboot + local size="$(stat -c "%s" "$outfile")" + local bl1_size="$(stat -c "%s" "$bl1")" + + [ "$bl1_size" = "$((0x2000))" ] || die "Incorrect BL1 input file." + dd if="$bl1" of=${outfile} conv=notrunc +} + +is_servod_ready() { + ps -C servod >/dev/null 2>&1 +} + +main() { + make + merge_bl1 "$OUTPUT" + create_diff_128k "$OUTPUT" "$TMP_DIFF" + echo "OK: Generated image (with BL1) in $OUTPUT" + if is_servod_ready; then + echo "servod detected - flashing into device." + fast_flash_image "$OUTPUT" "$TMP_DIFF" + echo "OK: Generated and flashed 128k of image into device via servo." + else + echo "(servod is not running, flashing into device is skipped)" + fi +} + +set -e +main "$@"

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New patch to review for coreboot: b5375f0 exynos5250: Hacked up lowlevel_init_c
by David Hendricks 11 Jan '13

11 Jan '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2133 -gerrit commit b5375f0e8afb5b47501b7afc9cf667ccf1f9f08e Author: David Hendricks <dhendrix(a)chromium.org> Date: Thu Jan 10 15:05:22 2013 -0800 exynos5250: Hacked up lowlevel_init_c This is the first lowlevel init routine that gets called in romstage. It's fugly and needs a lot of clean-up, but does the job for now. Change-Id: Id54bf4f1c3753bcbed5f6b5eeb4b48bc3b41ce93 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/cpu/samsung/exynos5250/lowlevel_init_c.c | 25 ++++++++++++++++--------- 1 file changed, 16 insertions(+), 9 deletions(-) diff --git a/src/cpu/samsung/exynos5250/lowlevel_init_c.c b/src/cpu/samsung/exynos5250/lowlevel_init_c.c index 2215fb7..848ebee 100644 --- a/src/cpu/samsung/exynos5250/lowlevel_init_c.c +++ b/src/cpu/samsung/exynos5250/lowlevel_init_c.c @@ -36,6 +36,7 @@ #include <cpu/samsung/exynos5250/tzpc.h> #include "setup.h" +#include <console/console.h> void do_barriers(void); /* FIXME: make gcc shut up about "no previous prototype" */ @@ -70,14 +71,15 @@ enum { int lowlevel_init_subsystems(void) { - uint32_t reset_status; +// uint32_t reset_status; int actions = 0; - do_barriers(); +// do_barriers(); /* Setup cpu info which is needed to select correct register offsets */ cpu_info_init(); +#if 0 reset_status = power_read_reset_status(); switch (reset_status) { @@ -91,24 +93,28 @@ int lowlevel_init_subsystems(void) /* This is a normal boot (not a wake from sleep) */ actions = DO_UART | DO_CLOCKS | DO_POWER; } +#endif + actions = DO_UART | DO_CLOCKS | DO_POWER; if (actions & DO_POWER) power_init(); if (actions & DO_CLOCKS) system_clock_init(); if (actions & DO_UART) { + /* Set up serial UART so we can printf() */ -// exynos_pinmux_config(EXYNOS_UART, PINMUX_FLAG_NONE); /* FIXME(dhendrix): add a function for mapping CONFIG_CONSOLE_SERIAL_UART_ADDRESS to PERIPH_ID_UARTn */ +// exynos_pinmux_config(EXYNOS_UART, PINMUX_FLAG_NONE); exynos_pinmux_config(PERIPH_ID_UART3, PINMUX_FLAG_NONE); - /* FIXME(dhendrix): serial_init() does not seem to - actually do anything !?!? */ -// serial_init(); - init_timer(); /* FIXME(dhendrix): was timer_init() */ + + console_init(); + while (1) { + console_tx_byte('C'); + } } + init_timer(); /* FIXME(dhendrix): was timer_init() */ -/* FIXME(dhendrix): place this somewhere for ramstage... */ #if 0 if (actions & DO_CLOCKS) { mem_ctrl_init(); @@ -116,5 +122,6 @@ int lowlevel_init_subsystems(void) } #endif - return actions & DO_WAKEUP; +// return actions & DO_WAKEUP; + return 0; }

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coreboot January 2013