coreboot January 2013

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Patch set updated for coreboot: 7b95bb0 Fix high dword of MTRR mask set with CONFIG_CPU_ADDR_BITS
by Martin Roth 14 Jan '13

14 Jan '13

Martin Roth (martin.roth(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2146 -gerrit commit 7b95bb0af21621fc61508c463bc2c9330498a53e Author: Martin Roth <martin(a)se-eng.com> Date: Mon Jan 14 15:46:38 2013 -0700 Fix high dword of MTRR mask set with CONFIG_CPU_ADDR_BITS Bits were being shifted off the end of the mask accidentally. This results in all masks being 32 bits wide instead of 48. Change-Id: I5f4d1b6a323df1aa4568ff4491f82447b8a2f839 Signed-off-by: Martin Roth <martin.roth(a)se-eng.com> --- src/mainboard/amd/dinar/agesawrapper.c | 2 +- src/mainboard/amd/parmer/agesawrapper.c | 2 +- src/mainboard/amd/thatcher/agesawrapper.c | 2 +- src/mainboard/amd/torpedo/agesawrapper.c | 2 +- src/mainboard/supermicro/h8qgi/agesawrapper.c | 2 +- src/mainboard/supermicro/h8scm/agesawrapper.c | 2 +- src/mainboard/tyan/s8226/agesawrapper.c | 2 +- 7 files changed, 7 insertions(+), 7 deletions(-) diff --git a/src/mainboard/amd/dinar/agesawrapper.c b/src/mainboard/amd/dinar/agesawrapper.c index e2b6038..e738cba 100644 --- a/src/mainboard/amd/dinar/agesawrapper.c +++ b/src/mainboard/amd/dinar/agesawrapper.c @@ -270,7 +270,7 @@ agesawrapper_amdinitmmio ( /* Set ROM cache onto WP to decrease post time */ MsrReg = (0x0100000000 - CONFIG_ROM_SIZE) | 5; LibAmdMsrWrite (0x20E, &MsrReg, &StdHeader); - MsrReg = ((1UL << CONFIG_CPU_ADDR_BITS) - CONFIG_ROM_SIZE) | 0x800; + MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CONFIG_ROM_SIZE) | 0x800ull; LibAmdMsrWrite (0x20F, &MsrReg, &StdHeader); Status = AGESA_SUCCESS; diff --git a/src/mainboard/amd/parmer/agesawrapper.c b/src/mainboard/amd/parmer/agesawrapper.c index 720de43..c9315fe 100644 --- a/src/mainboard/amd/parmer/agesawrapper.c +++ b/src/mainboard/amd/parmer/agesawrapper.c @@ -166,7 +166,7 @@ agesawrapper_amdinitmmio ( /* Set ROM cache onto WP to decrease post time */ MsrReg = (0x0100000000ull - CONFIG_ROM_SIZE) | 5ull; LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader); - MsrReg = ((1UL << CONFIG_CPU_ADDR_BITS) - CONFIG_ROM_SIZE) | 0x800ull; + MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CONFIG_ROM_SIZE) | 0x800ull; LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader); Status = AGESA_SUCCESS; diff --git a/src/mainboard/amd/thatcher/agesawrapper.c b/src/mainboard/amd/thatcher/agesawrapper.c index 7a3616b..aaff34b 100644 --- a/src/mainboard/amd/thatcher/agesawrapper.c +++ b/src/mainboard/amd/thatcher/agesawrapper.c @@ -166,7 +166,7 @@ agesawrapper_amdinitmmio ( /* Set ROM cache onto WP to decrease post time */ MsrReg = (0x0100000000ull - CONFIG_ROM_SIZE) | 5ull; LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader); - MsrReg = ((1UL << CONFIG_CPU_ADDR_BITS) - CONFIG_ROM_SIZE) | 0x800ull; + MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CONFIG_ROM_SIZE) | 0x800ull; LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader); Status = AGESA_SUCCESS; diff --git a/src/mainboard/amd/torpedo/agesawrapper.c b/src/mainboard/amd/torpedo/agesawrapper.c index 2c7b092..97fdbb3 100644 --- a/src/mainboard/amd/torpedo/agesawrapper.c +++ b/src/mainboard/amd/torpedo/agesawrapper.c @@ -281,7 +281,7 @@ agesawrapper_amdinitmmio ( /* Set ROM cache onto WP to decrease post time */ MsrReg = (0x0100000000ull - CONFIG_ROM_SIZE) | 5ull; LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader); - MsrReg = ((1UL << CONFIG_CPU_ADDR_BITS) - CONFIG_ROM_SIZE) | 0x800ull; + MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CONFIG_ROM_SIZE) | 0x800ull; LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader); /* Clear all pending SMI. On S3 clear power button enable so it wll not generate an SMI */ diff --git a/src/mainboard/supermicro/h8qgi/agesawrapper.c b/src/mainboard/supermicro/h8qgi/agesawrapper.c index 66236ed..9720bed 100644 --- a/src/mainboard/supermicro/h8qgi/agesawrapper.c +++ b/src/mainboard/supermicro/h8qgi/agesawrapper.c @@ -194,7 +194,7 @@ UINT32 agesawrapper_amdinitmmio(VOID) /* Set ROM cache onto WP to decrease post time */ MsrReg = (0x0100000000 - CONFIG_ROM_SIZE) | 5; LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader); - MsrReg = ((1UL << CONFIG_CPU_ADDR_BITS) - CONFIG_ROM_SIZE) | 0x800; + MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CONFIG_ROM_SIZE) | 0x800ull; LibAmdMsrWrite(0x20D, &MsrReg, &StdHeader); Status = AGESA_SUCCESS; diff --git a/src/mainboard/supermicro/h8scm/agesawrapper.c b/src/mainboard/supermicro/h8scm/agesawrapper.c index a841629..fc3d092 100644 --- a/src/mainboard/supermicro/h8scm/agesawrapper.c +++ b/src/mainboard/supermicro/h8scm/agesawrapper.c @@ -194,7 +194,7 @@ UINT32 agesawrapper_amdinitmmio(VOID) /* Set ROM cache onto WP to decrease post time */ MsrReg = (0x0100000000 - CONFIG_ROM_SIZE) | 5; LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader); - MsrReg = ((1UL << CONFIG_CPU_ADDR_BITS) - CONFIG_ROM_SIZE) | 0x800; + MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CONFIG_ROM_SIZE) | 0x800ull; LibAmdMsrWrite(0x20D, &MsrReg, &StdHeader); Status = AGESA_SUCCESS; diff --git a/src/mainboard/tyan/s8226/agesawrapper.c b/src/mainboard/tyan/s8226/agesawrapper.c index 6f18f5c..c8620a7 100644 --- a/src/mainboard/tyan/s8226/agesawrapper.c +++ b/src/mainboard/tyan/s8226/agesawrapper.c @@ -204,7 +204,7 @@ agesawrapper_amdinitmmio ( /* Set ROM cache onto WP to decrease post time */ MsrReg = (0x0100000000ull - CONFIG_ROM_SIZE) | 5ull; LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader); - MsrReg = ((1UL << CONFIG_CPU_ADDR_BITS) - CONFIG_ROM_SIZE) | 0x800ull; + MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CONFIG_ROM_SIZE) | 0x800ull; LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader); Status = AGESA_SUCCESS;

2 1

New patch to review for coreboot: 2d7f0ce make crossgcc: compile all required toolchains
by Stefan Reinauer 14 Jan '13

14 Jan '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2147 -gerrit commit 2d7f0ce3c5a9d718104c77619a1d9fb3ec9eae7d Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Mon Jan 14 16:08:10 2013 -0800 make crossgcc: compile all required toolchains The ARMv7 toolchain is now also needed for abuild (at least if you want to be able to compile ARM images) Change-Id: If1253203a2198f7dea632ba45540222ba3361932 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- util/crossgcc/Makefile | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/util/crossgcc/Makefile b/util/crossgcc/Makefile index b63cc06..da3b36b 100644 --- a/util/crossgcc/Makefile +++ b/util/crossgcc/Makefile @@ -1,11 +1,13 @@ all: build build: - bash ./buildgcc -G + bash ./buildgcc -G -p i386-elf + bash ./buildgcc -G -p armv7a-eabi .PHONY: build-without-gdb build-without-gdb: - bash ./buildgcc + bash ./buildgcc -p i386-elf + bash ./buildgcc -p armv7a-eabi clean: rm -rf xgcc

1 0

Patch set updated for coreboot: 4d6f5a9 bootblock_cpu_init() stub for exynos5250
by David Hendricks 14 Jan '13

14 Jan '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2138 -gerrit commit 4d6f5a90f836c83ea58c035c6f8ce81c75672c03 Author: David Hendricks <dhendrix(a)chromium.org> Date: Fri Jan 11 11:34:06 2013 -0800 bootblock_cpu_init() stub for exynos5250 This adds a stub for bootblock_cpu_init() for exynos5250. It will eventually contain code to copy ROM content from SPI to SRAM. Change-Id: I26ee62a1e701013f38f76f200579faa680530860 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/cpu/samsung/exynos5250/Kconfig | 6 +++--- src/cpu/samsung/exynos5250/bootblock.c | 32 ++++++++++++++++++++++++++++++++ 2 files changed, 35 insertions(+), 3 deletions(-) diff --git a/src/cpu/samsung/exynos5250/Kconfig b/src/cpu/samsung/exynos5250/Kconfig index a334b63..cd20153 100644 --- a/src/cpu/samsung/exynos5250/Kconfig +++ b/src/cpu/samsung/exynos5250/Kconfig @@ -8,10 +8,10 @@ config BOOTBLOCK_OFFSET this value is pre-determined by the vendor-provided BL1. config BOOTBLOCK_CPU_INIT - bool - default n + string + default "cpu/samsung/exynos5250/bootblock.c" help - Run CPU/SoC-specific bootblock code. This is useful if the + CPU/SoC-specific bootblock code. This is useful if the bootblock must load microcode or copy data from ROM before searching for the bootblock. diff --git a/src/cpu/samsung/exynos5250/bootblock.c b/src/cpu/samsung/exynos5250/bootblock.c new file mode 100644 index 0000000..58d0919 --- /dev/null +++ b/src/cpu/samsung/exynos5250/bootblock.c @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 The Chromium OS Authors + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +void bootblock_cpu_init(void); +void bootblock_cpu_init(void) +{ + /* + * FIXME: this is a stub for now. It should eventually copy + * romstage data (and maybe more) from SPI to SRAM. + */ +#if 0 + volatile unsigned long *addr = (unsigned long *)0x1004330c; + *addr |= 0x100; + while (1) ; +#endif +}

1 0

Patch set updated for coreboot: 7a82575 WIP: first attempt at porting SPI driver into bootblock
by David Hendricks 14 Jan '13

14 Jan '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2142 -gerrit commit 7a82575ceccd3824df561f77ab93edb399c3bcf1 Author: David Hendricks <dhendrix(a)chromium.org> Date: Fri Jan 11 15:31:56 2013 -0800 WIP: first attempt at porting SPI driver into bootblock ** do not submit ** This is just a lame attempt at copying the necessary code into snow's bootblock so that we can copy SPI content into SRAM. Change-Id: I2a33605504abecee5ed2689400cf6c555da3f2c3 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/arch/armv7/Makefile.inc | 2 +- src/arch/armv7/bootblock_simple.c | 1 + src/arch/armv7/include/arch/cbfs.h | 62 ++++- src/cpu/samsung/exynos5250/bootblock.c | 16 ++ src/cpu/samsung/exynos5250/clk.h | 2 + src/mainboard/google/snow/Kconfig | 4 + src/mainboard/google/snow/bootblock.c | 431 +++++++++++++++++++++++++++++++++ 7 files changed, 513 insertions(+), 5 deletions(-) diff --git a/src/arch/armv7/Makefile.inc b/src/arch/armv7/Makefile.inc index b783ac6..9ddd87f 100644 --- a/src/arch/armv7/Makefile.inc +++ b/src/arch/armv7/Makefile.inc @@ -258,7 +258,7 @@ $(objcbfs)/bootblock.debug: $(objgenerated)/bootblock.o $(objgenerated)/bootbloc ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) $(LD) -m armelf_linux_eabi -static -o $@.tmp -L$(obj) $< -T $(objgenerated)/bootblock.ld else - $(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(objgenerated)/bootblock.ld $< + $(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(objgenerated)/bootblock.ld -Wl,--start-group $< $(LIBGCC_FILE_NAME) -Wl,--end-group endif ################################################################################ diff --git a/src/arch/armv7/bootblock_simple.c b/src/arch/armv7/bootblock_simple.c index c10ee1f..6897e15 100644 --- a/src/arch/armv7/bootblock_simple.c +++ b/src/arch/armv7/bootblock_simple.c @@ -40,6 +40,7 @@ void main(unsigned long bist) if (boot_cpu()) { bootblock_mainboard_init(); + bootblock_cpu_init(); } entry = findstage(target1); diff --git a/src/arch/armv7/include/arch/cbfs.h b/src/arch/armv7/include/arch/cbfs.h index afcfa6a..5ade67b 100644 --- a/src/arch/armv7/include/arch/cbfs.h +++ b/src/arch/armv7/include/arch/cbfs.h @@ -31,23 +31,71 @@ static int cbfs_check_magic(struct cbfs_file *file) return !strcmp(file->magic, CBFS_FILE_MAGIC) ? 1 : 0; } +#if 0 static unsigned long findstage(const char* target) { unsigned long offset; void *ptr = (void *)*((unsigned long *) CBFS_HEADPTR_ADDR); struct cbfs_header *header = (struct cbfs_header *) ptr; + volatile unsigned long *addr = (unsigned long *)0x1004330c; // if (ntohl(header->magic) != CBFS_HEADER_MAGIC) // printk(BIOS_ERR, "ERROR: No valid CBFS header found!\n"); /* FIXME(dhendrix,reinauer): should this be ntohl(header->offset)? */ - offset = 0 - ntohl(header->romsize) + ntohl(header->offset); + offset = ntohl(header->offset); int align = ntohl(header->align); while(1) { struct cbfs_file *file = (struct cbfs_file *) offset; - if (!cbfs_check_magic(file)) + if (!cbfs_check_magic(file)) { return 0; - if (!strcmp(CBFS_NAME(file), target)) + } + if (!strcmp(CBFS_NAME(file), target)) { return (unsigned long)CBFS_SUBHEADER(file); + } + + int flen = ntohl(file->len); + int foffset = ntohl(file->offset); + unsigned long oldoffset = offset; + offset = ALIGN(offset + foffset + flen, align); + if (offset <= oldoffset) + return 0; + /* FIXME(dhendrix,reinauer): calculate the limit correctly */ + if (offset < ntohl(header->offset) + ntohl(header->romsize)) + return 0; + } +#if 0 + /* FIXME: for debugging */ + volatile unsigned long *addr = (unsigned long *)0x1004330c; + *addr |= 0x100; +#endif + while(1); /* FIXME: for debugging */ +} +#endif + +static unsigned long findstage(const char* target) +{ + unsigned long offset; + /* FIXME: CBFS_HEADPTR_ADDR is completely wrong. */ + void *ptr = (void *)*((unsigned long *) CBFS_HEADPTR_ADDR); + struct cbfs_header *header = (struct cbfs_header *) ptr; + volatile unsigned long *addr = (unsigned long *)0x1004330c; + // if (ntohl(header->magic) != CBFS_HEADER_MAGIC) + // printk(BIOS_ERR, "ERROR: No valid CBFS header found!\n"); + + *addr |= 0x100; + while(1); /* FIXME: for debugging */ + /* FIXME(dhendrix,reinauer): should this be ntohl(header->offset)? */ + offset = ntohl(header->offset); + int align = ntohl(header->align); + while(1) { + struct cbfs_file *file = (struct cbfs_file *) offset; + if (!cbfs_check_magic(file)) { + return 0; + } + if (!strcmp(CBFS_NAME(file), target)) { + return (unsigned long)CBFS_SUBHEADER(file); + } + int flen = ntohl(file->len); int foffset = ntohl(file->offset); unsigned long oldoffset = offset; @@ -55,9 +103,15 @@ static unsigned long findstage(const char* target) if (offset <= oldoffset) return 0; /* FIXME(dhendrix,reinauer): calculate the limit correctly */ - if (offset < 0xFFFFFFFF - ntohl(header->romsize)) + if (offset < ntohl(header->offset) + ntohl(header->romsize)) return 0; } +#if 0 + /* FIXME: for debugging */ + volatile unsigned long *addr = (unsigned long *)0x1004330c; + *addr |= 0x100; + while(1); /* FIXME: for debugging */ +#endif } static inline void call(unsigned long addr) diff --git a/src/cpu/samsung/exynos5250/bootblock.c b/src/cpu/samsung/exynos5250/bootblock.c index 58d0919..46b52b9 100644 --- a/src/cpu/samsung/exynos5250/bootblock.c +++ b/src/cpu/samsung/exynos5250/bootblock.c @@ -17,6 +17,22 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#if 0 +/* + * Set/clear program flow prediction and return the previous state. + */ +static int config_branch_prediction(int set_cr_z) +{ + unsigned int cr; + + /* System Control Register: 11th bit Z Branch prediction enable */ + cr = get_cr(); + set_cr(set_cr_z ? cr | CR_Z : cr & ~CR_Z); + + return cr & CR_Z; +} +#endif + void bootblock_cpu_init(void); void bootblock_cpu_init(void) { diff --git a/src/cpu/samsung/exynos5250/clk.h b/src/cpu/samsung/exynos5250/clk.h index 2de949a..762dbf3 100644 --- a/src/cpu/samsung/exynos5250/clk.h +++ b/src/cpu/samsung/exynos5250/clk.h @@ -25,6 +25,8 @@ #include <cpu/samsung/exynos5-common/clk.h> #include <cpu/samsung/exynos5250/pinmux.h> +enum periph_id; + /* * Set mshci controller instances clock drivder * diff --git a/src/mainboard/google/snow/Kconfig b/src/mainboard/google/snow/Kconfig index 21cdfa5..8f41c64 100644 --- a/src/mainboard/google/snow/Kconfig +++ b/src/mainboard/google/snow/Kconfig @@ -56,6 +56,10 @@ config MAINBOARD_VENDOR string default "Samsung" +config BOOTBLOCK_MAINBOARD_INIT + string + default "mainboard/google/snow/bootblock.c" + # SPL (second-phase loader) stuff config SPL_TEXT_BASE hex diff --git a/src/mainboard/google/snow/bootblock.c b/src/mainboard/google/snow/bootblock.c new file mode 100644 index 0000000..09f6f74 --- /dev/null +++ b/src/mainboard/google/snow/bootblock.c @@ -0,0 +1,431 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdlib.h> +#include <types.h> +#include <arch/io.h> +#include "cpu/samsung/exynos5250/clk.h" +#include "cpu/samsung/exynos5250/cpu.h" +#include "cpu/samsung/exynos5250/gpio.h" +#include "cpu/samsung/s5p-common/gpio.h" +#include "cpu/samsung/exynos5-common/spi.h" + +#define EXYNOS5_CLOCK_BASE 0x10010000 + +/* FIXME(dhendrix): Can we move this SPI stuff elsewhere? */ +static void spi_rx_tx(struct exynos_spi *regs, int todo, + void *dinp, void const *doutp, int i) +{ + unsigned int *rxp = (unsigned int *)(dinp + (i * (32 * 1024))); + int rx_lvl, tx_lvl; + unsigned int out_bytes, in_bytes; + + out_bytes = in_bytes = todo; + setbits_le32(&regs->ch_cfg, SPI_CH_RST); + clrbits_le32(&regs->ch_cfg, SPI_CH_RST); + writel(((todo * 8) / 32) | SPI_PACKET_CNT_EN, &regs->pkt_cnt); + + while (in_bytes) { + uint32_t spi_sts; + int temp; + + spi_sts = readl(&regs->spi_sts); + rx_lvl = ((spi_sts >> 15) & 0x7f); + tx_lvl = ((spi_sts >> 6) & 0x7f); + while (tx_lvl < 32 && out_bytes) { + temp = 0xffffffff; + writel(temp, &regs->tx_data); + out_bytes -= 4; + tx_lvl += 4; + } + while (rx_lvl >= 4 && in_bytes) { + temp = readl(&regs->rx_data); + if (rxp) + *rxp++ = temp; + in_bytes -= 4; + rx_lvl -= 4; + } + } +} + +#if 0 +void clock_ll_set_pre_ratio(enum periph_id periph_id, unsigned divisor) +{ + struct exynos5_clock *clk = + (struct exynos5_clock *)samsung_get_base_clock(); + unsigned shift; + unsigned mask = 0xff; + u32 *reg; + + /* + * For now we only handle a very small subset of peipherals here. + * Others will need to (and do) mangle the clock registers + * themselves, At some point it is hoped that this function can work + * from a table or calculated register offset / mask. For now this + * is at least better than spreading clock control code around + * U-Boot. + */ + switch (periph_id) { + case PERIPH_ID_SPI0: + reg = &clk->div_peric1; + shift = 8; + break; + case PERIPH_ID_SPI1: + reg = &clk->div_peric1; + shift = 24; + break; + case PERIPH_ID_SPI2: + reg = &clk->div_peric2; + shift = 8; + break; + case PERIPH_ID_SPI3: + reg = &clk->sclk_div_isp; + shift = 4; + break; + case PERIPH_ID_SPI4: + reg = &clk->sclk_div_isp; + shift = 16; + break; + default: + debug("%s: Unsupported peripheral ID %d\n", __func__, + periph_id); + return; + } +} +#endif +void clock_ll_set_pre_ratio(enum periph_id periph_id, unsigned divisor) +{ + struct exynos5_clock *clk = + (struct exynos5_clock *)EXYNOS5_CLOCK_BASE; + unsigned shift; + unsigned mask = 0xff; + u32 *reg; + + reg = &clk->div_peric1; + shift = 24; + clrsetbits_le32(reg, mask << shift, (divisor & mask) << shift); +} + +#if 0 +void clock_ll_set_ratio(enum periph_id periph_id, unsigned divisor) +{ + struct exynos5_clock *clk = + (struct exynos5_clock *)samsung_get_base_clock(); + unsigned shift; + unsigned mask = 0xff; + u32 *reg; + + switch (periph_id) { + case PERIPH_ID_SPI0: + reg = &clk->div_peric1; + shift = 0; + break; + case PERIPH_ID_SPI1: + reg = &clk->div_peric1; + shift = 16; + break; + case PERIPH_ID_SPI2: + reg = &clk->div_peric2; + shift = 0; + break; + case PERIPH_ID_SPI3: + reg = &clk->sclk_div_isp; + shift = 0; + break; + case PERIPH_ID_SPI4: + reg = &clk->sclk_div_isp; + shift = 12; + break; + default: + debug("%s: Unsupported peripheral ID %d\n", __func__, + periph_id); + return; + } +} +#endif +void clock_ll_set_ratio(enum periph_id periph_id, unsigned divisor) +{ + struct exynos5_clock *clk = + (struct exynos5_clock *)EXYNOS5_CLOCK_BASE; + unsigned shift; + unsigned mask = 0xff; + u32 *reg; + + reg = &clk->div_peric1; + shift = 16; + clrsetbits_le32(reg, mask << shift, (divisor & mask) << shift); +} + +/** + * Linearly searches for the most accurate main and fine stage clock scalars + * (divisors) for a specified target frequency and scalar bit sizes by checking + * all multiples of main_scalar_bits values. Will always return scalars up to or + * slower than target. + * + * @param main_scalar_bits Number of main scalar bits, must be > 0 and < 32 + * @param fine_scalar_bits Number of fine scalar bits, must be > 0 and < 32 + * @param input_freq Clock frequency to be scaled in Hz + * @param target_freq Desired clock frequency in Hz + * @param best_fine_scalar Pointer to store the fine stage divisor + * + * @return best_main_scalar Main scalar for desired frequency or -1 if none + * found + */ +static int clock_calc_best_scalar(unsigned int main_scaler_bits, + unsigned int fine_scalar_bits, unsigned int input_rate, + unsigned int target_rate, unsigned int *best_fine_scalar) +{ + int i; + int best_main_scalar = -1; + unsigned int best_error = target_rate; + const unsigned int cap = (1 << fine_scalar_bits) - 1; + const unsigned int loops = 1 << main_scaler_bits; + +#if 0 + debug("Input Rate is %u, Target is %u, Cap is %u\n", input_rate, + target_rate, cap); + + assert(best_fine_scalar != NULL); + assert(main_scaler_bits <= fine_scalar_bits); +#endif + + *best_fine_scalar = 1; + + if (input_rate == 0 || target_rate == 0) + return -1; + + if (target_rate >= input_rate) + return 1; + + for (i = 1; i <= loops; i++) { + const unsigned int effective_div = MAX(MIN(input_rate / i / + target_rate, cap), 1); + const unsigned int effective_rate = input_rate / i / + effective_div; + const int error = target_rate - effective_rate; + +#if 0 + debug("%d|effdiv:%u, effrate:%u, error:%d\n", i, effective_div, + effective_rate, error); +#endif + + if (error >= 0 && error <= best_error) { + best_error = error; + best_main_scalar = i; + *best_fine_scalar = effective_div; + } + } + + return best_main_scalar; +} + +#if 0 +int clock_set_rate(enum periph_id periph_id, unsigned int rate) +{ + int main; + unsigned int fine; + + switch (periph_id) { + case PERIPH_ID_SPI0: + case PERIPH_ID_SPI1: + case PERIPH_ID_SPI2: + case PERIPH_ID_SPI3: + case PERIPH_ID_SPI4: + main = clock_calc_best_scalar(4, 8, 400000000, rate, &fine); + if (main < 0) { + debug("%s: Cannot set clock rate for periph %d", + __func__, periph_id); + return -1; + } + clock_ll_set_ratio(periph_id, main - 1); + clock_ll_set_pre_ratio(periph_id, fine - 1); + break; + default: + debug("%s: Unsupported peripheral ID %d\n", __func__, + periph_id); + return -1; + } + main = clock_calc_best_scalar(4, 8, 400000000, rate, &fine); + if (main < 0) { + debug("%s: Cannot set clock rate for periph %d", + __func__, periph_id); + return -1; + } + clock_ll_set_ratio(PERIPH_ID_SPI1, main - 1); + clock_ll_set_pre_ratio(PERIPH_ID_SPI1, fine - 1); + + return 0; +} +#endif +int clock_set_rate(enum periph_id periph_id, unsigned int rate) +{ + int main; + unsigned int fine; + + main = clock_calc_best_scalar(4, 8, 400000000, rate, &fine); + if (main < 0) { +// debug("%s: Cannot set clock rate for periph %d", +// __func__, periph_id); + return -1; + } + clock_ll_set_ratio(-1, main - 1); + clock_ll_set_pre_ratio(-1, fine - 1); + + return 0; +} + +struct gpio_info { + unsigned int reg_addr; /* Address of register for this part */ + unsigned int max_gpio; /* Maximum GPIO in this part */ +}; + +static const struct gpio_info gpio_data[EXYNOS_GPIO_NUM_PARTS] = { + { EXYNOS5_GPIO_PART1_BASE, GPIO_MAX_PORT_PART_1 }, + { EXYNOS5_GPIO_PART2_BASE, GPIO_MAX_PORT_PART_2 }, + { EXYNOS5_GPIO_PART3_BASE, GPIO_MAX_PORT_PART_3 }, + { EXYNOS5_GPIO_PART4_BASE, GPIO_MAX_PORT_PART_4 }, + { EXYNOS5_GPIO_PART5_BASE, GPIO_MAX_PORT_PART_5 }, + { EXYNOS5_GPIO_PART6_BASE, GPIO_MAX_PORT }, +}; + +static struct s5p_gpio_bank *gpio_get_bank(unsigned int gpio) +{ + const struct gpio_info *data; + unsigned int upto; + int i; + + for (i = upto = 0, data = gpio_data; i < EXYNOS_GPIO_NUM_PARTS; + i++, upto = data->max_gpio, data++) { + if (gpio < data->max_gpio) { + struct s5p_gpio_bank *bank; + + bank = (struct s5p_gpio_bank *)data->reg_addr; + bank += (gpio - upto) / GPIO_PER_BANK; + return bank; + } + } + +#ifndef CONFIG_SPL_BUILD + assert(gpio < GPIO_MAX_PORT); /* ...which it will not be */ +#endif + return NULL; +} + +#define CON_MASK(x) (0xf << ((x) << 2)) +#define CON_SFR(x, v) ((v) << ((x) << 2)) + +/* This macro gets gpio pin offset from 0..7 */ +#define GPIO_BIT(x) ((x) & 0x7) + +void gpio_cfg_pin(int gpio, int cfg) +{ + unsigned int value; + struct s5p_gpio_bank *bank = gpio_get_bank(gpio); + + value = readl(&bank->con); + value &= ~CON_MASK(GPIO_BIT(gpio)); + value |= CON_SFR(GPIO_BIT(gpio), cfg); + writel(value, &bank->con); +} + +//static void exynos_spi_copy(unsigned int uboot_size) +static void copy_romstage(uint32_t spi_addr, uint32_t sram_addr, unsigned int len) +{ + int upto, todo; + int i; +// struct exynos_spi *regs = (struct exynos_spi *)samsung_get_base_spi1(); + struct exynos_spi *regs = (struct exynos_spi *)0x12d30000; + + clock_set_rate(PERIPH_ID_SPI1, 50000000); /* set spi clock to 50Mhz */ + /* set the spi1 GPIO */ +// exynos_pinmux_config(PERIPH_ID_SPI1, PINMUX_FLAG_NONE); + gpio_cfg_pin(GPIO_A24, 0x2); + gpio_cfg_pin(GPIO_A25, 0x2); + gpio_cfg_pin(GPIO_A26, 0x2); + gpio_cfg_pin(GPIO_A27, 0x2); + + /* set pktcnt and enable it */ + writel(4 | SPI_PACKET_CNT_EN, &regs->pkt_cnt); + /* set FB_CLK_SEL */ + writel(SPI_FB_DELAY_180, &regs->fb_clk); + /* set CH_WIDTH and BUS_WIDTH as word */ + setbits_le32(&regs->mode_cfg, SPI_MODE_CH_WIDTH_WORD | + SPI_MODE_BUS_WIDTH_WORD); + clrbits_le32(&regs->ch_cfg, SPI_CH_CPOL_L); /* CPOL: active high */ + + /* clear rx and tx channel if set priveously */ + clrbits_le32(&regs->ch_cfg, SPI_RX_CH_ON | SPI_TX_CH_ON); + + setbits_le32(&regs->swap_cfg, SPI_RX_SWAP_EN | + SPI_RX_BYTE_SWAP | + SPI_RX_HWORD_SWAP); + + /* do a soft reset */ + setbits_le32(&regs->ch_cfg, SPI_CH_RST); + clrbits_le32(&regs->ch_cfg, SPI_CH_RST); + + /* now set rx and tx channel ON */ + setbits_le32(&regs->ch_cfg, SPI_RX_CH_ON | SPI_TX_CH_ON | SPI_CH_HS_EN); + clrbits_le32(&regs->cs_reg, SPI_SLAVE_SIG_INACT); /* CS low */ + + /* Send read instruction (0x3h) followed by a 24 bit addr */ + writel((SF_READ_DATA_CMD << 24) | spi_addr, &regs->tx_data); + + /* waiting for TX done */ + while (!(readl(&regs->spi_sts) & SPI_ST_TX_DONE)); + + for (upto = 0, i = 0; upto < len; upto += todo, i++) { + todo = MIN(len - upto, (1 << 15)); + spi_rx_tx(regs, todo, (void *)(sram_addr), + (void *)(spi_addr), i); + } + + setbits_le32(&regs->cs_reg, SPI_SLAVE_SIG_INACT);/* make the CS high */ + + /* + * Let put controller mode to BYTE as + * SPI driver does not support WORD mode yet + */ + clrbits_le32(&regs->mode_cfg, SPI_MODE_CH_WIDTH_WORD | + SPI_MODE_BUS_WIDTH_WORD); + writel(0, &regs->swap_cfg); + + /* + * Flush spi tx, rx fifos and reset the SPI controller + * and clear rx/tx channel + */ + clrsetbits_le32(&regs->ch_cfg, SPI_CH_HS_EN, SPI_CH_RST); + clrbits_le32(&regs->ch_cfg, SPI_CH_RST); + clrbits_le32(&regs->ch_cfg, SPI_TX_CH_ON | SPI_RX_CH_ON); +} + +void bootblock_mainboard_init(void); +void bootblock_mainboard_init(void) +{ + /* Copy romstage data from SPI ROM to SRAM */ + /* FIXME: magic constant... */ + copy_romstage(0x2000, CONFIG_ROMSTAGE_BASE, CONFIG_XIP_ROM_SIZE); + +#if 0 + /* FIXME: for debugging... */ + volatile unsigned long *addr = (unsigned long *)0x1004330c; + *addr |= 0x100; + while (1); +#endif +}

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Patch set updated for coreboot: 290f7bd ARM bootblock approach (incomplete)
by David Hendricks 14 Jan '13

14 Jan '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2118 -gerrit commit 290f7bdbc425cf648574ecbcc35589c75cd4108d Author: David Hendricks <dhendrix(a)chromium.org> Date: Tue Jan 8 21:05:06 2013 -0800 ARM bootblock approach (incomplete) Do not attempt to commit, just making this available so it doesn't get lost Change-Id: I9cc2a8191d2db38b27b6363ba673e5a360de9684 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/arch/armv7/Makefile.inc | 26 +++++------ src/arch/armv7/bootblock.inc | 7 +-- src/arch/armv7/bootblock.lds | 49 +++++++++++++++++++++ src/arch/armv7/bootblock_simple.c | 34 +++++++-------- src/arch/armv7/include/arch/cbfs.h | 68 +++++++++++++++++++++++++++++ src/arch/armv7/include/bootblock_common.h | 71 ++++--------------------------- src/arch/armv7/lib/id.lds | 2 +- src/cpu/samsung/exynos5250/Kconfig | 12 +++++- 8 files changed, 164 insertions(+), 105 deletions(-) diff --git a/src/arch/armv7/Makefile.inc b/src/arch/armv7/Makefile.inc index 4cb97a6..b783ac6 100644 --- a/src/arch/armv7/Makefile.inc +++ b/src/arch/armv7/Makefile.inc @@ -49,7 +49,7 @@ prebuilt-files = $(foreach file,$(cbfs-files), $(call extract_nth,1,$(file))) $(obj)/coreboot.pre1: $(objcbfs)/bootblock.bin $$(prebuilt-files) $(CBFSTOOL) $(CBFSTOOL) $@.tmp create -m armv7 -s $(CONFIG_COREBOOT_ROMSIZE_KB)K \ -B $(objcbfs)/bootblock.bin -a 64 \ - -o $$(( $(CONFIG_ROM_SIZE) - $(CONFIG_CBFS_SIZE) )) + -o $(CONFIG_BOOTBLOCK_OFFSET) $(prebuild-files) true mv $@.tmp $@ else @@ -149,7 +149,6 @@ CFLAGS += \ # For various headers imported from Linux CFLAGS += -D__LINUX_ARM_ARCH__=7 -crt0s = $(src)/arch/armv7/bootblock.inc ldscripts = ldscripts += $(src)/arch/armv7/romstage.ld @@ -223,19 +222,14 @@ $(obj)/coreboot.pre: $(objcbfs)/romstage_xip.elf $(obj)/coreboot.pre1 $(CBFSTOOL ################################################################################ # Build the bootblock -#bootblock_lds = $(src)/arch/armv7/ldscript_fallback_cbfs.lb -bootblock_lds = $(src)/arch/armv7/lib/id.lds -#bootblock_lds = $(src)/arch/armv7/romstage.ld +bootblock_lds = $(src)/arch/armv7/bootblock.lds +bootblock_lds += $(src)/arch/armv7/lib/id.lds bootblock_lds += $(chipset_bootblock_lds) +bootblock_inc += $(src)/arch/armv7/bootblock.inc bootblock_inc += $(src)/arch/armv7/lib/id.inc bootblock_inc += $(chipset_bootblock_inc) - -# FIXME: CONFIG_NEON or something similar for ARM? -#ifeq ($(CONFIG_SSE),y) -#bootblock_inc += $(src)/cpu/x86/sse_enable.inc -#endif -#bootblock_inc += $(objgenerated)/bootblock.inc +bootblock_inc += $(objgenerated)/bootblock.inc $(objgenerated)/bootblock.ld: $$(bootblock_lds) $(obj)/ldoptions @printf " GEN $(subst $(obj)/,,$(@))\n" @@ -253,11 +247,11 @@ $(objgenerated)/bootblock.s: $(objgenerated)/bootblock_inc.S $(obj)/config.h $(o @printf " CC $(subst $(obj)/,,$(@))\n" $(CC) -MMD -x assembler-with-cpp -E -I$(src)/include -I$(src)/arch/armv7/include -I$(obj) -include $(obj)/build.h -include $(obj)/config.h -I. -I$(src) $< -o $@ -#$(objgenerated)/bootblock.inc: $(src)/arch/armv7/init/$(subst ",,$(CONFIG_BOOTBLOCK_SOURCE)) $(objutil)/romcc/romcc $(OPTION_TABLE_H) -# @printf " ROMCC $(subst $(obj)/,,$(@))\n" -# $(CC) $(INCLUDES) -MM -MT$(objgenerated)/bootblock.inc \ -# $< > $(objgenerated)/bootblock.inc.d -# $(ROMCC) -c -S $(bootblock_romccflags) $(ROMCCFLAGS) -I. $(INCLUDES) $< -o $@ +$(objgenerated)/bootblock.inc: $(src)/arch/armv7/$(subst ",,$(CONFIG_BOOTBLOCK_SOURCE)) $(OPTION_TABLE_H) + @printf " CC $(subst $(obj)/,,$(@))\n" + $(CC) $(INCLUDES) -MM -MT$(objgenerated)/bootblock.inc \ + $< > $(objgenerated)/bootblock.inc.d + $(CC) -c -S $(CFLAGS) -I. $(INCLUDES) $< -o $@ $(objcbfs)/bootblock.debug: $(objgenerated)/bootblock.o $(objgenerated)/bootblock.ld @printf " LINK $(subst $(obj)/,,$(@))\n" diff --git a/src/arch/armv7/bootblock.inc b/src/arch/armv7/bootblock.inc index f76391b..90850d6 100644 --- a/src/arch/armv7/bootblock.inc +++ b/src/arch/armv7/bootblock.inc @@ -36,8 +36,7 @@ _bl1: * on ARM, which is 8KB in size and it is prepended to the * reset vector */ - /* this comes a bit later. */ -// .skip 8192 + .skip 8192 .globl _start _start: b reset @@ -81,10 +80,6 @@ call_bootblock: * Thumb. However, "b" will not and GCC may attempt to create a * wrapper which is currently broken. */ - /* for now call board_init_f; change later. We're trying to get as much into ToT as - * we can - */ - bl board_init_f bl main wait_for_interrupt: diff --git a/src/arch/armv7/bootblock.lds b/src/arch/armv7/bootblock.lds new file mode 100644 index 0000000..90e37a0 --- /dev/null +++ b/src/arch/armv7/bootblock.lds @@ -0,0 +1,49 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2006 Advanced Micro Devices, Inc. + * Copyright (C) 2008-2010 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* We use ELF as output format. So that we can debug the code in some form. */ +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) + +TARGET(binary) +SECTIONS +{ + ROMLOC = 0x2023400 - 8192; + + /* This section might be better named .setup */ + .rom ROMLOC : { + _rom = .; + *(.text); + *(.text.*); + *(.rom.text); + *(.rom.data); + *(.rom.data.*); + *(.rodata.*); + _erom = .; + } = 0xff + + /DISCARD/ : { + *(.comment) + *(.note) + *(.comment.*) + *(.note.*) + *(.ARM.*) + } +} diff --git a/src/arch/armv7/bootblock_simple.c b/src/arch/armv7/bootblock_simple.c index f447a29..c10ee1f 100644 --- a/src/arch/armv7/bootblock_simple.c +++ b/src/arch/armv7/bootblock_simple.c @@ -19,33 +19,31 @@ * MA 02110-1301 USA */ - - #include <bootblock_common.h> +#include <arch/cbfs.h> +#include <arch/hlt.h> - -#include "../../lib/uart8250.c" -#include "lib/div.c" - -struct uart8250 uart = { - 115200 -}; +static int boot_cpu(void) +{ + /* + * FIXME: This is a stub for now. All non-boot CPUs should be + * waiting for an interrupt. We could move the chunk of assembly + * which puts them to sleep in here... + */ + return 1; +} void main(unsigned long bist) { - init_uart8250(CONFIG_TTYS0_BASE, &uart); - uart8250_tx_byte(CONFIG_TTYS0_BASE, '@'); + const char *target1 = "fallback/romstage"; + unsigned long entry; if (boot_cpu()) { - bootblock_cpu_init(); - bootblock_northbridge_init(); - bootblock_southbridge_init(); + bootblock_mainboard_init(); } - const char* target1 = "fallback/romstage"; - unsigned long entry; + entry = findstage(target1); - if (entry) call(entry, bist); + if (entry) call(entry); hlt(); } - diff --git a/src/arch/armv7/include/arch/cbfs.h b/src/arch/armv7/include/arch/cbfs.h new file mode 100644 index 0000000..afcfa6a --- /dev/null +++ b/src/arch/armv7/include/arch/cbfs.h @@ -0,0 +1,68 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __INCLUDE_ARCH_CBFS__ +#define __INCLUDE_ARCH_CBFS__ + +#include <string.h> +#include <types.h> +#include <cbfs_core.h> +#include <arch/byteorder.h> +#include <arch/cbfs.h> + +static int cbfs_check_magic(struct cbfs_file *file) +{ + return !strcmp(file->magic, CBFS_FILE_MAGIC) ? 1 : 0; +} + +static unsigned long findstage(const char* target) +{ + unsigned long offset; + void *ptr = (void *)*((unsigned long *) CBFS_HEADPTR_ADDR); + struct cbfs_header *header = (struct cbfs_header *) ptr; + // if (ntohl(header->magic) != CBFS_HEADER_MAGIC) + // printk(BIOS_ERR, "ERROR: No valid CBFS header found!\n"); + + /* FIXME(dhendrix,reinauer): should this be ntohl(header->offset)? */ + offset = 0 - ntohl(header->romsize) + ntohl(header->offset); + int align = ntohl(header->align); + while(1) { + struct cbfs_file *file = (struct cbfs_file *) offset; + if (!cbfs_check_magic(file)) + return 0; + if (!strcmp(CBFS_NAME(file), target)) + return (unsigned long)CBFS_SUBHEADER(file); + int flen = ntohl(file->len); + int foffset = ntohl(file->offset); + unsigned long oldoffset = offset; + offset = ALIGN(offset + foffset + flen, align); + if (offset <= oldoffset) + return 0; + /* FIXME(dhendrix,reinauer): calculate the limit correctly */ + if (offset < 0xFFFFFFFF - ntohl(header->romsize)) + return 0; + } +} + +static inline void call(unsigned long addr) +{ + void (*doit)(void) = (void *)addr; + doit(); +} +#endif diff --git a/src/arch/armv7/include/bootblock_common.h b/src/arch/armv7/include/bootblock_common.h index f5c7129..39af453 100644 --- a/src/arch/armv7/include/bootblock_common.h +++ b/src/arch/armv7/include/bootblock_common.h @@ -1,69 +1,14 @@ -#include <types.h> -#include <cbfs.h> -#include <string.h> -#include <arch/byteorder.h> - - -#define boot_cpu(x) 1 - #ifdef CONFIG_BOOTBLOCK_CPU_INIT #include CONFIG_BOOTBLOCK_CPU_INIT -#else -static void bootblock_cpu_init(void) { } -#endif -#ifdef CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT -#include CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT -#else -static void bootblock_northbridge_init(void) { } #endif -#ifdef CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT -#include CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT -#else -static void bootblock_southbridge_init(void) { } -#endif - -static int cbfs_check_magic(struct cbfs_file *file) -{ - return !strcmp(file->magic, CBFS_FILE_MAGIC) ? 1 : 0; -} - -static unsigned long findstage(const char* target) -{ - unsigned long offset; - - void *ptr = (void *)*((unsigned long *) CBFS_HEADPTR_ADDR); - struct cbfs_header *header = (struct cbfs_header *) ptr; - // if (ntohl(header->magic) != CBFS_HEADER_MAGIC) - // printk(BIOS_ERR, "ERROR: No valid CBFS header found!\n"); - - offset = 0 - ntohl(header->romsize) + ntohl(header->offset); - int align = ntohl(header->align); - while(1) { - struct cbfs_file *file = (struct cbfs_file *) offset; - if (!cbfs_check_magic(file)) - return 0; - if (!strcmp(CBFS_NAME(file), target)) - return (unsigned long)CBFS_SUBHEADER(file); - int flen = ntohl(file->len); - int foffset = ntohl(file->offset); - unsigned long oldoffset = offset; - offset = ALIGN(offset + foffset + flen, align); - if (offset <= oldoffset) - return 0; - if (offset < 0xFFFFFFFF - ntohl(header->romsize)) - return 0; - } -} - - -static void call(unsigned long addr, unsigned long bist) -{ - asm volatile ("mov r0, %1\nbx %0\n" : : "r" (addr), "r" (bist)); -} -static void hlt(void) +#ifdef CONFIG_BOOTBLOCK_MAINBOARD_INIT +#include CONFIG_BOOTBLOCK_MAINBOARD_INIT +#else +static void bootblock_mainboard_init(void) { - /* is there such a thing as hlt on ARM? */ - // asm volatile ("1:\n\thlt\n\tjmp 1b\n\t"); - asm volatile ("1:\nb 1b\n\t"); +#ifdef CONFIG_BOOTBLOCK_CPU_INIT + bootblock_cpu_init(); +#endif } +#endif diff --git a/src/arch/armv7/lib/id.lds b/src/arch/armv7/lib/id.lds index 9e31ee6..22b4a02 100644 --- a/src/arch/armv7/lib/id.lds +++ b/src/arch/armv7/lib/id.lds @@ -1,5 +1,5 @@ SECTIONS { - . = (0x100000000 - CONFIG_ID_SECTION_OFFSET) - (__id_end - __id_start); + . = (0x2024000) - (__id_end - __id_start); .id (.): { *(.id) } diff --git a/src/cpu/samsung/exynos5250/Kconfig b/src/cpu/samsung/exynos5250/Kconfig index 360c57f..a334b63 100644 --- a/src/cpu/samsung/exynos5250/Kconfig +++ b/src/cpu/samsung/exynos5250/Kconfig @@ -1,10 +1,20 @@ +# FIXME: shouldn't this be 0x3400? Or maybe the bootblock in ROM needs +# to follow the BL1 image, but in SRAM it needs to be at 0x3400? Hm... config BOOTBLOCK_OFFSET hex "Bootblock offset" - default 0x3400 + default 0x2000 help This is where the Coreboot bootblock resides. For Exynos5250, this value is pre-determined by the vendor-provided BL1. +config BOOTBLOCK_CPU_INIT + bool + default n + help + Run CPU/SoC-specific bootblock code. This is useful if the + bootblock must load microcode or copy data from ROM before + searching for the bootblock. + config EXYNOS_ACE_SHA bool default n

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New patch to review for coreboot: 00ee19f Fix high dword of MTRR mask set with CONFIG_CPU_ADDR_BITS
by Martin Roth 14 Jan '13

14 Jan '13

Martin Roth (martin.roth(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2146 -gerrit commit 00ee19f89fab67547b9036118250fe8ebe2ff057 Author: Martin Roth <martin(a)se-eng.com> Date: Mon Jan 14 15:46:38 2013 -0700 Fix high dword of MTRR mask set with CONFIG_CPU_ADDR_BITS Bits were being shifted off the end of the mask accidentally. This results in all masks being 32 bits wide instead of 48. Change-Id: I5f4d1b6a323df1aa4568ff4491f82447b8a2f839 Signed-off-by: Martin Roth <martin.roth(a)se-eng.com> --- src/mainboard/amd/dinar/agesawrapper.c | 2 +- src/mainboard/amd/parmer/agesawrapper.c | 2 +- src/mainboard/amd/thatcher/agesawrapper.c | 2 +- src/mainboard/amd/torpedo/agesawrapper.c | 2 +- src/mainboard/supermicro/h8qgi/agesawrapper.c | 2 +- src/mainboard/supermicro/h8scm/agesawrapper.c | 2 +- src/mainboard/tyan/s8226/agesawrapper.c | 2 +- 7 files changed, 7 insertions(+), 7 deletions(-) diff --git a/src/mainboard/amd/dinar/agesawrapper.c b/src/mainboard/amd/dinar/agesawrapper.c index e2b6038..da4afa6 100644 --- a/src/mainboard/amd/dinar/agesawrapper.c +++ b/src/mainboard/amd/dinar/agesawrapper.c @@ -270,7 +270,7 @@ agesawrapper_amdinitmmio ( /* Set ROM cache onto WP to decrease post time */ MsrReg = (0x0100000000 - CONFIG_ROM_SIZE) | 5; LibAmdMsrWrite (0x20E, &MsrReg, &StdHeader); - MsrReg = ((1UL << CONFIG_CPU_ADDR_BITS) - CONFIG_ROM_SIZE) | 0x800; + MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CONFIG_ROM_SIZE) | 0x800; LibAmdMsrWrite (0x20F, &MsrReg, &StdHeader); Status = AGESA_SUCCESS; diff --git a/src/mainboard/amd/parmer/agesawrapper.c b/src/mainboard/amd/parmer/agesawrapper.c index 720de43..c9315fe 100644 --- a/src/mainboard/amd/parmer/agesawrapper.c +++ b/src/mainboard/amd/parmer/agesawrapper.c @@ -166,7 +166,7 @@ agesawrapper_amdinitmmio ( /* Set ROM cache onto WP to decrease post time */ MsrReg = (0x0100000000ull - CONFIG_ROM_SIZE) | 5ull; LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader); - MsrReg = ((1UL << CONFIG_CPU_ADDR_BITS) - CONFIG_ROM_SIZE) | 0x800ull; + MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CONFIG_ROM_SIZE) | 0x800ull; LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader); Status = AGESA_SUCCESS; diff --git a/src/mainboard/amd/thatcher/agesawrapper.c b/src/mainboard/amd/thatcher/agesawrapper.c index 7a3616b..aaff34b 100644 --- a/src/mainboard/amd/thatcher/agesawrapper.c +++ b/src/mainboard/amd/thatcher/agesawrapper.c @@ -166,7 +166,7 @@ agesawrapper_amdinitmmio ( /* Set ROM cache onto WP to decrease post time */ MsrReg = (0x0100000000ull - CONFIG_ROM_SIZE) | 5ull; LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader); - MsrReg = ((1UL << CONFIG_CPU_ADDR_BITS) - CONFIG_ROM_SIZE) | 0x800ull; + MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CONFIG_ROM_SIZE) | 0x800ull; LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader); Status = AGESA_SUCCESS; diff --git a/src/mainboard/amd/torpedo/agesawrapper.c b/src/mainboard/amd/torpedo/agesawrapper.c index 2c7b092..97fdbb3 100644 --- a/src/mainboard/amd/torpedo/agesawrapper.c +++ b/src/mainboard/amd/torpedo/agesawrapper.c @@ -281,7 +281,7 @@ agesawrapper_amdinitmmio ( /* Set ROM cache onto WP to decrease post time */ MsrReg = (0x0100000000ull - CONFIG_ROM_SIZE) | 5ull; LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader); - MsrReg = ((1UL << CONFIG_CPU_ADDR_BITS) - CONFIG_ROM_SIZE) | 0x800ull; + MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CONFIG_ROM_SIZE) | 0x800ull; LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader); /* Clear all pending SMI. On S3 clear power button enable so it wll not generate an SMI */ diff --git a/src/mainboard/supermicro/h8qgi/agesawrapper.c b/src/mainboard/supermicro/h8qgi/agesawrapper.c index 66236ed..83377a5 100644 --- a/src/mainboard/supermicro/h8qgi/agesawrapper.c +++ b/src/mainboard/supermicro/h8qgi/agesawrapper.c @@ -194,7 +194,7 @@ UINT32 agesawrapper_amdinitmmio(VOID) /* Set ROM cache onto WP to decrease post time */ MsrReg = (0x0100000000 - CONFIG_ROM_SIZE) | 5; LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader); - MsrReg = ((1UL << CONFIG_CPU_ADDR_BITS) - CONFIG_ROM_SIZE) | 0x800; + MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CONFIG_ROM_SIZE) | 0x800; LibAmdMsrWrite(0x20D, &MsrReg, &StdHeader); Status = AGESA_SUCCESS; diff --git a/src/mainboard/supermicro/h8scm/agesawrapper.c b/src/mainboard/supermicro/h8scm/agesawrapper.c index a841629..ad914cd 100644 --- a/src/mainboard/supermicro/h8scm/agesawrapper.c +++ b/src/mainboard/supermicro/h8scm/agesawrapper.c @@ -194,7 +194,7 @@ UINT32 agesawrapper_amdinitmmio(VOID) /* Set ROM cache onto WP to decrease post time */ MsrReg = (0x0100000000 - CONFIG_ROM_SIZE) | 5; LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader); - MsrReg = ((1UL << CONFIG_CPU_ADDR_BITS) - CONFIG_ROM_SIZE) | 0x800; + MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CONFIG_ROM_SIZE) | 0x800; LibAmdMsrWrite(0x20D, &MsrReg, &StdHeader); Status = AGESA_SUCCESS; diff --git a/src/mainboard/tyan/s8226/agesawrapper.c b/src/mainboard/tyan/s8226/agesawrapper.c index 6f18f5c..c8620a7 100644 --- a/src/mainboard/tyan/s8226/agesawrapper.c +++ b/src/mainboard/tyan/s8226/agesawrapper.c @@ -204,7 +204,7 @@ agesawrapper_amdinitmmio ( /* Set ROM cache onto WP to decrease post time */ MsrReg = (0x0100000000ull - CONFIG_ROM_SIZE) | 5ull; LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader); - MsrReg = ((1UL << CONFIG_CPU_ADDR_BITS) - CONFIG_ROM_SIZE) | 0x800ull; + MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CONFIG_ROM_SIZE) | 0x800ull; LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader); Status = AGESA_SUCCESS;

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Patch merged into coreboot/master: 816e9d1 Support for Celeron 1007U
by gerrit＠coreboot.org 14 Jan '13

14 Jan '13

the following patch was just integrated into master: commit 816e9d1f0e1d317e360e26a43dfb6b7d36c2a514 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Mon Jan 14 10:25:43 2013 -0800 Support for Celeron 1007U Change-Id: I6b96b0e387dc3e6985eb1476fea612772a2288bc Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Reviewed-on: http://review.coreboot.org/2145 Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin(a)se-eng.com> Build-Tested: build bot (Jenkins) at Mon Jan 14 19:34:02 2013, giving +1 See http://review.coreboot.org/2145 for details. -gerrit

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Patch set updated for coreboot: a15085c Hudson: Changes for FADT for ACPI 3.0 and legacy free
by Martin Roth 14 Jan '13

14 Jan '13

Martin Roth (martin(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2140 -gerrit commit a15085c917830db02a8a6db57ef98f61accc8656 Author: Martin Roth <martin(a)se-eng.com> Date: Thu Jan 10 16:40:59 2013 -0700 Hudson: Changes for FADT for ACPI 3.0 and legacy free Update the southbridge/amd/agesa/hudson FADT generation for ACPI 3.0 compiance similar to what was done for SB800. According to the datasheet, PMA_CNT_BLK is no longer available and PM2_CNT_BLK should not be used. Setup for these have been removed from the table and .h file. Add Kconfig option for Legacy free and hook it into the parmer and thatcher AGESA initialization as well as the FADT code. This should really be done inside the southbridge wrapper and not in the mainboard, but for now the code to attach it to is inside the mainboard directories. Update Kconfig for parmer and thatcher to default to legacy free. Change-Id: Ied8eb1f26b4aa364d051ec5f7ed6f482bb440957 Signed-off-by: Martin Roth <martin(a)se-eng.com> --- src/mainboard/amd/parmer/BiosCallOuts.c | 5 +- src/mainboard/amd/parmer/Kconfig | 4 + src/mainboard/amd/thatcher/BiosCallOuts.c | 5 +- src/mainboard/amd/thatcher/Kconfig | 4 + src/southbridge/amd/agesa/hudson/Kconfig | 6 ++ src/southbridge/amd/agesa/hudson/fadt.c | 152 ++++++++++++++++++------------ src/southbridge/amd/agesa/hudson/hudson.h | 2 - 7 files changed, 115 insertions(+), 63 deletions(-) diff --git a/src/mainboard/amd/parmer/BiosCallOuts.c b/src/mainboard/amd/parmer/BiosCallOuts.c index 24268d7..c3ac4de 100644 --- a/src/mainboard/amd/parmer/BiosCallOuts.c +++ b/src/mainboard/amd/parmer/BiosCallOuts.c @@ -717,9 +717,12 @@ AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr) FCH_RESET_DATA_BLOCK *FchParams = (FCH_RESET_DATA_BLOCK *)FchData; if (FchParams->StdHeader->Func == AMD_INIT_RESET) { - //FCH_RESET_DATA_BLOCK *FchParams_reset = (FCH_RESET_DATA_BLOCK *) FchData; + FCH_RESET_DATA_BLOCK *FchParams_reset = (FCH_RESET_DATA_BLOCK *) FchData; printk(BIOS_DEBUG, "Fch OEM config in INIT RESET "); //FchParams_reset->EcChannel0 = TRUE; /* logical devicd 3 */ +#if CONFIG_HUDSON_LEGACY_FREE + FchParams_reset->LegacyFree = 1; +#endif } else if (FchParams->StdHeader->Func == AMD_INIT_ENV) { FCH_DATA_BLOCK *FchParams_env = (FCH_DATA_BLOCK *)FchData; printk(BIOS_DEBUG, "Fch OEM config in INIT ENV "); diff --git a/src/mainboard/amd/parmer/Kconfig b/src/mainboard/amd/parmer/Kconfig index e3b153d..a4da2e2 100644 --- a/src/mainboard/amd/parmer/Kconfig +++ b/src/mainboard/amd/parmer/Kconfig @@ -104,4 +104,8 @@ config WARNINGS_ARE_ERRORS bool default n +config HUDSON_LEGACY_FREE + bool + default y + endif # BOARD_AMD_PARMER diff --git a/src/mainboard/amd/thatcher/BiosCallOuts.c b/src/mainboard/amd/thatcher/BiosCallOuts.c index d4da61a..ba32727 100644 --- a/src/mainboard/amd/thatcher/BiosCallOuts.c +++ b/src/mainboard/amd/thatcher/BiosCallOuts.c @@ -717,9 +717,12 @@ AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr) FCH_RESET_DATA_BLOCK *FchParams = (FCH_RESET_DATA_BLOCK *)FchData; if (FchParams->StdHeader->Func == AMD_INIT_RESET) { - //FCH_RESET_DATA_BLOCK *FchParams_reset = (FCH_RESET_DATA_BLOCK *) FchData; + FCH_RESET_DATA_BLOCK *FchParams_reset = (FCH_RESET_DATA_BLOCK *) FchData; printk(BIOS_DEBUG, "Fch OEM config in INIT RESET "); //FchParams_reset->EcChannel0 = TRUE; /* logical devicd 3 */ +#if CONFIG_HUDSON_LEGACY_FREE + FchParams_reset->LegacyFree = 1; +#endif } else if (FchParams->StdHeader->Func == AMD_INIT_ENV) { FCH_DATA_BLOCK *FchParams_env = (FCH_DATA_BLOCK *)FchData; printk(BIOS_DEBUG, "Fch OEM config in INIT ENV "); diff --git a/src/mainboard/amd/thatcher/Kconfig b/src/mainboard/amd/thatcher/Kconfig index 7700034..0fe97fa 100644 --- a/src/mainboard/amd/thatcher/Kconfig +++ b/src/mainboard/amd/thatcher/Kconfig @@ -105,4 +105,8 @@ config WARNINGS_ARE_ERRORS bool default n +config HUDSON_LEGACY_FREE + bool + default y + endif # BOARD_AMD_THATCHER diff --git a/src/southbridge/amd/agesa/hudson/Kconfig b/src/southbridge/amd/agesa/hudson/Kconfig index c315250..3a97e60 100644 --- a/src/southbridge/amd/agesa/hudson/Kconfig +++ b/src/southbridge/amd/agesa/hudson/Kconfig @@ -213,3 +213,9 @@ config S3_VOLATILE_POS non-volitile storage at cold boot stage. endif + +config HUDSON_LEGACY_FREE + bool "System is legacy free" + help + Select y if there is no keyboard controller in the system. + This sets variables in AGESA and ACPI. diff --git a/src/southbridge/amd/agesa/hudson/fadt.c b/src/southbridge/amd/agesa/hudson/fadt.c index ee0334c..bf1b0fc 100644 --- a/src/southbridge/amd/agesa/hudson/fadt.c +++ b/src/southbridge/amd/agesa/hudson/fadt.c @@ -28,6 +28,20 @@ #include <device/device.h> #include "hudson.h" +#if CONFIG_HUDSON_LEGACY_FREE + #define FADT_BOOT_ARCH ACPI_FADT_LEGACY_FREE +#else + #define FADT_BOOT_ARCH (ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042) +#endif + +#ifndef FADT_PM_PROFILE + #define FADT_PM_PROFILE PM_UNSPECIFIED +#endif + +/* + * Reference section 5.2.9 Fixed ACPI Description Table (FADT) + * in the ACPI 3.0b specification. + */ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) { acpi_header_t *header = &(fadt->header); @@ -37,24 +51,23 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) /* Prepare the header */ memset((void *)fadt, 0, sizeof(acpi_fadt_t)); memcpy(header->signature, "FACP", 4); - header->length = 244; - header->revision = 3; + header->length = sizeof(acpi_fadt_t); + header->revision = ACPI_FADT_REV_ACPI_3_0; memcpy(header->oem_id, OEM_ID, 6); - memcpy(header->oem_table_id, "COREBOOT", 8); + memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); memcpy(header->asl_compiler_id, ASLC, 4); header->asl_compiler_revision = 0; fadt->firmware_ctrl = (u32) facs; fadt->dsdt = (u32) dsdt; - /* 3=Workstation,4=Enterprise Server, 7=Performance Server */ - fadt->preferred_pm_profile = 0x03; - fadt->sci_int = 9; - /* disable system management mode by setting to 0: */ - fadt->smi_cmd = 0; - fadt->acpi_enable = 0xf0; - fadt->acpi_disable = 0xf1; - fadt->s4bios_req = 0x0; - fadt->pstate_cnt = 0xe2; + fadt->model = 0; /* reserved, should be 0 ACPI 3.0 */ + fadt->preferred_pm_profile = FADT_PM_PROFILE; + fadt->sci_int = 9; /* HUDSON - IRQ 09 – ACPI SCI */ + fadt->smi_cmd = 0; /* disable system management mode */ + fadt->acpi_enable = 0; /* unused if SMI_CMD = 0 */ + fadt->acpi_disable = 0; /* unused if SMI_CMD = 0 */ + fadt->s4bios_req = 0; /* unused if SMI_CMD = 0 */ + fadt->pstate_cnt = 0; /* unused if SMI_CMD = 0 */ pm_iowrite(0x60, ACPI_PM_EVT_BLK & 0xFF); pm_iowrite(0x61, ACPI_PM_EVT_BLK >> 8); @@ -72,113 +85,134 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) pm_iowrite(0x6A, 0); /* AcpiSmiCmdLo */ pm_iowrite(0x6B, 0); /* AcpiSmiCmdHi */ - pm_iowrite(0x6C, ACPI_PMA_CNT_BLK & 0xFF); - pm_iowrite(0x6D, ACPI_PMA_CNT_BLK >> 8); - pm_iowrite(0x74, 1<<0 | 1<<1 | 1<<4 | 1<<2); /* AcpiDecodeEnable, When set, SB uses * the contents of the PM registers at * index 60-6B to decode ACPI I/O address. * AcpiSmiEn & SmiCmdEn*/ /* RTC_En_En, TMR_En_En, GBL_EN_EN */ - outl(0x1, ACPI_PM1_CNT_BLK); /* set SCI_EN */ + outl(0x1, ACPI_PM1_CNT_BLK); /* set SCI_EN */ fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK; fadt->pm1b_evt_blk = 0x0000; fadt->pm1a_cnt_blk = ACPI_PM1_CNT_BLK; fadt->pm1b_cnt_blk = 0x0000; - fadt->pm2_cnt_blk = ACPI_PMA_CNT_BLK; + fadt->pm2_cnt_blk = 0x0000; fadt->pm_tmr_blk = ACPI_PM_TMR_BLK; fadt->gpe0_blk = ACPI_GPE0_BLK; - fadt->gpe1_blk = 0x0000; /* we dont have gpe1 block, do we? */ + fadt->gpe1_blk = 0x0000; /* No gpe1 block in hudson */ - fadt->pm1_evt_len = 4; - fadt->pm1_cnt_len = 2; - fadt->pm2_cnt_len = 1; - fadt->pm_tmr_len = 4; - fadt->gpe0_blk_len = 8; + fadt->pm1_evt_len = 4; /* 32 bits */ + fadt->pm1_cnt_len = 2; /* 16 bits */ + fadt->pm2_cnt_len = 0; + fadt->pm_tmr_len = 4; /* 32 bits */ + fadt->gpe0_blk_len = 8; /* 64 bits */ fadt->gpe1_blk_len = 0; fadt->gpe1_base = 0; - fadt->cst_cnt = 0xe3; - fadt->p_lvl2_lat = 101; - fadt->p_lvl3_lat = 1001; - fadt->flush_size = 0; - fadt->flush_stride = 0; - fadt->duty_offset = 1; - fadt->duty_width = 3; + fadt->cst_cnt = 0x00; /* unused if SMI_CMD = 0 */ + fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED; + fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; + fadt->flush_size = 0; /* set to 0 if WBINVD is 1 in flags */ + fadt->flush_stride = 0; /* set to 0 if WBINVD is 1 in flags */ + fadt->duty_offset = 1; /* CLK_VAL bits 3:1 */ + fadt->duty_width = 3; /* CLK_VAL bits 3:1 */ fadt->day_alrm = 0; /* 0x7d these have to be */ fadt->mon_alrm = 0; /* 0x7e added to cmos.layout */ - fadt->century = 0; /* 0x7f to make rtc alrm work */ - fadt->iapc_boot_arch = 0x3; /* See table 5-11 */ - fadt->flags = 0x0001c1a5 | 1 << 10;/* 0x25; */ - - fadt->res2 = 0; - - fadt->reset_reg.space_id = 1; + fadt->century = 0; /* 0x7f to make rtc alarm work */ + fadt->iapc_boot_arch = FADT_BOOT_ARCH; /* See table 5-10 */ + fadt->res2 = 0; /* reserved, MUST be 0 ACPI 3.0 */ + fadt->flags = ACPI_FADT_WBINVD | /* See table 5-10 ACPI 3.0a spec */ + ACPI_FADT_C1_SUPPORTED | + ACPI_FADT_SLEEP_BUTTON | + ACPI_FADT_S4_RTC_WAKE | + ACPI_FADT_32BIT_TIMER | + ACPI_FADT_RESET_REGISTER | + ACPI_FADT_PCI_EXPRESS_WAKE | + ACPI_FADT_PLATFORM_CLOCK | + ACPI_FADT_S4_RTC_VALID | + ACPI_FADT_REMOTE_POWER_ON; + + /* Format is from 5.2.3.1: Generic Address Structure */ + /* reset_reg: see section 4.7.3.6 ACPI 3.0a spec */ + /* 8 bit write of value 0x06 to 0xCF9 in IO space */ + fadt->reset_reg.space_id = ACPI_ADDRESS_SPACE_IO; fadt->reset_reg.bit_width = 8; fadt->reset_reg.bit_offset = 0; - fadt->reset_reg.resv = 0; + fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; fadt->reset_reg.addrl = 0xcf9; fadt->reset_reg.addrh = 0x0; fadt->reset_value = 6; - fadt->x_firmware_ctl_l = (u32) facs; + + fadt->res3 = 0; /* reserved, MUST be 0 ACPI 3.0 */ + fadt->res4 = 0; /* reserved, MUST be 0 ACPI 3.0 */ + fadt->res5 = 0; /* reserved, MUST be 0 ACPI 3.0 */ + + fadt->x_firmware_ctl_l = 0; /* set to 0 if firmware_ctrl is used */ fadt->x_firmware_ctl_h = 0; fadt->x_dsdt_l = (u32) dsdt; fadt->x_dsdt_h = 0; - fadt->x_pm1a_evt_blk.space_id = 1; + fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm1a_evt_blk.bit_width = 32; fadt->x_pm1a_evt_blk.bit_offset = 0; - fadt->x_pm1a_evt_blk.resv = 0; + fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; fadt->x_pm1a_evt_blk.addrl = ACPI_PM_EVT_BLK; fadt->x_pm1a_evt_blk.addrh = 0x0; - fadt->x_pm1b_evt_blk.space_id = 1; - fadt->x_pm1b_evt_blk.bit_width = 4; + fadt->x_pm1b_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_pm1b_evt_blk.bit_width = 0; fadt->x_pm1b_evt_blk.bit_offset = 0; - fadt->x_pm1b_evt_blk.resv = 0; + fadt->x_pm1b_evt_blk.access_size = 0; fadt->x_pm1b_evt_blk.addrl = 0x0; fadt->x_pm1b_evt_blk.addrh = 0x0; - fadt->x_pm1a_cnt_blk.space_id = 1; + + fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm1a_cnt_blk.bit_width = 16; fadt->x_pm1a_cnt_blk.bit_offset = 0; - fadt->x_pm1a_cnt_blk.resv = 0; + fadt->x_pm1a_cnt_blk.access_size = 0; fadt->x_pm1a_cnt_blk.addrl = ACPI_PM1_CNT_BLK; fadt->x_pm1a_cnt_blk.addrh = 0x0; - fadt->x_pm1b_cnt_blk.space_id = 1; - fadt->x_pm1b_cnt_blk.bit_width = 2; + fadt->x_pm1b_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_pm1b_cnt_blk.bit_width = 0; fadt->x_pm1b_cnt_blk.bit_offset = 0; - fadt->x_pm1b_cnt_blk.resv = 0; + fadt->x_pm1b_cnt_blk.access_size = 0; fadt->x_pm1b_cnt_blk.addrl = 0x0; fadt->x_pm1b_cnt_blk.addrh = 0x0; - fadt->x_pm2_cnt_blk.space_id = 1; + /* + * Note: Under this current AMD C state implementation, this is no longer + * used and should not be reported to OS. + */ + fadt->x_pm2_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm2_cnt_blk.bit_width = 0; fadt->x_pm2_cnt_blk.bit_offset = 0; - fadt->x_pm2_cnt_blk.resv = 0; - fadt->x_pm2_cnt_blk.addrl = ACPI_PMA_CNT_BLK; + fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; + fadt->x_pm2_cnt_blk.addrl = 0; fadt->x_pm2_cnt_blk.addrh = 0x0; - fadt->x_pm_tmr_blk.space_id = 1; + + fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm_tmr_blk.bit_width = 32; fadt->x_pm_tmr_blk.bit_offset = 0; - fadt->x_pm_tmr_blk.resv = 0; + fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; fadt->x_pm_tmr_blk.addrl = ACPI_PM_TMR_BLK; fadt->x_pm_tmr_blk.addrh = 0x0; - fadt->x_gpe0_blk.space_id = 1; - fadt->x_gpe0_blk.bit_width = 32; + + fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_gpe0_blk.bit_width = 64; /* EventStatus + Event Enable */ fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.resv = 0; + fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; fadt->x_gpe0_blk.addrl = ACPI_GPE0_BLK; fadt->x_gpe0_blk.addrh = 0x0; - fadt->x_gpe1_blk.space_id = 1; + + fadt->x_gpe1_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_gpe1_blk.bit_width = 0; fadt->x_gpe1_blk.bit_offset = 0; - fadt->x_gpe1_blk.resv = 0; + fadt->x_gpe1_blk.access_size = 0; fadt->x_gpe1_blk.addrl = 0; fadt->x_gpe1_blk.addrh = 0x0; diff --git a/src/southbridge/amd/agesa/hudson/hudson.h b/src/southbridge/amd/agesa/hudson/hudson.h index 15738aa..ef44874 100644 --- a/src/southbridge/amd/agesa/hudson/hudson.h +++ b/src/southbridge/amd/agesa/hudson/hudson.h @@ -35,7 +35,6 @@ #define ACPI_PM_EVT_BLK (HUDSON_ACPI_IO_BASE + 0x00) /* 4 bytes */ #define ACPI_PM1_CNT_BLK (HUDSON_ACPI_IO_BASE + 0x04) /* 2 bytes */ -#define ACPI_PMA_CNT_BLK (HUDSON_ACPI_IO_BASE + 0x0F) /* 1 byte, TODO: Is it 0xFE00? */ #define ACPI_PM_TMR_BLK (HUDSON_ACPI_IO_BASE + 0x18) /* 4 bytes */ #define ACPI_GPE0_BLK (HUDSON_ACPI_IO_BASE + 0x10) /* 8 bytes */ #define ACPI_CPU_CONTROL (HUDSON_ACPI_IO_BASE + 0x08) /* 6 bytes */ @@ -55,7 +54,6 @@ void set_sm_enable_bits(device_t sm_dev, u32 reg_pos, u32 mask, u32 val); #define CPU_CNT_BLK_ADDRESS 0x810 // CpuControlBlkAddr; #define GPE0_BLK_ADDRESS 0x820 // AcpiGpe0BlkAddr; #define SMI_CMD_PORT 0xB0 // SmiCmdPortAddr; -#define ACPI_PMA_CNT_BLK_ADDRESS 0xFE00 // AcpiPmaCntBlkAddr; #define SPIROM_BASE_ADDRESS_REGISTER 0xA0 #ifdef __PRE_RAM__

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Patch set updated for coreboot: 5304a2d armv7: invoke intermediate build rules
by Stefan Reinauer 14 Jan '13

14 Jan '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2095 -gerrit commit 5304a2d953756f085165046105c909cc0d298cff Author: David Hendricks <dhendrix(a)chromium.org> Date: Wed Jan 2 17:48:49 2013 -0800 armv7: invoke intermediate build rules This adds $$(INTERMEDIATE) as a pre-requisite for coreboot.rom on armv7. It is modeled after the $(obj)/coreboot.rom rule for x86. Change-Id: I483a88035fa2288829b6e042e51ef932c8c4f23c Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/arch/armv7/Makefile.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/arch/armv7/Makefile.inc b/src/arch/armv7/Makefile.inc index 4cb97a6..caa6375 100644 --- a/src/arch/armv7/Makefile.inc +++ b/src/arch/armv7/Makefile.inc @@ -58,7 +58,7 @@ $(obj)/coreboot.pre1: $(CBFSTOOL) mv $(obj)/coreboot.rom $@ endif -$(obj)/coreboot.rom: $(obj)/coreboot.pre $(objcbfs)/coreboot_ram.elf $(CBFSTOOL) $(call strip_quotes,$(COREBOOT_ROM_DEPENDENCIES)) +$(obj)/coreboot.rom: $(obj)/coreboot.pre $(objcbfs)/coreboot_ram.elf $(CBFSTOOL) $(call strip_quotes,$(COREBOOT_ROM_DEPENDENCIES)) $$(INTERMEDIATE) @printf " CBFS $(subst $(obj)/,,$(@))\n" cp $(obj)/coreboot.pre $@.tmp if [ -f $(objcbfs)/coreboot_ap.elf ]; \

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New patch to review for coreboot: 896a455 Support for Celeron 1007U
by Stefan Reinauer 14 Jan '13

14 Jan '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2145 -gerrit commit 896a45547672ec5a468112ce4892c93a1dfeda18 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Mon Jan 14 10:25:43 2013 -0800 Support for Celeron 1007U Change-Id: I6b96b0e387dc3e6985eb1476fea612772a2288bc Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/northbridge/intel/sandybridge/early_init.c | 3 ++- src/northbridge/intel/sandybridge/gma.c | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c index b060831..c184fa2 100644 --- a/src/northbridge/intel/sandybridge/early_init.c +++ b/src/northbridge/intel/sandybridge/early_init.c @@ -97,7 +97,8 @@ static void sandybridge_setup_graphics(void) case 0x0116: /* GT2 Mobile */ case 0x0122: /* GT2 Desktop >=1.3GHz */ case 0x0126: /* GT2 Mobile >=1.3GHz */ - case 0x0166: /* IvyBridge ??? */ + case 0x0156: /* IvyBridge */ + case 0x0166: /* IvyBridge */ break; default: printk(BIOS_DEBUG, "Graphics not supported by this CPU/chipset.\n"); diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c index 8c09571..52707bd 100644 --- a/src/northbridge/intel/sandybridge/gma.c +++ b/src/northbridge/intel/sandybridge/gma.c @@ -318,6 +318,7 @@ u32 map_oprom_vendev(u32 vendev) case 0x80860116: /* GT2 Mobile */ case 0x80860122: /* GT2 Desktop >=1.3GHz */ case 0x80860126: /* GT2 Mobile >=1.3GHz */ + case 0x80860156: /* IVB */ case 0x80860166: /* IVB */ new_vendev=0x80860106; /* GT1 Mobile */ break; @@ -660,7 +661,7 @@ static struct device_operations gma_func0_ops = { }; static const unsigned short gma_ids[] = { - 0x0102, 0x0106, 0x010a, 0x0112, 0x0116, 0x0122, 0x0126, 0x166, + 0x0102, 0x0106, 0x010a, 0x0112, 0x0116, 0x0122, 0x0126, 0x0156, 0x166, 0, }; static const struct pci_driver gma_gt1_desktop __pci_driver = {

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coreboot January 2013