coreboot January 2013

coreboot@coreboot.org

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New patch to review for coreboot: 60f9406 a few small fix-ups for snow's romstage...
by David Hendricks 15 Jan '13

15 Jan '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2155 -gerrit commit 60f9406b3bf3c78a6676bf39c01163dbefc690b1 Author: David Hendricks <dhendrix(a)chromium.org> Date: Tue Jan 15 21:52:08 2013 -0800 a few small fix-ups for snow's romstage... - romstage-y += romstage.c in Makefile.inc - get rid of argument to main() Change-Id: I4e9ad40b609cb4d3a521f7f6012ff02e26c32fc2 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/mainboard/google/snow/Makefile.inc | 2 +- src/mainboard/google/snow/romstage.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mainboard/google/snow/Makefile.inc b/src/mainboard/google/snow/Makefile.inc index 01488d0..26378db 100644 --- a/src/mainboard/google/snow/Makefile.inc +++ b/src/mainboard/google/snow/Makefile.inc @@ -17,7 +17,7 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -#romstage-y += romstage.c +romstage-y += romstage.c # ramstage-y += ec.c diff --git a/src/mainboard/google/snow/romstage.c b/src/mainboard/google/snow/romstage.c index 29e4555..bb67c94 100644 --- a/src/mainboard/google/snow/romstage.c +++ b/src/mainboard/google/snow/romstage.c @@ -26,7 +26,7 @@ static void mmu_setup(void) dram_bank_mmu_setup(CONFIG_SYS_SDRAM_BASE, CONFIG_DRAM_SIZE_MB * 1024); } -void main(unsigned long bist) +void main() { mmu_setup(); }

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New patch to review for coreboot: 9e1343b use a relative path for #line 3
by David Hendricks 15 Jan '13

15 Jan '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2153 -gerrit commit 9e1343b513e316fadc07f68ef0eeb4919d6d4e1f Author: David Hendricks <dhendrix(a)chromium.org> Date: Tue Jan 15 16:09:08 2013 -0800 use a relative path for #line 3 The current path doesn't make much sense (unless you're Sven) and may also incur a very long access penalty if /home happens to be on a network mounted filesystem. Change-Id: I8cfceb3cf237757ce9ea8f1953bce5a72691838a Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- util/sconfig/lex.yy.c_shipped | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/util/sconfig/lex.yy.c_shipped b/util/sconfig/lex.yy.c_shipped index 4eee138..215da56 100644 --- a/util/sconfig/lex.yy.c_shipped +++ b/util/sconfig/lex.yy.c_shipped @@ -1,5 +1,5 @@ -#line 3 "/home/svens/coreboot/coreboot-i5000-latest/util/sconfig/lex.yy.c_shipped" +#line 3 "util/sconfig/lex.yy.c_shipped" #define YY_INT_ALIGNED short int

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Patch merged into coreboot/master: 9382bd6 armv7: delete unneeded ptrace.h
by gerrit＠coreboot.org 15 Jan '13

15 Jan '13

the following patch was just integrated into master: commit 9382bd65d4ebee690fe7ee6602d418144ed92d54 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Wed Jan 16 00:26:41 2013 +0100 armv7: delete unneeded ptrace.h ... and delete traces in source files. Change-Id: Ie0f70a479f1eadadc654a41fa3c426d1d4ac2f2b Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Reviewed-on: http://review.coreboot.org/2152 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Build-Tested: build bot (Jenkins) at Wed Jan 16 00:42:05 2013, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Wed Jan 16 00:48:02 2013, giving +2 See http://review.coreboot.org/2152 for details. -gerrit

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New patch to review for coreboot: 8201b22 armv7: delete unneeded ptrace.h
by Stefan Reinauer 15 Jan '13

15 Jan '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2152 -gerrit commit 8201b22dc758a3a9fd55e816edf6caaf0b9c6c66 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Wed Jan 16 00:26:41 2013 +0100 armv7: delete unneeded ptrace.h ... and delete traces in source files. Change-Id: Ie0f70a479f1eadadc654a41fa3c426d1d4ac2f2b Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/arch/armv7/include/common.h | 13 ------------- src/arch/armv7/include/ptrace.h | 30 ------------------------------ src/arch/armv7/lib/interrupts.c | 1 - 3 files changed, 44 deletions(-) diff --git a/src/arch/armv7/include/common.h b/src/arch/armv7/include/common.h index 2d4d020..a2cd9ae 100644 --- a/src/arch/armv7/include/common.h +++ b/src/arch/armv7/include/common.h @@ -24,9 +24,6 @@ #ifndef __COMMON_H_ #define __COMMON_H_ 1 -#undef _LINUX_CONFIG_H -#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ - #ifndef __ASSEMBLER__ /* put C only stuff in this section */ typedef unsigned char uchar; @@ -36,17 +33,7 @@ typedef volatile unsigned char vu_char; typedef unsigned long ulong; typedef unsigned int uint; -//#include <config.h> -//#include <asm-offsets.h> -//#include <linux/bitops.h> -//#include <linux/string.h> -//#include <asm/ptrace.h> #include <types.h> -//#include <stdarg.h> - -//#include <part.h> -//#include <flash.h> -//#include <image.h> #ifdef DEBUG #define debug(fmt,args...) printf (fmt ,##args) diff --git a/src/arch/armv7/include/ptrace.h b/src/arch/armv7/include/ptrace.h deleted file mode 100644 index e981cad..0000000 --- a/src/arch/armv7/include/ptrace.h +++ /dev/null @@ -1,30 +0,0 @@ -#ifndef __ASM_ARM_PTRACE_H -#define __ASM_ARM_PTRACE_H - -#define PTRACE_GETREGS 12 -#define PTRACE_SETREGS 13 -#define PTRACE_GETFPREGS 14 -#define PTRACE_SETFPREGS 15 - -#define PTRACE_SETOPTIONS 21 - -/* options set using PTRACE_SETOPTIONS */ -#define PTRACE_O_TRACESYSGOOD 0x00000001 - -#include <asm/proc/ptrace.h> - -#ifndef __ASSEMBLER__ -#define pc_pointer(v) \ - ((v) & ~PCMASK) - -#define instruction_pointer(regs) \ - (pc_pointer((regs)->ARM_pc)) - -extern void show_regs(struct pt_regs *); - -#define predicate(x) (x & 0xf0000000) -#define PREDICATE_ALWAYS 0xe0000000 - -#endif /* __ASSEMBLER__ */ - -#endif diff --git a/src/arch/armv7/lib/interrupts.c b/src/arch/armv7/lib/interrupts.c index 6ee3f26..ab9a80c 100644 --- a/src/arch/armv7/lib/interrupts.c +++ b/src/arch/armv7/lib/interrupts.c @@ -36,7 +36,6 @@ */ #include <common.h> -//#include <asm/proc-armv/ptrace.h> DECLARE_GLOBAL_DATA_PTR;

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Patch set updated for coreboot: e84d1a1 libpayload: add EHCI QH/qTD debugging
by Paul Menzel 15 Jan '13

15 Jan '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2053 -gerrit commit e84d1a108d471961270fbdaccae49b6efc3a7801 Author: Anton Kochkov <anton.kochkov(a)gmail.com> Date: Wed Dec 19 12:32:32 2012 +0400 libpayload: add EHCI QH/qTD debugging Improve USB debugging for EHCI by adding dump_qh and enhacing dump_td to dump all queue chain and information. Change-Id: Ia8ecf19c6dac085cf9558bdf659a5e74ce332714 Signed-off-by: Anton Kochkov <anton.kochkov(a)gmail.com> --- payloads/libpayload/drivers/usb/ehci.c | 80 ++++++++++++++++++++++++++++++++-- 1 file changed, 77 insertions(+), 3 deletions(-) diff --git a/payloads/libpayload/drivers/usb/ehci.c b/payloads/libpayload/drivers/usb/ehci.c index f27658d..3e57902 100644 --- a/payloads/libpayload/drivers/usb/ehci.c +++ b/payloads/libpayload/drivers/usb/ehci.c @@ -34,9 +34,83 @@ static void dump_td(u32 addr) { qtd_t *td = phys_to_virt(addr); - usb_debug("td at phys(%x): status: %x\n\n", addr, td->token & QTD_STATUS_MASK); - usb_debug("- cerr: %x, total_len: %x\n\n", (td->token & QTD_CERR_MASK) >> QTD_CERR_SHIFT, - (td->token & QTD_TOTAL_LEN_MASK) >> QTD_TOTAL_LEN_SHIFT); + usb_debug("+---------------------------------------------------+\n"); + if (((td->token & (3UL << 8)) >> 8) == 2) + usb_debug("|..[SETUP]..........................................|\n"); + else if (((td->token & (3UL << 8)) >> 8) == 1) + usb_debug("|..[IN].............................................|\n"); + else if (((td->token & (3UL << 8)) >> 8) == 0) + usb_debug("|..[OUT]............................................|\n"); + else + usb_debug("|..[]...............................................|\n"); + usb_debug("|:|============ EHCI TD at [0x%08lx] ==========|:|\n", addr); + usb_debug("|:| ERRORS = [%ld] | TOKEN = [0x%08lx] | |:|\n", + 3 - ((td->token & QTD_CERR_MASK) >> QTD_CERR_SHIFT), td->token); + usb_debug("|:+-----------------------------------------------+:|\n"); + usb_debug("|:| Next qTD [0x%08lx] |:|\n", td->next_qtd); + usb_debug("|:+-----------------------------------------------+:|\n"); + usb_debug("|:| Alt. Next qTD [0x%08lx] |:|\n", td->alt_next_qtd); + usb_debug("|:+-----------------------------------------------+:|\n"); + usb_debug("|:| | Bytes to Transfer | [%04ld] |:|\n", (td->token & (0x7FUL << 16)) >> 16); + usb_debug("|:| | PID CODE: | [%ld] |:|\n", (td->token & (3UL << 8)) >> 8); + usb_debug("|:| | Interrupt On Complete (IOC) | [%ld] |:|\n", (td->token & (1UL << 15)) >> 15); + usb_debug("|:| | Status Active | [%ld] |:|\n", (td->token & (1UL << 7)) >> 7); + usb_debug("|:| | Status Halted | [%ld] |:|\n", (td->token & (1UL << 6)) >> 6); + usb_debug("|:| TOKEN | Status Data Buffer Error | [%ld] |:|\n", (td->token & (1UL << 5)) >> 5); + usb_debug("|:| | Status Babble detected | [%ld] |:|\n", (td->token & (1UL << 4)) >> 4); + usb_debug("|:| | Status Transaction Error | [%ld] |:|\n", (td->token & (1UL << 3)) >> 3); + usb_debug("|:| | Status Missed Micro Frame | [%ld] |:|\n", (td->token & (1UL << 2)) >> 2); + usb_debug("|:| | Split Transaction State | [%ld] |:|\n", (td->token & (1UL << 1)) >> 1); + usb_debug("|:| | Ping State | [%ld] |:|\n", td->token & 1UL); + usb_debug("|:|-----------------------------------------------|:|\n"); + usb_debug("|...................................................|\n"); + usb_debug("+---------------------------------------------------+\n"); +} + +static void dump_qh(ehci_qh_t *cur) +{ + qtd_t *tmp_qtd = NULL; + usb_debug("+===================================================+\n"); + usb_debug("| ############# EHCI QH at [0x%08lx] ########### |\n", virt_to_phys(cur)); + usb_debug("+---------------------------------------------------+\n"); + usb_debug("| Horizonal Link Pointer [0x%08lx] |\n", cur->horiz_link_ptr); + usb_debug("+------------------[ 0x%08lx ]-------------------+\n", cur->epchar); + usb_debug("| | Maximum Packet Length | [%04ld] |\n", ((cur->epchar & (0x7ffUL << 16)) >> 16)); + usb_debug("| | Device Address | [%ld] |\n", cur->epchar & 0x7F); + usb_debug("| | Inactivate on Next Transaction | [%ld] |\n", ((cur->epchar & (1UL << 7)) >> 7)); + usb_debug("| | Endpoint Number | [%ld] |\n", ((cur->epchar & (0xFUL << 8)) >> 8)); + usb_debug("| EPCHAR | Endpoint Speed | [%ld] |\n", ((cur->epchar & (3UL << 12)) >> 12)); + usb_debug("| | Data Toggle Control | [%ld] |\n", ((cur->epchar & (1UL << 14)) >> 14)); + usb_debug("| | Head of Reclamation List Flag | [%ld] |\n", ((cur->epchar & (1UL << 15)) >> 15)); + usb_debug("| | Control Endpoint Flag | [%ld] |\n", ((cur->epchar & (1UL << 27)) >> 27)); + usb_debug("| | Nak Count Reload | [%ld] |\n", ((cur->epchar & (0xFUL << 28)) >> 28)); + if (((cur->epchar & (1UL << QH_NON_HS_CTRL_EP_SHIFT)) >> QH_NON_HS_CTRL_EP_SHIFT) == 1) { /* Split transaction */ + usb_debug("+--------+---------[ 0x%08lx ]----------+--------+\n", cur->epcaps); + usb_debug("| | Hub Port | [%ld] |\n", ((cur->epcaps & (0x7FUL << 23)) >> 23)); /* [29:23] */ + usb_debug("| | Hub Address | [%ld] |\n", ((cur->epcaps & (0x7FUL << 16)) >> 16)); /* [22:16] */ + } + usb_debug("+---------------------------------------------------+\n"); + usb_debug("| Current QTD [0x%08lx] |\n", cur->current_td_ptr); + + if (!((cur->horiz_link_ptr == 0) && (cur->epchar == 0))) { + /* Dump overlay QTD for this QH */ + usb_debug("+---------------------------------------------------+\n"); + usb_debug("|::::::::::::::::::: QTD OVERLAY :::::::::::::::::::|\n"); + dump_td(virt_to_phys((void *)&(cur->td))); + /* Dump all TD tree for this QH */ + tmp_qtd = (qtd_t *)phys_to_virt((cur->td.next_qtd & ~0x1FUL)); + if (tmp_qtd != NULL) + usb_debug("|:::::::::::::::::: EHCI QTD CHAIN :::::::::::::::::|\n"); + while (tmp_qtd != NULL) + { + dump_td(virt_to_phys(tmp_qtd)); + tmp_qtd = (qtd_t *)phys_to_virt((tmp_qtd->next_qtd & ~0x1FUL)); + } + usb_debug("|:::::::::::::::: EOF EHCI QTD CHAIN :::::::::::::::|\n"); + usb_debug("+---------------------------------------------------+\n"); + } else { + usb_debug("+---------------------------------------------------+\n"); + } } static void ehci_start (hci_t *controller)

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Re: [coreboot] how to use TianoCore as a coreboot payload
by Philip Schulz 15 Jan '13

15 Jan '13

Hi, I'm not subscribed, so please cc: me if you want me to see your email. Peter Stuge wrote: > David Hendricks wrote: >> >> http://www.phisch.org/website/efiboot/ >> >> Perhaps you can contact the author? His e-mail address is at the >> very bottom of the efiboot website. > > This has been attempted by several people already, and as far as I > know noone has even received a reply. > It's true that a few people have contacted me and asked for source code. I think everyone has received a reply, although the reply may not have been what the sender probably wanted it to be. I'd like to make a general comment about "efiboot": You need to realize that this is really a very, very thin layer of code. The only thing it does is to act as a coreboot payload (through libpayload); build a minimal UEFI-compliant HOB list and pass it to the DXE core. To do that, you also need to load and start the DXE core from the Firmware Flash the TianoCore build process creates. I think anyone can do this and I believe the hardest part about this is understanding UEFI and TianoCore. The good thing about that part is that there is a lot of documentation plus I think you need to understand UEFI (and the TianoCore implementation) anyways -- if you're seriously going to use it. Please don't take this as an angry comment about people sending me emails. In fact, I'm always happy to hear from people interested in my projects. Also, I'm more than happy to help with questions, but please respect that I cannot release source code. Phil.

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Patch set updated for coreboot: a82e0eb libpayload: added EHCI QH/qTD debugging
by Anton Kochkov 15 Jan '13

15 Jan '13

Anton Kochkov (anton.kochkov(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2053 -gerrit commit a82e0ebca10b3a40df812af8a9db108178503814 Author: Anton Kochkov <anton.kochkov(a)gmail.com> Date: Wed Dec 19 12:32:32 2012 +0400 libpayload: added EHCI QH/qTD debugging Improved USB debugging for EHCI by adding dump_qh and enhacing dump_td to dump all queue chain and information Change-Id: Ia8ecf19c6dac085cf9558bdf659a5e74ce332714 Signed-off-by: Anton Kochkov <anton.kochkov(a)gmail.com> --- payloads/libpayload/drivers/usb/ehci.c | 80 ++++++++++++++++++++++++++++++++-- 1 file changed, 77 insertions(+), 3 deletions(-) diff --git a/payloads/libpayload/drivers/usb/ehci.c b/payloads/libpayload/drivers/usb/ehci.c index f27658d..3e57902 100644 --- a/payloads/libpayload/drivers/usb/ehci.c +++ b/payloads/libpayload/drivers/usb/ehci.c @@ -34,9 +34,83 @@ static void dump_td(u32 addr) { qtd_t *td = phys_to_virt(addr); - usb_debug("td at phys(%x): status: %x\n\n", addr, td->token & QTD_STATUS_MASK); - usb_debug("- cerr: %x, total_len: %x\n\n", (td->token & QTD_CERR_MASK) >> QTD_CERR_SHIFT, - (td->token & QTD_TOTAL_LEN_MASK) >> QTD_TOTAL_LEN_SHIFT); + usb_debug("+---------------------------------------------------+\n"); + if (((td->token & (3UL << 8)) >> 8) == 2) + usb_debug("|..[SETUP]..........................................|\n"); + else if (((td->token & (3UL << 8)) >> 8) == 1) + usb_debug("|..[IN].............................................|\n"); + else if (((td->token & (3UL << 8)) >> 8) == 0) + usb_debug("|..[OUT]............................................|\n"); + else + usb_debug("|..[]...............................................|\n"); + usb_debug("|:|============ EHCI TD at [0x%08lx] ==========|:|\n", addr); + usb_debug("|:| ERRORS = [%ld] | TOKEN = [0x%08lx] | |:|\n", + 3 - ((td->token & QTD_CERR_MASK) >> QTD_CERR_SHIFT), td->token); + usb_debug("|:+-----------------------------------------------+:|\n"); + usb_debug("|:| Next qTD [0x%08lx] |:|\n", td->next_qtd); + usb_debug("|:+-----------------------------------------------+:|\n"); + usb_debug("|:| Alt. Next qTD [0x%08lx] |:|\n", td->alt_next_qtd); + usb_debug("|:+-----------------------------------------------+:|\n"); + usb_debug("|:| | Bytes to Transfer | [%04ld] |:|\n", (td->token & (0x7FUL << 16)) >> 16); + usb_debug("|:| | PID CODE: | [%ld] |:|\n", (td->token & (3UL << 8)) >> 8); + usb_debug("|:| | Interrupt On Complete (IOC) | [%ld] |:|\n", (td->token & (1UL << 15)) >> 15); + usb_debug("|:| | Status Active | [%ld] |:|\n", (td->token & (1UL << 7)) >> 7); + usb_debug("|:| | Status Halted | [%ld] |:|\n", (td->token & (1UL << 6)) >> 6); + usb_debug("|:| TOKEN | Status Data Buffer Error | [%ld] |:|\n", (td->token & (1UL << 5)) >> 5); + usb_debug("|:| | Status Babble detected | [%ld] |:|\n", (td->token & (1UL << 4)) >> 4); + usb_debug("|:| | Status Transaction Error | [%ld] |:|\n", (td->token & (1UL << 3)) >> 3); + usb_debug("|:| | Status Missed Micro Frame | [%ld] |:|\n", (td->token & (1UL << 2)) >> 2); + usb_debug("|:| | Split Transaction State | [%ld] |:|\n", (td->token & (1UL << 1)) >> 1); + usb_debug("|:| | Ping State | [%ld] |:|\n", td->token & 1UL); + usb_debug("|:|-----------------------------------------------|:|\n"); + usb_debug("|...................................................|\n"); + usb_debug("+---------------------------------------------------+\n"); +} + +static void dump_qh(ehci_qh_t *cur) +{ + qtd_t *tmp_qtd = NULL; + usb_debug("+===================================================+\n"); + usb_debug("| ############# EHCI QH at [0x%08lx] ########### |\n", virt_to_phys(cur)); + usb_debug("+---------------------------------------------------+\n"); + usb_debug("| Horizonal Link Pointer [0x%08lx] |\n", cur->horiz_link_ptr); + usb_debug("+------------------[ 0x%08lx ]-------------------+\n", cur->epchar); + usb_debug("| | Maximum Packet Length | [%04ld] |\n", ((cur->epchar & (0x7ffUL << 16)) >> 16)); + usb_debug("| | Device Address | [%ld] |\n", cur->epchar & 0x7F); + usb_debug("| | Inactivate on Next Transaction | [%ld] |\n", ((cur->epchar & (1UL << 7)) >> 7)); + usb_debug("| | Endpoint Number | [%ld] |\n", ((cur->epchar & (0xFUL << 8)) >> 8)); + usb_debug("| EPCHAR | Endpoint Speed | [%ld] |\n", ((cur->epchar & (3UL << 12)) >> 12)); + usb_debug("| | Data Toggle Control | [%ld] |\n", ((cur->epchar & (1UL << 14)) >> 14)); + usb_debug("| | Head of Reclamation List Flag | [%ld] |\n", ((cur->epchar & (1UL << 15)) >> 15)); + usb_debug("| | Control Endpoint Flag | [%ld] |\n", ((cur->epchar & (1UL << 27)) >> 27)); + usb_debug("| | Nak Count Reload | [%ld] |\n", ((cur->epchar & (0xFUL << 28)) >> 28)); + if (((cur->epchar & (1UL << QH_NON_HS_CTRL_EP_SHIFT)) >> QH_NON_HS_CTRL_EP_SHIFT) == 1) { /* Split transaction */ + usb_debug("+--------+---------[ 0x%08lx ]----------+--------+\n", cur->epcaps); + usb_debug("| | Hub Port | [%ld] |\n", ((cur->epcaps & (0x7FUL << 23)) >> 23)); /* [29:23] */ + usb_debug("| | Hub Address | [%ld] |\n", ((cur->epcaps & (0x7FUL << 16)) >> 16)); /* [22:16] */ + } + usb_debug("+---------------------------------------------------+\n"); + usb_debug("| Current QTD [0x%08lx] |\n", cur->current_td_ptr); + + if (!((cur->horiz_link_ptr == 0) && (cur->epchar == 0))) { + /* Dump overlay QTD for this QH */ + usb_debug("+---------------------------------------------------+\n"); + usb_debug("|::::::::::::::::::: QTD OVERLAY :::::::::::::::::::|\n"); + dump_td(virt_to_phys((void *)&(cur->td))); + /* Dump all TD tree for this QH */ + tmp_qtd = (qtd_t *)phys_to_virt((cur->td.next_qtd & ~0x1FUL)); + if (tmp_qtd != NULL) + usb_debug("|:::::::::::::::::: EHCI QTD CHAIN :::::::::::::::::|\n"); + while (tmp_qtd != NULL) + { + dump_td(virt_to_phys(tmp_qtd)); + tmp_qtd = (qtd_t *)phys_to_virt((tmp_qtd->next_qtd & ~0x1FUL)); + } + usb_debug("|:::::::::::::::: EOF EHCI QTD CHAIN :::::::::::::::|\n"); + usb_debug("+---------------------------------------------------+\n"); + } else { + usb_debug("+---------------------------------------------------+\n"); + } } static void ehci_start (hci_t *controller)

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Patch merged into coreboot/master: 09e16dc libpayload: Style fixes
by gerrit＠coreboot.org 15 Jan '13

15 Jan '13

the following patch was just integrated into master: commit 09e16dc21597d20f215c822d63f8409271baacca Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Mon Jan 14 10:20:15 2013 -0800 libpayload: Style fixes Change-Id: Ic3164fbffd8da6bd9d506d80e425ad89efc0f1af Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-on: http://review.coreboot.org/2144 Tested-by: build bot (Jenkins) Reviewed-by: Dave Frodin <dave.frodin(a)se-eng.com> Reviewed-by: Martin Roth <martin.roth(a)se-eng.com> Reviewed-by: Anton Kochkov <anton.kochkov(a)gmail.com> Build-Tested: build bot (Jenkins) at Mon Jan 14 19:27:22 2013, giving +1 Reviewed-By: Anton Kochkov <anton.kochkov(a)gmail.com> at Tue Jan 15 09:29:30 2013, giving +2 See http://review.coreboot.org/2144 for details. -gerrit

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Patch set updated for coreboot: ac7f853 armv7: Place reset vector + CBFS header + bootblock dynamically
by David Hendricks 14 Jan '13

14 Jan '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2148 -gerrit commit ac7f853cebdb9d7574b4f4c05d644433d9123034 Author: David Hendricks <dhendrix(a)chromium.org> Date: Mon Jan 14 20:58:50 2013 -0800 armv7: Place reset vector + CBFS header + bootblock dynamically This replaces hard-coded bootblock offsets using the new scheme. The assembler will place the initial branch instruction after BL1, skip 2 aligned chunks, and place the remaining bootblock code after. It will also leave an anchor string, currently 0xdeadbeef which cbfstool will find. Once found, cbfstool will place the master CBFS header at the next aligned offset. Here is how it looks: 0x0000 |--------------| | BL1 | 0x2000 |--------------| | branch | 0x2000 + align |--------------| | CBFS header | 0x2000 + align * 2 |--------------| | bootblock | |--------------| TODO: The option for alignment passed into cbfstool has always been 64. Can we set it to 16 instead? Change-Id: Icbe817cbd8a37f11990aaf060aab77d2dc113cb1 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/arch/armv7/Makefile.inc | 3 +-- src/arch/armv7/bootblock.inc | 4 ++-- src/cpu/samsung/exynos5250/Kconfig | 9 --------- util/cbfstool/common.c | 37 +++++++++++++++++++++++-------------- 4 files changed, 26 insertions(+), 27 deletions(-) diff --git a/src/arch/armv7/Makefile.inc b/src/arch/armv7/Makefile.inc index b783ac6..cc30633 100644 --- a/src/arch/armv7/Makefile.inc +++ b/src/arch/armv7/Makefile.inc @@ -48,8 +48,7 @@ prebuilt-files = $(foreach file,$(cbfs-files), $(call extract_nth,1,$(file))) $(obj)/coreboot.pre1: $(objcbfs)/bootblock.bin $$(prebuilt-files) $(CBFSTOOL) $(CBFSTOOL) $@.tmp create -m armv7 -s $(CONFIG_COREBOOT_ROMSIZE_KB)K \ - -B $(objcbfs)/bootblock.bin -a 64 \ - -o $(CONFIG_BOOTBLOCK_OFFSET) + -B $(objcbfs)/bootblock.bin -a 64 $(prebuild-files) true mv $@.tmp $@ else diff --git a/src/arch/armv7/bootblock.inc b/src/arch/armv7/bootblock.inc index 90850d6..461b6c6 100644 --- a/src/arch/armv7/bootblock.inc +++ b/src/arch/armv7/bootblock.inc @@ -43,11 +43,11 @@ _start: b reset .balignl 16,0xdeadbeef _cbfs_master_header: - /* The CBFS master header is inserted here by cbfstool + /* The CBFS master header is inserted at the first aligned * when coreboot.rom is being created. Hence, we leave * some space for it. */ - .skip 64 + .skip 128 @ Assumes 64-byte alignment reset: /* diff --git a/src/cpu/samsung/exynos5250/Kconfig b/src/cpu/samsung/exynos5250/Kconfig index cd20153..3d66c77 100644 --- a/src/cpu/samsung/exynos5250/Kconfig +++ b/src/cpu/samsung/exynos5250/Kconfig @@ -1,12 +1,3 @@ -# FIXME: shouldn't this be 0x3400? Or maybe the bootblock in ROM needs -# to follow the BL1 image, but in SRAM it needs to be at 0x3400? Hm... -config BOOTBLOCK_OFFSET - hex "Bootblock offset" - default 0x2000 - help - This is where the Coreboot bootblock resides. For Exynos5250, - this value is pre-determined by the vendor-provided BL1. - config BOOTBLOCK_CPU_INIT string default "cpu/samsung/exynos5250/bootblock.c" diff --git a/util/cbfstool/common.c b/util/cbfstool/common.c index 195cda1..5413958 100644 --- a/util/cbfstool/common.c +++ b/util/cbfstool/common.c @@ -565,23 +565,32 @@ int create_cbfs_image(const char *romfile, uint32_t _romsize, /* Set up physical/virtual mapping */ offset = romarea; - // should be aligned to align - uint32_t *arm_vec = (uint32_t *)(romarea + offs); - master_header = (struct cbfs_header *)(romarea + offs + 0x20); - loadfile(bootblock, &bootblocksize, romarea + offs + 0x20 + - sizeof(struct cbfs_header), SEEK_SET); - /* - * Encoding for this branch instruction is: - * 31:28 - condition (0xe for always/unconditional) - * 27:24 - Branch (0xa, encoding A1) - * 23: 0 - sign-extended offset (in multiples of 4) + * The initial jump instruction and bootblock will be placed + * before and after the master header, respectively. The + * bootblock image must contain a blank, aligned region large + * enough for the master header to fit. * - * When executing the branch, the PC will read as the address - * of current instruction + 8. + * An anchor string must be left such that when cbfstool is run + * we can find it and insert the master header at the next + * aligned boundary. */ - uint32_t imm = ((0x20 + sizeof(struct cbfs_header)) - 8) / 4; - arm_vec[0] = imm | (0xa << 24) | (0xe << 28); + loadfile(bootblock, &bootblocksize, romarea + offs, SEEK_SET); + + unsigned char *p = romarea + offs; + while (1) { + /* FIXME: assumes little endian... */ + if (*(uint32_t *)p == 0xdeadbeef) + break; + if (p >= (romarea + _romsize)) { + fprintf(stderr, "E: Could not determine CBFS " + "header location.\n", bootblock); + return 1; + } + p += (sizeof(unsigned int)); + } + unsigned int u = ALIGN((unsigned int)(p - romarea), align); + master_header = (struct cbfs_header *)(romarea + u); master_header->magic = ntohl(CBFS_HEADER_MAGIC); master_header->version = ntohl(CBFS_HEADER_VERSION);

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New patch to review for coreboot: 7e96950 armv7: Place reset vector + CBFS header + bootblock dynamically
by David Hendricks 14 Jan '13

14 Jan '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2148 -gerrit commit 7e969509ff6ba95f8c30d03c178558078da901f8 Author: David Hendricks <dhendrix(a)chromium.org> Date: Mon Jan 14 20:58:50 2013 -0800 armv7: Place reset vector + CBFS header + bootblock dynamically This replaces hard-coded bootblock offsets using the new scheme. The assembler will place the initial branch instruction after BL1, skip 2 aligned chunks, and place the remaining bootblock code after. It will also leave an anchor string, currently 0xdeadbeef which cbfstool will find. Once found, cbfstool will place the master CBFS header at the next aligned offset. Here is how it looks: 0x0000 |--------------| | BL1 | 0x2000 |--------------| | branch | 0x2000 + align |--------------| | CBFS header | 0x2000 + align * 2 |--------------| | bootblock | |--------------| TODO: The option for alignment passed into cbfstool has always been 64. Can we set it to 16 instead? Change-Id: Icbe817cbd8a37f11990aaf060aab77d2dc113cb1 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/arch/armv7/Makefile.inc | 3 +-- src/arch/armv7/bootblock.inc | 4 ++-- src/cpu/samsung/exynos5250/Kconfig | 9 --------- util/cbfstool/common.c | 37 +++++++++++++++++++++++-------------- 4 files changed, 26 insertions(+), 27 deletions(-) diff --git a/src/arch/armv7/Makefile.inc b/src/arch/armv7/Makefile.inc index b783ac6..cc30633 100644 --- a/src/arch/armv7/Makefile.inc +++ b/src/arch/armv7/Makefile.inc @@ -48,8 +48,7 @@ prebuilt-files = $(foreach file,$(cbfs-files), $(call extract_nth,1,$(file))) $(obj)/coreboot.pre1: $(objcbfs)/bootblock.bin $$(prebuilt-files) $(CBFSTOOL) $(CBFSTOOL) $@.tmp create -m armv7 -s $(CONFIG_COREBOOT_ROMSIZE_KB)K \ - -B $(objcbfs)/bootblock.bin -a 64 \ - -o $(CONFIG_BOOTBLOCK_OFFSET) + -B $(objcbfs)/bootblock.bin -a 64 $(prebuild-files) true mv $@.tmp $@ else diff --git a/src/arch/armv7/bootblock.inc b/src/arch/armv7/bootblock.inc index 90850d6..461b6c6 100644 --- a/src/arch/armv7/bootblock.inc +++ b/src/arch/armv7/bootblock.inc @@ -43,11 +43,11 @@ _start: b reset .balignl 16,0xdeadbeef _cbfs_master_header: - /* The CBFS master header is inserted here by cbfstool + /* The CBFS master header is inserted at the first aligned * when coreboot.rom is being created. Hence, we leave * some space for it. */ - .skip 64 + .skip 128 @ Assumes 64-byte alignment reset: /* diff --git a/src/cpu/samsung/exynos5250/Kconfig b/src/cpu/samsung/exynos5250/Kconfig index cd20153..3d66c77 100644 --- a/src/cpu/samsung/exynos5250/Kconfig +++ b/src/cpu/samsung/exynos5250/Kconfig @@ -1,12 +1,3 @@ -# FIXME: shouldn't this be 0x3400? Or maybe the bootblock in ROM needs -# to follow the BL1 image, but in SRAM it needs to be at 0x3400? Hm... -config BOOTBLOCK_OFFSET - hex "Bootblock offset" - default 0x2000 - help - This is where the Coreboot bootblock resides. For Exynos5250, - this value is pre-determined by the vendor-provided BL1. - config BOOTBLOCK_CPU_INIT string default "cpu/samsung/exynos5250/bootblock.c" diff --git a/util/cbfstool/common.c b/util/cbfstool/common.c index 195cda1..448b273 100644 --- a/util/cbfstool/common.c +++ b/util/cbfstool/common.c @@ -565,23 +565,32 @@ int create_cbfs_image(const char *romfile, uint32_t _romsize, /* Set up physical/virtual mapping */ offset = romarea; - // should be aligned to align - uint32_t *arm_vec = (uint32_t *)(romarea + offs); - master_header = (struct cbfs_header *)(romarea + offs + 0x20); - loadfile(bootblock, &bootblocksize, romarea + offs + 0x20 + - sizeof(struct cbfs_header), SEEK_SET); - /* - * Encoding for this branch instruction is: - * 31:28 - condition (0xe for always/unconditional) - * 27:24 - Branch (0xa, encoding A1) - * 23: 0 - sign-extended offset (in multiples of 4) + * The initial jump instruction and bootblock will be placed + * before and after the master header, respectively. The + * bootblock image must contain a blank, aligned region large + * enough for the master header to fit. * - * When executing the branch, the PC will read as the address - * of current instruction + 8. + * An anchor string must be left such that when cbfstool is run + * we can find it and insert the master header at the next + * aligned boundary. */ - uint32_t imm = ((0x20 + sizeof(struct cbfs_header)) - 8) / 4; - arm_vec[0] = imm | (0xa << 24) | (0xe << 28); + loadfile(bootblock, &bootblocksize, romarea + offs, SEEK_SET); + + unsigned char *p = romarea + offs; + while (1) { + /* FIXME: assumes little endian... */ + if (*(uint32_t *)p == 0xdeadbeef) + break; + if (p >= (romarea + _romsize)) { + fprintf(stderr, "E: Could not determine CBFS header " + "location.\n", bootblock); + return 1; + } + p += (sizeof(unsigned int)); + } + unsigned int u = (unsigned int)(p - romarea); + master_header = (struct cbfs_header *)(romarea + ALIGN(u, align)); master_header->magic = ntohl(CBFS_HEADER_MAGIC); master_header->version = ntohl(CBFS_HEADER_VERSION);

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coreboot January 2013