coreboot January 2013

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Patch set updated for coreboot: 1a01576 Update gcov patch in documentation
by Stefan Reinauer 17 Jan '13

17 Jan '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2158 -gerrit commit 1a015769b1ddc02d7dcf85d602657a6fbc5a8668 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Wed Jan 16 09:47:54 2013 -0800 Update gcov patch in documentation .. to reflect the recent changes w.r.t avoiding trouble with the coreboot pre-commit hooks. and fix two whitespace errors. Change-Id: I6c94e95dd439940cf3b44231c8aab5126e9d45c7 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- documentation/gcov.txt | 54 ++++++++++++++++++++++++++++++++++++++++++++++++-- src/lib/libgcov.c | 4 ++-- 2 files changed, 54 insertions(+), 4 deletions(-) diff --git a/documentation/gcov.txt b/documentation/gcov.txt index 795f827..896ec93 100644 --- a/documentation/gcov.txt +++ b/documentation/gcov.txt @@ -3,7 +3,7 @@ The file gcov-iov.h is taken from a gcc build (produced at compile time). The file gcov-io.c is unchanged. --- gcc-4.7.2/gcc/gcov-io.h 2011-12-04 10:27:19.000000000 -0800 -+++ coreboot/src/lib/gcov-io.h 2013-01-09 15:29:19.000000000 -0800 ++++ coreboot/src/lib/gcov-io.h 2013-01-12 16:45:57.000000000 -0800 @@ -163,6 +163,24 @@ #ifndef GCC_GCOV_IO_H #define GCC_GCOV_IO_H @@ -51,7 +51,7 @@ time). The file gcov-io.c is unchanged. /* The merge function that just sums the counters. */ extern void __gcov_merge_add (gcov_type *, unsigned) ATTRIBUTE_HIDDEN; --- gcc-4.7.2/libgcc/libgcov.c 2012-01-11 10:50:21.000000000 -0800 -+++ coreboot/src/lib/libgcov.c 2013-01-09 15:32:37.000000000 -0800 ++++ coreboot/src/lib/libgcov.c 2013-01-16 09:45:11.000000000 -0800 @@ -25,12 +25,41 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see <http://www.gnu.org/licenses/>. */ @@ -175,3 +175,53 @@ time). The file gcov-io.c is unchanged. info->next = gcov_list; gcov_list = info; +@@ -767,14 +811,15 @@ + + #ifdef L_gcov_merge_single + /* The profile merging function for choosing the most common value. +- It is given an array COUNTERS of N_COUNTERS old counters and it +- reads the same number of counters from the gcov file. The counters +- are split into 3-tuples where the members of the tuple have +- meanings: +- +- -- the stored candidate on the most common value of the measured entity +- -- counter +- -- total number of evaluations of the value */ ++ * It is given an array COUNTERS of N_COUNTERS old counters and it ++ * reads the same number of counters from the gcov file. The counters ++ * are split into 3-tuples where the members of the tuple have ++ * meanings: ++ * ++ * -- the stored candidate on the most common value of the measured entity ++ * -- counter ++ * -- total number of evaluations of the value ++ */ + void + __gcov_merge_single (gcov_type *counters, unsigned n_counters) + { +@@ -805,15 +850,16 @@ + + #ifdef L_gcov_merge_delta + /* The profile merging function for choosing the most common +- difference between two consecutive evaluations of the value. It is +- given an array COUNTERS of N_COUNTERS old counters and it reads the +- same number of counters from the gcov file. The counters are split +- into 4-tuples where the members of the tuple have meanings: +- +- -- the last value of the measured entity +- -- the stored candidate on the most common difference +- -- counter +- -- total number of evaluations of the value */ ++ * difference between two consecutive evaluations of the value. It is ++ * given an array COUNTERS of N_COUNTERS old counters and it reads the ++ * same number of counters from the gcov file. The counters are split ++ * into 4-tuples where the members of the tuple have meanings: ++ * ++ * -- the last value of the measured entity ++ * -- the stored candidate on the most common difference ++ * -- counter ++ * -- total number of evaluations of the value ++ */ + void + __gcov_merge_delta (gcov_type *counters, unsigned n_counters) + { diff --git a/src/lib/libgcov.c b/src/lib/libgcov.c index 6107407..47a427f 100644 --- a/src/lib/libgcov.c +++ b/src/lib/libgcov.c @@ -818,7 +818,7 @@ __gcov_merge_ior (gcov_type *counters, unsigned n_counters) * * -- the stored candidate on the most common value of the measured entity * -- counter - * -- total number of evaluations of the value + * -- total number of evaluations of the value */ void __gcov_merge_single (gcov_type *counters, unsigned n_counters) @@ -858,7 +858,7 @@ __gcov_merge_single (gcov_type *counters, unsigned n_counters) * -- the last value of the measured entity * -- the stored candidate on the most common difference * -- counter - * -- total number of evaluations of the value + * -- total number of evaluations of the value */ void __gcov_merge_delta (gcov_type *counters, unsigned n_counters)

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Patch merged into coreboot/master: 018724e remove argument in snow's romstage main()
by gerrit＠coreboot.org 17 Jan '13

17 Jan '13

the following patch was just integrated into master: commit 018724ec1b102435afc7a6374e49e30091f4a2a8 Author: David Hendricks <dhendrix(a)chromium.org> Date: Wed Jan 16 14:58:48 2013 -0800 remove argument in snow's romstage main() We don't pass any arguments into romstage on ARM. Change-Id: I018f28a57fc486c9240345cf0f4043b79027d864 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Reviewed-on: http://review.coreboot.org/2162 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Build-Tested: build bot (Jenkins) at Thu Jan 17 00:31:40 2013, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Thu Jan 17 01:53:33 2013, giving +2 See http://review.coreboot.org/2162 for details. -gerrit

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Patch merged into coreboot/master: 694719a bootblock_cpu_init() stub for exynos5250
by gerrit＠coreboot.org 17 Jan '13

17 Jan '13

the following patch was just integrated into master: commit 694719aff0a782782fd1c0a0d6635f7af1729ba1 Author: David Hendricks <dhendrix(a)chromium.org> Date: Fri Jan 11 11:34:06 2013 -0800 bootblock_cpu_init() stub for exynos5250 This adds a stub for bootblock_cpu_init() for exynos5250. It will eventually contain code to copy ROM content from SPI to SRAM. Change-Id: I26ee62a1e701013f38f76f200579faa680530860 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Reviewed-on: http://review.coreboot.org/2138 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Build-Tested: build bot (Jenkins) at Wed Jan 16 22:27:52 2013, giving +1 See http://review.coreboot.org/2138 for details. -gerrit

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Patch merged into coreboot/master: 0b23d47 armv7: Place reset vector + CBFS header + bootblock dynamically
by gerrit＠coreboot.org 17 Jan '13

17 Jan '13

the following patch was just integrated into master: commit 0b23d47ffd1c87cb41df9e3e1b73cdfddd425dcd Author: David Hendricks <dhendrix(a)chromium.org> Date: Mon Jan 14 20:58:50 2013 -0800 armv7: Place reset vector + CBFS header + bootblock dynamically This replaces hard-coded bootblock offsets using the new scheme. The assembler will place the initial branch instruction after BL1, skip 2 aligned chunks, and place the remaining bootblock code after. It will also leave an anchor string, currently 0xdeadbeef which cbfstool will find. Once found, cbfstool will place the master CBFS header at the next aligned offset. Here is how it looks: 0x0000 |--------------| | BL1 | 0x2000 |--------------| | branch | 0x2000 + align |--------------| | CBFS header | 0x2000 + align * 2 |--------------| | bootblock | |--------------| TODO: The option for alignment passed into cbfstool has always been 64. Can we set it to 16 instead? Change-Id: Icbe817cbd8a37f11990aaf060aab77d2dc113cb1 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Reviewed-on: http://review.coreboot.org/2148 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Build-Tested: build bot (Jenkins) at Wed Jan 16 22:14:38 2013, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Wed Jan 16 23:15:50 2013, giving +2 See http://review.coreboot.org/2148 for details. -gerrit

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Patch merged into coreboot/master: 3d7344a ARM bootblock approach
by gerrit＠coreboot.org 17 Jan '13

17 Jan '13

the following patch was just integrated into master: commit 3d7344a7a1fcf09406460da59b61baff564bbbd3 Author: David Hendricks <dhendrix(a)chromium.org> Date: Tue Jan 8 21:05:06 2013 -0800 ARM bootblock approach This lays out the groundwork for using a proper bootblock on ARM. Currently we bypass the bootblock entirely and go straight to romstage. However we want to utilize CBFS to maximize flexibility of placing code without relying on a lot of magic numbers which will break depending on the SoC in use. Change-Id: I9cc2a8191d2db38b27b6363ba673e5a360de9684 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Reviewed-on: http://review.coreboot.org/2118 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Build-Tested: build bot (Jenkins) at Wed Jan 16 23:32:06 2013, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Thu Jan 17 01:06:15 2013, giving +2 See http://review.coreboot.org/2118 for details. -gerrit

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New patch to review for coreboot: 52c2eb8 make main() in snow's romstage.c our romstage entry point
by David Hendricks 17 Jan '13

17 Jan '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2163 -gerrit commit 52c2eb8730c7a282aa861fa5622d6478c829e1ac Author: David Hendricks <dhendrix(a)chromium.org> Date: Wed Jan 16 15:00:07 2013 -0800 make main() in snow's romstage.c our romstage entry point Our earlier attempt was jumping straight from asm to the old u-boot board_init_f in lowlevel_init_c.c. We are getting ready to transition to using a real bootblock for ARM, so add romstage.c to the files compiled and we'll make main() our entry point. This also updates romstage.ld to place main() (*(.text.startup)) at the beginning of romstage. Change-Id: Ifc77a6bfba27d915c4cad62c6c8040665294628a Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/arch/armv7/Makefile.inc | 15 ++++++++------- src/arch/armv7/romstage.ld | 2 ++ src/mainboard/google/snow/Makefile.inc | 2 +- 3 files changed, 11 insertions(+), 8 deletions(-) diff --git a/src/arch/armv7/Makefile.inc b/src/arch/armv7/Makefile.inc index 4cb97a6..9d0b3b4 100644 --- a/src/arch/armv7/Makefile.inc +++ b/src/arch/armv7/Makefile.inc @@ -149,7 +149,7 @@ CFLAGS += \ # For various headers imported from Linux CFLAGS += -D__LINUX_ARM_ARCH__=7 -crt0s = $(src)/arch/armv7/bootblock.inc +#crt0s = $(src)/arch/armv7/bootblock.inc ldscripts = ldscripts += $(src)/arch/armv7/romstage.ld @@ -166,17 +166,18 @@ ifeq ($(CONFIG_LLSHELL),y) crt0s += $(src)/arch/armv7/llshell/llshell.inc endif -crt0s += $(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc +# FIXME: do we need romstage.inc? Maybe just get rid of this entirely. +#crt0s += $(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc $(obj)/mainboard/$(MAINBOARDDIR)/romstage.pre.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(OPTION_TABLE_H) $(obj)/build.h $(obj)/config.h @printf " CC romstage.inc\n" $(CC) -MMD $(CFLAGS) -D__PRE_RAM__ -I$(src) -I. -I$(obj) -c -S $< -o $@ -$(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(obj)/mainboard/$(MAINBOARDDIR)/romstage.pre.inc - @printf " POST romstage.inc\n" - sed -e 's/\.rodata/.rom.data/g' -e 's/\^\.text/.section .rom.text/g' \ - -e 's/\^\.section \.text/.section .rom.text/g' $^ > $@.tmp - mv $@.tmp $@ +#$(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(obj)/mainboard/$(MAINBOARDDIR)/romstage.pre.inc +# @printf " POST romstage.inc\n" +# sed -e 's/\.rodata/.rom.data/g' -e 's/\^\.text/.section .rom.text/g' \ +# -e 's/\^\.section \.text/.section .rom.text/g' $^ > $@.tmp +# mv $@.tmp $@ # Things that appear in every board romstage-srcs += $(objgenerated)/crt0.s diff --git a/src/arch/armv7/romstage.ld b/src/arch/armv7/romstage.ld index b63a78e..61e3479 100644 --- a/src/arch/armv7/romstage.ld +++ b/src/arch/armv7/romstage.ld @@ -43,6 +43,8 @@ SECTIONS .romtext . : { _rom = .; + _start = .; + *(.text.startup); *(.text); } diff --git a/src/mainboard/google/snow/Makefile.inc b/src/mainboard/google/snow/Makefile.inc index 01488d0..26378db 100644 --- a/src/mainboard/google/snow/Makefile.inc +++ b/src/mainboard/google/snow/Makefile.inc @@ -17,7 +17,7 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -#romstage-y += romstage.c +romstage-y += romstage.c # ramstage-y += ec.c

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New patch to review for coreboot: f0fcdda remove argument in snow's romstage main()
by David Hendricks 17 Jan '13

17 Jan '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2162 -gerrit commit f0fcddabb1f4036a193a99c3e772a0fb15467227 Author: David Hendricks <dhendrix(a)chromium.org> Date: Wed Jan 16 14:58:48 2013 -0800 remove argument in snow's romstage main() We don't pass any arguments into romstage on ARM. Change-Id: I018f28a57fc486c9240345cf0f4043b79027d864 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/mainboard/google/snow/romstage.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/google/snow/romstage.c b/src/mainboard/google/snow/romstage.c index 29e4555..9092b7c 100644 --- a/src/mainboard/google/snow/romstage.c +++ b/src/mainboard/google/snow/romstage.c @@ -26,7 +26,7 @@ static void mmu_setup(void) dram_bank_mmu_setup(CONFIG_SYS_SDRAM_BASE, CONFIG_DRAM_SIZE_MB * 1024); } -void main(unsigned long bist) +void main(void) { mmu_setup(); }

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Patch merged into coreboot/master: 09574d5 Fix high dword of MTRR mask set with CONFIG_CPU_ADDR_BITS
by gerrit＠coreboot.org 16 Jan '13

16 Jan '13

the following patch was just integrated into master: commit 09574d5c3c920d2959336a25064f9651df39e30e Author: Martin Roth <martin(a)se-eng.com> Date: Mon Jan 14 15:46:38 2013 -0700 Fix high dword of MTRR mask set with CONFIG_CPU_ADDR_BITS Bits were being shifted off the end of the mask accidentally. This results in all masks being 32 bits wide instead of 48. Change-Id: I5f4d1b6a323df1aa4568ff4491f82447b8a2f839 Signed-off-by: Martin Roth <martin.roth(a)se-eng.com> Reviewed-on: http://review.coreboot.org/2146 Tested-by: build bot (Jenkins) Reviewed-by: Zheng Bao <zheng.bao(a)amd.com> Reviewed-by: Marc Jones <marcj303(a)gmail.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Build-Tested: build bot (Jenkins) at Tue Jan 15 02:17:44 2013, giving +1 Reviewed-By: Marc Jones <marcj303(a)gmail.com> at Wed Jan 16 21:40:57 2013, giving +2 Reviewed-By: Zheng Bao <zheng.bao(a)amd.com> at Tue Jan 15 03:04:36 2013, giving +1 Reviewed-By: Paul Menzel <paulepanter(a)users.sourceforge.net> at Wed Jan 16 23:59:08 2013, giving +2 See http://review.coreboot.org/2146 for details. -gerrit

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Patch set updated for coreboot: 3666cd6 ARM bootblock approach
by David Hendricks 16 Jan '13

16 Jan '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2118 -gerrit commit 3666cd614cba7d078cf133e1163e766ccb95df39 Author: David Hendricks <dhendrix(a)chromium.org> Date: Tue Jan 8 21:05:06 2013 -0800 ARM bootblock approach This lays out the groundwork for using a proper bootblock on ARM. Currently we bypass the bootblock entirely and go straight to romstage. However we want to utilize CBFS to maximize flexibility of placing code without relying on a lot of magic numbers which will break depending on the SoC in use. Change-Id: I9cc2a8191d2db38b27b6363ba673e5a360de9684 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/arch/armv7/Makefile.inc | 24 ++++------- src/arch/armv7/bootblock.inc | 7 +-- src/arch/armv7/bootblock.lds | 49 +++++++++++++++++++++ src/arch/armv7/bootblock_simple.c | 34 +++++++-------- src/arch/armv7/include/arch/cbfs.h | 67 +++++++++++++++++++++++++++++ src/arch/armv7/include/bootblock_common.h | 71 ++++--------------------------- src/arch/armv7/lib/id.lds | 3 +- src/cpu/samsung/exynos5250/Kconfig | 7 --- 8 files changed, 152 insertions(+), 110 deletions(-) diff --git a/src/arch/armv7/Makefile.inc b/src/arch/armv7/Makefile.inc index 4cb97a6..a4f57f3 100644 --- a/src/arch/armv7/Makefile.inc +++ b/src/arch/armv7/Makefile.inc @@ -149,7 +149,6 @@ CFLAGS += \ # For various headers imported from Linux CFLAGS += -D__LINUX_ARM_ARCH__=7 -crt0s = $(src)/arch/armv7/bootblock.inc ldscripts = ldscripts += $(src)/arch/armv7/romstage.ld @@ -223,19 +222,14 @@ $(obj)/coreboot.pre: $(objcbfs)/romstage_xip.elf $(obj)/coreboot.pre1 $(CBFSTOOL ################################################################################ # Build the bootblock -#bootblock_lds = $(src)/arch/armv7/ldscript_fallback_cbfs.lb -bootblock_lds = $(src)/arch/armv7/lib/id.lds -#bootblock_lds = $(src)/arch/armv7/romstage.ld +bootblock_lds = $(src)/arch/armv7/bootblock.lds +bootblock_lds += $(src)/arch/armv7/lib/id.lds bootblock_lds += $(chipset_bootblock_lds) +bootblock_inc += $(src)/arch/armv7/bootblock.inc bootblock_inc += $(src)/arch/armv7/lib/id.inc bootblock_inc += $(chipset_bootblock_inc) - -# FIXME: CONFIG_NEON or something similar for ARM? -#ifeq ($(CONFIG_SSE),y) -#bootblock_inc += $(src)/cpu/x86/sse_enable.inc -#endif -#bootblock_inc += $(objgenerated)/bootblock.inc +bootblock_inc += $(objgenerated)/bootblock.inc $(objgenerated)/bootblock.ld: $$(bootblock_lds) $(obj)/ldoptions @printf " GEN $(subst $(obj)/,,$(@))\n" @@ -253,11 +247,11 @@ $(objgenerated)/bootblock.s: $(objgenerated)/bootblock_inc.S $(obj)/config.h $(o @printf " CC $(subst $(obj)/,,$(@))\n" $(CC) -MMD -x assembler-with-cpp -E -I$(src)/include -I$(src)/arch/armv7/include -I$(obj) -include $(obj)/build.h -include $(obj)/config.h -I. -I$(src) $< -o $@ -#$(objgenerated)/bootblock.inc: $(src)/arch/armv7/init/$(subst ",,$(CONFIG_BOOTBLOCK_SOURCE)) $(objutil)/romcc/romcc $(OPTION_TABLE_H) -# @printf " ROMCC $(subst $(obj)/,,$(@))\n" -# $(CC) $(INCLUDES) -MM -MT$(objgenerated)/bootblock.inc \ -# $< > $(objgenerated)/bootblock.inc.d -# $(ROMCC) -c -S $(bootblock_romccflags) $(ROMCCFLAGS) -I. $(INCLUDES) $< -o $@ +$(objgenerated)/bootblock.inc: $(src)/arch/armv7/$(subst ",,$(CONFIG_BOOTBLOCK_SOURCE)) $(OPTION_TABLE_H) + @printf " CC $(subst $(obj)/,,$(@))\n" + $(CC) $(INCLUDES) -MM -MT$(objgenerated)/bootblock.inc \ + $< > $(objgenerated)/bootblock.inc.d + $(CC) -c -S $(CFLAGS) -I. $(INCLUDES) $< -o $@ $(objcbfs)/bootblock.debug: $(objgenerated)/bootblock.o $(objgenerated)/bootblock.ld @printf " LINK $(subst $(obj)/,,$(@))\n" diff --git a/src/arch/armv7/bootblock.inc b/src/arch/armv7/bootblock.inc index f76391b..90850d6 100644 --- a/src/arch/armv7/bootblock.inc +++ b/src/arch/armv7/bootblock.inc @@ -36,8 +36,7 @@ _bl1: * on ARM, which is 8KB in size and it is prepended to the * reset vector */ - /* this comes a bit later. */ -// .skip 8192 + .skip 8192 .globl _start _start: b reset @@ -81,10 +80,6 @@ call_bootblock: * Thumb. However, "b" will not and GCC may attempt to create a * wrapper which is currently broken. */ - /* for now call board_init_f; change later. We're trying to get as much into ToT as - * we can - */ - bl board_init_f bl main wait_for_interrupt: diff --git a/src/arch/armv7/bootblock.lds b/src/arch/armv7/bootblock.lds new file mode 100644 index 0000000..90e37a0 --- /dev/null +++ b/src/arch/armv7/bootblock.lds @@ -0,0 +1,49 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2006 Advanced Micro Devices, Inc. + * Copyright (C) 2008-2010 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* We use ELF as output format. So that we can debug the code in some form. */ +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) + +TARGET(binary) +SECTIONS +{ + ROMLOC = 0x2023400 - 8192; + + /* This section might be better named .setup */ + .rom ROMLOC : { + _rom = .; + *(.text); + *(.text.*); + *(.rom.text); + *(.rom.data); + *(.rom.data.*); + *(.rodata.*); + _erom = .; + } = 0xff + + /DISCARD/ : { + *(.comment) + *(.note) + *(.comment.*) + *(.note.*) + *(.ARM.*) + } +} diff --git a/src/arch/armv7/bootblock_simple.c b/src/arch/armv7/bootblock_simple.c index f447a29..c10ee1f 100644 --- a/src/arch/armv7/bootblock_simple.c +++ b/src/arch/armv7/bootblock_simple.c @@ -19,33 +19,31 @@ * MA 02110-1301 USA */ - - #include <bootblock_common.h> +#include <arch/cbfs.h> +#include <arch/hlt.h> - -#include "../../lib/uart8250.c" -#include "lib/div.c" - -struct uart8250 uart = { - 115200 -}; +static int boot_cpu(void) +{ + /* + * FIXME: This is a stub for now. All non-boot CPUs should be + * waiting for an interrupt. We could move the chunk of assembly + * which puts them to sleep in here... + */ + return 1; +} void main(unsigned long bist) { - init_uart8250(CONFIG_TTYS0_BASE, &uart); - uart8250_tx_byte(CONFIG_TTYS0_BASE, '@'); + const char *target1 = "fallback/romstage"; + unsigned long entry; if (boot_cpu()) { - bootblock_cpu_init(); - bootblock_northbridge_init(); - bootblock_southbridge_init(); + bootblock_mainboard_init(); } - const char* target1 = "fallback/romstage"; - unsigned long entry; + entry = findstage(target1); - if (entry) call(entry, bist); + if (entry) call(entry); hlt(); } - diff --git a/src/arch/armv7/include/arch/cbfs.h b/src/arch/armv7/include/arch/cbfs.h new file mode 100644 index 0000000..0affa5e --- /dev/null +++ b/src/arch/armv7/include/arch/cbfs.h @@ -0,0 +1,67 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __INCLUDE_ARCH_CBFS__ +#define __INCLUDE_ARCH_CBFS__ + +#include <string.h> +#include <types.h> +#include <cbfs_core.h> +#include <arch/byteorder.h> +#include <arch/cbfs.h> + +static int cbfs_check_magic(struct cbfs_file *file) +{ + return !strcmp(file->magic, CBFS_FILE_MAGIC) ? 1 : 0; +} + +static unsigned long findstage(const char* target) +{ + unsigned long offset, align; + /* FIXME: magic offsets */ + struct cbfs_header *header = (struct cbfs_header *)(0x02023400 + 0x40); + // if (ntohl(header->magic) != CBFS_HEADER_MAGIC) + // printk(BIOS_ERR, "ERROR: No valid CBFS header found!\n"); + + offset = ntohl(header->offset); + align = ntohl(header->align); + while(1) { + struct cbfs_file *file; + file = (struct cbfs_file *)(offset + CONFIG_ROMSTAGE_BASE); + if (!cbfs_check_magic(file)) + return 0; + if (!strcmp(CBFS_NAME(file), target)) + return (unsigned long)CBFS_SUBHEADER(file); + int flen = ntohl(file->len); + int foffset = ntohl(file->offset); + unsigned long oldoffset = offset; + offset = ALIGN(offset + foffset + flen, align); + if (offset <= oldoffset) + return 0; + if (offset < CONFIG_ROMSTAGE_BASE + ntohl(header->romsize)); + return 0; + } +} + +static inline void call(unsigned long addr) +{ + void (*doit)(void) = (void *)addr; + doit(); +} +#endif diff --git a/src/arch/armv7/include/bootblock_common.h b/src/arch/armv7/include/bootblock_common.h index f5c7129..39af453 100644 --- a/src/arch/armv7/include/bootblock_common.h +++ b/src/arch/armv7/include/bootblock_common.h @@ -1,69 +1,14 @@ -#include <types.h> -#include <cbfs.h> -#include <string.h> -#include <arch/byteorder.h> - - -#define boot_cpu(x) 1 - #ifdef CONFIG_BOOTBLOCK_CPU_INIT #include CONFIG_BOOTBLOCK_CPU_INIT -#else -static void bootblock_cpu_init(void) { } -#endif -#ifdef CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT -#include CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT -#else -static void bootblock_northbridge_init(void) { } #endif -#ifdef CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT -#include CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT -#else -static void bootblock_southbridge_init(void) { } -#endif - -static int cbfs_check_magic(struct cbfs_file *file) -{ - return !strcmp(file->magic, CBFS_FILE_MAGIC) ? 1 : 0; -} - -static unsigned long findstage(const char* target) -{ - unsigned long offset; - - void *ptr = (void *)*((unsigned long *) CBFS_HEADPTR_ADDR); - struct cbfs_header *header = (struct cbfs_header *) ptr; - // if (ntohl(header->magic) != CBFS_HEADER_MAGIC) - // printk(BIOS_ERR, "ERROR: No valid CBFS header found!\n"); - - offset = 0 - ntohl(header->romsize) + ntohl(header->offset); - int align = ntohl(header->align); - while(1) { - struct cbfs_file *file = (struct cbfs_file *) offset; - if (!cbfs_check_magic(file)) - return 0; - if (!strcmp(CBFS_NAME(file), target)) - return (unsigned long)CBFS_SUBHEADER(file); - int flen = ntohl(file->len); - int foffset = ntohl(file->offset); - unsigned long oldoffset = offset; - offset = ALIGN(offset + foffset + flen, align); - if (offset <= oldoffset) - return 0; - if (offset < 0xFFFFFFFF - ntohl(header->romsize)) - return 0; - } -} - - -static void call(unsigned long addr, unsigned long bist) -{ - asm volatile ("mov r0, %1\nbx %0\n" : : "r" (addr), "r" (bist)); -} -static void hlt(void) +#ifdef CONFIG_BOOTBLOCK_MAINBOARD_INIT +#include CONFIG_BOOTBLOCK_MAINBOARD_INIT +#else +static void bootblock_mainboard_init(void) { - /* is there such a thing as hlt on ARM? */ - // asm volatile ("1:\n\thlt\n\tjmp 1b\n\t"); - asm volatile ("1:\nb 1b\n\t"); +#ifdef CONFIG_BOOTBLOCK_CPU_INIT + bootblock_cpu_init(); +#endif } +#endif diff --git a/src/arch/armv7/lib/id.lds b/src/arch/armv7/lib/id.lds index 9e31ee6..f2b794a 100644 --- a/src/arch/armv7/lib/id.lds +++ b/src/arch/armv7/lib/id.lds @@ -1,5 +1,6 @@ SECTIONS { - . = (0x100000000 - CONFIG_ID_SECTION_OFFSET) - (__id_end - __id_start); + /* FIXME: determine a sensible location... */ + . = (0x2024000) - (__id_end - __id_start); .id (.): { *(.id) } diff --git a/src/cpu/samsung/exynos5250/Kconfig b/src/cpu/samsung/exynos5250/Kconfig index 360c57f..c2d9b9f 100644 --- a/src/cpu/samsung/exynos5250/Kconfig +++ b/src/cpu/samsung/exynos5250/Kconfig @@ -1,10 +1,3 @@ -config BOOTBLOCK_OFFSET - hex "Bootblock offset" - default 0x3400 - help - This is where the Coreboot bootblock resides. For Exynos5250, - this value is pre-determined by the vendor-provided BL1. - config EXYNOS_ACE_SHA bool default n

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Patch set updated for coreboot: cb979b4 bootblock_cpu_init() stub for exynos5250
by David Hendricks 16 Jan '13

16 Jan '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2138 -gerrit commit cb979b465a6b91ba51b5c380a7e9ae408299e76b Author: David Hendricks <dhendrix(a)chromium.org> Date: Fri Jan 11 11:34:06 2013 -0800 bootblock_cpu_init() stub for exynos5250 This adds a stub for bootblock_cpu_init() for exynos5250. It will eventually contain code to copy ROM content from SPI to SRAM. Change-Id: I26ee62a1e701013f38f76f200579faa680530860 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/cpu/samsung/exynos5250/Kconfig | 8 ++++++++ src/cpu/samsung/exynos5250/bootblock.c | 32 ++++++++++++++++++++++++++++++++ 2 files changed, 40 insertions(+) diff --git a/src/cpu/samsung/exynos5250/Kconfig b/src/cpu/samsung/exynos5250/Kconfig index c2d9b9f..3d66c77 100644 --- a/src/cpu/samsung/exynos5250/Kconfig +++ b/src/cpu/samsung/exynos5250/Kconfig @@ -1,3 +1,11 @@ +config BOOTBLOCK_CPU_INIT + string + default "cpu/samsung/exynos5250/bootblock.c" + help + CPU/SoC-specific bootblock code. This is useful if the + bootblock must load microcode or copy data from ROM before + searching for the bootblock. + config EXYNOS_ACE_SHA bool default n diff --git a/src/cpu/samsung/exynos5250/bootblock.c b/src/cpu/samsung/exynos5250/bootblock.c new file mode 100644 index 0000000..58d0919 --- /dev/null +++ b/src/cpu/samsung/exynos5250/bootblock.c @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 The Chromium OS Authors + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +void bootblock_cpu_init(void); +void bootblock_cpu_init(void) +{ + /* + * FIXME: this is a stub for now. It should eventually copy + * romstage data (and maybe more) from SPI to SRAM. + */ +#if 0 + volatile unsigned long *addr = (unsigned long *)0x1004330c; + *addr |= 0x100; + while (1) ; +#endif +}

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coreboot January 2013