coreboot January 2013

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Patch set updated for coreboot: 01f61be WIP: add UART support in bootblock for exynos5250
by David Hendricks 17 Jan '13

17 Jan '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2156 -gerrit commit 01f61beacd52b15d9dd7c7dcf69cf4c396b8a7f4 Author: David Hendricks <dhendrix(a)chromium.org> Date: Tue Jan 15 21:37:52 2013 -0800 WIP: add UART support in bootblock for exynos5250 ** do not submit ** This is a very rough hack to get basic UART support in the bootblock for exynos5250. It is basically just a bunch of copy+pasted portions from other portions of the code. A few magic offsets had to be adjusted too, or so I thought... Change-Id: I4aae023ebf9335fac88bcb5ae49cb99c15f6c29e Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/mainboard/google/snow/bootblock.c | 39 +++++++++++++---------------------- 1 file changed, 14 insertions(+), 25 deletions(-) diff --git a/src/mainboard/google/snow/bootblock.c b/src/mainboard/google/snow/bootblock.c index 6716d05..3a600d7 100644 --- a/src/mainboard/google/snow/bootblock.c +++ b/src/mainboard/google/snow/bootblock.c @@ -732,7 +732,7 @@ static void exynos5_uart_tx_byte(unsigned char data) writeb(data, &uart->utxh); } -extern void puts(const char *s); +void puts(const char *s); void puts(const char *s) { int n = 0; @@ -1852,6 +1852,13 @@ static void clock_init(void) #define is_digit isdigit #define isxdigit(c) (((c) >= '0' && (c) <= '9') || ((c) >= 'a' && (c) <= 'f') || ((c) >= 'A' && (c) <= 'F')) +void __div0 (void); +void __div0 (void) +{ + puts("divide by zero detected"); + while(1) ; +} + static int skip_atoi(const char **s) { int i=0; @@ -1870,8 +1877,6 @@ static int number(void (*tx_byte)(unsigned char byte), int i; int count = 0; - puts("number: entered"); - puts("number: checkpoint 1"); if (type & LARGE) digits = "0123456789ABCDEFGHIJKLMNOPQRSTUVWXYZ"; if (type & LEFT) @@ -1880,7 +1885,6 @@ static int number(void (*tx_byte)(unsigned char byte), return 0; c = (type & ZEROPAD) ? '0' : ' '; sign = 0; - puts("number: checkpoint 2"); if (type & SIGN) { if ((signed long long)num < 0) { sign = '-'; @@ -1894,7 +1898,6 @@ static int number(void (*tx_byte)(unsigned char byte), size--; } } - puts("number: checkpoint 3"); if (type & SPECIAL) { if (base == 16) size -= 2; @@ -1902,20 +1905,17 @@ static int number(void (*tx_byte)(unsigned char byte), size--; } i = 0; - puts("number: checkpoint 4"); if (num == 0) { - puts("number: checkpoint 4a"); tmp[i++]='0'; - puts("number: checkpoint 4b"); } else while (num != 0) { - puts("number: checkpoint 4c"); - tmp[i++] = digits[do_div(num,base)]; - puts("number: checkpoint 4d"); + /* FIXME: do_div was broken */ +// tmp[i++] = digits[do_div(num,base)]; + tmp[i++] = digits[num & 0xf]; + num = num >> 4; } if (i > precision) precision = i; size -= precision; - puts("number: checkpoint 5"); if (!(type&(ZEROPAD+LEFT))) while(size-->0) tx_byte(' '), count++; @@ -1938,7 +1938,6 @@ static int number(void (*tx_byte)(unsigned char byte), tx_byte(tmp[i]), count++; while (size-- > 0) tx_byte(' '), count++; - puts("number: returning"); return count; } @@ -1990,7 +1989,6 @@ repeat: } } - puts("vtxprintf: checkpoint 1\n"); /* get the precision */ precision = -1; if (*fmt == '.') { @@ -2020,7 +2018,6 @@ repeat: /* default base */ base = 10; - puts("vtxprintf: checkpoint 2\n"); switch (*fmt) { case 'c': if (!(flags & LEFT)) @@ -2070,7 +2067,6 @@ repeat: } continue; - puts("vtxprintf: checkpoint 3\n"); case '%': tx_byte('%'), count++; continue; @@ -2100,7 +2096,6 @@ repeat: --fmt; continue; } - puts("vtxprintf: checkpoint 4\n"); if (qualifier == 'L') { num = va_arg(args, unsigned long long); } else if (qualifier == 'l') { @@ -2116,9 +2111,7 @@ repeat: } else { num = va_arg(args, unsigned int); } - puts("vtxprintf: checkpoint 5\n"); count += number(tx_byte, num, base, field_width, precision, flags); - puts("vtxprintf: checkpoint 6\n"); } return count; } @@ -2138,18 +2131,14 @@ int do_printk(int msg_level, const char *fmt, ...) void bootblock_mainboard_init(void); void bootblock_mainboard_init(void) { -// uint32_t test = 0xdeadbeef; /* FIXME: we should not need UART in bootblock, this is only done for testing purposes */ i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); power_init(); clock_init(); do_serial(); - puts("checkpoint 1"); - printk(BIOS_INFO, "%x\n", test); - /* FIXME: printk doens't work with numbers due to division issues... */ -// printk(BIOS_INFO, "%d\n", 0xdeadbeef); - puts("checkpoint 2"); +// printk(BIOS_INFO, "num: %x\n", 0xdeadbeef); +// printk(BIOS_INFO, "pointer: %p\n", (void *)0xdeadbeef); /* Copy romstage data from SPI ROM to SRAM */ /* FIXME: test with something benign, then fix the offsets once

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Patch set updated for coreboot: 8d0f41a Utility to run the snow bios in user mode
by Ronald G. Minnich 17 Jan '13

17 Jan '13

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2159 -gerrit commit 8d0f41a754da02824d861639ad91b74c90723d48 Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Wed Jan 16 11:59:34 2013 -0600 Utility to run the snow bios in user mode This program lets you test run a snow coreboot image in user mode on a properly equipped arm system (usually an ARM chromebook). This is a real time saver as you don't have to flash each time. We've found and fixed some nasty bugs with this one. Anyway, the instructions on how to use this are in the binary. Change-Id: Ib555ef51fd7e930905a2ee5cbfda1cc6f068278e Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- util/runfw/Makefile | 23 ++++++++ util/runfw/googlesnow.c | 137 ++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 160 insertions(+) diff --git a/util/runfw/Makefile b/util/runfw/Makefile new file mode 100644 index 0000000..cd5a1f7 --- /dev/null +++ b/util/runfw/Makefile @@ -0,0 +1,23 @@ +# +# runfw -- run firmware in user mode. +# +# Copyright (C) 2013 The ChromiumOS Authors. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA +# + +all: googlesnow + +googlesnow: googlesnow.c + cc -g -o googlesnow googlesnow.c diff --git a/util/runfw/googlesnow.c b/util/runfw/googlesnow.c new file mode 100644 index 0000000..25ef3a2 --- /dev/null +++ b/util/runfw/googlesnow.c @@ -0,0 +1,137 @@ +/* + * googlesnow - run google snow firmware in user mode + * + * Copyright (C) 2013 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA + */ + +#include <stdio.h> +#include <err.h> +#include <sys/mman.h> + +#include <string.h> + +enum addresses { + regs = 0x10000000, + sram = 0x2020000, + sramsize = 0x77fff, +}; + +// 0x20234b0 +main(int argc, char *argv[]) +{ + int fd; + int devmem; + void *regbase; + void *srambase; + void (*coreboot)(void) = (void *)0x2023400; + + if (argc != 3) + errx(1, "usage: runbios rom-file start-address"); + + fd = open(argv[1], 2); + if (fd < 0) + err(1, argv[1]); + devmem = open("/dev/mem", 2); + if (devmem < 0) + err(1, argv[1]); + srambase = mmap((void *)sram, sramsize, PROT_EXEC|PROT_READ|PROT_WRITE, MAP_ANONYMOUS|MAP_PRIVATE, -1, 0); + if (-1 == (int)sram) + err(1, "mmap"); + memset((void *)sram, 0xff, sramsize); + + /* now sort of do what bl1 does: read the 'rom' into the sram */ + /* skip the bl1. We don't run it. */ + if (pread(fd, coreboot, 30*1024, 0x2000) < 30*1024) + err(1, "read 'rom'"); + /* you want to be in gdb at this point. */ + coreboot = (void *) (strtoul(argv[2], 0, 0)); + coreboot(); +} +#if 0 +/* cc -g googlesnow.c */ +/* typical run +gdb a.out +(gdb) list 50 + +45 i2c = mmap((void *)0x12c60000, 0x10000, PROT_READ|PROT_WRITE, MAP_ANONYMOUS|MAP_PRIVATE, devmem, (off_t) 0x12c60000); +46 if (-1 == (int)i2c) +47 err(1, "mmap i2c"); +48 +49 /* now sort of do what bl1 does: read the 'rom' into the sram */ +50 if (pread(fd, coreboot, 30*1024, 0x2000) < 30*1024) +51 err(1, "read 'rom'"); +52 /* you want to be in gdb at this point. */ +53 coreboot = (void *) strtoull(argv[2], 0, 0); +54 coreboot(); +(gdb) br 54 +Breakpoint 3 at 0x8798: file runbios.c, line 54. +(gdb) run ~/coreboot/build/coreboot.rom 0x020234b0 +The program being debugged has been started already. +Start it from the beginning? (y or n) y + +Starting program: /root/coreboot/util/runarmbios/a.out ~/coreboot/build/coreboot.rom 0x020234b0 + +Breakpoint 3, main (argc=3, argv=0x7efff7c4) at runbios.c:54 +54 coreboot(); +(gdb) symbol-file ~/coreboot/build/cbfs/fallback/bootblock.debug +Load new symbol table from "/root/coreboot/build/cbfs/fallback/bootblock.debug"? (y or n) y +Reading symbols from /root/coreboot/build/cbfs/fallback/bootblock.debug...done. +Error in re-setting breakpoint 3: No source file named runbios.c. +(gdb) display/i $pc +1: x/i $pc +=> 0x8798: ldr r3, [r11, #-8] +(gdb) stepi +0x0000879c in ?? () +1: x/i $pc +=> 0x879c: blx r3 +(gdb) +0x020234b0 in call_bootblock () +1: x/i $pc +=> 0x20234b0 <call_bootblock>: ldr sp, [pc, #3800] ; 0x2024390 +(gdb) +0x020234b4 in call_bootblock () +1: x/i $pc +=> 0x20234b4 <call_bootblock+4>: bic sp, sp, #7 +(gdb) +0x020234b8 in call_bootblock () +1: x/i $pc +=> 0x20234b8 <call_bootblock+8>: mov r0, #0 +(gdb) +0x020234bc in call_bootblock () +1: x/i $pc +=> 0x20234bc <call_bootblock+12>: blx 0x20244b8 <main> +(gdb) +main (bist=0) at src/arch/armv7/bootblock_simple.c:37 +37 { +1: x/i $pc +=> 0x20244b8 <main>: push {r3, lr} +(gdb) +42 bootblock_mainboard_init(); +1: x/i $pc +=> 0x20244ba <main+2>: bl 0x2023c08 <bootblock_mainboard_init> +(gdb) +bootblock_mainboard_init () at src/mainboard/google/snow/bootblock.c:2124 +2124 { +1: x/i $pc +=> 0x2023c08 <bootblock_mainboard_init>: stmdb sp!, {r4, r5, r6, r7, r9, r10, r11, lr} +(gdb) +2127 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); +1: x/i $pc +=> 0x2023c0c <bootblock_mainboard_init+4>: movs r1, #0 + +Note you are now debugging source, and pretty much all commands work. +*/ +#endif

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Patch set updated for coreboot: d0c39ce F15tn: Modify devicetree to fix S3 resume
by Paul Menzel 17 Jan '13

17 Jan '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2160 -gerrit commit d0c39ce6c0868bf8e8dc9b11f78af5aefc3be81e Author: Martin Roth <martin(a)se-eng.com> Date: Thu Jan 10 12:41:40 2013 -0700 F15tn: Modify devicetree to fix S3 resume The way that devicetree.cb was configured for the family 15tn boards was doing... interesting things to the video device initialization. This was causing S3 resume to fail. There is a disconnect between how the devicetree should be configured if there are multiple HT links on the CPU and how it's configured if there's only one HT link. These platforms were set up as if they had multiple HT links, which was causing duplicate instances of devices in the device list. The scan for the IO Hub was removed from the northbridge code which isn't a problem for F15tn devices. Change-Id: I3556b43027746e36b07de7cb1bece4d1b37a3c34 Signed-off-by: Martin Roth <martin(a)se-eng.com> --- src/mainboard/amd/parmer/devicetree.cb | 4 +--- src/mainboard/amd/thatcher/devicetree.cb | 4 +--- src/northbridge/amd/agesa/family15tn/northbridge.c | 23 ---------------------- 3 files changed, 2 insertions(+), 29 deletions(-) diff --git a/src/mainboard/amd/parmer/devicetree.cb b/src/mainboard/amd/parmer/devicetree.cb index 4a59b51..32f5484 100644 --- a/src/mainboard/amd/parmer/devicetree.cb +++ b/src/mainboard/amd/parmer/devicetree.cb @@ -25,7 +25,6 @@ chip northbridge/amd/agesa/family15tn/root_complex device pci_domain 0 on subsystemid 0x1022 0x1410 inherit chip northbridge/amd/agesa/family15tn # CPU side of HT root complex - device pci 18.0 on # northbridge chip northbridge/amd/agesa/family15tn # PCI side of HT root complex device pci 0.0 on end # Root Complex device pci 1.0 on end # Internal Graphics P2P bridge 0x9804 @@ -38,7 +37,6 @@ chip northbridge/amd/agesa/family15tn/root_complex device pci 7.0 on end # LAN device pci 8.0 off end # NB/SB Link P2P bridge end - end chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus device pci 10.0 on end # XHCI HC0 device pci 10.1 on end # XHCI HC1 @@ -75,7 +73,7 @@ chip northbridge/amd/agesa/family15tn/root_complex register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE register "gpp_configuration" = "4" end #southbridge/amd/hudson -# device pci 18.0 on end + device pci 18.0 on end #device pci 18.0 on end device pci 18.1 on end device pci 18.2 on end diff --git a/src/mainboard/amd/thatcher/devicetree.cb b/src/mainboard/amd/thatcher/devicetree.cb index 2a91e1a..561a5b2 100644 --- a/src/mainboard/amd/thatcher/devicetree.cb +++ b/src/mainboard/amd/thatcher/devicetree.cb @@ -25,7 +25,6 @@ chip northbridge/amd/agesa/family15tn/root_complex device pci_domain 0 on subsystemid 0x1022 0x1410 inherit chip northbridge/amd/agesa/family15tn # CPU side of HT root complex - device pci 18.0 on # northbridge chip northbridge/amd/agesa/family15tn # PCI side of HT root complex device pci 0.0 on end # Root Complex device pci 1.0 on end # Internal Graphics P2P bridge 0x9804 @@ -38,7 +37,6 @@ chip northbridge/amd/agesa/family15tn/root_complex device pci 7.0 on end # LAN device pci 8.0 off end # NB/SB Link P2P bridge end - end chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus device pci 10.0 on end # XHCI HC0 device pci 10.1 on end # XHCI HC1 @@ -92,7 +90,7 @@ chip northbridge/amd/agesa/family15tn/root_complex register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE register "gpp_configuration" = "4" end #southbridge/amd/hudson -# device pci 18.0 on end + device pci 18.0 on end #device pci 18.0 on end device pci 18.1 on end device pci 18.2 on end diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index 9318164..df632e3 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -446,35 +446,12 @@ static void northbridge_init(struct device *dev) { } -static unsigned scan_chains(device_t dev, unsigned max) -{ - unsigned nodeid; - struct bus *link; - device_t io_hub = NULL; - u32 next_unitid = 0x18; - nodeid = amdfam15_nodeid(dev); - if (nodeid == 0) { - for (link = dev->link_list; link; link = link->next) { - //if (link->link_num == sblink) { /* devicetree put IO Hub on link_lsit[sblink] */ - if (link->link_num == 0) { /* devicetree put IO Hub on link_lsit[0] */ - io_hub = link->children; - if (!io_hub || !io_hub->enabled) { - die("I can't find the IO Hub, or IO Hub not enabled, please check the device tree.\n"); - } - /* Now that nothing is overlapping it is safe to scan the children. */ - max = pci_scan_bus(link, 0x00, ((next_unitid - 1) << 3) | 7, 0); - } - } - } - return max; -} static struct device_operations northbridge_operations = { .read_resources = read_resources, .set_resources = set_resources, .enable_resources = pci_dev_enable_resources, .init = northbridge_init, - .scan_bus = scan_chains, .enable = 0, .ops_pci = 0, };

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Patch set updated for coreboot: 768c6d1 F15tn: Modify devicetree to fix S3 resume
by Paul Menzel 17 Jan '13

17 Jan '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2160 -gerrit commit 768c6d18e8457ffa069c7f4538ccd6f4ac163f4c Author: Martin Roth <martin(a)se-eng.com> Date: Thu Jan 10 12:41:40 2013 -0700 F15tn: Modify devicetree to fix S3 resume The way that devicetree.cb was configured for the family 15tn boards was doing... interesting things to the video device initialization. This was causing S3 resume to fail. There is a disconnect between how the devicetree should be configured if there are multiple HT links on the CPU and how it's configured if there's only one HT link. These platforms were set up as if they had multiple HT links, which was causing duplicate instances of devices in the device list. The scan for the IO Hub was removed from the northbridge code which isn't a problem for f15tn devices. Change-Id: I3556b43027746e36b07de7cb1bece4d1b37a3c34 Signed-off-by: Martin Roth <martin(a)se-eng.com> --- src/mainboard/amd/parmer/devicetree.cb | 4 +--- src/mainboard/amd/thatcher/devicetree.cb | 4 +--- src/northbridge/amd/agesa/family15tn/northbridge.c | 23 ---------------------- 3 files changed, 2 insertions(+), 29 deletions(-) diff --git a/src/mainboard/amd/parmer/devicetree.cb b/src/mainboard/amd/parmer/devicetree.cb index 4a59b51..32f5484 100644 --- a/src/mainboard/amd/parmer/devicetree.cb +++ b/src/mainboard/amd/parmer/devicetree.cb @@ -25,7 +25,6 @@ chip northbridge/amd/agesa/family15tn/root_complex device pci_domain 0 on subsystemid 0x1022 0x1410 inherit chip northbridge/amd/agesa/family15tn # CPU side of HT root complex - device pci 18.0 on # northbridge chip northbridge/amd/agesa/family15tn # PCI side of HT root complex device pci 0.0 on end # Root Complex device pci 1.0 on end # Internal Graphics P2P bridge 0x9804 @@ -38,7 +37,6 @@ chip northbridge/amd/agesa/family15tn/root_complex device pci 7.0 on end # LAN device pci 8.0 off end # NB/SB Link P2P bridge end - end chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus device pci 10.0 on end # XHCI HC0 device pci 10.1 on end # XHCI HC1 @@ -75,7 +73,7 @@ chip northbridge/amd/agesa/family15tn/root_complex register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE register "gpp_configuration" = "4" end #southbridge/amd/hudson -# device pci 18.0 on end + device pci 18.0 on end #device pci 18.0 on end device pci 18.1 on end device pci 18.2 on end diff --git a/src/mainboard/amd/thatcher/devicetree.cb b/src/mainboard/amd/thatcher/devicetree.cb index 2a91e1a..561a5b2 100644 --- a/src/mainboard/amd/thatcher/devicetree.cb +++ b/src/mainboard/amd/thatcher/devicetree.cb @@ -25,7 +25,6 @@ chip northbridge/amd/agesa/family15tn/root_complex device pci_domain 0 on subsystemid 0x1022 0x1410 inherit chip northbridge/amd/agesa/family15tn # CPU side of HT root complex - device pci 18.0 on # northbridge chip northbridge/amd/agesa/family15tn # PCI side of HT root complex device pci 0.0 on end # Root Complex device pci 1.0 on end # Internal Graphics P2P bridge 0x9804 @@ -38,7 +37,6 @@ chip northbridge/amd/agesa/family15tn/root_complex device pci 7.0 on end # LAN device pci 8.0 off end # NB/SB Link P2P bridge end - end chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus device pci 10.0 on end # XHCI HC0 device pci 10.1 on end # XHCI HC1 @@ -92,7 +90,7 @@ chip northbridge/amd/agesa/family15tn/root_complex register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE register "gpp_configuration" = "4" end #southbridge/amd/hudson -# device pci 18.0 on end + device pci 18.0 on end #device pci 18.0 on end device pci 18.1 on end device pci 18.2 on end diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index 9318164..df632e3 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -446,35 +446,12 @@ static void northbridge_init(struct device *dev) { } -static unsigned scan_chains(device_t dev, unsigned max) -{ - unsigned nodeid; - struct bus *link; - device_t io_hub = NULL; - u32 next_unitid = 0x18; - nodeid = amdfam15_nodeid(dev); - if (nodeid == 0) { - for (link = dev->link_list; link; link = link->next) { - //if (link->link_num == sblink) { /* devicetree put IO Hub on link_lsit[sblink] */ - if (link->link_num == 0) { /* devicetree put IO Hub on link_lsit[0] */ - io_hub = link->children; - if (!io_hub || !io_hub->enabled) { - die("I can't find the IO Hub, or IO Hub not enabled, please check the device tree.\n"); - } - /* Now that nothing is overlapping it is safe to scan the children. */ - max = pci_scan_bus(link, 0x00, ((next_unitid - 1) << 3) | 7, 0); - } - } - } - return max; -} static struct device_operations northbridge_operations = { .read_resources = read_resources, .set_resources = set_resources, .enable_resources = pci_dev_enable_resources, .init = northbridge_init, - .scan_bus = scan_chains, .enable = 0, .ops_pci = 0, };

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Patch set updated for coreboot: 65bc4ed Hudson: Changes to agesa/hudson FADT for ACPI 3.0
by Paul Menzel 17 Jan '13

17 Jan '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2140 -gerrit commit 65bc4edb7b1f263e08b8486a168b211496856e53 Author: Martin Roth <martin(a)se-eng.com> Date: Thu Jan 10 16:40:59 2013 -0700 Hudson: Changes to agesa/hudson FADT for ACPI 3.0 Update the southbridge/amd/agesa/hudson FADT generation for ACPI 3.0 compliance similar to what was done for cimx/SB800/fadt.c in commit 9aa4389. commit 9aa43892e6899b719fe7f4754901a0eae379a934 Author: Martin Roth <martin(a)se-eng.com> Date: Fri May 25 12:23:32 2012 -0600 Update SB800 CIMX FADT According to the datasheet, PMA_CNT_BLK is no longer available and PM2_CNT_BLK should not be used. Setup for these has been removed from the table and .h file. Change-Id: Ied8eb1f26b4aa364d051ec5f7ed6f482bb440957 Signed-off-by: Martin Roth <martin(a)se-eng.com> --- src/southbridge/amd/agesa/hudson/fadt.c | 146 ++++++++++++++++++------------ src/southbridge/amd/agesa/hudson/hudson.h | 2 - 2 files changed, 88 insertions(+), 60 deletions(-) diff --git a/src/southbridge/amd/agesa/hudson/fadt.c b/src/southbridge/amd/agesa/hudson/fadt.c index ee0334c..27b5600 100644 --- a/src/southbridge/amd/agesa/hudson/fadt.c +++ b/src/southbridge/amd/agesa/hudson/fadt.c @@ -28,6 +28,16 @@ #include <device/device.h> #include "hudson.h" +#define FADT_BOOT_ARCH (ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042) + +#ifndef FADT_PM_PROFILE + #define FADT_PM_PROFILE PM_UNSPECIFIED +#endif + +/* + * Reference section 5.2.9 Fixed ACPI Description Table (FADT) + * in the ACPI 3.0b specification. + */ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) { acpi_header_t *header = &(fadt->header); @@ -37,24 +47,23 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) /* Prepare the header */ memset((void *)fadt, 0, sizeof(acpi_fadt_t)); memcpy(header->signature, "FACP", 4); - header->length = 244; - header->revision = 3; + header->length = sizeof(acpi_fadt_t); + header->revision = ACPI_FADT_REV_ACPI_3_0; memcpy(header->oem_id, OEM_ID, 6); - memcpy(header->oem_table_id, "COREBOOT", 8); + memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); memcpy(header->asl_compiler_id, ASLC, 4); header->asl_compiler_revision = 0; fadt->firmware_ctrl = (u32) facs; fadt->dsdt = (u32) dsdt; - /* 3=Workstation,4=Enterprise Server, 7=Performance Server */ - fadt->preferred_pm_profile = 0x03; - fadt->sci_int = 9; - /* disable system management mode by setting to 0: */ - fadt->smi_cmd = 0; - fadt->acpi_enable = 0xf0; - fadt->acpi_disable = 0xf1; - fadt->s4bios_req = 0x0; - fadt->pstate_cnt = 0xe2; + fadt->model = 0; /* reserved, should be 0 ACPI 3.0 */ + fadt->preferred_pm_profile = FADT_PM_PROFILE; + fadt->sci_int = 9; /* HUDSON - IRQ 09 – ACPI SCI */ + fadt->smi_cmd = 0; /* disable system management mode */ + fadt->acpi_enable = 0; /* unused if SMI_CMD = 0 */ + fadt->acpi_disable = 0; /* unused if SMI_CMD = 0 */ + fadt->s4bios_req = 0; /* unused if SMI_CMD = 0 */ + fadt->pstate_cnt = 0; /* unused if SMI_CMD = 0 */ pm_iowrite(0x60, ACPI_PM_EVT_BLK & 0xFF); pm_iowrite(0x61, ACPI_PM_EVT_BLK >> 8); @@ -72,9 +81,6 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) pm_iowrite(0x6A, 0); /* AcpiSmiCmdLo */ pm_iowrite(0x6B, 0); /* AcpiSmiCmdHi */ - pm_iowrite(0x6C, ACPI_PMA_CNT_BLK & 0xFF); - pm_iowrite(0x6D, ACPI_PMA_CNT_BLK >> 8); - pm_iowrite(0x74, 1<<0 | 1<<1 | 1<<4 | 1<<2); /* AcpiDecodeEnable, When set, SB uses * the contents of the PM registers at * index 60-6B to decode ACPI I/O address. @@ -85,100 +91,124 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) fadt->pm1b_evt_blk = 0x0000; fadt->pm1a_cnt_blk = ACPI_PM1_CNT_BLK; fadt->pm1b_cnt_blk = 0x0000; - fadt->pm2_cnt_blk = ACPI_PMA_CNT_BLK; + fadt->pm2_cnt_blk = 0x0000; fadt->pm_tmr_blk = ACPI_PM_TMR_BLK; fadt->gpe0_blk = ACPI_GPE0_BLK; - fadt->gpe1_blk = 0x0000; /* we dont have gpe1 block, do we? */ + fadt->gpe1_blk = 0x0000; /* No gpe1 block in hudson */ - fadt->pm1_evt_len = 4; - fadt->pm1_cnt_len = 2; - fadt->pm2_cnt_len = 1; - fadt->pm_tmr_len = 4; - fadt->gpe0_blk_len = 8; + fadt->pm1_evt_len = 4; /* 32 bits */ + fadt->pm1_cnt_len = 2; /* 16 bits */ + fadt->pm2_cnt_len = 0; + fadt->pm_tmr_len = 4; /* 32 bits */ + fadt->gpe0_blk_len = 8; /* 64 bits */ fadt->gpe1_blk_len = 0; fadt->gpe1_base = 0; - fadt->cst_cnt = 0xe3; - fadt->p_lvl2_lat = 101; - fadt->p_lvl3_lat = 1001; - fadt->flush_size = 0; - fadt->flush_stride = 0; - fadt->duty_offset = 1; - fadt->duty_width = 3; + fadt->cst_cnt = 0x00; /* unused if SMI_CMD = 0 */ + fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED; + fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; + fadt->flush_size = 0; /* set to 0 if WBINVD is 1 in flags */ + fadt->flush_stride = 0; /* set to 0 if WBINVD is 1 in flags */ + fadt->duty_offset = 1; /* CLK_VAL bits 3:1 */ + fadt->duty_width = 3; /* CLK_VAL bits 3:1 */ fadt->day_alrm = 0; /* 0x7d these have to be */ fadt->mon_alrm = 0; /* 0x7e added to cmos.layout */ - fadt->century = 0; /* 0x7f to make rtc alrm work */ - fadt->iapc_boot_arch = 0x3; /* See table 5-11 */ - fadt->flags = 0x0001c1a5 | 1 << 10;/* 0x25; */ - - fadt->res2 = 0; - - fadt->reset_reg.space_id = 1; + fadt->century = 0; /* 0x7f to make rtc alarm work */ + fadt->iapc_boot_arch = FADT_BOOT_ARCH; /* See table 5-10 */ + fadt->res2 = 0; /* reserved, MUST be 0 ACPI 3.0 */ + fadt->flags = ACPI_FADT_WBINVD | /* See table 5-10 ACPI 3.0a spec */ + ACPI_FADT_C1_SUPPORTED | + ACPI_FADT_SLEEP_BUTTON | + ACPI_FADT_S4_RTC_WAKE | + ACPI_FADT_32BIT_TIMER | + ACPI_FADT_RESET_REGISTER | + ACPI_FADT_PCI_EXPRESS_WAKE | + ACPI_FADT_PLATFORM_CLOCK | + ACPI_FADT_S4_RTC_VALID | + ACPI_FADT_REMOTE_POWER_ON; + + /* Format is from 5.2.3.1: Generic Address Structure */ + /* reset_reg: see section 4.7.3.6 ACPI 3.0a spec */ + /* 8 bit write of value 0x06 to 0xCF9 in IO space */ + fadt->reset_reg.space_id = ACPI_ADDRESS_SPACE_IO; fadt->reset_reg.bit_width = 8; fadt->reset_reg.bit_offset = 0; - fadt->reset_reg.resv = 0; + fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; fadt->reset_reg.addrl = 0xcf9; fadt->reset_reg.addrh = 0x0; fadt->reset_value = 6; - fadt->x_firmware_ctl_l = (u32) facs; + + fadt->res3 = 0; /* reserved, MUST be 0 ACPI 3.0 */ + fadt->res4 = 0; /* reserved, MUST be 0 ACPI 3.0 */ + fadt->res5 = 0; /* reserved, MUST be 0 ACPI 3.0 */ + + fadt->x_firmware_ctl_l = 0; /* set to 0 if firmware_ctrl is used */ fadt->x_firmware_ctl_h = 0; fadt->x_dsdt_l = (u32) dsdt; fadt->x_dsdt_h = 0; - fadt->x_pm1a_evt_blk.space_id = 1; + fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm1a_evt_blk.bit_width = 32; fadt->x_pm1a_evt_blk.bit_offset = 0; - fadt->x_pm1a_evt_blk.resv = 0; + fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; fadt->x_pm1a_evt_blk.addrl = ACPI_PM_EVT_BLK; fadt->x_pm1a_evt_blk.addrh = 0x0; - fadt->x_pm1b_evt_blk.space_id = 1; - fadt->x_pm1b_evt_blk.bit_width = 4; + fadt->x_pm1b_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_pm1b_evt_blk.bit_width = 0; fadt->x_pm1b_evt_blk.bit_offset = 0; - fadt->x_pm1b_evt_blk.resv = 0; + fadt->x_pm1b_evt_blk.access_size = 0; fadt->x_pm1b_evt_blk.addrl = 0x0; fadt->x_pm1b_evt_blk.addrh = 0x0; - fadt->x_pm1a_cnt_blk.space_id = 1; + + fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm1a_cnt_blk.bit_width = 16; fadt->x_pm1a_cnt_blk.bit_offset = 0; - fadt->x_pm1a_cnt_blk.resv = 0; + fadt->x_pm1a_cnt_blk.access_size = 0; fadt->x_pm1a_cnt_blk.addrl = ACPI_PM1_CNT_BLK; fadt->x_pm1a_cnt_blk.addrh = 0x0; - fadt->x_pm1b_cnt_blk.space_id = 1; - fadt->x_pm1b_cnt_blk.bit_width = 2; + fadt->x_pm1b_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_pm1b_cnt_blk.bit_width = 0; fadt->x_pm1b_cnt_blk.bit_offset = 0; - fadt->x_pm1b_cnt_blk.resv = 0; + fadt->x_pm1b_cnt_blk.access_size = 0; fadt->x_pm1b_cnt_blk.addrl = 0x0; fadt->x_pm1b_cnt_blk.addrh = 0x0; - fadt->x_pm2_cnt_blk.space_id = 1; + /* + * Note: Under this current AMD C state implementation, this is no longer + * used and should not be reported to OS. + */ + fadt->x_pm2_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm2_cnt_blk.bit_width = 0; fadt->x_pm2_cnt_blk.bit_offset = 0; - fadt->x_pm2_cnt_blk.resv = 0; - fadt->x_pm2_cnt_blk.addrl = ACPI_PMA_CNT_BLK; + fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; + fadt->x_pm2_cnt_blk.addrl = 0; fadt->x_pm2_cnt_blk.addrh = 0x0; - fadt->x_pm_tmr_blk.space_id = 1; + + fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm_tmr_blk.bit_width = 32; fadt->x_pm_tmr_blk.bit_offset = 0; - fadt->x_pm_tmr_blk.resv = 0; + fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; fadt->x_pm_tmr_blk.addrl = ACPI_PM_TMR_BLK; fadt->x_pm_tmr_blk.addrh = 0x0; - fadt->x_gpe0_blk.space_id = 1; - fadt->x_gpe0_blk.bit_width = 32; + + fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_gpe0_blk.bit_width = 64; /* EventStatus + Event Enable */ fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.resv = 0; + fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; fadt->x_gpe0_blk.addrl = ACPI_GPE0_BLK; fadt->x_gpe0_blk.addrh = 0x0; - fadt->x_gpe1_blk.space_id = 1; + + fadt->x_gpe1_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_gpe1_blk.bit_width = 0; fadt->x_gpe1_blk.bit_offset = 0; - fadt->x_gpe1_blk.resv = 0; + fadt->x_gpe1_blk.access_size = 0; fadt->x_gpe1_blk.addrl = 0; fadt->x_gpe1_blk.addrh = 0x0; diff --git a/src/southbridge/amd/agesa/hudson/hudson.h b/src/southbridge/amd/agesa/hudson/hudson.h index 15738aa..ef44874 100644 --- a/src/southbridge/amd/agesa/hudson/hudson.h +++ b/src/southbridge/amd/agesa/hudson/hudson.h @@ -35,7 +35,6 @@ #define ACPI_PM_EVT_BLK (HUDSON_ACPI_IO_BASE + 0x00) /* 4 bytes */ #define ACPI_PM1_CNT_BLK (HUDSON_ACPI_IO_BASE + 0x04) /* 2 bytes */ -#define ACPI_PMA_CNT_BLK (HUDSON_ACPI_IO_BASE + 0x0F) /* 1 byte, TODO: Is it 0xFE00? */ #define ACPI_PM_TMR_BLK (HUDSON_ACPI_IO_BASE + 0x18) /* 4 bytes */ #define ACPI_GPE0_BLK (HUDSON_ACPI_IO_BASE + 0x10) /* 8 bytes */ #define ACPI_CPU_CONTROL (HUDSON_ACPI_IO_BASE + 0x08) /* 6 bytes */ @@ -55,7 +54,6 @@ void set_sm_enable_bits(device_t sm_dev, u32 reg_pos, u32 mask, u32 val); #define CPU_CNT_BLK_ADDRESS 0x810 // CpuControlBlkAddr; #define GPE0_BLK_ADDRESS 0x820 // AcpiGpe0BlkAddr; #define SMI_CMD_PORT 0xB0 // SmiCmdPortAddr; -#define ACPI_PMA_CNT_BLK_ADDRESS 0xFE00 // AcpiPmaCntBlkAddr; #define SPIROM_BASE_ADDRESS_REGISTER 0xA0 #ifdef __PRE_RAM__

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New patch to review for coreboot: a41e4d1 AGESA F15tn: Move callouts into northbridge wrapper
by Martin Roth 17 Jan '13

17 Jan '13

Martin Roth (martin.roth(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2169 -gerrit commit a41e4d17b4eb6ac57aace28f5edd1a279c15e951 Author: Martin Roth <martin.roth(a)se-eng.com> Date: Thu Jan 17 12:04:08 2013 -0700 AGESA F15tn: Move callouts into northbridge wrapper There are currently too many things in the mainboard directories that are really more suited to being in the northbridge / southbridge wrappers. This is a start at moving some of those functions down into the wrappers. Move the bios callback functions into the northbridge/amd/agesa/family15tn directory from the mainboard directories. These can still be overridden by any mainboard just by updating the pointer in the callback table to point to a customized version of the function. Change-Id: Icefaa014f4a4abbe51870aee7aa2fa1164e324c1 Signed-off-by: Martin Roth <martin.roth(a)se-eng.com> --- src/mainboard/amd/parmer/BiosCallOuts.c | 464 +-------------------- src/mainboard/amd/parmer/BiosCallOuts.h | 55 +-- src/mainboard/amd/thatcher/BiosCallOuts.c | 464 +-------------------- src/mainboard/amd/thatcher/BiosCallOuts.h | 55 +-- src/northbridge/amd/agesa/family15tn/Makefile.inc | 4 + .../amd/agesa/family15tn/fam15tn_callouts.c | 405 ++++++++++++++++++ .../amd/agesa/family15tn/fam15tn_callouts.h | 53 +++ 7 files changed, 492 insertions(+), 1008 deletions(-) diff --git a/src/mainboard/amd/parmer/BiosCallOuts.c b/src/mainboard/amd/parmer/BiosCallOuts.c index c3ac4de..7af5597 100644 --- a/src/mainboard/amd/parmer/BiosCallOuts.c +++ b/src/mainboard/amd/parmer/BiosCallOuts.c @@ -29,52 +29,18 @@ STATIC CONST BIOS_CALLOUT_STRUCT BiosCallouts[] = { - {AGESA_ALLOCATE_BUFFER, - BiosAllocateBuffer - }, - - {AGESA_DEALLOCATE_BUFFER, - BiosDeallocateBuffer - }, - - {AGESA_DO_RESET, - BiosReset - }, - - {AGESA_LOCATE_BUFFER, - BiosLocateBuffer - }, - - {AGESA_READ_SPD, - BiosReadSpd - }, - - {AGESA_READ_SPD_RECOVERY, - BiosDefaultRet - }, - - {AGESA_RUNFUNC_ONAP, - BiosRunFuncOnAp - }, - - {AGESA_GET_IDS_INIT_DATA, - BiosGetIdsInitData - }, - - {AGESA_HOOKBEFORE_DQS_TRAINING, - BiosHookBeforeDQSTraining - }, - - {AGESA_HOOKBEFORE_EXIT_SELF_REF, - BiosHookBeforeExitSelfRefresh - }, - - {AGESA_FCH_OEM_CALLOUT, - Fch_Oem_config - }, - {AGESA_GNB_GFX_GET_VBIOS_IMAGE, - BiosHookGfxGetVbiosImage - } + {AGESA_ALLOCATE_BUFFER, fam15tn_AllocateBuffer }, + {AGESA_DEALLOCATE_BUFFER, fam15tn_DeallocateBuffer }, + {AGESA_DO_RESET, fam15tn_Reset }, + {AGESA_LOCATE_BUFFER, fam15tn_LocateBuffer }, + {AGESA_READ_SPD, BiosReadSpd }, + {AGESA_READ_SPD_RECOVERY, fam15tn_DefaultRet }, + {AGESA_RUNFUNC_ONAP, fam15tn_RunFuncOnAp }, + {AGESA_GET_IDS_INIT_DATA, fam15tn_GetIdsInitData }, + {AGESA_HOOKBEFORE_DQS_TRAINING, fam15tn_HookBeforeDQSTraining }, + {AGESA_HOOKBEFORE_EXIT_SELF_REF,fam15tn_HookBeforeExitSelfRefresh }, + {AGESA_FCH_OEM_CALLOUT, Fch_Oem_config }, + {AGESA_GNB_GFX_GET_VBIOS_IMAGE, fam15tn_HookGfxGetVbiosImage } }; AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr) @@ -86,398 +52,17 @@ AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr) for (i = 0; i < CallOutCount; i++) { if (BiosCallouts[i].CalloutName == Func) - { break; - } } if(i >= CallOutCount) - { return AGESA_UNSUPPORTED; - } CalloutStatus = BiosCallouts[i].CalloutPtr (Func, Data, ConfigPtr); return CalloutStatus; } -CONST IDS_NV_ITEM IdsData[] = -{ - /*{ - AGESA_IDS_NV_MAIN_PLL_CON, - 0x1 - }, - { - AGESA_IDS_NV_MAIN_PLL_FID_EN, - 0x1 - }, - { - AGESA_IDS_NV_MAIN_PLL_FID, - 0x8 - }, - - { - AGESA_IDS_NV_CUSTOM_NB_PSTATE, - }, - { - AGESA_IDS_NV_CUSTOM_NB_P0_DIV_CTRL, - }, - { - AGESA_IDS_NV_CUSTOM_NB_P1_DIV_CTRL, - }, - { - AGESA_IDS_NV_FORCE_NB_PSTATE, - }, - */ - { - 0xFFFF, - 0xFFFF - } -}; - -#define NUM_IDS_ENTRIES (sizeof (IdsData) / sizeof (IDS_NV_ITEM)) - -AGESA_STATUS BiosGetIdsInitData (UINT32 Func, UINT32 Data, VOID *ConfigPtr) -{ - UINTN i; - IDS_NV_ITEM *IdsPtr; - - IdsPtr = ((IDS_CALLOUT_STRUCT *) ConfigPtr)->IdsNvPtr; - - if (Data == IDS_CALLOUT_INIT) { - for (i = 0; i < NUM_IDS_ENTRIES; i++) { - IdsPtr[i].IdsNvValue = IdsData[i].IdsNvValue; - IdsPtr[i].IdsNvId = IdsData[i].IdsNvId; - } - } - return AGESA_SUCCESS; -} - -AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) -{ - UINT32 AvailableHeapSize; - UINT8 *BiosHeapBaseAddr; - UINT32 CurrNodeOffset; - UINT32 PrevNodeOffset; - UINT32 FreedNodeOffset; - UINT32 BestFitNodeOffset; - UINT32 BestFitPrevNodeOffset; - UINT32 NextFreeOffset; - BIOS_BUFFER_NODE *CurrNodePtr; - BIOS_BUFFER_NODE *FreedNodePtr; - BIOS_BUFFER_NODE *BestFitNodePtr; - BIOS_BUFFER_NODE *BestFitPrevNodePtr; - BIOS_BUFFER_NODE *NextFreePtr; - BIOS_HEAP_MANAGER *BiosHeapBasePtr; - AGESA_BUFFER_PARAMS *AllocParams; - - AllocParams = ((AGESA_BUFFER_PARAMS *) ConfigPtr); - AllocParams->BufferPointer = NULL; - - AvailableHeapSize = BIOS_HEAP_SIZE - sizeof (BIOS_HEAP_MANAGER); - BiosHeapBaseAddr = (UINT8 *) GetHeapBase(&(AllocParams->StdHeader)); - BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BiosHeapBaseAddr; - - if (BiosHeapBasePtr->StartOfAllocatedNodes == 0) { - /* First allocation */ - CurrNodeOffset = sizeof (BIOS_HEAP_MANAGER); - CurrNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + CurrNodeOffset); - CurrNodePtr->BufferHandle = AllocParams->BufferHandle; - CurrNodePtr->BufferSize = AllocParams->BufferLength; - CurrNodePtr->NextNodeOffset = 0; - AllocParams->BufferPointer = (UINT8 *) CurrNodePtr + sizeof (BIOS_BUFFER_NODE); - - /* Update the remaining free space */ - FreedNodeOffset = CurrNodeOffset + CurrNodePtr->BufferSize + sizeof (BIOS_BUFFER_NODE); - FreedNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + FreedNodeOffset); - FreedNodePtr->BufferSize = AvailableHeapSize - sizeof (BIOS_BUFFER_NODE) - CurrNodePtr->BufferSize; - FreedNodePtr->NextNodeOffset = 0; - - /* Update the offsets for Allocated and Freed nodes */ - BiosHeapBasePtr->StartOfAllocatedNodes = CurrNodeOffset; - BiosHeapBasePtr->StartOfFreedNodes = FreedNodeOffset; - } else { - /* Find out whether BufferHandle has been allocated on the heap. */ - /* If it has, return AGESA_BOUNDS_CHK */ - CurrNodeOffset = BiosHeapBasePtr->StartOfAllocatedNodes; - CurrNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + CurrNodeOffset); - - while (CurrNodeOffset != 0) { - CurrNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + CurrNodeOffset); - if (CurrNodePtr->BufferHandle == AllocParams->BufferHandle) { - return AGESA_BOUNDS_CHK; - } - CurrNodeOffset = CurrNodePtr->NextNodeOffset; - /* If BufferHandle has not been allocated on the heap, CurrNodePtr here points - to the end of the allocated nodes list. - */ - - } - /* Find the node that best fits the requested buffer size */ - FreedNodeOffset = BiosHeapBasePtr->StartOfFreedNodes; - PrevNodeOffset = FreedNodeOffset; - BestFitNodeOffset = 0; - BestFitPrevNodeOffset = 0; - while (FreedNodeOffset != 0) { - FreedNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + FreedNodeOffset); - if (FreedNodePtr->BufferSize >= (AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE))) { - if (BestFitNodeOffset == 0) { - /* First node that fits the requested buffer size */ - BestFitNodeOffset = FreedNodeOffset; - BestFitPrevNodeOffset = PrevNodeOffset; - } else { - /* Find out whether current node is a better fit than the previous nodes */ - BestFitNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + BestFitNodeOffset); - if (BestFitNodePtr->BufferSize > FreedNodePtr->BufferSize) { - BestFitNodeOffset = FreedNodeOffset; - BestFitPrevNodeOffset = PrevNodeOffset; - } - } - } - PrevNodeOffset = FreedNodeOffset; - FreedNodeOffset = FreedNodePtr->NextNodeOffset; - } /* end of while loop */ - - if (BestFitNodeOffset == 0) { - /* If we could not find a node that fits the requested buffer */ - /* size, return AGESA_BOUNDS_CHK */ - return AGESA_BOUNDS_CHK; - } else { - BestFitNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + BestFitNodeOffset); - BestFitPrevNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + BestFitPrevNodeOffset); - - /* If BestFitNode is larger than the requested buffer, fragment the node further */ - if (BestFitNodePtr->BufferSize > (AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE))) { - NextFreeOffset = BestFitNodeOffset + AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE); - - NextFreePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextFreeOffset); - NextFreePtr->BufferSize = BestFitNodePtr->BufferSize - (AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE)); - NextFreePtr->NextNodeOffset = BestFitNodePtr->NextNodeOffset; - } else { - /* Otherwise, next free node is NextNodeOffset of BestFitNode */ - NextFreeOffset = BestFitNodePtr->NextNodeOffset; - } - - /* If BestFitNode is the first buffer in the list, then update - StartOfFreedNodes to reflect the new free node - */ - if (BestFitNodeOffset == BiosHeapBasePtr->StartOfFreedNodes) { - BiosHeapBasePtr->StartOfFreedNodes = NextFreeOffset; - } else { - BestFitPrevNodePtr->NextNodeOffset = NextFreeOffset; - } - - /* Add BestFitNode to the list of Allocated nodes */ - CurrNodePtr->NextNodeOffset = BestFitNodeOffset; - BestFitNodePtr->BufferSize = AllocParams->BufferLength; - BestFitNodePtr->BufferHandle = AllocParams->BufferHandle; - BestFitNodePtr->NextNodeOffset = 0; - - /* Remove BestFitNode from list of Freed nodes */ - AllocParams->BufferPointer = (UINT8 *) BestFitNodePtr + sizeof (BIOS_BUFFER_NODE); - } - } - - return AGESA_SUCCESS; -} - -AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) -{ - - UINT8 *BiosHeapBaseAddr; - UINT32 AllocNodeOffset; - UINT32 PrevNodeOffset; - UINT32 NextNodeOffset; - UINT32 FreedNodeOffset; - UINT32 EndNodeOffset; - BIOS_BUFFER_NODE *AllocNodePtr; - BIOS_BUFFER_NODE *PrevNodePtr; - BIOS_BUFFER_NODE *FreedNodePtr; - BIOS_BUFFER_NODE *NextNodePtr; - BIOS_HEAP_MANAGER *BiosHeapBasePtr; - AGESA_BUFFER_PARAMS *AllocParams; - - AllocParams = (AGESA_BUFFER_PARAMS *) ConfigPtr; - - BiosHeapBaseAddr = (UINT8 *) GetHeapBase(&(AllocParams->StdHeader)); - BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BiosHeapBaseAddr; - - /* Find target node to deallocate in list of allocated nodes. - Return AGESA_BOUNDS_CHK if the BufferHandle is not found - */ - AllocNodeOffset = BiosHeapBasePtr->StartOfAllocatedNodes; - AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset); - PrevNodeOffset = AllocNodeOffset; - - while (AllocNodePtr->BufferHandle != AllocParams->BufferHandle) { - if (AllocNodePtr->NextNodeOffset == 0) { - return AGESA_BOUNDS_CHK; - } - PrevNodeOffset = AllocNodeOffset; - AllocNodeOffset = AllocNodePtr->NextNodeOffset; - AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset); - } - - /* Remove target node from list of allocated nodes */ - PrevNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + PrevNodeOffset); - PrevNodePtr->NextNodeOffset = AllocNodePtr->NextNodeOffset; - - /* Zero out the buffer, and clear the BufferHandle */ - LibAmdMemFill ((UINT8 *)AllocNodePtr + sizeof (BIOS_BUFFER_NODE), 0, AllocNodePtr->BufferSize, &(AllocParams->StdHeader)); - AllocNodePtr->BufferHandle = 0; - AllocNodePtr->BufferSize += sizeof (BIOS_BUFFER_NODE); - - /* Add deallocated node in order to the list of freed nodes */ - FreedNodeOffset = BiosHeapBasePtr->StartOfFreedNodes; - FreedNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + FreedNodeOffset); - - EndNodeOffset = AllocNodeOffset + AllocNodePtr->BufferSize; - - if (AllocNodeOffset < FreedNodeOffset) { - /* Add to the start of the freed list */ - if (EndNodeOffset == FreedNodeOffset) { - /* If the freed node is adjacent to the first node in the list, concatenate both nodes */ - AllocNodePtr->BufferSize += FreedNodePtr->BufferSize; - AllocNodePtr->NextNodeOffset = FreedNodePtr->NextNodeOffset; - - /* Clear the BufferSize and NextNodeOffset of the previous first node */ - FreedNodePtr->BufferSize = 0; - FreedNodePtr->NextNodeOffset = 0; - - } else { - /* Otherwise, add freed node to the start of the list - Update NextNodeOffset and BufferSize to include the - size of BIOS_BUFFER_NODE - */ - AllocNodePtr->NextNodeOffset = FreedNodeOffset; - } - /* Update StartOfFreedNodes to the new first node */ - BiosHeapBasePtr->StartOfFreedNodes = AllocNodeOffset; - } else { - /* Traverse list of freed nodes to find where the deallocated node - should be place - */ - NextNodeOffset = FreedNodeOffset; - NextNodePtr = FreedNodePtr; - while (AllocNodeOffset > NextNodeOffset) { - PrevNodeOffset = NextNodeOffset; - if (NextNodePtr->NextNodeOffset == 0) { - break; - } - NextNodeOffset = NextNodePtr->NextNodeOffset; - NextNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextNodeOffset); - } - - /* If deallocated node is adjacent to the next node, - concatenate both nodes - */ - if (NextNodeOffset == EndNodeOffset) { - NextNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextNodeOffset); - AllocNodePtr->BufferSize += NextNodePtr->BufferSize; - AllocNodePtr->NextNodeOffset = NextNodePtr->NextNodeOffset; - - NextNodePtr->BufferSize = 0; - NextNodePtr->NextNodeOffset = 0; - } else { - /*AllocNodePtr->NextNodeOffset = FreedNodePtr->NextNodeOffset; */ - AllocNodePtr->NextNodeOffset = NextNodeOffset; - } - /* If deallocated node is adjacent to the previous node, - concatenate both nodes - */ - PrevNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + PrevNodeOffset); - EndNodeOffset = PrevNodeOffset + PrevNodePtr->BufferSize; - if (AllocNodeOffset == EndNodeOffset) { - PrevNodePtr->NextNodeOffset = AllocNodePtr->NextNodeOffset; - PrevNodePtr->BufferSize += AllocNodePtr->BufferSize; - - AllocNodePtr->BufferSize = 0; - AllocNodePtr->NextNodeOffset = 0; - } else { - PrevNodePtr->NextNodeOffset = AllocNodeOffset; - } - } - return AGESA_SUCCESS; -} - -AGESA_STATUS BiosLocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) -{ - UINT32 AllocNodeOffset; - UINT8 *BiosHeapBaseAddr; - BIOS_BUFFER_NODE *AllocNodePtr; - BIOS_HEAP_MANAGER *BiosHeapBasePtr; - AGESA_BUFFER_PARAMS *AllocParams; - - AllocParams = (AGESA_BUFFER_PARAMS *) ConfigPtr; - - BiosHeapBaseAddr = (UINT8 *) GetHeapBase(&(AllocParams->StdHeader)); - BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BiosHeapBaseAddr; - - AllocNodeOffset = BiosHeapBasePtr->StartOfAllocatedNodes; - AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset); - - while (AllocParams->BufferHandle != AllocNodePtr->BufferHandle) { - if (AllocNodePtr->NextNodeOffset == 0) { - AllocParams->BufferPointer = NULL; - AllocParams->BufferLength = 0; - return AGESA_BOUNDS_CHK; - } else { - AllocNodeOffset = AllocNodePtr->NextNodeOffset; - AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset); - } - } - - AllocParams->BufferPointer = (UINT8 *) ((UINT8 *) AllocNodePtr + sizeof (BIOS_BUFFER_NODE)); - AllocParams->BufferLength = AllocNodePtr->BufferSize; - - return AGESA_SUCCESS; - -} - -AGESA_STATUS BiosRunFuncOnAp (UINT32 Func, UINT32 Data, VOID *ConfigPtr) -{ - AGESA_STATUS Status; - - Status = agesawrapper_amdlaterunaptask (Func, Data, ConfigPtr); - return Status; -} - -AGESA_STATUS BiosReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) -{ - AGESA_STATUS Status; - UINT8 Value; - UINTN ResetType; - AMD_CONFIG_PARAMS *StdHeader; - - ResetType = Data; - StdHeader = ConfigPtr; - - // - // Perform the RESET based upon the ResetType. In case of - // WARM_RESET_WHENVER and COLD_RESET_WHENEVER, the request will go to - // AmdResetManager. During the critical condition, where reset is required - // immediately, the reset will be invoked directly by writing 0x04 to port - // 0xCF9 (Reset Port). - // - switch (ResetType) { - case WARM_RESET_WHENEVER: - case COLD_RESET_WHENEVER: - break; - - case WARM_RESET_IMMEDIATELY: - case COLD_RESET_IMMEDIATELY: - Value = 0x06; - LibAmdIoWrite (AccessWidth8, 0xCf9, &Value, StdHeader); - break; - - default: - break; - } - - Status = 0; - return Status; -} - AGESA_STATUS BiosReadSpd (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { AGESA_STATUS Status; @@ -486,23 +71,6 @@ AGESA_STATUS BiosReadSpd (UINT32 Func, UINT32 Data, VOID *ConfigPtr) return Status; } -AGESA_STATUS BiosDefaultRet (UINT32 Func, UINT32 Data, VOID *ConfigPtr) -{ - return AGESA_UNSUPPORTED; -} - -/* Call the host environment interface to provide a user hook opportunity. */ -AGESA_STATUS BiosHookBeforeDQSTraining (UINT32 Func, UINT32 Data, VOID *ConfigPtr) -{ - return AGESA_SUCCESS; -} - -/* Call the host environment interface to provide a user hook opportunity. */ -AGESA_STATUS BiosHookBeforeExitSelfRefresh (UINT32 Func, UINT32 Data, VOID *ConfigPtr) -{ - return AGESA_SUCCESS; -} - /** * AMD Parmer Platform ALC272 Verb Table */ @@ -740,11 +308,3 @@ AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr) return AGESA_SUCCESS; } - -AGESA_STATUS BiosHookGfxGetVbiosImage(UINT32 Func, UINT32 FchData, VOID *ConfigPrt) -{ - GFX_VBIOS_IMAGE_INFO *pVbiosImageInfo = (GFX_VBIOS_IMAGE_INFO *)ConfigPrt; - pVbiosImageInfo->ImagePtr = cbfs_find_file("pci"CONFIG_VGA_BIOS_ID".rom", CBFS_TYPE_OPTIONROM); - /* printk(BIOS_DEBUG, "IMGptr=%x\n", pVbiosImageInfo->ImagePtr); */ - return pVbiosImageInfo->ImagePtr == NULL ? AGESA_WARNING : AGESA_SUCCESS; -} diff --git a/src/mainboard/amd/parmer/BiosCallOuts.h b/src/mainboard/amd/parmer/BiosCallOuts.h index b449c68..66db8cd 100644 --- a/src/mainboard/amd/parmer/BiosCallOuts.h +++ b/src/mainboard/amd/parmer/BiosCallOuts.h @@ -20,64 +20,15 @@ #ifndef _BIOS_CALLOUT_H_ #define _BIOS_CALLOUT_H_ -#include "Porting.h" -#include "AGESA.h" +#include <northbridge/amd/agesa/family15tn/fam15tn_callouts.h> -#define BIOS_HEAP_START_ADDRESS 0x010000000 -#define BIOS_HEAP_SIZE 0x30000 -#define BSP_STACK_BASE_ADDR 0x30000 - - -typedef struct _BIOS_HEAP_MANAGER { - //UINT32 AvailableSize; - UINT32 StartOfAllocatedNodes; - UINT32 StartOfFreedNodes; -} BIOS_HEAP_MANAGER; - -typedef struct _BIOS_BUFFER_NODE { - UINT32 BufferHandle; - UINT32 BufferSize; - UINT32 NextNodeOffset; -} BIOS_BUFFER_NODE; -/* - * CALLOUTS - */ +/* CALLOUT Initialization */ AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr); -/* REQUIRED CALLOUTS - * AGESA ADVANCED CALLOUTS - CPU - */ -AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr); -AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr); -AGESA_STATUS BiosLocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr); -AGESA_STATUS BiosRunFuncOnAp (UINT32 Func, UINT32 Data, VOID *ConfigPtr); -AGESA_STATUS BiosReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr); -AGESA_STATUS BiosGetIdsInitData (UINT32 Func, UINT32 Data, VOID *ConfigPtr); - /* AGESA ADVANCED CALLOUTS - MEMORY */ AGESA_STATUS BiosReadSpd (UINT32 Func,UINT32 Data,VOID *ConfigPtr); -/* BIOS DEFAULT RET */ -AGESA_STATUS BiosDefaultRet (UINT32 Func, UINT32 Data, VOID *ConfigPtr); - -/* Call the host environment interface to provide a user hook opportunity. */ -AGESA_STATUS BiosHookBeforeDQSTraining (UINT32 Func, UINT32 Data, VOID *ConfigPtr); -/* Call the host environment interface to provide a user hook opportunity. */ -AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr); -/* Call the host environment interface to provide a user hook opportunity. */ -AGESA_STATUS BiosHookBeforeExitSelfRefresh (UINT32 Func, UINT32 Data, VOID *ConfigPtr); -/* PCIE slot reset control */ -AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr); /* FCH OEM Config*/ AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr); -/* Get Vbios Image */ -AGESA_STATUS BiosHookGfxGetVbiosImage(UINT32 Func, UINT32 FchData, VOID *ConfigPrt); -#define SB_GPIO_REG02 2 -#define SB_GPIO_REG09 9 -#define SB_GPIO_REG10 10 -#define SB_GPIO_REG15 15 -#define SB_GPIO_REG17 17 -#define SB_GPIO_REG21 21 -#define SB_GPIO_REG25 25 -#define SB_GPIO_REG28 28 + #endif //_BIOS_CALLOUT_H_ diff --git a/src/mainboard/amd/thatcher/BiosCallOuts.c b/src/mainboard/amd/thatcher/BiosCallOuts.c index ba32727..25de23e 100644 --- a/src/mainboard/amd/thatcher/BiosCallOuts.c +++ b/src/mainboard/amd/thatcher/BiosCallOuts.c @@ -29,52 +29,18 @@ STATIC CONST BIOS_CALLOUT_STRUCT BiosCallouts[] = { - {AGESA_ALLOCATE_BUFFER, - BiosAllocateBuffer - }, - - {AGESA_DEALLOCATE_BUFFER, - BiosDeallocateBuffer - }, - - {AGESA_DO_RESET, - BiosReset - }, - - {AGESA_LOCATE_BUFFER, - BiosLocateBuffer - }, - - {AGESA_READ_SPD, - BiosReadSpd - }, - - {AGESA_READ_SPD_RECOVERY, - BiosDefaultRet - }, - - {AGESA_RUNFUNC_ONAP, - BiosRunFuncOnAp - }, - - {AGESA_GET_IDS_INIT_DATA, - BiosGetIdsInitData - }, - - {AGESA_HOOKBEFORE_DQS_TRAINING, - BiosHookBeforeDQSTraining - }, - - {AGESA_HOOKBEFORE_EXIT_SELF_REF, - BiosHookBeforeExitSelfRefresh - }, - - {AGESA_FCH_OEM_CALLOUT, - Fch_Oem_config - }, - {AGESA_GNB_GFX_GET_VBIOS_IMAGE, - BiosHookGfxGetVbiosImage - } + {AGESA_ALLOCATE_BUFFER, fam15tn_AllocateBuffer }, + {AGESA_DEALLOCATE_BUFFER, fam15tn_DeallocateBuffer }, + {AGESA_DO_RESET, fam15tn_Reset }, + {AGESA_LOCATE_BUFFER, fam15tn_LocateBuffer }, + {AGESA_READ_SPD, BiosReadSpd }, + {AGESA_READ_SPD_RECOVERY, fam15tn_DefaultRet }, + {AGESA_RUNFUNC_ONAP, fam15tn_RunFuncOnAp }, + {AGESA_GET_IDS_INIT_DATA, fam15tn_GetIdsInitData }, + {AGESA_HOOKBEFORE_DQS_TRAINING, fam15tn_HookBeforeDQSTraining }, + {AGESA_HOOKBEFORE_EXIT_SELF_REF,fam15tn_HookBeforeExitSelfRefresh }, + {AGESA_FCH_OEM_CALLOUT, Fch_Oem_config }, + {AGESA_GNB_GFX_GET_VBIOS_IMAGE, fam15tn_HookGfxGetVbiosImage } }; AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr) @@ -86,398 +52,17 @@ AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr) for (i = 0; i < CallOutCount; i++) { if (BiosCallouts[i].CalloutName == Func) - { break; - } } if(i >= CallOutCount) - { return AGESA_UNSUPPORTED; - } CalloutStatus = BiosCallouts[i].CalloutPtr (Func, Data, ConfigPtr); return CalloutStatus; } -CONST IDS_NV_ITEM IdsData[] = -{ - /*{ - AGESA_IDS_NV_MAIN_PLL_CON, - 0x1 - }, - { - AGESA_IDS_NV_MAIN_PLL_FID_EN, - 0x1 - }, - { - AGESA_IDS_NV_MAIN_PLL_FID, - 0x8 - }, - - { - AGESA_IDS_NV_CUSTOM_NB_PSTATE, - }, - { - AGESA_IDS_NV_CUSTOM_NB_P0_DIV_CTRL, - }, - { - AGESA_IDS_NV_CUSTOM_NB_P1_DIV_CTRL, - }, - { - AGESA_IDS_NV_FORCE_NB_PSTATE, - }, - */ - { - 0xFFFF, - 0xFFFF - } -}; - -#define NUM_IDS_ENTRIES (sizeof (IdsData) / sizeof (IDS_NV_ITEM)) - -AGESA_STATUS BiosGetIdsInitData (UINT32 Func, UINT32 Data, VOID *ConfigPtr) -{ - UINTN i; - IDS_NV_ITEM *IdsPtr; - - IdsPtr = ((IDS_CALLOUT_STRUCT *) ConfigPtr)->IdsNvPtr; - - if (Data == IDS_CALLOUT_INIT) { - for (i = 0; i < NUM_IDS_ENTRIES; i++) { - IdsPtr[i].IdsNvValue = IdsData[i].IdsNvValue; - IdsPtr[i].IdsNvId = IdsData[i].IdsNvId; - } - } - return AGESA_SUCCESS; -} - -AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) -{ - UINT32 AvailableHeapSize; - UINT8 *BiosHeapBaseAddr; - UINT32 CurrNodeOffset; - UINT32 PrevNodeOffset; - UINT32 FreedNodeOffset; - UINT32 BestFitNodeOffset; - UINT32 BestFitPrevNodeOffset; - UINT32 NextFreeOffset; - BIOS_BUFFER_NODE *CurrNodePtr; - BIOS_BUFFER_NODE *FreedNodePtr; - BIOS_BUFFER_NODE *BestFitNodePtr; - BIOS_BUFFER_NODE *BestFitPrevNodePtr; - BIOS_BUFFER_NODE *NextFreePtr; - BIOS_HEAP_MANAGER *BiosHeapBasePtr; - AGESA_BUFFER_PARAMS *AllocParams; - - AllocParams = ((AGESA_BUFFER_PARAMS *) ConfigPtr); - AllocParams->BufferPointer = NULL; - - AvailableHeapSize = BIOS_HEAP_SIZE - sizeof (BIOS_HEAP_MANAGER); - BiosHeapBaseAddr = (UINT8 *) GetHeapBase(&(AllocParams->StdHeader)); - BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BiosHeapBaseAddr; - - if (BiosHeapBasePtr->StartOfAllocatedNodes == 0) { - /* First allocation */ - CurrNodeOffset = sizeof (BIOS_HEAP_MANAGER); - CurrNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + CurrNodeOffset); - CurrNodePtr->BufferHandle = AllocParams->BufferHandle; - CurrNodePtr->BufferSize = AllocParams->BufferLength; - CurrNodePtr->NextNodeOffset = 0; - AllocParams->BufferPointer = (UINT8 *) CurrNodePtr + sizeof (BIOS_BUFFER_NODE); - - /* Update the remaining free space */ - FreedNodeOffset = CurrNodeOffset + CurrNodePtr->BufferSize + sizeof (BIOS_BUFFER_NODE); - FreedNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + FreedNodeOffset); - FreedNodePtr->BufferSize = AvailableHeapSize - sizeof (BIOS_BUFFER_NODE) - CurrNodePtr->BufferSize; - FreedNodePtr->NextNodeOffset = 0; - - /* Update the offsets for Allocated and Freed nodes */ - BiosHeapBasePtr->StartOfAllocatedNodes = CurrNodeOffset; - BiosHeapBasePtr->StartOfFreedNodes = FreedNodeOffset; - } else { - /* Find out whether BufferHandle has been allocated on the heap. */ - /* If it has, return AGESA_BOUNDS_CHK */ - CurrNodeOffset = BiosHeapBasePtr->StartOfAllocatedNodes; - CurrNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + CurrNodeOffset); - - while (CurrNodeOffset != 0) { - CurrNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + CurrNodeOffset); - if (CurrNodePtr->BufferHandle == AllocParams->BufferHandle) { - return AGESA_BOUNDS_CHK; - } - CurrNodeOffset = CurrNodePtr->NextNodeOffset; - /* If BufferHandle has not been allocated on the heap, CurrNodePtr here points - to the end of the allocated nodes list. - */ - - } - /* Find the node that best fits the requested buffer size */ - FreedNodeOffset = BiosHeapBasePtr->StartOfFreedNodes; - PrevNodeOffset = FreedNodeOffset; - BestFitNodeOffset = 0; - BestFitPrevNodeOffset = 0; - while (FreedNodeOffset != 0) { - FreedNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + FreedNodeOffset); - if (FreedNodePtr->BufferSize >= (AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE))) { - if (BestFitNodeOffset == 0) { - /* First node that fits the requested buffer size */ - BestFitNodeOffset = FreedNodeOffset; - BestFitPrevNodeOffset = PrevNodeOffset; - } else { - /* Find out whether current node is a better fit than the previous nodes */ - BestFitNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + BestFitNodeOffset); - if (BestFitNodePtr->BufferSize > FreedNodePtr->BufferSize) { - BestFitNodeOffset = FreedNodeOffset; - BestFitPrevNodeOffset = PrevNodeOffset; - } - } - } - PrevNodeOffset = FreedNodeOffset; - FreedNodeOffset = FreedNodePtr->NextNodeOffset; - } /* end of while loop */ - - if (BestFitNodeOffset == 0) { - /* If we could not find a node that fits the requested buffer */ - /* size, return AGESA_BOUNDS_CHK */ - return AGESA_BOUNDS_CHK; - } else { - BestFitNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + BestFitNodeOffset); - BestFitPrevNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + BestFitPrevNodeOffset); - - /* If BestFitNode is larger than the requested buffer, fragment the node further */ - if (BestFitNodePtr->BufferSize > (AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE))) { - NextFreeOffset = BestFitNodeOffset + AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE); - - NextFreePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextFreeOffset); - NextFreePtr->BufferSize = BestFitNodePtr->BufferSize - (AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE)); - NextFreePtr->NextNodeOffset = BestFitNodePtr->NextNodeOffset; - } else { - /* Otherwise, next free node is NextNodeOffset of BestFitNode */ - NextFreeOffset = BestFitNodePtr->NextNodeOffset; - } - - /* If BestFitNode is the first buffer in the list, then update - StartOfFreedNodes to reflect the new free node - */ - if (BestFitNodeOffset == BiosHeapBasePtr->StartOfFreedNodes) { - BiosHeapBasePtr->StartOfFreedNodes = NextFreeOffset; - } else { - BestFitPrevNodePtr->NextNodeOffset = NextFreeOffset; - } - - /* Add BestFitNode to the list of Allocated nodes */ - CurrNodePtr->NextNodeOffset = BestFitNodeOffset; - BestFitNodePtr->BufferSize = AllocParams->BufferLength; - BestFitNodePtr->BufferHandle = AllocParams->BufferHandle; - BestFitNodePtr->NextNodeOffset = 0; - - /* Remove BestFitNode from list of Freed nodes */ - AllocParams->BufferPointer = (UINT8 *) BestFitNodePtr + sizeof (BIOS_BUFFER_NODE); - } - } - - return AGESA_SUCCESS; -} - -AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) -{ - - UINT8 *BiosHeapBaseAddr; - UINT32 AllocNodeOffset; - UINT32 PrevNodeOffset; - UINT32 NextNodeOffset; - UINT32 FreedNodeOffset; - UINT32 EndNodeOffset; - BIOS_BUFFER_NODE *AllocNodePtr; - BIOS_BUFFER_NODE *PrevNodePtr; - BIOS_BUFFER_NODE *FreedNodePtr; - BIOS_BUFFER_NODE *NextNodePtr; - BIOS_HEAP_MANAGER *BiosHeapBasePtr; - AGESA_BUFFER_PARAMS *AllocParams; - - AllocParams = (AGESA_BUFFER_PARAMS *) ConfigPtr; - - BiosHeapBaseAddr = (UINT8 *) GetHeapBase(&(AllocParams->StdHeader)); - BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BiosHeapBaseAddr; - - /* Find target node to deallocate in list of allocated nodes. - Return AGESA_BOUNDS_CHK if the BufferHandle is not found - */ - AllocNodeOffset = BiosHeapBasePtr->StartOfAllocatedNodes; - AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset); - PrevNodeOffset = AllocNodeOffset; - - while (AllocNodePtr->BufferHandle != AllocParams->BufferHandle) { - if (AllocNodePtr->NextNodeOffset == 0) { - return AGESA_BOUNDS_CHK; - } - PrevNodeOffset = AllocNodeOffset; - AllocNodeOffset = AllocNodePtr->NextNodeOffset; - AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset); - } - - /* Remove target node from list of allocated nodes */ - PrevNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + PrevNodeOffset); - PrevNodePtr->NextNodeOffset = AllocNodePtr->NextNodeOffset; - - /* Zero out the buffer, and clear the BufferHandle */ - LibAmdMemFill ((UINT8 *)AllocNodePtr + sizeof (BIOS_BUFFER_NODE), 0, AllocNodePtr->BufferSize, &(AllocParams->StdHeader)); - AllocNodePtr->BufferHandle = 0; - AllocNodePtr->BufferSize += sizeof (BIOS_BUFFER_NODE); - - /* Add deallocated node in order to the list of freed nodes */ - FreedNodeOffset = BiosHeapBasePtr->StartOfFreedNodes; - FreedNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + FreedNodeOffset); - - EndNodeOffset = AllocNodeOffset + AllocNodePtr->BufferSize; - - if (AllocNodeOffset < FreedNodeOffset) { - /* Add to the start of the freed list */ - if (EndNodeOffset == FreedNodeOffset) { - /* If the freed node is adjacent to the first node in the list, concatenate both nodes */ - AllocNodePtr->BufferSize += FreedNodePtr->BufferSize; - AllocNodePtr->NextNodeOffset = FreedNodePtr->NextNodeOffset; - - /* Clear the BufferSize and NextNodeOffset of the previous first node */ - FreedNodePtr->BufferSize = 0; - FreedNodePtr->NextNodeOffset = 0; - - } else { - /* Otherwise, add freed node to the start of the list - Update NextNodeOffset and BufferSize to include the - size of BIOS_BUFFER_NODE - */ - AllocNodePtr->NextNodeOffset = FreedNodeOffset; - } - /* Update StartOfFreedNodes to the new first node */ - BiosHeapBasePtr->StartOfFreedNodes = AllocNodeOffset; - } else { - /* Traverse list of freed nodes to find where the deallocated node - should be place - */ - NextNodeOffset = FreedNodeOffset; - NextNodePtr = FreedNodePtr; - while (AllocNodeOffset > NextNodeOffset) { - PrevNodeOffset = NextNodeOffset; - if (NextNodePtr->NextNodeOffset == 0) { - break; - } - NextNodeOffset = NextNodePtr->NextNodeOffset; - NextNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextNodeOffset); - } - - /* If deallocated node is adjacent to the next node, - concatenate both nodes - */ - if (NextNodeOffset == EndNodeOffset) { - NextNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextNodeOffset); - AllocNodePtr->BufferSize += NextNodePtr->BufferSize; - AllocNodePtr->NextNodeOffset = NextNodePtr->NextNodeOffset; - - NextNodePtr->BufferSize = 0; - NextNodePtr->NextNodeOffset = 0; - } else { - /*AllocNodePtr->NextNodeOffset = FreedNodePtr->NextNodeOffset; */ - AllocNodePtr->NextNodeOffset = NextNodeOffset; - } - /* If deallocated node is adjacent to the previous node, - concatenate both nodes - */ - PrevNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + PrevNodeOffset); - EndNodeOffset = PrevNodeOffset + PrevNodePtr->BufferSize; - if (AllocNodeOffset == EndNodeOffset) { - PrevNodePtr->NextNodeOffset = AllocNodePtr->NextNodeOffset; - PrevNodePtr->BufferSize += AllocNodePtr->BufferSize; - - AllocNodePtr->BufferSize = 0; - AllocNodePtr->NextNodeOffset = 0; - } else { - PrevNodePtr->NextNodeOffset = AllocNodeOffset; - } - } - return AGESA_SUCCESS; -} - -AGESA_STATUS BiosLocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) -{ - UINT32 AllocNodeOffset; - UINT8 *BiosHeapBaseAddr; - BIOS_BUFFER_NODE *AllocNodePtr; - BIOS_HEAP_MANAGER *BiosHeapBasePtr; - AGESA_BUFFER_PARAMS *AllocParams; - - AllocParams = (AGESA_BUFFER_PARAMS *) ConfigPtr; - - BiosHeapBaseAddr = (UINT8 *) GetHeapBase(&(AllocParams->StdHeader)); - BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BiosHeapBaseAddr; - - AllocNodeOffset = BiosHeapBasePtr->StartOfAllocatedNodes; - AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset); - - while (AllocParams->BufferHandle != AllocNodePtr->BufferHandle) { - if (AllocNodePtr->NextNodeOffset == 0) { - AllocParams->BufferPointer = NULL; - AllocParams->BufferLength = 0; - return AGESA_BOUNDS_CHK; - } else { - AllocNodeOffset = AllocNodePtr->NextNodeOffset; - AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset); - } - } - - AllocParams->BufferPointer = (UINT8 *) ((UINT8 *) AllocNodePtr + sizeof (BIOS_BUFFER_NODE)); - AllocParams->BufferLength = AllocNodePtr->BufferSize; - - return AGESA_SUCCESS; - -} - -AGESA_STATUS BiosRunFuncOnAp (UINT32 Func, UINT32 Data, VOID *ConfigPtr) -{ - AGESA_STATUS Status; - - Status = agesawrapper_amdlaterunaptask (Func, Data, ConfigPtr); - return Status; -} - -AGESA_STATUS BiosReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) -{ - AGESA_STATUS Status; - UINT8 Value; - UINTN ResetType; - AMD_CONFIG_PARAMS *StdHeader; - - ResetType = Data; - StdHeader = ConfigPtr; - - // - // Perform the RESET based upon the ResetType. In case of - // WARM_RESET_WHENVER and COLD_RESET_WHENEVER, the request will go to - // AmdResetManager. During the critical condition, where reset is required - // immediately, the reset will be invoked directly by writing 0x04 to port - // 0xCF9 (Reset Port). - // - switch (ResetType) { - case WARM_RESET_WHENEVER: - case COLD_RESET_WHENEVER: - break; - - case WARM_RESET_IMMEDIATELY: - case COLD_RESET_IMMEDIATELY: - Value = 0x06; - LibAmdIoWrite (AccessWidth8, 0xCf9, &Value, StdHeader); - break; - - default: - break; - } - - Status = 0; - return Status; -} - AGESA_STATUS BiosReadSpd (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { AGESA_STATUS Status; @@ -486,23 +71,6 @@ AGESA_STATUS BiosReadSpd (UINT32 Func, UINT32 Data, VOID *ConfigPtr) return Status; } -AGESA_STATUS BiosDefaultRet (UINT32 Func, UINT32 Data, VOID *ConfigPtr) -{ - return AGESA_UNSUPPORTED; -} - -/* Call the host environment interface to provide a user hook opportunity. */ -AGESA_STATUS BiosHookBeforeDQSTraining (UINT32 Func, UINT32 Data, VOID *ConfigPtr) -{ - return AGESA_SUCCESS; -} - -/* Call the host environment interface to provide a user hook opportunity. */ -AGESA_STATUS BiosHookBeforeExitSelfRefresh (UINT32 Func, UINT32 Data, VOID *ConfigPtr) -{ - return AGESA_SUCCESS; -} - /** * AMD Thatcher Platform ALC272 Verb Table */ @@ -742,11 +310,3 @@ AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr) return AGESA_SUCCESS; } - -AGESA_STATUS BiosHookGfxGetVbiosImage(UINT32 Func, UINT32 FchData, VOID *ConfigPrt) -{ - GFX_VBIOS_IMAGE_INFO *pVbiosImageInfo = (GFX_VBIOS_IMAGE_INFO *)ConfigPrt; - pVbiosImageInfo->ImagePtr = cbfs_find_file("pci"CONFIG_VGA_BIOS_ID".rom", CBFS_TYPE_OPTIONROM); - /* printk(BIOS_DEBUG, "IMGptr=%x\n", pVbiosImageInfo->ImagePtr); */ - return pVbiosImageInfo->ImagePtr == NULL ? AGESA_WARNING : AGESA_SUCCESS; -} diff --git a/src/mainboard/amd/thatcher/BiosCallOuts.h b/src/mainboard/amd/thatcher/BiosCallOuts.h index b449c68..66db8cd 100644 --- a/src/mainboard/amd/thatcher/BiosCallOuts.h +++ b/src/mainboard/amd/thatcher/BiosCallOuts.h @@ -20,64 +20,15 @@ #ifndef _BIOS_CALLOUT_H_ #define _BIOS_CALLOUT_H_ -#include "Porting.h" -#include "AGESA.h" +#include <northbridge/amd/agesa/family15tn/fam15tn_callouts.h> -#define BIOS_HEAP_START_ADDRESS 0x010000000 -#define BIOS_HEAP_SIZE 0x30000 -#define BSP_STACK_BASE_ADDR 0x30000 - - -typedef struct _BIOS_HEAP_MANAGER { - //UINT32 AvailableSize; - UINT32 StartOfAllocatedNodes; - UINT32 StartOfFreedNodes; -} BIOS_HEAP_MANAGER; - -typedef struct _BIOS_BUFFER_NODE { - UINT32 BufferHandle; - UINT32 BufferSize; - UINT32 NextNodeOffset; -} BIOS_BUFFER_NODE; -/* - * CALLOUTS - */ +/* CALLOUT Initialization */ AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr); -/* REQUIRED CALLOUTS - * AGESA ADVANCED CALLOUTS - CPU - */ -AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr); -AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr); -AGESA_STATUS BiosLocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr); -AGESA_STATUS BiosRunFuncOnAp (UINT32 Func, UINT32 Data, VOID *ConfigPtr); -AGESA_STATUS BiosReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr); -AGESA_STATUS BiosGetIdsInitData (UINT32 Func, UINT32 Data, VOID *ConfigPtr); - /* AGESA ADVANCED CALLOUTS - MEMORY */ AGESA_STATUS BiosReadSpd (UINT32 Func,UINT32 Data,VOID *ConfigPtr); -/* BIOS DEFAULT RET */ -AGESA_STATUS BiosDefaultRet (UINT32 Func, UINT32 Data, VOID *ConfigPtr); - -/* Call the host environment interface to provide a user hook opportunity. */ -AGESA_STATUS BiosHookBeforeDQSTraining (UINT32 Func, UINT32 Data, VOID *ConfigPtr); -/* Call the host environment interface to provide a user hook opportunity. */ -AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr); -/* Call the host environment interface to provide a user hook opportunity. */ -AGESA_STATUS BiosHookBeforeExitSelfRefresh (UINT32 Func, UINT32 Data, VOID *ConfigPtr); -/* PCIE slot reset control */ -AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr); /* FCH OEM Config*/ AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr); -/* Get Vbios Image */ -AGESA_STATUS BiosHookGfxGetVbiosImage(UINT32 Func, UINT32 FchData, VOID *ConfigPrt); -#define SB_GPIO_REG02 2 -#define SB_GPIO_REG09 9 -#define SB_GPIO_REG10 10 -#define SB_GPIO_REG15 15 -#define SB_GPIO_REG17 17 -#define SB_GPIO_REG21 21 -#define SB_GPIO_REG25 25 -#define SB_GPIO_REG28 28 + #endif //_BIOS_CALLOUT_H_ diff --git a/src/northbridge/amd/agesa/family15tn/Makefile.inc b/src/northbridge/amd/agesa/family15tn/Makefile.inc index 121bf22..b0cf7ff 100644 --- a/src/northbridge/amd/agesa/family15tn/Makefile.inc +++ b/src/northbridge/amd/agesa/family15tn/Makefile.inc @@ -17,4 +17,8 @@ # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # +romstage-y += fam15tn_callouts.c + ramstage-y += northbridge.c +ramstage-y += fam15tn_callouts.c + diff --git a/src/northbridge/amd/agesa/family15tn/fam15tn_callouts.c b/src/northbridge/amd/agesa/family15tn/fam15tn_callouts.c new file mode 100644 index 0000000..afe75f8 --- /dev/null +++ b/src/northbridge/amd/agesa/family15tn/fam15tn_callouts.c @@ -0,0 +1,405 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "agesawrapper.h" +#include "amdlib.h" +#include "Ids.h" +#include "OptionsIds.h" +#include "heapManager.h" +#include "FchPlatform.h" +#include "cbfs.h" +#include "fam15tn_callouts.h" + +AGESA_STATUS fam15tn_AllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + UINT32 AvailableHeapSize; + UINT8 *BiosHeapBaseAddr; + UINT32 CurrNodeOffset; + UINT32 PrevNodeOffset; + UINT32 FreedNodeOffset; + UINT32 BestFitNodeOffset; + UINT32 BestFitPrevNodeOffset; + UINT32 NextFreeOffset; + BIOS_BUFFER_NODE *CurrNodePtr; + BIOS_BUFFER_NODE *FreedNodePtr; + BIOS_BUFFER_NODE *BestFitNodePtr; + BIOS_BUFFER_NODE *BestFitPrevNodePtr; + BIOS_BUFFER_NODE *NextFreePtr; + BIOS_HEAP_MANAGER *BiosHeapBasePtr; + AGESA_BUFFER_PARAMS *AllocParams; + + AllocParams = ((AGESA_BUFFER_PARAMS *) ConfigPtr); + AllocParams->BufferPointer = NULL; + + AvailableHeapSize = BIOS_HEAP_SIZE - sizeof (BIOS_HEAP_MANAGER); + BiosHeapBaseAddr = (UINT8 *) GetHeapBase(&(AllocParams->StdHeader)); + BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BiosHeapBaseAddr; + + if (BiosHeapBasePtr->StartOfAllocatedNodes == 0) { + /* First allocation */ + CurrNodeOffset = sizeof (BIOS_HEAP_MANAGER); + CurrNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + CurrNodeOffset); + CurrNodePtr->BufferHandle = AllocParams->BufferHandle; + CurrNodePtr->BufferSize = AllocParams->BufferLength; + CurrNodePtr->NextNodeOffset = 0; + AllocParams->BufferPointer = (UINT8 *) CurrNodePtr + sizeof (BIOS_BUFFER_NODE); + + /* Update the remaining free space */ + FreedNodeOffset = CurrNodeOffset + CurrNodePtr->BufferSize + sizeof (BIOS_BUFFER_NODE); + FreedNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + FreedNodeOffset); + FreedNodePtr->BufferSize = AvailableHeapSize - sizeof (BIOS_BUFFER_NODE) - CurrNodePtr->BufferSize; + FreedNodePtr->NextNodeOffset = 0; + + /* Update the offsets for Allocated and Freed nodes */ + BiosHeapBasePtr->StartOfAllocatedNodes = CurrNodeOffset; + BiosHeapBasePtr->StartOfFreedNodes = FreedNodeOffset; + } else { + /* Find out whether BufferHandle has been allocated on the heap. */ + /* If it has, return AGESA_BOUNDS_CHK */ + CurrNodeOffset = BiosHeapBasePtr->StartOfAllocatedNodes; + CurrNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + CurrNodeOffset); + + while (CurrNodeOffset != 0) { + CurrNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + CurrNodeOffset); + if (CurrNodePtr->BufferHandle == AllocParams->BufferHandle) { + return AGESA_BOUNDS_CHK; + } + CurrNodeOffset = CurrNodePtr->NextNodeOffset; + /* If BufferHandle has not been allocated on the heap, CurrNodePtr here points + to the end of the allocated nodes list. + */ + + } + /* Find the node that best fits the requested buffer size */ + FreedNodeOffset = BiosHeapBasePtr->StartOfFreedNodes; + PrevNodeOffset = FreedNodeOffset; + BestFitNodeOffset = 0; + BestFitPrevNodeOffset = 0; + while (FreedNodeOffset != 0) { + FreedNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + FreedNodeOffset); + if (FreedNodePtr->BufferSize >= (AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE))) { + if (BestFitNodeOffset == 0) { + /* First node that fits the requested buffer size */ + BestFitNodeOffset = FreedNodeOffset; + BestFitPrevNodeOffset = PrevNodeOffset; + } else { + /* Find out whether current node is a better fit than the previous nodes */ + BestFitNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + BestFitNodeOffset); + if (BestFitNodePtr->BufferSize > FreedNodePtr->BufferSize) { + BestFitNodeOffset = FreedNodeOffset; + BestFitPrevNodeOffset = PrevNodeOffset; + } + } + } + PrevNodeOffset = FreedNodeOffset; + FreedNodeOffset = FreedNodePtr->NextNodeOffset; + } /* end of while loop */ + + if (BestFitNodeOffset == 0) { + /* If we could not find a node that fits the requested buffer */ + /* size, return AGESA_BOUNDS_CHK */ + return AGESA_BOUNDS_CHK; + } else { + BestFitNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + BestFitNodeOffset); + BestFitPrevNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + BestFitPrevNodeOffset); + + /* If BestFitNode is larger than the requested buffer, fragment the node further */ + if (BestFitNodePtr->BufferSize > (AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE))) { + NextFreeOffset = BestFitNodeOffset + AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE); + + NextFreePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextFreeOffset); + NextFreePtr->BufferSize = BestFitNodePtr->BufferSize - (AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE)); + NextFreePtr->NextNodeOffset = BestFitNodePtr->NextNodeOffset; + } else { + /* Otherwise, next free node is NextNodeOffset of BestFitNode */ + NextFreeOffset = BestFitNodePtr->NextNodeOffset; + } + + /* If BestFitNode is the first buffer in the list, then update + StartOfFreedNodes to reflect the new free node + */ + if (BestFitNodeOffset == BiosHeapBasePtr->StartOfFreedNodes) { + BiosHeapBasePtr->StartOfFreedNodes = NextFreeOffset; + } else { + BestFitPrevNodePtr->NextNodeOffset = NextFreeOffset; + } + + /* Add BestFitNode to the list of Allocated nodes */ + CurrNodePtr->NextNodeOffset = BestFitNodeOffset; + BestFitNodePtr->BufferSize = AllocParams->BufferLength; + BestFitNodePtr->BufferHandle = AllocParams->BufferHandle; + BestFitNodePtr->NextNodeOffset = 0; + + /* Remove BestFitNode from list of Freed nodes */ + AllocParams->BufferPointer = (UINT8 *) BestFitNodePtr + sizeof (BIOS_BUFFER_NODE); + } + } + + return AGESA_SUCCESS; +} + +AGESA_STATUS fam15tn_DeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + + UINT8 *BiosHeapBaseAddr; + UINT32 AllocNodeOffset; + UINT32 PrevNodeOffset; + UINT32 NextNodeOffset; + UINT32 FreedNodeOffset; + UINT32 EndNodeOffset; + BIOS_BUFFER_NODE *AllocNodePtr; + BIOS_BUFFER_NODE *PrevNodePtr; + BIOS_BUFFER_NODE *FreedNodePtr; + BIOS_BUFFER_NODE *NextNodePtr; + BIOS_HEAP_MANAGER *BiosHeapBasePtr; + AGESA_BUFFER_PARAMS *AllocParams; + + AllocParams = (AGESA_BUFFER_PARAMS *) ConfigPtr; + + BiosHeapBaseAddr = (UINT8 *) GetHeapBase(&(AllocParams->StdHeader)); + BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BiosHeapBaseAddr; + + /* Find target node to deallocate in list of allocated nodes. + Return AGESA_BOUNDS_CHK if the BufferHandle is not found + */ + AllocNodeOffset = BiosHeapBasePtr->StartOfAllocatedNodes; + AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset); + PrevNodeOffset = AllocNodeOffset; + + while (AllocNodePtr->BufferHandle != AllocParams->BufferHandle) { + if (AllocNodePtr->NextNodeOffset == 0) { + return AGESA_BOUNDS_CHK; + } + PrevNodeOffset = AllocNodeOffset; + AllocNodeOffset = AllocNodePtr->NextNodeOffset; + AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset); + } + + /* Remove target node from list of allocated nodes */ + PrevNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + PrevNodeOffset); + PrevNodePtr->NextNodeOffset = AllocNodePtr->NextNodeOffset; + + /* Zero out the buffer, and clear the BufferHandle */ + LibAmdMemFill ((UINT8 *)AllocNodePtr + sizeof (BIOS_BUFFER_NODE), 0, AllocNodePtr->BufferSize, &(AllocParams->StdHeader)); + AllocNodePtr->BufferHandle = 0; + AllocNodePtr->BufferSize += sizeof (BIOS_BUFFER_NODE); + + /* Add deallocated node in order to the list of freed nodes */ + FreedNodeOffset = BiosHeapBasePtr->StartOfFreedNodes; + FreedNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + FreedNodeOffset); + + EndNodeOffset = AllocNodeOffset + AllocNodePtr->BufferSize; + + if (AllocNodeOffset < FreedNodeOffset) { + /* Add to the start of the freed list */ + if (EndNodeOffset == FreedNodeOffset) { + /* If the freed node is adjacent to the first node in the list, concatenate both nodes */ + AllocNodePtr->BufferSize += FreedNodePtr->BufferSize; + AllocNodePtr->NextNodeOffset = FreedNodePtr->NextNodeOffset; + + /* Clear the BufferSize and NextNodeOffset of the previous first node */ + FreedNodePtr->BufferSize = 0; + FreedNodePtr->NextNodeOffset = 0; + + } else { + /* Otherwise, add freed node to the start of the list + Update NextNodeOffset and BufferSize to include the + size of BIOS_BUFFER_NODE + */ + AllocNodePtr->NextNodeOffset = FreedNodeOffset; + } + /* Update StartOfFreedNodes to the new first node */ + BiosHeapBasePtr->StartOfFreedNodes = AllocNodeOffset; + } else { + /* Traverse list of freed nodes to find where the deallocated node + should be place + */ + NextNodeOffset = FreedNodeOffset; + NextNodePtr = FreedNodePtr; + while (AllocNodeOffset > NextNodeOffset) { + PrevNodeOffset = NextNodeOffset; + if (NextNodePtr->NextNodeOffset == 0) { + break; + } + NextNodeOffset = NextNodePtr->NextNodeOffset; + NextNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextNodeOffset); + } + + /* If deallocated node is adjacent to the next node, + concatenate both nodes + */ + if (NextNodeOffset == EndNodeOffset) { + NextNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextNodeOffset); + AllocNodePtr->BufferSize += NextNodePtr->BufferSize; + AllocNodePtr->NextNodeOffset = NextNodePtr->NextNodeOffset; + + NextNodePtr->BufferSize = 0; + NextNodePtr->NextNodeOffset = 0; + } else { + /*AllocNodePtr->NextNodeOffset = FreedNodePtr->NextNodeOffset; */ + AllocNodePtr->NextNodeOffset = NextNodeOffset; + } + /* If deallocated node is adjacent to the previous node, + concatenate both nodes + */ + PrevNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + PrevNodeOffset); + EndNodeOffset = PrevNodeOffset + PrevNodePtr->BufferSize; + if (AllocNodeOffset == EndNodeOffset) { + PrevNodePtr->NextNodeOffset = AllocNodePtr->NextNodeOffset; + PrevNodePtr->BufferSize += AllocNodePtr->BufferSize; + + AllocNodePtr->BufferSize = 0; + AllocNodePtr->NextNodeOffset = 0; + } else { + PrevNodePtr->NextNodeOffset = AllocNodeOffset; + } + } + return AGESA_SUCCESS; +} + +AGESA_STATUS fam15tn_LocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + UINT32 AllocNodeOffset; + UINT8 *BiosHeapBaseAddr; + BIOS_BUFFER_NODE *AllocNodePtr; + BIOS_HEAP_MANAGER *BiosHeapBasePtr; + AGESA_BUFFER_PARAMS *AllocParams; + + AllocParams = (AGESA_BUFFER_PARAMS *) ConfigPtr; + + BiosHeapBaseAddr = (UINT8 *) GetHeapBase(&(AllocParams->StdHeader)); + BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BiosHeapBaseAddr; + + AllocNodeOffset = BiosHeapBasePtr->StartOfAllocatedNodes; + AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset); + + while (AllocParams->BufferHandle != AllocNodePtr->BufferHandle) { + if (AllocNodePtr->NextNodeOffset == 0) { + AllocParams->BufferPointer = NULL; + AllocParams->BufferLength = 0; + return AGESA_BOUNDS_CHK; + } else { + AllocNodeOffset = AllocNodePtr->NextNodeOffset; + AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset); + } + } + + AllocParams->BufferPointer = (UINT8 *) ((UINT8 *) AllocNodePtr + sizeof (BIOS_BUFFER_NODE)); + AllocParams->BufferLength = AllocNodePtr->BufferSize; + + return AGESA_SUCCESS; + +} + +CONST IDS_NV_ITEM IdsData[] = +{ + { + 0xFFFF, + 0xFFFF + } +}; + +#define NUM_IDS_ENTRIES (sizeof (IdsData) / sizeof (IDS_NV_ITEM)) + +AGESA_STATUS fam15tn_GetIdsInitData (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + UINTN i; + IDS_NV_ITEM *IdsPtr; + + IdsPtr = ((IDS_CALLOUT_STRUCT *) ConfigPtr)->IdsNvPtr; + + if (Data == IDS_CALLOUT_INIT) { + for (i = 0; i < NUM_IDS_ENTRIES; i++) { + IdsPtr[i].IdsNvValue = IdsData[i].IdsNvValue; + IdsPtr[i].IdsNvId = IdsData[i].IdsNvId; + } + } + return AGESA_SUCCESS; +} + +AGESA_STATUS fam15tn_Reset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + AGESA_STATUS Status; + UINT8 Value; + UINTN ResetType; + AMD_CONFIG_PARAMS *StdHeader; + + ResetType = Data; + StdHeader = ConfigPtr; + + // + // Perform the RESET based upon the ResetType. In case of + // WARM_RESET_WHENVER and COLD_RESET_WHENEVER, the request will go to + // AmdResetManager. During the critical condition, where reset is required + // immediately, the reset will be invoked directly by writing 0x04 to port + // 0xCF9 (Reset Port). + // + switch (ResetType) { + case WARM_RESET_WHENEVER: + case COLD_RESET_WHENEVER: + break; + + case WARM_RESET_IMMEDIATELY: + case COLD_RESET_IMMEDIATELY: + Value = 0x06; + LibAmdIoWrite (AccessWidth8, 0xCf9, &Value, StdHeader); + break; + + default: + break; + } + + Status = 0; + return Status; +} + +AGESA_STATUS fam15tn_RunFuncOnAp (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + AGESA_STATUS Status; + + Status = agesawrapper_amdlaterunaptask (Func, Data, ConfigPtr); + return Status; +} + +/* Call the host environment interface to provide a user hook opportunity. */ +AGESA_STATUS fam15tn_HookBeforeDQSTraining (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + return AGESA_SUCCESS; +} + +/* Call the host environment interface to provide a user hook opportunity. */ +AGESA_STATUS fam15tn_HookBeforeExitSelfRefresh (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + return AGESA_SUCCESS; +} + +AGESA_STATUS fam15tn_DefaultRet (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + return AGESA_UNSUPPORTED; +} + + +AGESA_STATUS fam15tn_HookGfxGetVbiosImage(UINT32 Func, UINT32 FchData, VOID *ConfigPrt) +{ + GFX_VBIOS_IMAGE_INFO *pVbiosImageInfo = (GFX_VBIOS_IMAGE_INFO *)ConfigPrt; + pVbiosImageInfo->ImagePtr = cbfs_find_file("pci"CONFIG_VGA_BIOS_ID".rom", CBFS_TYPE_OPTIONROM); + /* printk(BIOS_DEBUG, "IMGptr=%x\n", pVbiosImageInfo->ImagePtr); */ + return pVbiosImageInfo->ImagePtr == NULL ? AGESA_WARNING : AGESA_SUCCESS; +} + diff --git a/src/northbridge/amd/agesa/family15tn/fam15tn_callouts.h b/src/northbridge/amd/agesa/family15tn/fam15tn_callouts.h new file mode 100644 index 0000000..1056a46 --- /dev/null +++ b/src/northbridge/amd/agesa/family15tn/fam15tn_callouts.h @@ -0,0 +1,53 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef CALLOUTS_AMD_AGESA_FAM15TN_H +#define CALLOUTS_AMD_AGESA_FAM15TN_H + +#include "Porting.h" +#include "AGESA.h" + +#define BIOS_HEAP_START_ADDRESS 0x010000000 +#define BIOS_HEAP_SIZE 0x30000 +#define BSP_STACK_BASE_ADDR 0x30000 + + +typedef struct _BIOS_HEAP_MANAGER { + UINT32 StartOfAllocatedNodes; + UINT32 StartOfFreedNodes; +} BIOS_HEAP_MANAGER; + +typedef struct _BIOS_BUFFER_NODE { + UINT32 BufferHandle; + UINT32 BufferSize; + UINT32 NextNodeOffset; +} BIOS_BUFFER_NODE; + +AGESA_STATUS fam15tn_AllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +AGESA_STATUS fam15tn_DeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +AGESA_STATUS fam15tn_LocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +AGESA_STATUS fam15tn_GetIdsInitData (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +AGESA_STATUS fam15tn_Reset (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +AGESA_STATUS fam15tn_RunFuncOnAp (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +AGESA_STATUS fam15tn_HookBeforeDQSTraining (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +AGESA_STATUS fam15tn_HookBeforeExitSelfRefresh (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +AGESA_STATUS fam15tn_DefaultRet (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +AGESA_STATUS fam15tn_HookGfxGetVbiosImage(UINT32 Func, UINT32 FchData, VOID *ConfigPrt); + +#endif /* CALLOUTS_AMD_AGESA_FAM15TN_H */

1 0

Patch set updated for coreboot: f59736a F15tn / Hudson: Change SATA NumOfPorts register setting
by Paul Menzel 17 Jan '13

17 Jan '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2165 -gerrit commit f59736a755351379209f17a653dd14ebd4187efb Author: Martin Roth <martin.roth(a)se-eng.com> Date: Wed Jan 16 17:50:32 2013 -0700 F15tn / Hudson: Change SATA NumOfPorts register setting The Number of Ports register says that it should be set to the maximum number of ports supported by the silicon. AGESA was setting this to be the number of enabled ports. If port 1 was the only port with a drive, this value got set to 0, indicating 1 port. This causes SeaBIOS to only look at port 0 and quit, never finding the drive on port 1. Dave Frodin: I also verified that this patch allows a SATA drive plugged into port 2 to be detected without a device in port 1. Change-Id: I5d49e351864449520e3957bbb07edf0f3ec2fd47 Signed-off-by: Martin Roth <martin.roth(a)se-eng.com> --- .../Fch/Sata/Family/Hudson2/Hudson2SataService.c | 25 ++++++---------------- 1 file changed, 7 insertions(+), 18 deletions(-) diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/Family/Hudson2/Hudson2SataService.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/Family/Hudson2/Hudson2SataService.c index d3eb263..bf97f8b 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/Family/Hudson2/Hudson2SataService.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/Family/Hudson2/Hudson2SataService.c @@ -83,7 +83,6 @@ * D E F I N I T I O N S A N D M A C R O S *---------------------------------------------------------------------------------------- */ -UINT8 NumOfSataPorts = 8; /** * FchSataGpioInitial - Sata GPIO function Procedure @@ -581,7 +580,6 @@ FchShutdownUnconnectedSataPortClock ( { UINT8 PortNumByte; UINT8 PortSataStatusByte; - UINT8 NumOfPorts; UINT8 FchSataClkAutoOff; FCH_DATA_BLOCK *LocalCfgPtr; AMD_CONFIG_PARAMS *StdHeader; @@ -590,7 +588,6 @@ FchShutdownUnconnectedSataPortClock ( StdHeader = LocalCfgPtr->StdHeader; FchSataClkAutoOff = (UINT8) LocalCfgPtr->Sata.SataClkAutoOff; - NumOfPorts = 0; // // Enable SATA auto clock control by default // @@ -606,28 +603,20 @@ FchShutdownUnconnectedSataPortClock ( } } ///end of for (PortNumByte=0;PortNumByte<6;PortNumByte++) - ReadMem (Bar5 + 0x0C, AccessWidth8, &PortSataStatusByte); - // + //Set the Ports Implemented register //if all ports are in disabled state, report at least one port // + ReadMem (Bar5 + 0x0C, AccessWidth8, &PortSataStatusByte); if ( (PortSataStatusByte & 0xFF) == 0) { RwMem (Bar5 + 0x0C, AccessWidth8, (UINT32) ~(0xFF), 01); } - ReadMem (Bar5 + 0x0C, AccessWidth8, &PortSataStatusByte); - - for (PortNumByte = 0; PortNumByte < MAX_SATA_PORTS; PortNumByte ++) { - if (PortSataStatusByte & (1 << PortNumByte)) { - NumOfPorts++; - } - } - - if ( NumOfPorts == 0) { - NumOfPorts = 0x01; - } - - RwMem (Bar5 + 0x00, AccessWidth8, 0xE0, NumOfPorts - 1); + // + // Number of Ports (NP): 0’s based value indicating the maximum number + // of ports supported by the HBA silicon. + // + RwMem (Bar5 + 0x00, AccessWidth8, 0xE0, MAX_SATA_PORTS - 1); } /**

1 0

Patch set updated for coreboot: ea85253 Utility to run the snow bios in user mode
by Ronald G. Minnich 17 Jan '13

17 Jan '13

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2159 -gerrit commit ea852533f42707c5c5122986f350a57a61e7a2a9 Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Wed Jan 16 11:59:34 2013 -0600 Utility to run the snow bios in user mode This program lets you test run a snow coreboot image in user mode on a properly equipped arm system (usually an ARM chromebook). This is a real time saver as you don't have to flash each time. We've found and fixed some nasty bugs with this one. Anyway, the instructions on how to use this are in the binary. Change-Id: Ib555ef51fd7e930905a2ee5cbfda1cc6f068278e Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- util/runfw/Makefile | 23 ++++++++ util/runfw/googlesnow.c | 138 ++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 161 insertions(+) diff --git a/util/runfw/Makefile b/util/runfw/Makefile new file mode 100644 index 0000000..1c96adc --- /dev/null +++ b/util/runfw/Makefile @@ -0,0 +1,23 @@ +# +# runfw -- fun firmware in user mode. +# +# Copyright (C) 2013 The ChromiumOS Authors. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA +# + +all: googlesnow + +googlesnow: googlesnow.c + cc -g -o googlesnow googlesnow.c diff --git a/util/runfw/googlesnow.c b/util/runfw/googlesnow.c new file mode 100644 index 0000000..80b9913 --- /dev/null +++ b/util/runfw/googlesnow.c @@ -0,0 +1,138 @@ +/* + * googlesnow - run google snow firmware in user mode + * + * Copyright (C) 2013 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA + */ + +#include <stdio.h> +#include <err.h> +#include <sys/mman.h> + +#include <string.h> + +enum addresses { + regs = 0x10000000, + sram = 0x2020000, + sramsize = 0x77fff, +}; + +// 0x20234b0 +main(int argc, char *argv[]) +{ + int fd; + int devmem; + void *regbase; + void *srambase; + void (*coreboot)(void) = (void *)0x2023400; + + if (argc != 3) + errx(1, "usage: runbios rom-file start-address"); + + fd = open(argv[1], 2); + if (fd < 0) + err(1, argv[1]); + devmem = open("/dev/mem", 2); + if (devmem < 0) + err(1, argv[1]); + srambase = mmap((void *)sram, sramsize, PROT_EXEC|PROT_READ|PROT_WRITE, MAP_ANONYMOUS|MAP_PRIVATE, -1, 0); + if (-1 == (int)sram) + err(1, "mmap"); + memset((void *)sram, 0xff, sramsize); + + + /* now sort of do what bl1 does: read the 'rom' into the sram */ + /* skip the bl1. We don't run it. */ + if (pread(fd, coreboot, 30*1024, 0x2000) < 30*1024) + err(1, "read 'rom'"); + /* you want to be in gdb at this point. */ + coreboot = (void *) (strtoul(argv[2], 0, 0)); + coreboot(); +} +#if 0 +/* cc -g googlesnow.c */ +/* typical run +gdb a.out +(gdb) list 50 + +45 i2c = mmap((void *)0x12c60000, 0x10000, PROT_READ|PROT_WRITE, MAP_ANONYMOUS|MAP_PRIVATE, devmem, (off_t) 0x12c60000); +46 if (-1 == (int)i2c) +47 err(1, "mmap i2c"); +48 +49 /* now sort of do what bl1 does: read the 'rom' into the sram */ +50 if (pread(fd, coreboot, 30*1024, 0x2000) < 30*1024) +51 err(1, "read 'rom'"); +52 /* you want to be in gdb at this point. */ +53 coreboot = (void *) strtoull(argv[2], 0, 0); +54 coreboot(); +(gdb) br 54 +Breakpoint 3 at 0x8798: file runbios.c, line 54. +(gdb) run ~/coreboot/build/coreboot.rom 0x020234b0 +The program being debugged has been started already. +Start it from the beginning? (y or n) y + +Starting program: /root/coreboot/util/runarmbios/a.out ~/coreboot/build/coreboot.rom 0x020234b0 + +Breakpoint 3, main (argc=3, argv=0x7efff7c4) at runbios.c:54 +54 coreboot(); +(gdb) symbol-file ~/coreboot/build/cbfs/fallback/bootblock.debug +Load new symbol table from "/root/coreboot/build/cbfs/fallback/bootblock.debug"? (y or n) y +Reading symbols from /root/coreboot/build/cbfs/fallback/bootblock.debug...done. +Error in re-setting breakpoint 3: No source file named runbios.c. +(gdb) display/i $pc +1: x/i $pc +=> 0x8798: ldr r3, [r11, #-8] +(gdb) stepi +0x0000879c in ?? () +1: x/i $pc +=> 0x879c: blx r3 +(gdb) +0x020234b0 in call_bootblock () +1: x/i $pc +=> 0x20234b0 <call_bootblock>: ldr sp, [pc, #3800] ; 0x2024390 +(gdb) +0x020234b4 in call_bootblock () +1: x/i $pc +=> 0x20234b4 <call_bootblock+4>: bic sp, sp, #7 +(gdb) +0x020234b8 in call_bootblock () +1: x/i $pc +=> 0x20234b8 <call_bootblock+8>: mov r0, #0 +(gdb) +0x020234bc in call_bootblock () +1: x/i $pc +=> 0x20234bc <call_bootblock+12>: blx 0x20244b8 <main> +(gdb) +main (bist=0) at src/arch/armv7/bootblock_simple.c:37 +37 { +1: x/i $pc +=> 0x20244b8 <main>: push {r3, lr} +(gdb) +42 bootblock_mainboard_init(); +1: x/i $pc +=> 0x20244ba <main+2>: bl 0x2023c08 <bootblock_mainboard_init> +(gdb) +bootblock_mainboard_init () at src/mainboard/google/snow/bootblock.c:2124 +2124 { +1: x/i $pc +=> 0x2023c08 <bootblock_mainboard_init>: stmdb sp!, {r4, r5, r6, r7, r9, r10, r11, lr} +(gdb) +2127 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); +1: x/i $pc +=> 0x2023c0c <bootblock_mainboard_init+4>: movs r1, #0 + +Note you are now debugging source, and pretty much all commands work. +*/ +#endif

1 0

Patch merged into coreboot/master: 1c706dc Fix the stack setup code so we can use an arbitrary 32-bit value
by gerrit＠coreboot.org 17 Jan '13

17 Jan '13

the following patch was just integrated into master: commit 1c706dc85830a1d91c7ff7c99ac48efd8d085613 Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Thu Jan 17 11:14:17 2013 -0800 Fix the stack setup code so we can use an arbitrary 32-bit value We've had obscure errors as the size of the bootblock changes. This fix allows us to use a 32-bit constant. Please test on real hardware before you ack. Change-Id: Ic3d9f4763554bd6104ae9c4ce5bbacd17b40872c Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Reviewed-on: http://review.coreboot.org/2168 Reviewed-by: David Hendricks <dhendrix(a)chromium.org> Tested-by: build bot (Jenkins) Build-Tested: build bot (Jenkins) at Thu Jan 17 20:21:54 2013, giving +1 Reviewed-By: David Hendricks <dhendrix(a)chromium.org> at Thu Jan 17 20:17:43 2013, giving +2 See http://review.coreboot.org/2168 for details. -gerrit

1 0

Patch set updated for coreboot: f4d65fb Utility to run the snow bios in user mode
by Ronald G. Minnich 17 Jan '13

17 Jan '13

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2159 -gerrit commit f4d65fb24718e4d9851cc137e222898a7c3a4350 Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Wed Jan 16 11:59:34 2013 -0600 Utility to run the snow bios in user mode This program lets you test run a snow coreboot image in user mode on a properly equipped arm system (usually an ARM chromebook). This is a real time saver as you don't have to flash each time. We've found and fixed some nasty bugs with this one. Anyway, the instructions on how to use this are in the binary. Change-Id: Ib555ef51fd7e930905a2ee5cbfda1cc6f068278e Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- util/runfw/Makefile | 4 ++ util/runfw/googlesnow.c | 119 ++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 123 insertions(+) diff --git a/util/runfw/Makefile b/util/runfw/Makefile new file mode 100644 index 0000000..597046e --- /dev/null +++ b/util/runfw/Makefile @@ -0,0 +1,4 @@ +all: googlesnow + +googlesnow: googlesnow.c + cc -g -o googlesnow googlesnow.c diff --git a/util/runfw/googlesnow.c b/util/runfw/googlesnow.c new file mode 100644 index 0000000..54ef43c --- /dev/null +++ b/util/runfw/googlesnow.c @@ -0,0 +1,119 @@ +#include <stdio.h> +#include <err.h> +#include <sys/mman.h> + +#include <string.h> + +enum addresses { + regs = 0x10000000, + sram = 0x2020000, + sramsize = 0x77fff, +}; + +// 0x20234b0 +main(int argc, char *argv[]) +{ + int fd; + int devmem; + void *regbase; + void *srambase; + void (*coreboot)(void) = (void *)0x2023400; + + if (argc != 3) + errx(1, "usage: runbios rom-file start-address"); + + fd = open(argv[1], 2); + if (fd < 0) + err(1, argv[1]); + devmem = open("/dev/mem", 2); + if (devmem < 0) + err(1, argv[1]); + srambase = mmap((void *)sram, sramsize, PROT_EXEC|PROT_READ|PROT_WRITE, MAP_ANONYMOUS|MAP_PRIVATE, -1, 0); + if (-1 == (int)sram) + err(1, "mmap"); + memset((void *)sram, 0xff, sramsize); + + + /* now sort of do what bl1 does: read the 'rom' into the sram */ + /* skip the bl1. We don't run it. */ + if (pread(fd, coreboot, 30*1024, 0x2000) < 30*1024) + err(1, "read 'rom'"); + /* you want to be in gdb at this point. */ + coreboot = (void *) (strtoul(argv[2], 0, 0)); + coreboot(); +} +#if 0 +/* cc -g googlesnow.c */ +/* typical run +gdb a.out +(gdb) list 50 + +45 i2c = mmap((void *)0x12c60000, 0x10000, PROT_READ|PROT_WRITE, MAP_ANONYMOUS|MAP_PRIVATE, devmem, (off_t) 0x12c60000); +46 if (-1 == (int)i2c) +47 err(1, "mmap i2c"); +48 +49 /* now sort of do what bl1 does: read the 'rom' into the sram */ +50 if (pread(fd, coreboot, 30*1024, 0x2000) < 30*1024) +51 err(1, "read 'rom'"); +52 /* you want to be in gdb at this point. */ +53 coreboot = (void *) strtoull(argv[2], 0, 0); +54 coreboot(); +(gdb) br 54 +Breakpoint 3 at 0x8798: file runbios.c, line 54. +(gdb) run ~/coreboot/build/coreboot.rom 0x020234b0 +The program being debugged has been started already. +Start it from the beginning? (y or n) y + +Starting program: /root/coreboot/util/runarmbios/a.out ~/coreboot/build/coreboot.rom 0x020234b0 + +Breakpoint 3, main (argc=3, argv=0x7efff7c4) at runbios.c:54 +54 coreboot(); +(gdb) symbol-file ~/coreboot/build/cbfs/fallback/bootblock.debug +Load new symbol table from "/root/coreboot/build/cbfs/fallback/bootblock.debug"? (y or n) y +Reading symbols from /root/coreboot/build/cbfs/fallback/bootblock.debug...done. +Error in re-setting breakpoint 3: No source file named runbios.c. +(gdb) display/i $pc +1: x/i $pc +=> 0x8798: ldr r3, [r11, #-8] +(gdb) stepi +0x0000879c in ?? () +1: x/i $pc +=> 0x879c: blx r3 +(gdb) +0x020234b0 in call_bootblock () +1: x/i $pc +=> 0x20234b0 <call_bootblock>: ldr sp, [pc, #3800] ; 0x2024390 +(gdb) +0x020234b4 in call_bootblock () +1: x/i $pc +=> 0x20234b4 <call_bootblock+4>: bic sp, sp, #7 +(gdb) +0x020234b8 in call_bootblock () +1: x/i $pc +=> 0x20234b8 <call_bootblock+8>: mov r0, #0 +(gdb) +0x020234bc in call_bootblock () +1: x/i $pc +=> 0x20234bc <call_bootblock+12>: blx 0x20244b8 <main> +(gdb) +main (bist=0) at src/arch/armv7/bootblock_simple.c:37 +37 { +1: x/i $pc +=> 0x20244b8 <main>: push {r3, lr} +(gdb) +42 bootblock_mainboard_init(); +1: x/i $pc +=> 0x20244ba <main+2>: bl 0x2023c08 <bootblock_mainboard_init> +(gdb) +bootblock_mainboard_init () at src/mainboard/google/snow/bootblock.c:2124 +2124 { +1: x/i $pc +=> 0x2023c08 <bootblock_mainboard_init>: stmdb sp!, {r4, r5, r6, r7, r9, r10, r11, lr} +(gdb) +2127 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); +1: x/i $pc +=> 0x2023c0c <bootblock_mainboard_init+4>: movs r1, #0 + +Note you are now debugging source, and pretty much all commands work. +*/ +#endif

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coreboot January 2013