coreboot January 2013

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Patch set updated for coreboot: faf6bb0 WIP: armv7/snow patch dump
by David Hendricks 18 Jan '13

18 Jan '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2174 -gerrit commit faf6bb02b90339194f40e32efb4eb34f5dd9dc4f Author: David Hendricks <dhendrix(a)chromium.org> Date: Thu Jan 17 20:52:21 2013 -0800 WIP: armv7/snow patch dump ** do not submit ** This is just a patch dump so others can more easily get up to speed. The user should see a bunch of prints to the UART, and PSHOLD will be held high so the machine should not turn itself off. We are actually able to CBFS and get the romstage address successfully, but calling romstage's main() function fails... Add romstage as a stage (a later patch adds it as a binary, which is probably wrong). The Makefile magic is complex enough that we let it build the XIP file for now, but we no longer use it. replace findstage with loadstage. Loadstage will find a stage, load the code to memory, and zero the remaining part of memory. Now we can link the romstage to go anywhere! TODO: - Eliminate magic offsets (in romstage.ld and cbfs.h) - Make it so that the call to romstage's address does not switch to a mode that's incompatible with romstage's entry point. Depends-On: 2173 Change-Id: Iae4d2f9e7f429cb1df15d49daf9a08b88d75d79d Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- src/arch/armv7/Makefile.inc | 5 +-- src/arch/armv7/bootblock_simple.c | 6 +-- src/arch/armv7/include/arch/cbfs.h | 68 +++++++++++++++++++++++++++++----- src/arch/armv7/include/arch/hlt.h | 1 - src/arch/armv7/romstage.ld | 5 ++- src/cpu/samsung/exynos5250/bootblock.c | 3 +- src/mainboard/google/snow/bootblock.c | 18 +++++---- src/mainboard/google/snow/romstage.c | 25 +++++++++++++ 8 files changed, 104 insertions(+), 27 deletions(-) diff --git a/src/arch/armv7/Makefile.inc b/src/arch/armv7/Makefile.inc index ecb5aee..a5833a7 100644 --- a/src/arch/armv7/Makefile.inc +++ b/src/arch/armv7/Makefile.inc @@ -215,9 +215,8 @@ $(obj)/coreboot.pre: $(objcbfs)/romstage_xip.elf $(obj)/coreboot.pre1 $(CBFSTOOL @printf " CBFS $(subst $(obj)/,,$(@))\n" cp $(obj)/coreboot.pre1 $@.tmp $(CBFSTOOL) $@.tmp add-stage \ - -f $(objcbfs)/romstage_xip.elf \ - -n $(CONFIG_CBFS_PREFIX)/romstage -c none \ - -b $(shell cat $(objcbfs)/base_xip.txt) + -f $(objcbfs)/romstage_null.debug \ + -n $(CONFIG_CBFS_PREFIX)/romstage -c none mv $@.tmp $@ ################################################################################ diff --git a/src/arch/armv7/bootblock_simple.c b/src/arch/armv7/bootblock_simple.c index 6897e15..a48a490 100644 --- a/src/arch/armv7/bootblock_simple.c +++ b/src/arch/armv7/bootblock_simple.c @@ -39,12 +39,12 @@ void main(unsigned long bist) unsigned long entry; if (boot_cpu()) { - bootblock_mainboard_init(); bootblock_cpu_init(); + bootblock_mainboard_init(); } - entry = findstage(target1); + entry = loadstage(target1); + printk(BIOS_INFO, "entry: 0x%08lx\n", entry); if (entry) call(entry); - hlt(); } diff --git a/src/arch/armv7/include/arch/cbfs.h b/src/arch/armv7/include/arch/cbfs.h index 0affa5e..ed55d80 100644 --- a/src/arch/armv7/include/arch/cbfs.h +++ b/src/arch/armv7/include/arch/cbfs.h @@ -26,42 +26,92 @@ #include <arch/byteorder.h> #include <arch/cbfs.h> + static int cbfs_check_magic(struct cbfs_file *file) { - return !strcmp(file->magic, CBFS_FILE_MAGIC) ? 1 : 0; + return strcmp(file->magic, CBFS_FILE_MAGIC) ? 0 : 1; } -static unsigned long findstage(const char* target) +static unsigned long loadstage(const char* target) { unsigned long offset, align; /* FIXME: magic offsets */ - struct cbfs_header *header = (struct cbfs_header *)(0x02023400 + 0x40); + struct cbfs_header *header = (struct cbfs_header *)(0x02062040); // if (ntohl(header->magic) != CBFS_HEADER_MAGIC) // printk(BIOS_ERR, "ERROR: No valid CBFS header found!\n"); offset = ntohl(header->offset); align = ntohl(header->align); + printk(BIOS_INFO, "cbfs header (%p)\n", header); + printk(BIOS_INFO, "\tmagic: 0x%08x\n", ntohl(header->magic)); + printk(BIOS_INFO, "\tversion: 0x%08x\n", ntohl(header->version)); + printk(BIOS_INFO, "\tromsize: 0x%08x\n", ntohl(header->romsize)); + printk(BIOS_INFO, "\tbootblocksize: 0x%08x\n", ntohl(header->bootblocksize)); + printk(BIOS_INFO, "\talign: 0x%08x\n", ntohl(header->align)); + printk(BIOS_INFO, "\toffset: 0x%08x\n", ntohl(header->offset)); while(1) { struct cbfs_file *file; - file = (struct cbfs_file *)(offset + CONFIG_ROMSTAGE_BASE); - if (!cbfs_check_magic(file)) + struct cbfs_stage *stage; + file = (struct cbfs_file *)(offset + 0x02060000); + if (!cbfs_check_magic(file)) { + printk(BIOS_INFO, "magic is wrong, file: %p\n", file); return 0; - if (!strcmp(CBFS_NAME(file), target)) - return (unsigned long)CBFS_SUBHEADER(file); + } + if (!strcmp(CBFS_NAME(file), target)) { + uint32_t load, entry; + printk(BIOS_INFO, "CBFS name matched, offset: %p\n", file); + printk(BIOS_INFO, "\tmagic: %02x%02x%02x%02x%02x%02x%02x%02x\n", + file->magic[0], file->magic[1], file->magic[2], file->magic[3], + file->magic[4], file->magic[5], file->magic[6], file->magic[7]); + printk(BIOS_INFO, "\tlen: 0x%08x\n", ntohl(file->len)); + printk(BIOS_INFO, "\ttype: 0x%08x\n", ntohl(file->type)); + printk(BIOS_INFO, "\tchecksum: 0x%08x\n", ntohl(file->checksum)); + printk(BIOS_INFO, "\toffset: 0x%08x\n", ntohl(file->offset)); + /* exploit the fact that this is all word-aligned. */ + stage = CBFS_SUBHEADER(file); + load = stage->load; + entry = stage->entry; + int i; + u32 *to = (void *)load; + u32 *from = (void *)((u8 *)stage+sizeof(*stage)); + /* we could do memmove/memset here. But the math gets messy. + * far easier just to do what we want. + */ + printk(BIOS_INFO, "entry: 0x%08x, load: 0x%08x, " + "len: 0x%08x, memlen: 0x%08x\n", entry, + load, stage->len, stage->memlen); + for(i = 0; i < stage->len; i += 4) + *to++ = *from++; + for(; i < stage->memlen; i += 4) + *to++ = 0; + return entry; + } int flen = ntohl(file->len); int foffset = ntohl(file->offset); unsigned long oldoffset = offset; offset = ALIGN(offset + foffset + flen, align); + printk(BIOS_INFO, "offset: 0x%08lx\n", offset); if (offset <= oldoffset) return 0; - if (offset < CONFIG_ROMSTAGE_BASE + ntohl(header->romsize)); + if (offset > (128 * 1024)) return 0; } } static inline void call(unsigned long addr) { - void (*doit)(void) = (void *)addr; + __attribute__((noreturn)) void (*doit)(void) = (void *)addr; + printk(BIOS_INFO, "addr: %08lx, doit: %p\n", addr, doit); + /* FIXME: dumping SRAM content for sanity checking */ + int i; + for (i = 0; i < 128; i++) { + if (i % 16 == 0) + printk(BIOS_INFO, "\n0x%08lx: ", addr + i); + else + printk(BIOS_INFO, " "); + printk(BIOS_INFO, "%02x", *(uint8_t *)(addr + i)); + } + /* FIXME: do we need to change to/from arm/thumb? */ doit(); } #endif diff --git a/src/arch/armv7/include/arch/hlt.h b/src/arch/armv7/include/arch/hlt.h index 535508a..285b6f8 100644 --- a/src/arch/armv7/include/arch/hlt.h +++ b/src/arch/armv7/include/arch/hlt.h @@ -4,7 +4,6 @@ static inline __attribute__((always_inline)) void hlt(void) { for (;;) ; - //asm("hlt"); } #endif /* ARCH_HLT_H */ diff --git a/src/arch/armv7/romstage.ld b/src/arch/armv7/romstage.ld index d40d2ef..8343a4a 100644 --- a/src/arch/armv7/romstage.ld +++ b/src/arch/armv7/romstage.ld @@ -35,11 +35,12 @@ OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") OUTPUT_ARCH(arm) -/* ENTRY(_start) */ +ENTRY(_start) SECTIONS { - . = 0x02023400 + 0x4000; + /* TODO make this a configurable option (per chipset). */ + . = 0x02050000; .romtext . : { _rom = .; diff --git a/src/cpu/samsung/exynos5250/bootblock.c b/src/cpu/samsung/exynos5250/bootblock.c index 0d65676..2852764 100644 --- a/src/cpu/samsung/exynos5250/bootblock.c +++ b/src/cpu/samsung/exynos5250/bootblock.c @@ -36,5 +36,6 @@ static int config_branch_prediction(int set_cr_z) void bootblock_cpu_init(void); void bootblock_cpu_init(void) { - /* FIXME: this is a stub for now */ + volatile unsigned long *pshold = (unsigned long *)0x1004330c; + *pshold |= 0x100; } diff --git a/src/mainboard/google/snow/bootblock.c b/src/mainboard/google/snow/bootblock.c index a025b28..48854a7 100644 --- a/src/mainboard/google/snow/bootblock.c +++ b/src/mainboard/google/snow/bootblock.c @@ -42,8 +42,6 @@ #define EXYNOS5_CLOCK_BASE 0x10010000 -volatile unsigned long *pshold = (unsigned long *)0x1004330c; - /* FIXME(dhendrix): Can we move this SPI stuff elsewhere? */ static void spi_rx_tx(struct exynos_spi *regs, int todo, void *dinp, void const *doutp, int i) @@ -723,6 +721,9 @@ static void exynos5_uart_tx_byte(unsigned char data) // struct s5p_uart *const uart = s5p_get_base_uart(dev_index); struct s5p_uart *uart = (struct s5p_uart *)uart3_base; + if (data == '\n') + exynos5_uart_tx_byte('\r'); + /* wait for room in the tx FIFO */ while ((readl(uart->ufstat) & TX_FIFO_FULL_MASK)) { if (exynos5_uart_err_check(1)) @@ -738,12 +739,13 @@ void puts(const char *s) int n = 0; while (*s) { + if (*s == '\n') { + exynos5_uart_tx_byte(0xd); /* CR */ + } + exynos5_uart_tx_byte(*s++); n++; } - - exynos5_uart_tx_byte(0xd); /* CR */ - exynos5_uart_tx_byte(0xa); /* LF */ } static void do_serial(void) @@ -2140,7 +2142,7 @@ void bootblock_mainboard_init(void) printk(BIOS_INFO, "%s: hello world\n", __func__); /* Copy romstage data from SPI ROM to SRAM */ - /* FIXME: test with something benign, then fix the offsets once - we're more confident in this */ - copy_romstage(0x2000, 0x2060000, 0x800); + /* FIXME: magic offsets */ + copy_romstage(0x0, 0x2060000, 0x10000); + printk(BIOS_INFO, "%s: goodbye world\n", __func__); } diff --git a/src/mainboard/google/snow/romstage.c b/src/mainboard/google/snow/romstage.c index 9092b7c..859c69e 100644 --- a/src/mainboard/google/snow/romstage.c +++ b/src/mainboard/google/snow/romstage.c @@ -21,6 +21,22 @@ #include <system.h> #include <cache.h> +#if 0 +#include <arch/io.h> + +/* FIXME: make i2c.h use standard types */ +#define uchar unsigned char +#define uint unsigned int +#include <device/i2c.h> + +#include <cpu/samsung/s5p-common/s3c24x0_i2c.h> +#include "cpu/samsung/exynos5250/dmc.h" +#include <cpu/samsung/exynos5250/power.h> +#include <cpu/samsung/exynos5250/clock_init.h> +#include <cpu/samsung/exynos5-common/uart.h> +#endif +#include <console/console.h> + static void mmu_setup(void) { dram_bank_mmu_setup(CONFIG_SYS_SDRAM_BASE, CONFIG_DRAM_SIZE_MB * 1024); @@ -28,5 +44,14 @@ static void mmu_setup(void) void main(void) { +// volatile unsigned long *pshold = (unsigned long *)0x1004330c; +// i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); +// power_init(); +// clock_init(); +// exynos_pinmux_config(PERIPH_ID_UART3, PINMUX_FLAG_NONE); + console_init(); + printk(BIOS_INFO, "hello from romstage\n"); + +// *pshold &= ~0x100; /* shut down */ mmu_setup(); }

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Patch set updated for coreboot: 8e1db5e armv7: add a wrapper for romstage's main() for ARM ISA
by David Hendricks 18 Jan '13

18 Jan '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2175 -gerrit commit 8e1db5edc2cba795d3d17ef336c0b931a32281e4 Author: David Hendricks <dhendrix(a)chromium.org> Date: Thu Jan 17 22:26:36 2013 -0800 armv7: add a wrapper for romstage's main() for ARM ISA This adds a wrapper around main() in romstage which is compiled using -marm. This assumes that the bootblock branches to romstage in ARM mode. The long-term idea is to enforce ABI compatibility when handing off to the next stage by using shims which are which are compiled in a pre- determiend manner and leave the main portions of each stage up to whatever the compiler wants. So it will eventually look like this: 1. bootblock_main (ARM/Thumb) 2. bootblock_exit (ARM) 3. romstage_entry (ARM) 4. romstage_main (ARM/Thumb) (credit to Gabe Black for writing the patch, I'm just uploading it) Change-Id: I4fdb8d2c6c2c0a7178bcb9154c378ddce0567309 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/arch/armv7/Makefile.inc | 15 +++++++++++---- src/arch/armv7/romstage.ld | 1 + src/arch/armv7/romstage_main.c | 29 +++++++++++++++++++++++++++++ src/mainboard/google/snow/romstage.c | 1 + 4 files changed, 42 insertions(+), 4 deletions(-) diff --git a/src/arch/armv7/Makefile.inc b/src/arch/armv7/Makefile.inc index a5833a7..2cf6ed9 100644 --- a/src/arch/armv7/Makefile.inc +++ b/src/arch/armv7/Makefile.inc @@ -264,21 +264,28 @@ endif ################################################################################ # Build the romstage +romstage_main_c = $(src)/arch/armv7/romstage_main.c +romstage_main_o = $(obj)/arch/armv7/romstage_main.o + +$(romstage_main_o): $(romstage_main_c) + @printf " CC $(subst $(obj)/,,$(@))\n" + $(CC) -nostdlib -nostartfiles -static -c -o $@ $< -marm + # FIXME(dhendrix): added debug printfs -$(objcbfs)/romstage_null.debug: $$(romstage-objs) $(objgenerated)/romstage_null.ld +$(objcbfs)/romstage_null.debug: $$(romstage-objs) $(romstage_main_o) $(objgenerated)/romstage_null.ld @printf " LINK $(subst $(obj)/,,$(@))\n" ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) $(LD) -nostdlib -nostartfiles -static -o $@ -L$(obj) $(romstage-objs) -T $(objgenerated)/romstage_null.ld else - $(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(objgenerated)/romstage_null.ld -Wl,--start-group $(romstage-objs) $(LIBGCC_FILE_NAME) -Wl,--end-group + $(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(objgenerated)/romstage_null.ld -Wl,--start-group $(romstage-objs) $(romstage_main_o) $(LIBGCC_FILE_NAME) -Wl,--end-group endif $(objcbfs)/romstage_xip.debug: $$(romstage-objs) $(objgenerated)/romstage_xip.ld @printf " LINK $(subst $(obj)/,,$(@))\n" ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) - $(LD) -nostdlib -nostartfiles -static -o $@ -L$(obj) $(romstage-objs) -T $(objgenerated)/romstage_xip.ld + $(LD) -nostdlib -nostartfiles -static -o $@ -L$(obj) $(romstage-objs) $(romstage_main_o) -T $(objgenerated)/romstage_xip.ld else - $(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(objgenerated)/romstage_xip.ld -Wl,--start-group $(romstage-objs) $(LIBGCC_FILE_NAME) -Wl,--end-group + $(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(objgenerated)/romstage_xip.ld -Wl,--start-group $(romstage-objs) $(romstage_main_o) $(LIBGCC_FILE_NAME) -Wl,--end-group endif $(objgenerated)/romstage_null.ld: $$(ldscripts) $(obj)/ldoptions diff --git a/src/arch/armv7/romstage.ld b/src/arch/armv7/romstage.ld index 8343a4a..cf69aa7 100644 --- a/src/arch/armv7/romstage.ld +++ b/src/arch/armv7/romstage.ld @@ -45,6 +45,7 @@ SECTIONS .romtext . : { _rom = .; _start = .; + *(.text.entry.armv7); *(.text.startup); *(.text); } diff --git a/src/arch/armv7/romstage_main.c b/src/arch/armv7/romstage_main.c new file mode 100644 index 0000000..0b463b8 --- /dev/null +++ b/src/arch/armv7/romstage_main.c @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +void main(void); + +/* romstage_main is simply a stub to invoke main(), to handle ARM mode switching + * (ARM/Thumb) properly. */ + +void romstage_main(void) __attribute__((section(".text.entry.armv7"))); +void romstage_main(void) +{ + main(); +} diff --git a/src/mainboard/google/snow/romstage.c b/src/mainboard/google/snow/romstage.c index 859c69e..45016a5 100644 --- a/src/mainboard/google/snow/romstage.c +++ b/src/mainboard/google/snow/romstage.c @@ -42,6 +42,7 @@ static void mmu_setup(void) dram_bank_mmu_setup(CONFIG_SYS_SDRAM_BASE, CONFIG_DRAM_SIZE_MB * 1024); } +void main(void); void main(void) { // volatile unsigned long *pshold = (unsigned long *)0x1004330c;

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New patch to review for coreboot: 9c9c32b Hudson: Cleanup - change SB800 references to hudson
by Martin Roth 18 Jan '13

18 Jan '13

Martin Roth (martin.roth(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2177 -gerrit commit 9c9c32b9cf6abc9cf6d3bcfcde451c138ba0f531 Author: Martin Roth <martin.roth(a)se-eng.com> Date: Fri Jan 18 12:55:40 2013 -0700 Hudson: Cleanup - change SB800 references to hudson Go through southbridge/amd/agesa/hudson, thatcher and parmer mainboard directories and change all references to sb800 to reference hudson instead. This is just cleanup and should make no functional difference. Change-Id: Icd6a9a08c4bbf5e1aed394362d24c05811ed1fba Signed-off-by: Martin Roth <martin.roth(a)se-eng.com> --- src/mainboard/amd/parmer/acpi_tables.c | 2 +- src/mainboard/amd/parmer/agesawrapper.c | 2 +- src/mainboard/amd/parmer/dsdt.asl | 2 +- src/mainboard/amd/parmer/get_bus_conf.c | 29 ++++++++++--------- src/mainboard/amd/parmer/irq_tables.c | 10 +++---- src/mainboard/amd/parmer/mptable.c | 46 +++++++++++++++---------------- src/mainboard/amd/parmer/romstage.c | 4 +-- src/mainboard/amd/thatcher/acpi_tables.c | 2 +- src/mainboard/amd/thatcher/agesawrapper.c | 2 +- src/mainboard/amd/thatcher/dsdt.asl | 2 +- src/mainboard/amd/thatcher/get_bus_conf.c | 29 ++++++++++--------- src/mainboard/amd/thatcher/irq_tables.c | 10 +++---- src/mainboard/amd/thatcher/mptable.c | 46 +++++++++++++++---------------- src/mainboard/amd/thatcher/romstage.c | 4 +-- src/southbridge/amd/agesa/hudson/hudson.c | 2 +- src/southbridge/amd/agesa/hudson/smbus.c | 4 +-- src/southbridge/amd/agesa/hudson/smbus.h | 4 +-- 17 files changed, 97 insertions(+), 103 deletions(-) diff --git a/src/mainboard/amd/parmer/acpi_tables.c b/src/mainboard/amd/parmer/acpi_tables.c index 0a64535..0cdea2d 100644 --- a/src/mainboard/amd/parmer/acpi_tables.c +++ b/src/mainboard/amd/parmer/acpi_tables.c @@ -62,7 +62,7 @@ unsigned long acpi_fill_madt(unsigned long current) /* create all subtables for processors */ current = acpi_create_madt_lapics(current); - /* Write SB800 IOAPIC, only one */ + /* Write Hudson IOAPIC, only one */ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS, IO_APIC_ADDR, 0); diff --git a/src/mainboard/amd/parmer/agesawrapper.c b/src/mainboard/amd/parmer/agesawrapper.c index c9315fe..41c1a94 100644 --- a/src/mainboard/amd/parmer/agesawrapper.c +++ b/src/mainboard/amd/parmer/agesawrapper.c @@ -100,7 +100,7 @@ agesawrapper_amdinitcpuio ( PciData = 1; LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - /* The platform BIOS needs to ensure the memory ranges of SB800 legacy + /* The platform BIOS needs to ensure the memory ranges of Hudson legacy * devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are * set to non-posted regions. */ diff --git a/src/mainboard/amd/parmer/dsdt.asl b/src/mainboard/amd/parmer/dsdt.asl index e0cc3fd..4b600e8 100644 --- a/src/mainboard/amd/parmer/dsdt.asl +++ b/src/mainboard/amd/parmer/dsdt.asl @@ -188,7 +188,7 @@ DefinitionBlock ( PM2D, 0x00000008, } - /* Power Management I/O registers, TODO:PMIO is quite different in SB800. */ + /* Power Management I/O registers. */ OperationRegion(PIOR, SystemIO, 0x00000CD6, 0x00000002) Field(PIOR, ByteAcc, NoLock, Preserve) { PIOI, 0x00000008, diff --git a/src/mainboard/amd/parmer/get_bus_conf.c b/src/mainboard/amd/parmer/get_bus_conf.c index 2636b9e..47b4f74 100644 --- a/src/mainboard/amd/parmer/get_bus_conf.c +++ b/src/mainboard/amd/parmer/get_bus_conf.c @@ -30,8 +30,8 @@ * and acpi_tables busnum is default. */ u8 bus_isa; -u8 bus_sb800[3]; -u32 apicid_sb800; +u8 bus_hudson[3]; +u32 apicid_hudson; /* * Here you only need to set value in pci1234 for HT-IO that could be installed or not @@ -43,7 +43,7 @@ u32 pci1234x[] = { }; u32 bus_type[256]; -u32 sbdn_sb800; +u32 sbdn_hudson; static u32 get_bus_conf_done = 0; @@ -95,10 +95,10 @@ void get_bus_conf(void) printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status); #endif - sbdn_sb800 = 0; + sbdn_hudson = 0; for (i = 0; i < 3; i++) { - bus_sb800[i] = 0; + bus_hudson[i] = 0; } for (i = 0; i < 256; i++) { @@ -107,34 +107,33 @@ void get_bus_conf(void) bus_type[0] = 1; /* pci */ - // bus_sb800[0] = (sysconf.pci1234[0] >> 16) & 0xff; - bus_sb800[0] = (pci1234x[0] >> 16) & 0xff; + bus_hudson[0] = (pci1234x[0] >> 16) & 0xff; - /* sb800 */ - dev = dev_find_slot(bus_sb800[0], PCI_DEVFN(sbdn_sb800 + 0x14, 4)); + /* Hudson */ + dev = dev_find_slot(bus_hudson[0], PCI_DEVFN(sbdn_hudson + 0x14, 4)); if (dev) { - bus_sb800[1] = pci_read_config8(dev, PCI_SECONDARY_BUS); + bus_hudson[1] = pci_read_config8(dev, PCI_SECONDARY_BUS); bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); bus_isa++; - for (j = bus_sb800[1]; j < bus_isa; j++) + for (j = bus_hudson[1]; j < bus_isa; j++) bus_type[j] = 1; } for (i = 0; i < 4; i++) { - dev = dev_find_slot(bus_sb800[0], PCI_DEVFN(sbdn_sb800 + 0x14, i)); + dev = dev_find_slot(bus_hudson[0], PCI_DEVFN(sbdn_hudson + 0x14, i)); if (dev) { - bus_sb800[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS); + bus_hudson[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS); bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); bus_isa++; } } - for (j = bus_sb800[2]; j < bus_isa; j++) + for (j = bus_hudson[2]; j < bus_isa; j++) bus_type[j] = 1; /* I/O APICs: APIC ID Version State Address */ bus_isa = 10; apicid_base = CONFIG_MAX_CPUS; - apicid_sb800 = apicid_base; + apicid_hudson = apicid_base; } diff --git a/src/mainboard/amd/parmer/irq_tables.c b/src/mainboard/amd/parmer/irq_tables.c index 3bcd3fb..3eb036a 100644 --- a/src/mainboard/amd/parmer/irq_tables.c +++ b/src/mainboard/amd/parmer/irq_tables.c @@ -44,8 +44,8 @@ static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, } extern u8 bus_isa; -extern u8 bus_sb800[2]; -extern unsigned long sbdn_sb800; +extern u8 bus_hudson[2]; +extern unsigned long sbdn_hudson; unsigned long write_pirq_routing_table(unsigned long addr) { @@ -72,8 +72,8 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq->signature = PIRQ_SIGNATURE; pirq->version = PIRQ_VERSION; - pirq->rtr_bus = bus_sb800[0]; - pirq->rtr_devfn = ((sbdn_sb800 + 0x14) << 3) | 4; + pirq->rtr_bus = bus_hudson[0]; + pirq->rtr_devfn = ((sbdn_hudson + 0x14) << 3) | 4; pirq->exclusive_irqs = 0; @@ -88,7 +88,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) slot_num = 0; /* pci bridge */ - write_pirq_info(pirq_info, bus_sb800[0], ((sbdn_sb800 + 0x14) << 3) | 4, + write_pirq_info(pirq_info, bus_hudson[0], ((sbdn_hudson + 0x14) << 3) | 4, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); pirq_info++; diff --git a/src/mainboard/amd/parmer/mptable.c b/src/mainboard/amd/parmer/mptable.c index 9dcc845..b8a9ab7 100644 --- a/src/mainboard/amd/parmer/mptable.c +++ b/src/mainboard/amd/parmer/mptable.c @@ -30,11 +30,11 @@ //-#define IO_APIC_ID CONFIG_MAX_PHYSICAL_CPUS + 1 #define IO_APIC_ID CONFIG_MAX_CPUS -extern u8 bus_sb800[3]; +extern u8 bus_hudson[3]; extern u32 bus_type[256]; -extern u32 sbdn_sb800; -extern u32 apicid_sb800; +extern u32 sbdn_hudson; +extern u32 apicid_hudson; u8 picr_data[0x54] = { 0x1F,0x1f,0x1f,0x1F,0x1F,0x1F,0x1F,0x1F,0x0A,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F, @@ -103,8 +103,8 @@ static void *smp_write_config_table(void *v) /* Set IO APIC ID onto IO_APIC_ID */ write32 (dword, 0x00); write32 (dword + 0x10, IO_APIC_ID << 24); - apicid_sb800 = IO_APIC_ID; - smp_write_ioapic(mc, apicid_sb800, 0x21, dword); + apicid_hudson = IO_APIC_ID; + smp_write_ioapic(mc, apicid_hudson, 0x21, dword); /* PIC IRQ routine */ for (byte = 0x0; byte < sizeof(picr_data); byte ++) { @@ -121,13 +121,13 @@ static void *smp_write_config_table(void *v) /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ #define IO_LOCAL_INT(type, intr, apicid, pin) \ smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); - mptable_add_isa_interrupts(mc, bus_isa, apicid_sb800, 0); + mptable_add_isa_interrupts(mc, bus_isa, apicid_hudson, 0); /* PCI interrupts are level triggered, and are * associated with a specific bus/device/function tuple. */ #define PCI_INT(bus, dev, int_sign, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), apicid_sb800, (pin)) + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), apicid_hudson, (pin)) /* Internal VGA */ PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]); @@ -156,26 +156,26 @@ static void *smp_write_config_table(void *v) /* PCI slots */ /* PCI_SLOT 0. */ - PCI_INT(bus_sb800[1], 0x5, 0x0, 0x14); - PCI_INT(bus_sb800[1], 0x5, 0x1, 0x15); - PCI_INT(bus_sb800[1], 0x5, 0x2, 0x16); - PCI_INT(bus_sb800[1], 0x5, 0x3, 0x17); + PCI_INT(bus_hudson[1], 0x5, 0x0, 0x14); + PCI_INT(bus_hudson[1], 0x5, 0x1, 0x15); + PCI_INT(bus_hudson[1], 0x5, 0x2, 0x16); + PCI_INT(bus_hudson[1], 0x5, 0x3, 0x17); /* PCI_SLOT 1. */ - PCI_INT(bus_sb800[1], 0x6, 0x0, 0x15); - PCI_INT(bus_sb800[1], 0x6, 0x1, 0x16); - PCI_INT(bus_sb800[1], 0x6, 0x2, 0x17); - PCI_INT(bus_sb800[1], 0x6, 0x3, 0x14); + PCI_INT(bus_hudson[1], 0x6, 0x0, 0x15); + PCI_INT(bus_hudson[1], 0x6, 0x1, 0x16); + PCI_INT(bus_hudson[1], 0x6, 0x2, 0x17); + PCI_INT(bus_hudson[1], 0x6, 0x3, 0x14); /* PCI_SLOT 2. */ - PCI_INT(bus_sb800[1], 0x7, 0x0, 0x16); - PCI_INT(bus_sb800[1], 0x7, 0x1, 0x17); - PCI_INT(bus_sb800[1], 0x7, 0x2, 0x14); - PCI_INT(bus_sb800[1], 0x7, 0x3, 0x15); - - PCI_INT(bus_sb800[2], 0x0, 0x0, 0x12); - PCI_INT(bus_sb800[2], 0x0, 0x1, 0x13); - PCI_INT(bus_sb800[2], 0x0, 0x2, 0x14); + PCI_INT(bus_hudson[1], 0x7, 0x0, 0x16); + PCI_INT(bus_hudson[1], 0x7, 0x1, 0x17); + PCI_INT(bus_hudson[1], 0x7, 0x2, 0x14); + PCI_INT(bus_hudson[1], 0x7, 0x3, 0x15); + + PCI_INT(bus_hudson[2], 0x0, 0x0, 0x12); + PCI_INT(bus_hudson[2], 0x0, 0x1, 0x13); + PCI_INT(bus_hudson[2], 0x0, 0x2, 0x14); /* PCIe Lan*/ PCI_INT(0x0, 0x06, 0x0, 0x13); diff --git a/src/mainboard/amd/parmer/romstage.c b/src/mainboard/amd/parmer/romstage.c index 335e56d..2e975f8 100644 --- a/src/mainboard/amd/parmer/romstage.c +++ b/src/mainboard/amd/parmer/romstage.c @@ -68,14 +68,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx); post_code(0x37); + printk(BIOS_DEBUG, "agesawrapper_amdinitreset "); val = agesawrapper_amdinitreset(); if(val) { printk(BIOS_DEBUG, "agesawrapper_amdinitreset failed: %x \n", val); } - post_code(0x38); - printk(BIOS_DEBUG, "Got past sb800_early_setup\n"); - post_code(0x39); val = agesawrapper_amdinitearly (); diff --git a/src/mainboard/amd/thatcher/acpi_tables.c b/src/mainboard/amd/thatcher/acpi_tables.c index 0a64535..0cdea2d 100644 --- a/src/mainboard/amd/thatcher/acpi_tables.c +++ b/src/mainboard/amd/thatcher/acpi_tables.c @@ -62,7 +62,7 @@ unsigned long acpi_fill_madt(unsigned long current) /* create all subtables for processors */ current = acpi_create_madt_lapics(current); - /* Write SB800 IOAPIC, only one */ + /* Write Hudson IOAPIC, only one */ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS, IO_APIC_ADDR, 0); diff --git a/src/mainboard/amd/thatcher/agesawrapper.c b/src/mainboard/amd/thatcher/agesawrapper.c index aaff34b..7b002b4 100644 --- a/src/mainboard/amd/thatcher/agesawrapper.c +++ b/src/mainboard/amd/thatcher/agesawrapper.c @@ -100,7 +100,7 @@ agesawrapper_amdinitcpuio ( PciData = 1; LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - /* The platform BIOS needs to ensure the memory ranges of SB800 legacy + /* The platform BIOS needs to ensure the memory ranges of Hudson legacy * devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are * set to non-posted regions. */ diff --git a/src/mainboard/amd/thatcher/dsdt.asl b/src/mainboard/amd/thatcher/dsdt.asl index e0cc3fd..4b600e8 100644 --- a/src/mainboard/amd/thatcher/dsdt.asl +++ b/src/mainboard/amd/thatcher/dsdt.asl @@ -188,7 +188,7 @@ DefinitionBlock ( PM2D, 0x00000008, } - /* Power Management I/O registers, TODO:PMIO is quite different in SB800. */ + /* Power Management I/O registers. */ OperationRegion(PIOR, SystemIO, 0x00000CD6, 0x00000002) Field(PIOR, ByteAcc, NoLock, Preserve) { PIOI, 0x00000008, diff --git a/src/mainboard/amd/thatcher/get_bus_conf.c b/src/mainboard/amd/thatcher/get_bus_conf.c index 2636b9e..47b4f74 100644 --- a/src/mainboard/amd/thatcher/get_bus_conf.c +++ b/src/mainboard/amd/thatcher/get_bus_conf.c @@ -30,8 +30,8 @@ * and acpi_tables busnum is default. */ u8 bus_isa; -u8 bus_sb800[3]; -u32 apicid_sb800; +u8 bus_hudson[3]; +u32 apicid_hudson; /* * Here you only need to set value in pci1234 for HT-IO that could be installed or not @@ -43,7 +43,7 @@ u32 pci1234x[] = { }; u32 bus_type[256]; -u32 sbdn_sb800; +u32 sbdn_hudson; static u32 get_bus_conf_done = 0; @@ -95,10 +95,10 @@ void get_bus_conf(void) printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status); #endif - sbdn_sb800 = 0; + sbdn_hudson = 0; for (i = 0; i < 3; i++) { - bus_sb800[i] = 0; + bus_hudson[i] = 0; } for (i = 0; i < 256; i++) { @@ -107,34 +107,33 @@ void get_bus_conf(void) bus_type[0] = 1; /* pci */ - // bus_sb800[0] = (sysconf.pci1234[0] >> 16) & 0xff; - bus_sb800[0] = (pci1234x[0] >> 16) & 0xff; + bus_hudson[0] = (pci1234x[0] >> 16) & 0xff; - /* sb800 */ - dev = dev_find_slot(bus_sb800[0], PCI_DEVFN(sbdn_sb800 + 0x14, 4)); + /* Hudson */ + dev = dev_find_slot(bus_hudson[0], PCI_DEVFN(sbdn_hudson + 0x14, 4)); if (dev) { - bus_sb800[1] = pci_read_config8(dev, PCI_SECONDARY_BUS); + bus_hudson[1] = pci_read_config8(dev, PCI_SECONDARY_BUS); bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); bus_isa++; - for (j = bus_sb800[1]; j < bus_isa; j++) + for (j = bus_hudson[1]; j < bus_isa; j++) bus_type[j] = 1; } for (i = 0; i < 4; i++) { - dev = dev_find_slot(bus_sb800[0], PCI_DEVFN(sbdn_sb800 + 0x14, i)); + dev = dev_find_slot(bus_hudson[0], PCI_DEVFN(sbdn_hudson + 0x14, i)); if (dev) { - bus_sb800[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS); + bus_hudson[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS); bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); bus_isa++; } } - for (j = bus_sb800[2]; j < bus_isa; j++) + for (j = bus_hudson[2]; j < bus_isa; j++) bus_type[j] = 1; /* I/O APICs: APIC ID Version State Address */ bus_isa = 10; apicid_base = CONFIG_MAX_CPUS; - apicid_sb800 = apicid_base; + apicid_hudson = apicid_base; } diff --git a/src/mainboard/amd/thatcher/irq_tables.c b/src/mainboard/amd/thatcher/irq_tables.c index 3bcd3fb..3eb036a 100644 --- a/src/mainboard/amd/thatcher/irq_tables.c +++ b/src/mainboard/amd/thatcher/irq_tables.c @@ -44,8 +44,8 @@ static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, } extern u8 bus_isa; -extern u8 bus_sb800[2]; -extern unsigned long sbdn_sb800; +extern u8 bus_hudson[2]; +extern unsigned long sbdn_hudson; unsigned long write_pirq_routing_table(unsigned long addr) { @@ -72,8 +72,8 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq->signature = PIRQ_SIGNATURE; pirq->version = PIRQ_VERSION; - pirq->rtr_bus = bus_sb800[0]; - pirq->rtr_devfn = ((sbdn_sb800 + 0x14) << 3) | 4; + pirq->rtr_bus = bus_hudson[0]; + pirq->rtr_devfn = ((sbdn_hudson + 0x14) << 3) | 4; pirq->exclusive_irqs = 0; @@ -88,7 +88,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) slot_num = 0; /* pci bridge */ - write_pirq_info(pirq_info, bus_sb800[0], ((sbdn_sb800 + 0x14) << 3) | 4, + write_pirq_info(pirq_info, bus_hudson[0], ((sbdn_hudson + 0x14) << 3) | 4, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); pirq_info++; diff --git a/src/mainboard/amd/thatcher/mptable.c b/src/mainboard/amd/thatcher/mptable.c index 329f731..4cdea62 100644 --- a/src/mainboard/amd/thatcher/mptable.c +++ b/src/mainboard/amd/thatcher/mptable.c @@ -30,11 +30,11 @@ //-#define IO_APIC_ID CONFIG_MAX_PHYSICAL_CPUS + 1 #define IO_APIC_ID CONFIG_MAX_CPUS -extern u8 bus_sb800[3]; +extern u8 bus_hudson[3]; extern u32 bus_type[256]; -extern u32 sbdn_sb800; -extern u32 apicid_sb800; +extern u32 sbdn_hudson; +extern u32 apicid_hudson; u8 picr_data[] = { 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x0A,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F, @@ -103,8 +103,8 @@ static void *smp_write_config_table(void *v) /* Set IO APIC ID onto IO_APIC_ID */ write32 (dword, 0x00); write32 (dword + 0x10, IO_APIC_ID << 24); - apicid_sb800 = IO_APIC_ID; - smp_write_ioapic(mc, apicid_sb800, 0x21, dword); + apicid_hudson = IO_APIC_ID; + smp_write_ioapic(mc, apicid_hudson, 0x21, dword); /* PIC IRQ routine */ for (byte = 0x0; byte < sizeof(picr_data); byte ++) { @@ -121,13 +121,13 @@ static void *smp_write_config_table(void *v) /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ #define IO_LOCAL_INT(type, intr, apicid, pin) \ smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); - mptable_add_isa_interrupts(mc, bus_isa, apicid_sb800, 0); + mptable_add_isa_interrupts(mc, bus_isa, apicid_hudson, 0); /* PCI interrupts are level triggered, and are * associated with a specific bus/device/function tuple. */ #define PCI_INT(bus, dev, int_sign, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), apicid_sb800, (pin)) + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), apicid_hudson, (pin)) /* Internal VGA */ PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]); @@ -156,26 +156,26 @@ static void *smp_write_config_table(void *v) /* PCI slots */ /* PCI_SLOT 0. */ - PCI_INT(bus_sb800[1], 0x5, 0x0, 0x14); - PCI_INT(bus_sb800[1], 0x5, 0x1, 0x15); - PCI_INT(bus_sb800[1], 0x5, 0x2, 0x16); - PCI_INT(bus_sb800[1], 0x5, 0x3, 0x17); + PCI_INT(bus_hudson[1], 0x5, 0x0, 0x14); + PCI_INT(bus_hudson[1], 0x5, 0x1, 0x15); + PCI_INT(bus_hudson[1], 0x5, 0x2, 0x16); + PCI_INT(bus_hudson[1], 0x5, 0x3, 0x17); /* PCI_SLOT 1. */ - PCI_INT(bus_sb800[1], 0x6, 0x0, 0x15); - PCI_INT(bus_sb800[1], 0x6, 0x1, 0x16); - PCI_INT(bus_sb800[1], 0x6, 0x2, 0x17); - PCI_INT(bus_sb800[1], 0x6, 0x3, 0x14); + PCI_INT(bus_hudson[1], 0x6, 0x0, 0x15); + PCI_INT(bus_hudson[1], 0x6, 0x1, 0x16); + PCI_INT(bus_hudson[1], 0x6, 0x2, 0x17); + PCI_INT(bus_hudson[1], 0x6, 0x3, 0x14); /* PCI_SLOT 2. */ - PCI_INT(bus_sb800[1], 0x7, 0x0, 0x16); - PCI_INT(bus_sb800[1], 0x7, 0x1, 0x17); - PCI_INT(bus_sb800[1], 0x7, 0x2, 0x14); - PCI_INT(bus_sb800[1], 0x7, 0x3, 0x15); - - PCI_INT(bus_sb800[2], 0x0, 0x0, 0x12); - PCI_INT(bus_sb800[2], 0x0, 0x1, 0x13); - PCI_INT(bus_sb800[2], 0x0, 0x2, 0x14); + PCI_INT(bus_hudson[1], 0x7, 0x0, 0x16); + PCI_INT(bus_hudson[1], 0x7, 0x1, 0x17); + PCI_INT(bus_hudson[1], 0x7, 0x2, 0x14); + PCI_INT(bus_hudson[1], 0x7, 0x3, 0x15); + + PCI_INT(bus_hudson[2], 0x0, 0x0, 0x12); + PCI_INT(bus_hudson[2], 0x0, 0x1, 0x13); + PCI_INT(bus_hudson[2], 0x0, 0x2, 0x14); /* PCIe Lan*/ PCI_INT(0x0, 0x06, 0x0, 0x13); diff --git a/src/mainboard/amd/thatcher/romstage.c b/src/mainboard/amd/thatcher/romstage.c index 445fe45..1c9ab10 100644 --- a/src/mainboard/amd/thatcher/romstage.c +++ b/src/mainboard/amd/thatcher/romstage.c @@ -85,14 +85,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx); post_code(0x37); + printk(BIOS_DEBUG, "agesawrapper_amdinitreset "); val = agesawrapper_amdinitreset(); if(val) { printk(BIOS_DEBUG, "agesawrapper_amdinitreset failed: %x \n", val); } - post_code(0x38); - printk(BIOS_DEBUG, "Got past sb800_early_setup\n"); - post_code(0x39); val = agesawrapper_amdinitearly (); diff --git a/src/southbridge/amd/agesa/hudson/hudson.c b/src/southbridge/amd/agesa/hudson/hudson.c index ce541fc..71b8f49 100644 --- a/src/southbridge/amd/agesa/hudson/hudson.c +++ b/src/southbridge/amd/agesa/hudson/hudson.c @@ -99,7 +99,7 @@ u8 pm2_ioread(u8 reg) void hudson_enable(device_t dev) { - printk(BIOS_DEBUG, "sb800_enable()\n"); + printk(BIOS_DEBUG, "hudson_enable()\n"); } struct cbmem_entry *get_cbmem_toc(void) diff --git a/src/southbridge/amd/agesa/hudson/smbus.c b/src/southbridge/amd/agesa/hudson/smbus.c index 9db936c..6786b35 100644 --- a/src/southbridge/amd/agesa/hudson/smbus.c +++ b/src/southbridge/amd/agesa/hudson/smbus.c @@ -17,8 +17,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef _SB800_SMBUS_C_ -#define _SB800_SMBUS_C_ +#ifndef _HUDSON_SMBUS_C_ +#define _HUDSON_SMBUS_C_ #include "smbus.h" diff --git a/src/southbridge/amd/agesa/hudson/smbus.h b/src/southbridge/amd/agesa/hudson/smbus.h index fce8e96..83a94a1 100644 --- a/src/southbridge/amd/agesa/hudson/smbus.h +++ b/src/southbridge/amd/agesa/hudson/smbus.h @@ -17,8 +17,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef SB800_SMBUS_H -#define SB800_SMBUS_H +#ifndef HUDSON_SMBUS_H +#define HUDSON_SMBUS_H //#include <stdint.h>

1 0

Patch set updated for coreboot: a95a11a WIP: armv7/snow patch dump
by Ronald G. Minnich 18 Jan '13

18 Jan '13

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2174 -gerrit commit a95a11a0293d2be8090f6d39e9bd7cc8c97fd390 Author: David Hendricks <dhendrix(a)chromium.org> Date: Thu Jan 17 20:52:21 2013 -0800 WIP: armv7/snow patch dump ** do not submit ** This is just a patch dump so others can more easily get up to speed. The user should see a bunch of prints to the UART, and PSHOLD will be held high so the machine should not turn itself off. We are actually able to CBFS and get the romstage address successfully, but calling romstage's main() function fails... Add romstage as a stage (a later patch adds it as a binary, which is probably wrong). The Makefile magic is complex enough that we let it build the XIP file for now, but we no longer use it. replace findstage with loadstage. Loadstage will find a stage, load the code to memory, and zero the remaining part of memory. Now we can link the romstage to go anywhere! TODO: - Eliminate magic offsets (in romstage.ld and cbfs.h) - Make it so that the call to romstage's address does not switch to a mode that's incompatible with romstage's entry point. Depends-On: 2173 Change-Id: Iae4d2f9e7f429cb1df15d49daf9a08b88d75d79d Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- src/arch/armv7/Makefile.inc | 5 +-- src/arch/armv7/bootblock_simple.c | 6 +-- src/arch/armv7/include/arch/cbfs.h | 67 +++++++++++++++++++++++++++++----- src/arch/armv7/include/arch/hlt.h | 1 - src/arch/armv7/romstage.ld | 4 +- src/cpu/samsung/exynos5250/bootblock.c | 3 +- src/mainboard/google/snow/bootblock.c | 18 +++++---- src/mainboard/google/snow/romstage.c | 25 +++++++++++++ 8 files changed, 102 insertions(+), 27 deletions(-) diff --git a/src/arch/armv7/Makefile.inc b/src/arch/armv7/Makefile.inc index ecb5aee..a5833a7 100644 --- a/src/arch/armv7/Makefile.inc +++ b/src/arch/armv7/Makefile.inc @@ -215,9 +215,8 @@ $(obj)/coreboot.pre: $(objcbfs)/romstage_xip.elf $(obj)/coreboot.pre1 $(CBFSTOOL @printf " CBFS $(subst $(obj)/,,$(@))\n" cp $(obj)/coreboot.pre1 $@.tmp $(CBFSTOOL) $@.tmp add-stage \ - -f $(objcbfs)/romstage_xip.elf \ - -n $(CONFIG_CBFS_PREFIX)/romstage -c none \ - -b $(shell cat $(objcbfs)/base_xip.txt) + -f $(objcbfs)/romstage_null.debug \ + -n $(CONFIG_CBFS_PREFIX)/romstage -c none mv $@.tmp $@ ################################################################################ diff --git a/src/arch/armv7/bootblock_simple.c b/src/arch/armv7/bootblock_simple.c index 6897e15..a48a490 100644 --- a/src/arch/armv7/bootblock_simple.c +++ b/src/arch/armv7/bootblock_simple.c @@ -39,12 +39,12 @@ void main(unsigned long bist) unsigned long entry; if (boot_cpu()) { - bootblock_mainboard_init(); bootblock_cpu_init(); + bootblock_mainboard_init(); } - entry = findstage(target1); + entry = loadstage(target1); + printk(BIOS_INFO, "entry: 0x%08lx\n", entry); if (entry) call(entry); - hlt(); } diff --git a/src/arch/armv7/include/arch/cbfs.h b/src/arch/armv7/include/arch/cbfs.h index 0affa5e..86c94d0 100644 --- a/src/arch/armv7/include/arch/cbfs.h +++ b/src/arch/armv7/include/arch/cbfs.h @@ -26,42 +26,91 @@ #include <arch/byteorder.h> #include <arch/cbfs.h> + static int cbfs_check_magic(struct cbfs_file *file) { - return !strcmp(file->magic, CBFS_FILE_MAGIC) ? 1 : 0; + return strcmp(file->magic, CBFS_FILE_MAGIC) ? 0 : 1; } -static unsigned long findstage(const char* target) +static unsigned long loadstage(const char* target) { unsigned long offset, align; /* FIXME: magic offsets */ - struct cbfs_header *header = (struct cbfs_header *)(0x02023400 + 0x40); + struct cbfs_header *header = (struct cbfs_header *)(0x02062040); // if (ntohl(header->magic) != CBFS_HEADER_MAGIC) // printk(BIOS_ERR, "ERROR: No valid CBFS header found!\n"); offset = ntohl(header->offset); align = ntohl(header->align); + printk(BIOS_INFO, "cbfs header (%p)\n", header); + printk(BIOS_INFO, "\tmagic: 0x%08x\n", ntohl(header->magic)); + printk(BIOS_INFO, "\tversion: 0x%08x\n", ntohl(header->version)); + printk(BIOS_INFO, "\tromsize: 0x%08x\n", ntohl(header->romsize)); + printk(BIOS_INFO, "\tbootblocksize: 0x%08x\n", ntohl(header->bootblocksize)); + printk(BIOS_INFO, "\talign: 0x%08x\n", ntohl(header->align)); + printk(BIOS_INFO, "\toffset: 0x%08x\n", ntohl(header->offset)); while(1) { struct cbfs_file *file; - file = (struct cbfs_file *)(offset + CONFIG_ROMSTAGE_BASE); - if (!cbfs_check_magic(file)) + struct cbfs_stage *stage; + file = (struct cbfs_file *)(offset + 0x02060000); + if (!cbfs_check_magic(file)) { + printk(BIOS_INFO, "magic is wrong, file: %p\n", file); return 0; - if (!strcmp(CBFS_NAME(file), target)) - return (unsigned long)CBFS_SUBHEADER(file); + } + if (!strcmp(CBFS_NAME(file), target)) { + uint32_t load, entry; + printk(BIOS_INFO, "CBFS name matched, offset: %p\n", file); + printk(BIOS_INFO, "\tmagic: %02x%02x%02x%02x%02x%02x%02x%02x\n", + file->magic[0], file->magic[1], file->magic[2], file->magic[3], + file->magic[4], file->magic[5], file->magic[6], file->magic[7]); + printk(BIOS_INFO, "\tlen: 0x%08x\n", ntohl(file->len)); + printk(BIOS_INFO, "\ttype: 0x%08x\n", ntohl(file->type)); + printk(BIOS_INFO, "\tchecksum: 0x%08x\n", ntohl(file->checksum)); + printk(BIOS_INFO, "\toffset: 0x%08x\n", ntohl(file->offset)); + /* exploit the fact that this is all word-aligned. */ + stage = CBFS_SUBHEADER(file); + load = stage->load; + entry = stage->entry; + int i; + u32 *to = (void *)load; + u32 *from = (void *)((u8 *)stage+sizeof(*stage)); + /* we could do memmove/memset here. But the math gets messy. + * far easier just to do what we want. + */ + for(i = 0; i < stage->len; i += 4) + *to++ = *from++; + for(; i < stage->memlen; i += 4) + *to++ = 0; + return entry; + } int flen = ntohl(file->len); int foffset = ntohl(file->offset); unsigned long oldoffset = offset; offset = ALIGN(offset + foffset + flen, align); + printk(BIOS_INFO, "offset: 0x%08lx\n", offset); if (offset <= oldoffset) return 0; - if (offset < CONFIG_ROMSTAGE_BASE + ntohl(header->romsize)); + if (offset > (128 * 1024)) return 0; } } static inline void call(unsigned long addr) { - void (*doit)(void) = (void *)addr; + __attribute__((noreturn)) void (*doit)(void) = (void *)addr; + printk(BIOS_INFO, "addr: %08lx, doit: %p\n", addr, doit); +#if 0 + /* FIXME: dumping SRAM content for sanity checking */ +// int i; + for (i = 0; i < 0x10000; i++) { + if (i % 16 == 0) + printk(BIOS_INFO, "\n0x%08lx: ", addr + i); + else + printk(BIOS_INFO, " "); + printk(BIOS_INFO, "%02x", *(uint8_t *)(addr + i)); + } +#endif + /* FIXME: do we need to change to/from arm/thumb? */ doit(); } #endif diff --git a/src/arch/armv7/include/arch/hlt.h b/src/arch/armv7/include/arch/hlt.h index 535508a..285b6f8 100644 --- a/src/arch/armv7/include/arch/hlt.h +++ b/src/arch/armv7/include/arch/hlt.h @@ -4,7 +4,6 @@ static inline __attribute__((always_inline)) void hlt(void) { for (;;) ; - //asm("hlt"); } #endif /* ARCH_HLT_H */ diff --git a/src/arch/armv7/romstage.ld b/src/arch/armv7/romstage.ld index d40d2ef..bf1b094 100644 --- a/src/arch/armv7/romstage.ld +++ b/src/arch/armv7/romstage.ld @@ -35,11 +35,11 @@ OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") OUTPUT_ARCH(arm) -/* ENTRY(_start) */ +ENTRY(_start) SECTIONS { - . = 0x02023400 + 0x4000; + . = 0x02065438; .romtext . : { _rom = .; diff --git a/src/cpu/samsung/exynos5250/bootblock.c b/src/cpu/samsung/exynos5250/bootblock.c index 0d65676..2852764 100644 --- a/src/cpu/samsung/exynos5250/bootblock.c +++ b/src/cpu/samsung/exynos5250/bootblock.c @@ -36,5 +36,6 @@ static int config_branch_prediction(int set_cr_z) void bootblock_cpu_init(void); void bootblock_cpu_init(void) { - /* FIXME: this is a stub for now */ + volatile unsigned long *pshold = (unsigned long *)0x1004330c; + *pshold |= 0x100; } diff --git a/src/mainboard/google/snow/bootblock.c b/src/mainboard/google/snow/bootblock.c index a025b28..48854a7 100644 --- a/src/mainboard/google/snow/bootblock.c +++ b/src/mainboard/google/snow/bootblock.c @@ -42,8 +42,6 @@ #define EXYNOS5_CLOCK_BASE 0x10010000 -volatile unsigned long *pshold = (unsigned long *)0x1004330c; - /* FIXME(dhendrix): Can we move this SPI stuff elsewhere? */ static void spi_rx_tx(struct exynos_spi *regs, int todo, void *dinp, void const *doutp, int i) @@ -723,6 +721,9 @@ static void exynos5_uart_tx_byte(unsigned char data) // struct s5p_uart *const uart = s5p_get_base_uart(dev_index); struct s5p_uart *uart = (struct s5p_uart *)uart3_base; + if (data == '\n') + exynos5_uart_tx_byte('\r'); + /* wait for room in the tx FIFO */ while ((readl(uart->ufstat) & TX_FIFO_FULL_MASK)) { if (exynos5_uart_err_check(1)) @@ -738,12 +739,13 @@ void puts(const char *s) int n = 0; while (*s) { + if (*s == '\n') { + exynos5_uart_tx_byte(0xd); /* CR */ + } + exynos5_uart_tx_byte(*s++); n++; } - - exynos5_uart_tx_byte(0xd); /* CR */ - exynos5_uart_tx_byte(0xa); /* LF */ } static void do_serial(void) @@ -2140,7 +2142,7 @@ void bootblock_mainboard_init(void) printk(BIOS_INFO, "%s: hello world\n", __func__); /* Copy romstage data from SPI ROM to SRAM */ - /* FIXME: test with something benign, then fix the offsets once - we're more confident in this */ - copy_romstage(0x2000, 0x2060000, 0x800); + /* FIXME: magic offsets */ + copy_romstage(0x0, 0x2060000, 0x10000); + printk(BIOS_INFO, "%s: goodbye world\n", __func__); } diff --git a/src/mainboard/google/snow/romstage.c b/src/mainboard/google/snow/romstage.c index 9092b7c..859c69e 100644 --- a/src/mainboard/google/snow/romstage.c +++ b/src/mainboard/google/snow/romstage.c @@ -21,6 +21,22 @@ #include <system.h> #include <cache.h> +#if 0 +#include <arch/io.h> + +/* FIXME: make i2c.h use standard types */ +#define uchar unsigned char +#define uint unsigned int +#include <device/i2c.h> + +#include <cpu/samsung/s5p-common/s3c24x0_i2c.h> +#include "cpu/samsung/exynos5250/dmc.h" +#include <cpu/samsung/exynos5250/power.h> +#include <cpu/samsung/exynos5250/clock_init.h> +#include <cpu/samsung/exynos5-common/uart.h> +#endif +#include <console/console.h> + static void mmu_setup(void) { dram_bank_mmu_setup(CONFIG_SYS_SDRAM_BASE, CONFIG_DRAM_SIZE_MB * 1024); @@ -28,5 +44,14 @@ static void mmu_setup(void) void main(void) { +// volatile unsigned long *pshold = (unsigned long *)0x1004330c; +// i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); +// power_init(); +// clock_init(); +// exynos_pinmux_config(PERIPH_ID_UART3, PINMUX_FLAG_NONE); + console_init(); + printk(BIOS_INFO, "hello from romstage\n"); + +// *pshold &= ~0x100; /* shut down */ mmu_setup(); }

1 0

Patch set updated for coreboot: de59280 WIP: armv7/snow patch dump
by Ronald G. Minnich 18 Jan '13

18 Jan '13

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2174 -gerrit commit de5928033384323251099d77d53c1fa155eb28b3 Author: David Hendricks <dhendrix(a)chromium.org> Date: Thu Jan 17 20:52:21 2013 -0800 WIP: armv7/snow patch dump ** do not submit ** This is just a patch dump so others can more easily get up to speed. The user should see a bunch of prints to the UART, and PSHOLD will be held high so the machine should not turn itself off. We are actually able to CBFS and get the romstage address successfully, but calling romstage's main() function fails... Add romstage as a stage (a later patch adds it as a binary, which is probably wrong). The Makefile magic is complex enough that we let it build the XIP file for now, but we don't use it. The next change will call the romstage stage. TODO: - Eliminate magic offsets (in romstage.ld and cbfs.h) - Make it so that the call to romstage's address does not switch to a mode that's incompatible with romstage's entry point. Depends-On: 2173 Change-Id: Iae4d2f9e7f429cb1df15d49daf9a08b88d75d79d Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- src/arch/armv7/Makefile.inc | 3 +-- src/arch/armv7/bootblock_simple.c | 4 +-- src/arch/armv7/include/arch/cbfs.h | 46 ++++++++++++++++++++++++++++------ src/arch/armv7/include/arch/hlt.h | 1 - src/arch/armv7/romstage.ld | 4 +-- src/cpu/samsung/exynos5250/bootblock.c | 3 ++- src/mainboard/google/snow/bootblock.c | 18 +++++++------ src/mainboard/google/snow/romstage.c | 25 ++++++++++++++++++ 8 files changed, 81 insertions(+), 23 deletions(-) diff --git a/src/arch/armv7/Makefile.inc b/src/arch/armv7/Makefile.inc index ecb5aee..45b96fc 100644 --- a/src/arch/armv7/Makefile.inc +++ b/src/arch/armv7/Makefile.inc @@ -215,9 +215,8 @@ $(obj)/coreboot.pre: $(objcbfs)/romstage_xip.elf $(obj)/coreboot.pre1 $(CBFSTOOL @printf " CBFS $(subst $(obj)/,,$(@))\n" cp $(obj)/coreboot.pre1 $@.tmp $(CBFSTOOL) $@.tmp add-stage \ - -f $(objcbfs)/romstage_xip.elf \ + -f $(objcbfs)/romstage_null.debug \ -n $(CONFIG_CBFS_PREFIX)/romstage -c none \ - -b $(shell cat $(objcbfs)/base_xip.txt) mv $@.tmp $@ ################################################################################ diff --git a/src/arch/armv7/bootblock_simple.c b/src/arch/armv7/bootblock_simple.c index 6897e15..de6269a 100644 --- a/src/arch/armv7/bootblock_simple.c +++ b/src/arch/armv7/bootblock_simple.c @@ -39,12 +39,12 @@ void main(unsigned long bist) unsigned long entry; if (boot_cpu()) { - bootblock_mainboard_init(); bootblock_cpu_init(); + bootblock_mainboard_init(); } entry = findstage(target1); + printk(BIOS_INFO, "entry: 0x%08lx\n", entry); if (entry) call(entry); - hlt(); } diff --git a/src/arch/armv7/include/arch/cbfs.h b/src/arch/armv7/include/arch/cbfs.h index 0affa5e..f19e7e6 100644 --- a/src/arch/armv7/include/arch/cbfs.h +++ b/src/arch/armv7/include/arch/cbfs.h @@ -28,40 +28,72 @@ static int cbfs_check_magic(struct cbfs_file *file) { - return !strcmp(file->magic, CBFS_FILE_MAGIC) ? 1 : 0; + return strcmp(file->magic, CBFS_FILE_MAGIC) ? 0 : 1; } static unsigned long findstage(const char* target) { unsigned long offset, align; /* FIXME: magic offsets */ - struct cbfs_header *header = (struct cbfs_header *)(0x02023400 + 0x40); + struct cbfs_header *header = (struct cbfs_header *)(0x02062040); // if (ntohl(header->magic) != CBFS_HEADER_MAGIC) // printk(BIOS_ERR, "ERROR: No valid CBFS header found!\n"); offset = ntohl(header->offset); align = ntohl(header->align); + printk(BIOS_INFO, "cbfs header (%p)\n", header); + printk(BIOS_INFO, "\tmagic: 0x%08x\n", ntohl(header->magic)); + printk(BIOS_INFO, "\tversion: 0x%08x\n", ntohl(header->version)); + printk(BIOS_INFO, "\tromsize: 0x%08x\n", ntohl(header->romsize)); + printk(BIOS_INFO, "\tbootblocksize: 0x%08x\n", ntohl(header->bootblocksize)); + printk(BIOS_INFO, "\talign: 0x%08x\n", ntohl(header->align)); + printk(BIOS_INFO, "\toffset: 0x%08x\n", ntohl(header->offset)); while(1) { struct cbfs_file *file; - file = (struct cbfs_file *)(offset + CONFIG_ROMSTAGE_BASE); - if (!cbfs_check_magic(file)) + file = (struct cbfs_file *)(offset + 0x02060000); + if (!cbfs_check_magic(file)) { + printk(BIOS_INFO, "magic is wrong, file: %p\n", file); return 0; - if (!strcmp(CBFS_NAME(file), target)) + } + if (!strcmp(CBFS_NAME(file), target)) { + printk(BIOS_INFO, "CBFS name matched, offset: %p\n", file); + printk(BIOS_INFO, "\tmagic: %02x%02x%02x%02x%02x%02x%02x%02x\n", + file->magic[0], file->magic[1], file->magic[2], file->magic[3], + file->magic[4], file->magic[5], file->magic[6], file->magic[7]); + printk(BIOS_INFO, "\tlen: 0x%08x\n", ntohl(file->len)); + printk(BIOS_INFO, "\ttype: 0x%08x\n", ntohl(file->type)); + printk(BIOS_INFO, "\tchecksum: 0x%08x\n", ntohl(file->checksum)); + printk(BIOS_INFO, "\toffset: 0x%08x\n", ntohl(file->offset)); return (unsigned long)CBFS_SUBHEADER(file); + } int flen = ntohl(file->len); int foffset = ntohl(file->offset); unsigned long oldoffset = offset; offset = ALIGN(offset + foffset + flen, align); + printk(BIOS_INFO, "offset: 0x%08lx\n", offset); if (offset <= oldoffset) return 0; - if (offset < CONFIG_ROMSTAGE_BASE + ntohl(header->romsize)); + if (offset > (128 * 1024)) return 0; } } static inline void call(unsigned long addr) { - void (*doit)(void) = (void *)addr; + __attribute__((noreturn)) void (*doit)(void) = (void *)addr; + printk(BIOS_INFO, "addr: %08lx, doit: %p\n", addr, doit); +#if 0 + /* FIXME: dumping SRAM content for sanity checking */ +// int i; + for (i = 0; i < 0x10000; i++) { + if (i % 16 == 0) + printk(BIOS_INFO, "\n0x%08lx: ", addr + i); + else + printk(BIOS_INFO, " "); + printk(BIOS_INFO, "%02x", *(uint8_t *)(addr + i)); + } +#endif + /* FIXME: do we need to change to/from arm/thumb? */ doit(); } #endif diff --git a/src/arch/armv7/include/arch/hlt.h b/src/arch/armv7/include/arch/hlt.h index 535508a..285b6f8 100644 --- a/src/arch/armv7/include/arch/hlt.h +++ b/src/arch/armv7/include/arch/hlt.h @@ -4,7 +4,6 @@ static inline __attribute__((always_inline)) void hlt(void) { for (;;) ; - //asm("hlt"); } #endif /* ARCH_HLT_H */ diff --git a/src/arch/armv7/romstage.ld b/src/arch/armv7/romstage.ld index d40d2ef..bf1b094 100644 --- a/src/arch/armv7/romstage.ld +++ b/src/arch/armv7/romstage.ld @@ -35,11 +35,11 @@ OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") OUTPUT_ARCH(arm) -/* ENTRY(_start) */ +ENTRY(_start) SECTIONS { - . = 0x02023400 + 0x4000; + . = 0x02065438; .romtext . : { _rom = .; diff --git a/src/cpu/samsung/exynos5250/bootblock.c b/src/cpu/samsung/exynos5250/bootblock.c index 0d65676..2852764 100644 --- a/src/cpu/samsung/exynos5250/bootblock.c +++ b/src/cpu/samsung/exynos5250/bootblock.c @@ -36,5 +36,6 @@ static int config_branch_prediction(int set_cr_z) void bootblock_cpu_init(void); void bootblock_cpu_init(void) { - /* FIXME: this is a stub for now */ + volatile unsigned long *pshold = (unsigned long *)0x1004330c; + *pshold |= 0x100; } diff --git a/src/mainboard/google/snow/bootblock.c b/src/mainboard/google/snow/bootblock.c index a025b28..48854a7 100644 --- a/src/mainboard/google/snow/bootblock.c +++ b/src/mainboard/google/snow/bootblock.c @@ -42,8 +42,6 @@ #define EXYNOS5_CLOCK_BASE 0x10010000 -volatile unsigned long *pshold = (unsigned long *)0x1004330c; - /* FIXME(dhendrix): Can we move this SPI stuff elsewhere? */ static void spi_rx_tx(struct exynos_spi *regs, int todo, void *dinp, void const *doutp, int i) @@ -723,6 +721,9 @@ static void exynos5_uart_tx_byte(unsigned char data) // struct s5p_uart *const uart = s5p_get_base_uart(dev_index); struct s5p_uart *uart = (struct s5p_uart *)uart3_base; + if (data == '\n') + exynos5_uart_tx_byte('\r'); + /* wait for room in the tx FIFO */ while ((readl(uart->ufstat) & TX_FIFO_FULL_MASK)) { if (exynos5_uart_err_check(1)) @@ -738,12 +739,13 @@ void puts(const char *s) int n = 0; while (*s) { + if (*s == '\n') { + exynos5_uart_tx_byte(0xd); /* CR */ + } + exynos5_uart_tx_byte(*s++); n++; } - - exynos5_uart_tx_byte(0xd); /* CR */ - exynos5_uart_tx_byte(0xa); /* LF */ } static void do_serial(void) @@ -2140,7 +2142,7 @@ void bootblock_mainboard_init(void) printk(BIOS_INFO, "%s: hello world\n", __func__); /* Copy romstage data from SPI ROM to SRAM */ - /* FIXME: test with something benign, then fix the offsets once - we're more confident in this */ - copy_romstage(0x2000, 0x2060000, 0x800); + /* FIXME: magic offsets */ + copy_romstage(0x0, 0x2060000, 0x10000); + printk(BIOS_INFO, "%s: goodbye world\n", __func__); } diff --git a/src/mainboard/google/snow/romstage.c b/src/mainboard/google/snow/romstage.c index 9092b7c..859c69e 100644 --- a/src/mainboard/google/snow/romstage.c +++ b/src/mainboard/google/snow/romstage.c @@ -21,6 +21,22 @@ #include <system.h> #include <cache.h> +#if 0 +#include <arch/io.h> + +/* FIXME: make i2c.h use standard types */ +#define uchar unsigned char +#define uint unsigned int +#include <device/i2c.h> + +#include <cpu/samsung/s5p-common/s3c24x0_i2c.h> +#include "cpu/samsung/exynos5250/dmc.h" +#include <cpu/samsung/exynos5250/power.h> +#include <cpu/samsung/exynos5250/clock_init.h> +#include <cpu/samsung/exynos5-common/uart.h> +#endif +#include <console/console.h> + static void mmu_setup(void) { dram_bank_mmu_setup(CONFIG_SYS_SDRAM_BASE, CONFIG_DRAM_SIZE_MB * 1024); @@ -28,5 +44,14 @@ static void mmu_setup(void) void main(void) { +// volatile unsigned long *pshold = (unsigned long *)0x1004330c; +// i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); +// power_init(); +// clock_init(); +// exynos_pinmux_config(PERIPH_ID_UART3, PINMUX_FLAG_NONE); + console_init(); + printk(BIOS_INFO, "hello from romstage\n"); + +// *pshold &= ~0x100; /* shut down */ mmu_setup(); }

1 0

New patch to review for coreboot: 458599f Add more information to the cbfstool print
by Ronald G. Minnich 18 Jan '13

18 Jan '13

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2176 -gerrit commit 458599f0754c6b73a8b0293a906960a63891f720 Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Fri Jan 18 10:58:42 2013 -0600 Add more information to the cbfstool print Show what's in a stage or payload. This will let people better understand what's in a stage or payload. Change-Id: If6d9a877b4aedd5cece76774e41f0daadb20c008 Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- util/cbfstool/cbfs.h | 2 ++ util/cbfstool/common.c | 58 +++++++++++++++++++++++++++++++++++++++++++++----- 2 files changed, 55 insertions(+), 5 deletions(-) diff --git a/util/cbfstool/cbfs.h b/util/cbfstool/cbfs.h index 617eeee..3dbeefd 100644 --- a/util/cbfstool/cbfs.h +++ b/util/cbfstool/cbfs.h @@ -106,6 +106,8 @@ struct cbfs_payload { #define CBFS_COMPONENT_NULL 0xFFFFFFFF int cbfs_file_header(unsigned long physaddr); +#define CBFS_SUBHEADER(_p) ( (void *) ((((uint8_t *) (_p)) + ntohl((_p)->offset))) ) + struct cbfs_file *cbfs_create_empty_file(uint32_t physaddr, uint32_t size); #endif diff --git a/util/cbfstool/common.c b/util/cbfstool/common.c index 5413958..deedb47 100644 --- a/util/cbfstool/common.c +++ b/util/cbfstool/common.c @@ -274,10 +274,10 @@ uint64_t intfiletype(const char *name) void print_cbfs_directory(const char *filename) { printf - ("%s: %d kB, bootblocksize %d, romsize %d, offset 0x%x\n" - "alignment: %d bytes, architecture: %s\n\n", - basename((char *)filename), romsize / 1024, ntohl(master_header->bootblocksize), - romsize, ntohl(master_header->offset), align, arch_to_string(arch)); + ("%s: %d kB, bootblocksize %d, romsize %d, offset 0x%x\n" + "alignment: %d bytes, architecture: %s\n\n", + basename((char *)filename), romsize / 1024, ntohl(master_header->bootblocksize), + romsize, ntohl(master_header->offset), align, arch_to_string(arch)); printf("%-30s %-10s %-12s Size\n", "Name", "Offset", "Type"); uint32_t current = phys_start; while (current < phys_end) { @@ -286,7 +286,7 @@ void print_cbfs_directory(const char *filename) continue; } struct cbfs_file *thisfile = - (struct cbfs_file *)phys_to_virt(current); + (struct cbfs_file *)phys_to_virt(current); uint32_t length = ntohl(thisfile->len); char *fname = (char *)(phys_to_virt(current) + sizeof(struct cbfs_file)); if (strlen(fname) == 0) @@ -295,6 +295,54 @@ void print_cbfs_directory(const char *filename) printf("%-30s 0x%-8x %-12s %d\n", fname, current - phys_start + ntohl(master_header->offset), strfiletype(ntohl(thisfile->type)), length); + /* note the components of the subheader are in host order ... */ + switch(ntohl(thisfile->type)){ + case CBFS_COMPONENT_STAGE: + { + struct cbfs_stage *stage = CBFS_SUBHEADER(thisfile); + printf("\tcompression:%x,entry:%016llx,load:%016llx,len:0x%x,memlen:0x%x\n", + stage->compression, + stage->entry, + stage->load, + stage->len, + stage->memlen); + break; + } + case CBFS_COMPONENT_PAYLOAD: + { + struct cbfs_payload_segment *payload = CBFS_SUBHEADER(thisfile); + printf("\ttype:%x,compression:%x,offset:0x%x,load:%016llx,len:0x%x,memlen:0x%x\n", + payload->type, + payload->compression, + payload->offset, + payload->load_addr, + payload->len, + payload->mem_len); + break; + } + case CBFS_COMPONENT_OPTIONROM: + break; + case CBFS_COMPONENT_BOOTSPLASH: + break; + case CBFS_COMPONENT_RAW: + break; + case CBFS_COMPONENT_VSA: + break; + case CBFS_COMPONENT_MBI: + break; + case CBFS_COMPONENT_MICROCODE: + break; + case CBFS_COMPONENT_CMOS_DEFAULT: + break; + case CBFS_COMPONENT_CMOS_LAYOUT: + break; + case CBFS_COMPONENT_DELETED: + break; + case CBFS_COMPONENT_NULL: + break; + default: + break; + } current = ALIGN(current + ntohl(thisfile->len) + ntohl(thisfile->offset), align);

1 0

Patch set updated for coreboot: fe4d2f2 armv7: add a wrapper for romstage's main() for ARM ISA
by Hung-Te Lin 18 Jan '13

18 Jan '13

Hung-Te Lin (hungte(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2175 -gerrit commit fe4d2f2896efa1d5fc808510850b51f147ff6ecb Author: David Hendricks <dhendrix(a)chromium.org> Date: Thu Jan 17 22:26:36 2013 -0800 armv7: add a wrapper for romstage's main() for ARM ISA This adds a wrapper around main() in romstage which is compiled using -marm. This assumes that the bootblock branches to romstage in ARM mode. (credit to Gabe Black for writing the patch, I'm just uploading it) Change-Id: I4fdb8d2c6c2c0a7178bcb9154c378ddce0567309 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/arch/armv7/Makefile.inc | 13 ++++++++++--- src/arch/armv7/romstage.ld | 2 ++ src/arch/armv7/romstage_main.c | 29 +++++++++++++++++++++++++++++ src/mainboard/google/snow/romstage.c | 1 + 4 files changed, 42 insertions(+), 3 deletions(-) diff --git a/src/arch/armv7/Makefile.inc b/src/arch/armv7/Makefile.inc index 9a3e95f..ff264c5 100644 --- a/src/arch/armv7/Makefile.inc +++ b/src/arch/armv7/Makefile.inc @@ -245,13 +245,20 @@ endif ################################################################################ # Build the romstage +romstage_main_c = $(src)/arch/armv7/romstage_main.c +romstage_main_o = $(obj)/arch/armv7/romstage_main.o + +$(romstage_main_o): $(romstage_main_c) + @printf " CC $(subst $(obj)/,,$(@))\n" + $(CC) -nostdlib -nostartfiles -static -c -o $@ $< -marm + # FIXME(dhendrix): added debug printfs -$(objcbfs)/romstage.debug: $$(romstage-objs) $(objgenerated)/romstage.ld +$(objcbfs)/romstage.debug: $$(romstage-objs) $(romstage_main_o) $(objgenerated)/romstage.ld @printf " LINK $(subst $(obj)/,,$(@))\n" ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) - $(LD) -nostdlib -nostartfiles -static -o $@ -L$(obj) $(romstage-objs) -T $(objgenerated)/romstage.ld + $(LD) -nostdlib -nostartfiles -static -o $@ -L$(obj) $(romstage-objs) $(romstage_main_o) -T $(objgenerated)/romstage.ld else - $(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(objgenerated)/romstage.ld -Wl,--start-group $(romstage-objs) $(LIBGCC_FILE_NAME) -Wl,--end-group + $(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(objgenerated)/romstage.ld -Wl,--start-group $(romstage-objs) $(romstage_main_o) $(LIBGCC_FILE_NAME) -Wl,--end-group endif $(objgenerated)/romstage.ld: $$(ldscripts) $(obj)/ldoptions diff --git a/src/arch/armv7/romstage.ld b/src/arch/armv7/romstage.ld index bf1b094..120a1ae 100644 --- a/src/arch/armv7/romstage.ld +++ b/src/arch/armv7/romstage.ld @@ -39,11 +39,13 @@ ENTRY(_start) SECTIONS { + /* TODO make this a configurable option (per chipset). */ . = 0x02065438; .romtext . : { _rom = .; _start = .; + *(.text.entry.armv7); *(.text.startup); *(.text); } diff --git a/src/arch/armv7/romstage_main.c b/src/arch/armv7/romstage_main.c new file mode 100644 index 0000000..0b463b8 --- /dev/null +++ b/src/arch/armv7/romstage_main.c @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +void main(void); + +/* romstage_main is simply a stub to invoke main(), to handle ARM mode switching + * (ARM/Thumb) properly. */ + +void romstage_main(void) __attribute__((section(".text.entry.armv7"))); +void romstage_main(void) +{ + main(); +} diff --git a/src/mainboard/google/snow/romstage.c b/src/mainboard/google/snow/romstage.c index 859c69e..45016a5 100644 --- a/src/mainboard/google/snow/romstage.c +++ b/src/mainboard/google/snow/romstage.c @@ -42,6 +42,7 @@ static void mmu_setup(void) dram_bank_mmu_setup(CONFIG_SYS_SDRAM_BASE, CONFIG_DRAM_SIZE_MB * 1024); } +void main(void); void main(void) { // volatile unsigned long *pshold = (unsigned long *)0x1004330c;

1 0

X201 porting
by Vladimir 'φ-coder/phcoder' Serbinenko 18 Jan '13

18 Jan '13

Hello, all. I've began porting coreboot to X201 laptop. I've analysed the original firmware (Phoenix). Video in original firmware is inited by VGA ROM. The firmware chip is an MX25L6445E SOIC8 package, 8 Mibibytes. Flashable externally with buspirate but you need an additional power supply and make sure that cable from chip to buspirate don't exceed ~10cm. One part of original consists of EFI executables. I've replaced the executables there with my own and when it ran, the RAM was already inited but not PCI. I attach the pcidump and memory maps from normal boot (normalboot.txt) and when I insert GRUB in BIOS (grubinbios.txt). As you can see the devices visible in both modes differ. Especially communication controllers and PCI-PCI bridge. I attach 2 programs: x201_analyze and x201_reconstruct. With them you can split the original (and create descriptive XML) and then recreate firmware with changed files. I could with it also remove files from pack 1 in order to free up some space and so modified BIOSes continued to boot. lzint code is borrowed from phdeco. Right now the only working output console is through the use of system speaker ("spkmodem") and analysing it on another machine. The keyboard works for input. I've added "spkmodem" to GRUB for this but this code depends on having calibrated TSC. I'll adjust it to use only PIT instead and will contribute to coreboot then. My next step is to remove all parts of original BIOS which are not used to executed before the point I was able to take over and put in a coreboot in freed space and launch it from small .efi to take over the boot at this point. How much more init is needed from this point to booted kernel? Especially how much new code fro coreboot is needed. In the next stage I'l be working on eliminating original memory initer and replace it with coreboot one. -- Regards Vladimir 'φ-coder/phcoder' Serbinenko

2 2

Patch set updated for coreboot: 7ddbe1a armv7: add a wrapper for romstage's main() for ARM ISA
by Hung-Te Lin 18 Jan '13

18 Jan '13

Hung-Te Lin (hungte(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2175 -gerrit commit 7ddbe1a17bfdeacb0f9f43f7af9d28a19b897d8a Author: David Hendricks <dhendrix(a)chromium.org> Date: Thu Jan 17 22:26:36 2013 -0800 armv7: add a wrapper for romstage's main() for ARM ISA This adds a wrapper around main() in romstage which is compiled using -marm. This assumes that the bootblock branches to romstage in ARM mode. (credit to Gabe Black for writing the patch, I'm just uploading it) Change-Id: I4fdb8d2c6c2c0a7178bcb9154c378ddce0567309 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/arch/armv7/Makefile.inc | 13 ++++++++++--- src/arch/armv7/romstage_main.c | 26 ++++++++++++++++++++++++++ src/mainboard/google/snow/romstage.c | 3 ++- 3 files changed, 38 insertions(+), 4 deletions(-) diff --git a/src/arch/armv7/Makefile.inc b/src/arch/armv7/Makefile.inc index 9a3e95f..ff264c5 100644 --- a/src/arch/armv7/Makefile.inc +++ b/src/arch/armv7/Makefile.inc @@ -245,13 +245,20 @@ endif ################################################################################ # Build the romstage +romstage_main_c = $(src)/arch/armv7/romstage_main.c +romstage_main_o = $(obj)/arch/armv7/romstage_main.o + +$(romstage_main_o): $(romstage_main_c) + @printf " CC $(subst $(obj)/,,$(@))\n" + $(CC) -nostdlib -nostartfiles -static -c -o $@ $< -marm + # FIXME(dhendrix): added debug printfs -$(objcbfs)/romstage.debug: $$(romstage-objs) $(objgenerated)/romstage.ld +$(objcbfs)/romstage.debug: $$(romstage-objs) $(romstage_main_o) $(objgenerated)/romstage.ld @printf " LINK $(subst $(obj)/,,$(@))\n" ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) - $(LD) -nostdlib -nostartfiles -static -o $@ -L$(obj) $(romstage-objs) -T $(objgenerated)/romstage.ld + $(LD) -nostdlib -nostartfiles -static -o $@ -L$(obj) $(romstage-objs) $(romstage_main_o) -T $(objgenerated)/romstage.ld else - $(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(objgenerated)/romstage.ld -Wl,--start-group $(romstage-objs) $(LIBGCC_FILE_NAME) -Wl,--end-group + $(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(objgenerated)/romstage.ld -Wl,--start-group $(romstage-objs) $(romstage_main_o) $(LIBGCC_FILE_NAME) -Wl,--end-group endif $(objgenerated)/romstage.ld: $$(ldscripts) $(obj)/ldoptions diff --git a/src/arch/armv7/romstage_main.c b/src/arch/armv7/romstage_main.c new file mode 100644 index 0000000..8025c80 --- /dev/null +++ b/src/arch/armv7/romstage_main.c @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +void romstage_main(void); + +void main(void) __attribute__((section(".text.startup"))); +void main(void) +{ + romstage_main(); +} diff --git a/src/mainboard/google/snow/romstage.c b/src/mainboard/google/snow/romstage.c index 859c69e..5577011 100644 --- a/src/mainboard/google/snow/romstage.c +++ b/src/mainboard/google/snow/romstage.c @@ -42,7 +42,8 @@ static void mmu_setup(void) dram_bank_mmu_setup(CONFIG_SYS_SDRAM_BASE, CONFIG_DRAM_SIZE_MB * 1024); } -void main(void) +void romstage_main(void); +void romstage_main(void) { // volatile unsigned long *pshold = (unsigned long *)0x1004330c; // i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);

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New patch to review for coreboot: c61bbd9 armv7: add a wrapper for romstage's main() for ARM ISA
by David Hendricks 18 Jan '13

18 Jan '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2175 -gerrit commit c61bbd9cbdbde5835c2067dcf4287af12bd7142d Author: David Hendricks <dhendrix(a)chromium.org> Date: Thu Jan 17 22:26:36 2013 -0800 armv7: add a wrapper for romstage's main() for ARM ISA This adds a wrapper around main() in romstage which is compiled using -marm. This assumes that the bootblock branches to romstage in ARM mode. (credit to Gabe Black for writing the patch, I'm just uploading it) Change-Id: I4fdb8d2c6c2c0a7178bcb9154c378ddce0567309 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/arch/armv7/Makefile.inc | 13 ++++++++++--- src/mainboard/google/snow/romstage.c | 3 ++- 2 files changed, 12 insertions(+), 4 deletions(-) diff --git a/src/arch/armv7/Makefile.inc b/src/arch/armv7/Makefile.inc index 9a3e95f..ff264c5 100644 --- a/src/arch/armv7/Makefile.inc +++ b/src/arch/armv7/Makefile.inc @@ -245,13 +245,20 @@ endif ################################################################################ # Build the romstage +romstage_main_c = $(src)/arch/armv7/romstage_main.c +romstage_main_o = $(obj)/arch/armv7/romstage_main.o + +$(romstage_main_o): $(romstage_main_c) + @printf " CC $(subst $(obj)/,,$(@))\n" + $(CC) -nostdlib -nostartfiles -static -c -o $@ $< -marm + # FIXME(dhendrix): added debug printfs -$(objcbfs)/romstage.debug: $$(romstage-objs) $(objgenerated)/romstage.ld +$(objcbfs)/romstage.debug: $$(romstage-objs) $(romstage_main_o) $(objgenerated)/romstage.ld @printf " LINK $(subst $(obj)/,,$(@))\n" ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) - $(LD) -nostdlib -nostartfiles -static -o $@ -L$(obj) $(romstage-objs) -T $(objgenerated)/romstage.ld + $(LD) -nostdlib -nostartfiles -static -o $@ -L$(obj) $(romstage-objs) $(romstage_main_o) -T $(objgenerated)/romstage.ld else - $(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(objgenerated)/romstage.ld -Wl,--start-group $(romstage-objs) $(LIBGCC_FILE_NAME) -Wl,--end-group + $(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(objgenerated)/romstage.ld -Wl,--start-group $(romstage-objs) $(romstage_main_o) $(LIBGCC_FILE_NAME) -Wl,--end-group endif $(objgenerated)/romstage.ld: $$(ldscripts) $(obj)/ldoptions diff --git a/src/mainboard/google/snow/romstage.c b/src/mainboard/google/snow/romstage.c index 859c69e..5577011 100644 --- a/src/mainboard/google/snow/romstage.c +++ b/src/mainboard/google/snow/romstage.c @@ -42,7 +42,8 @@ static void mmu_setup(void) dram_bank_mmu_setup(CONFIG_SYS_SDRAM_BASE, CONFIG_DRAM_SIZE_MB * 1024); } -void main(void) +void romstage_main(void); +void romstage_main(void) { // volatile unsigned long *pshold = (unsigned long *)0x1004330c; // i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);

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coreboot January 2013