coreboot January 2013

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Re: [coreboot] coreboot can boot Linux but cannot boot Windows7
by ron minnich 22 Jan '13

22 Jan '13

On Mon, Jan 21, 2013 at 6:14 PM, WANG Siyuan <wangsiyuanbuaa(a)gmail.com> wrote: > Hi, > I am debugging a board. coreboot could boot Linux and load graphic > driver, but it could not boot Windows 7. > Has anyone encountered similar problem? sure, and we had to fix it, but there is not enough information in your note to tell us what might be wrong. ron

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New patch to review for coreboot: 5f0a3fb armv7: add ARM-encoded bootblock_exit() stub
by David Hendricks 22 Jan '13

22 Jan '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2180 -gerrit commit 5f0a3fb5732821b70550a615cfd46c1da01a3646 Author: David Hendricks <dhendrix(a)chromium.org> Date: Mon Jan 21 20:02:15 2013 -0800 armv7: add ARM-encoded bootblock_exit() stub This replaces the call() function with a stub which is compiled separately using -marm. See http://review.coreboot.org/#/c/2175/ for details. Change-Id: I7f8c45b5e63ec97b0a82294488129d1c97ec0cbf Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/arch/armv7/Makefile.inc | 13 +++++++++++-- src/arch/armv7/bootblock_exit.c | 28 ++++++++++++++++++++++++++++ src/arch/armv7/bootblock_simple.c | 7 ++++--- src/arch/armv7/include/arch/bootblock_exit.h | 26 ++++++++++++++++++++++++++ src/arch/armv7/include/arch/cbfs.h | 17 ----------------- 5 files changed, 69 insertions(+), 22 deletions(-) diff --git a/src/arch/armv7/Makefile.inc b/src/arch/armv7/Makefile.inc index 2cf6ed9..872365c 100644 --- a/src/arch/armv7/Makefile.inc +++ b/src/arch/armv7/Makefile.inc @@ -239,10 +239,19 @@ $(objgenerated)/bootblock_inc.S: $$(bootblock_inc) @printf " GEN $(subst $(obj)/,,$(@))\n" printf '$(foreach crt0,$(bootblock_inc),#include "$(crt0)"\n)' > $@ +bootblock_exit_c = $(src)/arch/armv7/bootblock_exit.c +bootblock_exit_o = $(obj)/arch/armv7/bootblock_exit.o + +$(bootblock_exit_o): $(bootblock_exit_c) + @printf " CC $(subst $(obj)/,,$(@))\n" + $(CC) -Wa,-acdlns -I. $(INCLUDES) -c -o $@ $< -marm + $(objgenerated)/bootblock.o: $(objgenerated)/bootblock.s @printf " CC $(subst $(obj)/,,$(@))\n" $(CC) -Wa,-acdlns -c -o $@ $< > $(basename $(a)).disasm +BOOTBLOCK_OBJS = $(objgenerated)/bootblock.o $(bootblock_exit_o) + $(objgenerated)/bootblock.s: $(objgenerated)/bootblock_inc.S $(obj)/config.h $(obj)/build.h @printf " CC $(subst $(obj)/,,$(@))\n" $(CC) -MMD -x assembler-with-cpp -E -I$(src)/include -I$(src)/arch/armv7/include -I$(obj) -include $(obj)/build.h -include $(obj)/config.h -I. -I$(src) $< -o $@ @@ -253,12 +262,12 @@ $(objgenerated)/bootblock.inc: $(src)/arch/armv7/$(subst ",,$(CONFIG_BOOTBLOCK_S $< > $(objgenerated)/bootblock.inc.d $(CC) -c -S $(CFLAGS) -I. $(INCLUDES) $< -o $@ -$(objcbfs)/bootblock.debug: $(objgenerated)/bootblock.o $(objgenerated)/bootblock.ld +$(objcbfs)/bootblock.debug: $(BOOTBLOCK_OBJS) $(objgenerated)/bootblock.ld @printf " LINK $(subst $(obj)/,,$(@))\n" ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) $(LD) -m armelf_linux_eabi -static -o $@.tmp -L$(obj) $< -T $(objgenerated)/bootblock.ld else - $(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(objgenerated)/bootblock.ld -Wl,--start-group $< $(LIBGCC_FILE_NAME) -Wl,--end-group + $(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(objgenerated)/bootblock.ld -Wl,--start-group $(BOOTBLOCK_OBJS) $(LIBGCC_FILE_NAME) -Wl,--end-group endif ################################################################################ diff --git a/src/arch/armv7/bootblock_exit.c b/src/arch/armv7/bootblock_exit.c new file mode 100644 index 0000000..8b97d6b --- /dev/null +++ b/src/arch/armv7/bootblock_exit.c @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <arch/bootblock_exit.h> + +void bootblock_exit(unsigned long addr) +{ + __attribute__((noreturn)) void (*doit)(void) = (void *)addr; + doit(); +} diff --git a/src/arch/armv7/bootblock_simple.c b/src/arch/armv7/bootblock_simple.c index f6bcf98..af76d4c 100644 --- a/src/arch/armv7/bootblock_simple.c +++ b/src/arch/armv7/bootblock_simple.c @@ -20,6 +20,7 @@ */ #include <bootblock_common.h> +#include <arch/bootblock_exit.h> #include <arch/cbfs.h> #include <arch/hlt.h> @@ -36,7 +37,7 @@ static int boot_cpu(void) void main(unsigned long bist) { const char *target1 = "fallback/romstage"; - unsigned long entry; + unsigned long romstage_entry; if (boot_cpu()) { bootblock_cpu_init(); @@ -44,8 +45,8 @@ void main(unsigned long bist) } printk(BIOS_INFO, "bootblock main(): loading romstage\n"); - entry = loadstage(target1); + romstage_entry = loadstage(target1); printk(BIOS_INFO, "bootblock main(): jumping to romstage\n"); - if (entry) call(entry); + if (romstage_entry) bootblock_exit(romstage_entry); hlt(); } diff --git a/src/arch/armv7/include/arch/bootblock_exit.h b/src/arch/armv7/include/arch/bootblock_exit.h new file mode 100644 index 0000000..0a039e1 --- /dev/null +++ b/src/arch/armv7/include/arch/bootblock_exit.h @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +/** + * This is a shim that is to be compiled for the instruction set matching + * that of the entry point for the next boot stage (romstage). + */ +void bootblock_exit(unsigned long addr); diff --git a/src/arch/armv7/include/arch/cbfs.h b/src/arch/armv7/include/arch/cbfs.h index 99b7b43..f060643 100644 --- a/src/arch/armv7/include/arch/cbfs.h +++ b/src/arch/armv7/include/arch/cbfs.h @@ -98,21 +98,4 @@ static unsigned long loadstage(const char* target) return 0; } } - -static inline void call(unsigned long addr) -{ - __attribute__((noreturn)) void (*doit)(void) = (void *)addr; - printk(BIOS_INFO, "addr: %08lx, doit: %p\n", addr, doit); - /* FIXME: dumping SRAM content for sanity checking */ - int i; - for (i = 0; i < 128; i++) { - if (i % 16 == 0) - printk(BIOS_INFO, "\n0x%08lx: ", addr + i); - else - printk(BIOS_INFO, " "); - printk(BIOS_INFO, "%02x", *(uint8_t *)(addr + i)); - } - /* FIXME: do we need to change to/from arm/thumb? */ - doit(); -} #endif

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Patch set updated for coreboot: 8a796b4 Hudson: Legacy free question is hudson only
by Martin Roth 22 Jan '13

22 Jan '13

Martin Roth (martin.roth(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2179 -gerrit commit 8a796b494c49ebc167eba901102e8534ab87ea74 Author: Martin Roth <martin.roth(a)se-eng.com> Date: Mon Jan 21 19:33:22 2013 -0700 Hudson: Legacy free question is hudson only The "system is legacy free" question accidentally escaped from the hudson Kconfig where it was intended to stay and went coreboot-wide. This puts it back inside the boundries of the hudson southbridge where it belongs. I also commented the endif statements to make it easier to tell where things belong. Change-Id: I49f7a5eadb96d40c6101a93bc390e644617a5654 Signed-off-by: Martin Roth <martin.roth(a)se-eng.com> --- src/southbridge/amd/agesa/hudson/Kconfig | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/src/southbridge/amd/agesa/hudson/Kconfig b/src/southbridge/amd/agesa/hudson/Kconfig index 3a97e60..92e5960 100644 --- a/src/southbridge/amd/agesa/hudson/Kconfig +++ b/src/southbridge/amd/agesa/hudson/Kconfig @@ -105,7 +105,7 @@ config HUDSON_FWM_POSITION 0xFFC20000 if flash chip size is 4M 0xFF820000 if flash chip size is 8M 0xFF020000 if flash chip size is 16M -endif +endif # HUDSON_FWM choice prompt "SATA Mode" @@ -175,7 +175,7 @@ config AHCI_ROM_FILE string "AHCI ROM path and filename" depends on HUDSON_AHCI_ROM default "src/southbridge/amd/agesa/hudson/ahci.bin" -endif +endif # HUDSON_SATA_AHCI || HUDSON_SATA_AHCI7804 if HUDSON_SATA_RAID config RAID_ROM_ID @@ -202,7 +202,7 @@ config RAID_MISC_ROM_POSITION The RAID ROM requires that the MISC ROM is located between the range 0xFFF0_0000 to 0xFFF0_FFFF. Also, it must 1K bytes aligned. The CONFIG_ROM_SIZE must larger than 0x100000. -endif +endif # HUDSON_SATA_RAID config S3_VOLATILE_POS hex "S3 volatile storage position" @@ -212,10 +212,10 @@ config S3_VOLATILE_POS For a system with S3 feature, the BIOS needs to save some data to non-volitile storage at cold boot stage. -endif - config HUDSON_LEGACY_FREE bool "System is legacy free" help Select y if there is no keyboard controller in the system. This sets variables in AGESA and ACPI. + +endif # SOUTHBRIDGE_AMD_AGESA_HUDSON

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New patch to review for coreboot: 6d82f80 Hudson: Lecacy free question is hudson only
by Martin Roth 22 Jan '13

22 Jan '13

Martin Roth (martin.roth(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2179 -gerrit commit 6d82f8005a30f931d6e476d4f6fd44e718bd93aa Author: Martin Roth <martin.roth(a)se-eng.com> Date: Mon Jan 21 19:33:22 2013 -0700 Hudson: Lecacy free question is hudson only The "system is legacy free" question accidentally escaped from the hudson Kconfig where it was intended to stay and went coreboot-wide. This puts it back inside the boundries of the hudson southbridge where it belongs. I also commented the endif statements to make it easier to tell where things belong. Change-Id: I49f7a5eadb96d40c6101a93bc390e644617a5654 Signed-off-by: Martin Roth <martin.roth(a)se-eng.com> --- src/southbridge/amd/agesa/hudson/Kconfig | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/src/southbridge/amd/agesa/hudson/Kconfig b/src/southbridge/amd/agesa/hudson/Kconfig index 3a97e60..92e5960 100644 --- a/src/southbridge/amd/agesa/hudson/Kconfig +++ b/src/southbridge/amd/agesa/hudson/Kconfig @@ -105,7 +105,7 @@ config HUDSON_FWM_POSITION 0xFFC20000 if flash chip size is 4M 0xFF820000 if flash chip size is 8M 0xFF020000 if flash chip size is 16M -endif +endif # HUDSON_FWM choice prompt "SATA Mode" @@ -175,7 +175,7 @@ config AHCI_ROM_FILE string "AHCI ROM path and filename" depends on HUDSON_AHCI_ROM default "src/southbridge/amd/agesa/hudson/ahci.bin" -endif +endif # HUDSON_SATA_AHCI || HUDSON_SATA_AHCI7804 if HUDSON_SATA_RAID config RAID_ROM_ID @@ -202,7 +202,7 @@ config RAID_MISC_ROM_POSITION The RAID ROM requires that the MISC ROM is located between the range 0xFFF0_0000 to 0xFFF0_FFFF. Also, it must 1K bytes aligned. The CONFIG_ROM_SIZE must larger than 0x100000. -endif +endif # HUDSON_SATA_RAID config S3_VOLATILE_POS hex "S3 volatile storage position" @@ -212,10 +212,10 @@ config S3_VOLATILE_POS For a system with S3 feature, the BIOS needs to save some data to non-volitile storage at cold boot stage. -endif - config HUDSON_LEGACY_FREE bool "System is legacy free" help Select y if there is no keyboard controller in the system. This sets variables in AGESA and ACPI. + +endif # SOUTHBRIDGE_AMD_AGESA_HUDSON

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coreboot can boot Linux but cannot boot Windows7
by WANG Siyuan 22 Jan '13

22 Jan '13

Hi, I am debugging a board. coreboot could boot Linux and load graphic driver, but it could not boot Windows 7. Has anyone encountered similar problem? Thank you! -- Yours sincerely, WANG Siyuan

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Patch set updated for coreboot: 5d4c30d F15tn: Fix all warnings, enable warnings as errors
by Martin Roth 21 Jan '13

21 Jan '13

Martin Roth (martin.roth(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2171 -gerrit commit 5d4c30d90b2ffad4fef534e95c3b57465e33e0ec Author: Martin Roth <martin.roth(a)se-eng.com> Date: Thu Jan 17 16:28:30 2013 -0700 F15tn: Fix all warnings, enable warnings as errors Enable 'all warnings being treated as errors' in thatcher and parmer. Fixed the following warnings on parmer / thatcher: src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuFeatureLeveling.c: In function 'GetGlobalCpuFeatureListAddress': src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuFeatureLeveling.c:291:14: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] src/vendorcode/amd/agesa/f15tn/Proc/CPU/S3.c: In function 'SaveDeviceContext': src/vendorcode/amd/agesa/f15tn/Proc/CPU/S3.c:245:18: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] src/vendorcode/amd/agesa/f15tn/Proc/CPU/S3.c:309:16: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuPostInit.c: In function 'GetPstateGatherDataAddressAtPost': src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuPostInit.c:235:10: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mntn.c: In function 'MemNInitNBDataTN': src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mntn.c:353:32: warning: assignment from incompatible pointer type [enabled by default] src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mntn.c:363:23: warning: assignment from incompatible pointer type [enabled by default] src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuFeatureLeveling.c: In function 'GetGlobalCpuFeatureListAddress': src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuFeatureLeveling.c:291:14: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] src/vendorcode/amd/agesa/f15tn/Proc/CPU/S3.c: In function 'SaveDeviceContext': src/vendorcode/amd/agesa/f15tn/Proc/CPU/S3.c:245:18: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] src/vendorcode/amd/agesa/f15tn/Proc/CPU/S3.c:309:16: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] In file included from src/northbridge/amd/agesa/family15tn/northbridge.c:37:0: src/vendorcode/amd/agesa/f15tn/AGESA.h:1547:0: warning: "TOP_MEM" redefined [enabled by default] src/include/cpu/amd/mtrr.h:31:0: note: this is the location of the previous definition src/vendorcode/amd/agesa/f15tn/AGESA.h:1548:0: warning: "TOP_MEM2" redefined [enabled by default] src/include/cpu/amd/mtrr.h:34:0: note: this is the location of the previous definition In file included from src/northbridge/amd/agesa/family15tn/northbridge.c:41:0: src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuRegisters.h:378:0: warning: "LOCAL_APIC_ADDR" redefined [enabled by default] src/include/cpu/x86/lapic_def.h:9:0: note: this is the location of the previous definition In file included from src/mainboard/amd/parmer/BiosCallOuts.h:24:0, from src/mainboard/amd/parmer/mainboard.c:28: src/vendorcode/amd/agesa/f15tn/AGESA.h:1547:0: warning: "TOP_MEM" redefined [enabled by default] src/include/cpu/amd/mtrr.h:31:0: note: this is the location of the previous definition src/vendorcode/amd/agesa/f15tn/AGESA.h:1548:0: warning: "TOP_MEM2" redefined [enabled by default] src/include/cpu/amd/mtrr.h:34:0: note: this is the location of the previous definition Change-Id: Iecea28232f1761401cf09f7d2a77d3fbac2f5801 Signed-off-by: Martin Roth <martin.roth(a)se-eng.com> --- src/mainboard/amd/parmer/Kconfig | 4 ---- src/mainboard/amd/parmer/mainboard.c | 2 +- src/mainboard/amd/thatcher/Kconfig | 4 ---- src/mainboard/amd/thatcher/mainboard.c | 2 +- src/northbridge/amd/agesa/family15tn/northbridge.c | 2 +- src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuFeatureLeveling.c | 2 +- src/vendorcode/amd/agesa/f15tn/Proc/CPU/S3.c | 4 ++-- src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuPostInit.c | 2 +- src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuRegisters.h | 4 ++++ src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mntn.c | 2 +- src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/mn.c | 4 ++-- src/vendorcode/amd/agesa/f15tn/Proc/Mem/mn.h | 2 +- 12 files changed, 15 insertions(+), 19 deletions(-) diff --git a/src/mainboard/amd/parmer/Kconfig b/src/mainboard/amd/parmer/Kconfig index a4da2e2..9e42697 100644 --- a/src/mainboard/amd/parmer/Kconfig +++ b/src/mainboard/amd/parmer/Kconfig @@ -100,10 +100,6 @@ config VGA_BIOS_ID string default "1002,9900" -config WARNINGS_ARE_ERRORS - bool - default n - config HUDSON_LEGACY_FREE bool default y diff --git a/src/mainboard/amd/parmer/mainboard.c b/src/mainboard/amd/parmer/mainboard.c index a83cd42..7c5dfc0 100644 --- a/src/mainboard/amd/parmer/mainboard.c +++ b/src/mainboard/amd/parmer/mainboard.c @@ -22,10 +22,10 @@ #include <device/pci.h> #include <arch/io.h> #include <cpu/x86/msr.h> +#include "BiosCallOuts.h" #include <cpu/amd/mtrr.h> #include <device/pci_def.h> #include <arch/acpi.h> -#include "BiosCallOuts.h" #include <cpu/amd/agesa/s3_resume.h> #include "agesawrapper.h" diff --git a/src/mainboard/amd/thatcher/Kconfig b/src/mainboard/amd/thatcher/Kconfig index 0fe97fa..a68226c 100644 --- a/src/mainboard/amd/thatcher/Kconfig +++ b/src/mainboard/amd/thatcher/Kconfig @@ -101,10 +101,6 @@ config VGA_BIOS_ID string default "1002,9917" -config WARNINGS_ARE_ERRORS - bool - default n - config HUDSON_LEGACY_FREE bool default y diff --git a/src/mainboard/amd/thatcher/mainboard.c b/src/mainboard/amd/thatcher/mainboard.c index bc1d591..d1c389c 100644 --- a/src/mainboard/amd/thatcher/mainboard.c +++ b/src/mainboard/amd/thatcher/mainboard.c @@ -22,10 +22,10 @@ #include <device/pci.h> #include <arch/io.h> #include <cpu/x86/msr.h> +#include "BiosCallOuts.h" #include <cpu/amd/mtrr.h> #include <device/pci_def.h> #include <arch/acpi.h> -#include "BiosCallOuts.h" #include <cpu/amd/agesa/s3_resume.h> #include "agesawrapper.h" diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index df632e3..a22fc9d 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -29,12 +29,12 @@ #include <lib.h> #include <cpu/cpu.h> #include <cbmem.h> +#include <AGESA.h> #include <cpu/x86/lapic.h> #include <cpu/amd/mtrr.h> #include <Porting.h> -#include <AGESA.h> #include <Options.h> #include <Topology.h> #include <cpu/amd/amdfam15.h> diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuFeatureLeveling.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuFeatureLeveling.c index ffb33ab..4038181 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuFeatureLeveling.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuFeatureLeveling.c @@ -288,5 +288,5 @@ GetGlobalCpuFeatureListAddress ( AddressValue = GLOBAL_CPU_FEATURE_LIST_TEMP_ADDR; - *Address = (UINT64 *)(AddressValue); + *Address = (UINT64 *)(intptr_t)(AddressValue); } diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/S3.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/S3.c index af00f26..525bb1d 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/S3.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/S3.c @@ -242,7 +242,7 @@ SaveDeviceContext ( UINT64 EndAddress; VOID *OrMask; - StartAddress = (UINT64)DeviceList; + StartAddress = (UINT64)(intptr_t)DeviceList; Device.CommonDeviceHeader = (DEVICE_DESCRIPTOR *) &DeviceList[1]; OrMask = (UINT8 *) DeviceList + DeviceList->RelativeOrMaskOffset; @@ -306,7 +306,7 @@ SaveDeviceContext ( break; } } - EndAddress = (UINT64) OrMask; + EndAddress = (UINT64)(intptr_t)OrMask; *ActualBufferSize = (UINT32) (EndAddress - StartAddress); } diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuPostInit.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuPostInit.c index 5eda346..460955e 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuPostInit.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuPostInit.c @@ -232,7 +232,7 @@ GetPstateGatherDataAddressAtPost ( AddressValue = P_STATE_DATA_GATHER_TEMP_ADDR; - *Ptr = (UINT64 *)(AddressValue); + *Ptr = (UINT64 *)(intptr_t)(AddressValue); return AGESA_SUCCESS; } diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuRegisters.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuRegisters.h index 173044c..96e6c7f 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuRegisters.h +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuRegisters.h @@ -375,7 +375,11 @@ typedef struct { #define LAPIC_BASE_ADDR_MASK 0x0000FFFFFFFFF000ull #define APIC_EXT_BRDCST_MASK 0x000E0000ul #define APIC_ENABLE_BIT 0x00000800ul + +#ifndef LOCAL_APIC_ADDR #define LOCAL_APIC_ADDR 0xFEE00000ul +#endif + #define INT_CMD_REG_LO 0x300 #define INT_CMD_REG_HI 0x310 #define REMOTE_MSG_REG 0x380 diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mntn.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mntn.c index 63f255b..b93f4b6 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mntn.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mntn.c @@ -350,7 +350,7 @@ MemNInitNBDataTN ( NBPtr->ProgramCycTimings = MemNProgramCycTimingsUnb; NBPtr->SyncDctsReady = (BOOLEAN (*) (MEM_NB_BLOCK *)) memDefTrue; NBPtr->HtMemMapInit = MemNHtMemMapInitTN; - NBPtr->SyncAddrMapToAllNodes = (BOOLEAN (*) (MEM_NB_BLOCK *)) memDefTrue; + NBPtr->SyncAddrMapToAllNodes = (VOID (*) (MEM_NB_BLOCK *)) memDefRet; NBPtr->CpuMemTyping = MemNCPUMemTypingNb; NBPtr->BeforeDqsTraining = MemNBeforeDQSTrainingTN; NBPtr->AfterDqsTraining = MemNAfterDQSTrainingTN; diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/mn.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/mn.c index e203fd0..13900cd 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/mn.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/mn.c @@ -514,13 +514,13 @@ MemNInsDlyCompareTestPatternNb ( * * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK */ -BOOLEAN +VOID MemNTrainingFlowUnb ( IN OUT MEM_NB_BLOCK *NBPtr ) { memNTrainFlowControl[DDR3_TRAIN_FLOW] (NBPtr); - return TRUE; + return; } /*---------------------------------------------------------------------------- * LOCAL FUNCTIONS diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/mn.h b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/mn.h index 6174c98..98a78f1 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/mn.h +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/mn.h @@ -1417,7 +1417,7 @@ GetTrainDlyFromHeapNb ( IN DRBN Drbn ); -BOOLEAN +VOID MemNTrainingFlowUnb ( IN OUT MEM_NB_BLOCK *NBPtr );

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Patch merged into coreboot/master: f5726ea Hudson: Cleanup - change SB800 references to hudson
by gerrit＠coreboot.org 21 Jan '13

21 Jan '13

the following patch was just integrated into master: commit f5726ea544af904061b754fb6e369e477e93f0a5 Author: Martin Roth <martin.roth(a)se-eng.com> Date: Fri Jan 18 12:55:40 2013 -0700 Hudson: Cleanup - change SB800 references to hudson Go through southbridge/amd/agesa/hudson, thatcher and parmer mainboard directories and change all references to sb800 to reference hudson instead. This is just cleanup and should make no functional difference. Change-Id: Icd6a9a08c4bbf5e1aed394362d24c05811ed1fba Signed-off-by: Martin Roth <martin.roth(a)se-eng.com> Reviewed-on: http://review.coreboot.org/2177 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303(a)gmail.com> Reviewed-by: Dave Frodin <dave.frodin(a)se-eng.com> Build-Tested: build bot (Jenkins) at Fri Jan 18 21:06:36 2013, giving +1 Reviewed-By: Marc Jones <marcj303(a)gmail.com> at Fri Jan 18 21:39:11 2013, giving +2 See http://review.coreboot.org/2177 for details. -gerrit

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Patch merged into coreboot/master: 2892023 AGESA F15tn: Move callouts into northbridge wrapper
by gerrit＠coreboot.org 21 Jan '13

21 Jan '13

the following patch was just integrated into master: commit 2892023fd422794bb82658dde3e8d489af2bdd55 Author: Martin Roth <martin.roth(a)se-eng.com> Date: Thu Jan 17 12:04:08 2013 -0700 AGESA F15tn: Move callouts into northbridge wrapper There are currently too many things in the mainboard directories that are really more suited to being in the northbridge / southbridge wrappers. This is a start at moving some of those functions down into the wrappers. Move the bios callback functions into the northbridge/amd/agesa/family15tn directory from the mainboard directories. These can still be overridden by any mainboard just by updating the pointer in the callback table to point to a customized version of the function. Change-Id: Icefaa014f4a4abbe51870aee7aa2fa1164e324c1 Signed-off-by: Martin Roth <martin.roth(a)se-eng.com> Reviewed-on: http://review.coreboot.org/2169 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303(a)gmail.com> Build-Tested: build bot (Jenkins) at Fri Jan 18 22:46:44 2013, giving +1 Reviewed-By: Marc Jones <marcj303(a)gmail.com> at Fri Jan 18 22:57:38 2013, giving +2 See http://review.coreboot.org/2169 for details. -gerrit

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Patch merged into coreboot/master: e4cd00c Save and restore F15TN graphics command register
by gerrit＠coreboot.org 21 Jan '13

21 Jan '13

the following patch was just integrated into master: commit e4cd00cacb4b1ab374c575b972fa2662ec739642 Author: Martin Roth <martin.roth(a)se-eng.com> Date: Tue Jan 15 13:17:30 2013 -0700 Save and restore F15TN graphics command register In the AGESA routine GfxInitSview() called in the S3save path, the IO Space bit was getting cleared from the command register. This kept seabios from initializing the video bios. If the vbios was loaded by coreboot, this routine was skipped, allowing seabios to initialize vbios as well. I have modified the routine to save and restore the command register instead of clearing the IO Space bit. Change-Id: I756b0606adbc47da96780308c911852e39f547c7 Signed-off-by: Martin Roth <martin.roth(a)se-eng.com> Reviewed-on: http://review.coreboot.org/2172 Reviewed-by: Dave Frodin <dave.frodin(a)se-eng.com> Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303(a)gmail.com> Build-Tested: build bot (Jenkins) at Fri Jan 18 00:46:49 2013, giving +1 Reviewed-By: Marc Jones <marcj303(a)gmail.com> at Fri Jan 18 21:47:40 2013, giving +2 See http://review.coreboot.org/2172 for details. -gerrit

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Patch merged into coreboot/master: eac220f Hudson: Changes to support agesa/hudson for legacy free
by gerrit＠coreboot.org 21 Jan '13

21 Jan '13

the following patch was just integrated into master: commit eac220f8b5f0fc20f17d82ea270bd948a9b94c37 Author: Martin Roth <martin.roth(a)se-eng.com> Date: Wed Jan 16 09:07:30 2013 -0700 Hudson: Changes to support agesa/hudson for legacy free Add Kconfig option for Legacy free and hook it into the parmer AGESA initialization as well as the FADT code. This should really be done inside the southbridge wrapper and not in the mainboard, but for now the code to attach it to is inside the mainboard. Update Kconfig for parmer and thatcher to default to legacy free. Change-Id: Ib899bd02ddc5506caae4aca2c589cc2526638cb8 Signed-off-by: Martin Roth <martin.roth(a)se-eng.com> Reviewed-on: http://review.coreboot.org/2157 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303(a)gmail.com> Build-Tested: build bot (Jenkins) at Wed Jan 16 18:15:56 2013, giving +1 Reviewed-By: Marc Jones <marcj303(a)gmail.com> at Fri Jan 18 21:43:06 2013, giving +2 See http://review.coreboot.org/2157 for details. -gerrit

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coreboot January 2013