coreboot January 2013

coreboot@coreboot.org

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Patch merged into coreboot/master: 0fbaf18 Hudson: Changes to agesa/hudson FADT for ACPI 3.0
by gerrit＠coreboot.org 21 Jan '13

21 Jan '13

the following patch was just integrated into master: commit 0fbaf18ed4839910801905253b49c077cc1f346f Author: Martin Roth <martin(a)se-eng.com> Date: Thu Jan 10 16:40:59 2013 -0700 Hudson: Changes to agesa/hudson FADT for ACPI 3.0 Update the southbridge/amd/agesa/hudson FADT generation for ACPI 3.0 compliance similar to what was done for cimx/SB800/fadt.c in commit 9aa4389. commit 9aa43892e6899b719fe7f4754901a0eae379a934 Author: Martin Roth <martin(a)se-eng.com> Date: Fri May 25 12:23:32 2012 -0600 Update SB800 CIMX FADT According to the datasheet, PMA_CNT_BLK is no longer available and PM2_CNT_BLK should not be used. Setup for these has been removed from the table and .h file. Change-Id: Ied8eb1f26b4aa364d051ec5f7ed6f482bb440957 Signed-off-by: Martin Roth <martin(a)se-eng.com> Reviewed-on: http://review.coreboot.org/2140 Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303(a)gmail.com> Build-Tested: build bot (Jenkins) at Thu Jan 17 22:44:07 2013, giving +1 Reviewed-By: Marc Jones <marcj303(a)gmail.com> at Fri Jan 18 21:40:04 2013, giving +2 See http://review.coreboot.org/2140 for details. -gerrit

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Patch merged into coreboot/master: 931df3a F15tn / Hudson: Change SATA NumOfPorts register setting
by gerrit＠coreboot.org 21 Jan '13

21 Jan '13

the following patch was just integrated into master: commit 931df3a96bce9e3bc6f0d1058c301c49bee63747 Author: Martin Roth <martin.roth(a)se-eng.com> Date: Wed Jan 16 17:50:32 2013 -0700 F15tn / Hudson: Change SATA NumOfPorts register setting The Number of Ports register says that it should be set to the maximum number of ports supported by the silicon. AGESA was setting this to be the number of enabled ports. If port 1 was the only port with a drive, this value got set to 0, indicating 1 port. This causes SeaBIOS to only look at port 0 and quit, never finding the drive on port 1. Dave Frodin: I also verified that this patch allows a SATA drive plugged into port 2 to be detected without a device in port 1. Change-Id: I5d49e351864449520e3957bbb07edf0f3ec2fd47 Signed-off-by: Martin Roth <martin.roth(a)se-eng.com> Reviewed-on: http://review.coreboot.org/2165 Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Dave Frodin <dave.frodin(a)se-eng.com> Reviewed-by: Marc Jones <marcj303(a)gmail.com> Build-Tested: build bot (Jenkins) at Thu Jan 17 22:14:24 2013, giving +1 Reviewed-By: Marc Jones <marcj303(a)gmail.com> at Fri Jan 18 21:43:56 2013, giving +2 See http://review.coreboot.org/2165 for details. -gerrit

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Patch merged into coreboot/master: c89d3da Parmer / Thatcher: devicetree.cb cleanup and whitespace
by gerrit＠coreboot.org 21 Jan '13

21 Jan '13

the following patch was just integrated into master: commit c89d3daf32476f02b0bea7dc84572adfad55fc3d Author: Martin Roth <martin.roth(a)se-eng.com> Date: Wed Jan 16 19:18:09 2013 -0700 Parmer / Thatcher: devicetree.cb cleanup and whitespace Re-formatting and cleaning up the devicetree.cb files for parmer and thatcher. Change-Id: Ic458e59701c1f2593b0a035b96cac60df476ee82 Signed-off-by: Martin Roth <martin.roth(a)se-eng.com> Reviewed-on: http://review.coreboot.org/2164 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303(a)gmail.com> Reviewed-by: Zheng Bao <zheng.bao(a)amd.com> Build-Tested: build bot (Jenkins) at Thu Jan 17 03:28:34 2013, giving +1 Reviewed-By: Marc Jones <marcj303(a)gmail.com> at Thu Jan 17 19:19:01 2013, giving +2 Reviewed-By: Zheng Bao <zheng.bao(a)amd.com> at Fri Jan 18 03:05:43 2013, giving +1 See http://review.coreboot.org/2164 for details. -gerrit

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Patch merged into coreboot/master: 2d88151 F15tn: Modify devicetree to fix S3 resume
by gerrit＠coreboot.org 21 Jan '13

21 Jan '13

the following patch was just integrated into master: commit 2d8815197e7a8f7fa8c7e7dd6127937093369c7c Author: Martin Roth <martin(a)se-eng.com> Date: Thu Jan 10 12:41:40 2013 -0700 F15tn: Modify devicetree to fix S3 resume The way that devicetree.cb was configured for the family 15tn boards was doing... interesting things to the video device initialization. This was causing S3 resume to fail. There is a disconnect between how the devicetree should be configured if there are multiple HT links on the CPU and how it's configured if there's only one HT link. These platforms were set up as if they had multiple HT links, which was causing duplicate instances of devices in the device list. The scan for the IO Hub was removed from the northbridge code which isn't a problem for F15tn devices. Change-Id: I3556b43027746e36b07de7cb1bece4d1b37a3c34 Signed-off-by: Martin Roth <martin(a)se-eng.com> Reviewed-on: http://review.coreboot.org/2160 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303(a)gmail.com> Build-Tested: build bot (Jenkins) at Thu Jan 17 22:59:17 2013, giving +1 Reviewed-By: Marc Jones <marcj303(a)gmail.com> at Fri Jan 18 21:41:41 2013, giving +2 See http://review.coreboot.org/2160 for details. -gerrit

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Fwd: Re: spkmodem
by Vladimir 'φ-coder/phcoder' Serbinenko 21 Jan '13

21 Jan '13

-------- Original Message -------- Subject: Re: [coreboot] spkmodem Date: Mon, 21 Jan 2013 15:05:19 +0100 From: Vladimir 'φ-coder/phcoder' Serbinenko <phcoder(a)gmail.com> To: Peter Stuge <peter(a)stuge.se> On 21.01.2013 05:30, Peter Stuge wrote: > Vladimir 'φ-coder/phcoder' Serbinenko wrote: >> files are just 3K + 5K. Trying to resend > > They are not on the list. > > Make sure that they are sent as text/plain MIME type attachments > and/or inline attachments. I have no idea if any of that is possible > to set for gmail, my experience is that gmail is consistently > completely useless for people trying to work sanely with attachments > and mailing lists. > I used thunderbird, not gmail web interface. The MIME types are text/x-diff and text/x-csrc which should be fine. > > //Peter > > > -- Regards Vladimir 'φ-coder/phcoder' Serbinenko

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spkmodem
by Vladimir 'φ-coder/phcoder' Serbinenko 20 Jan '13

20 Jan '13

Hello, all. I send a patch to make coreboot output console using system beeper and a corresponding code to interpret those beeps. I publish it under GPLv2+ but other licensing arrangements are possible. This was very useful to get console on X201 where I have neither serial nor EHCI debug. -- Regards Vladimir 'φ-coder/phcoder' Serbinenko

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Patch merged into coreboot/master: b867281 Utility to run the snow bios in user mode
by gerrit＠coreboot.org 19 Jan '13

19 Jan '13

the following patch was just integrated into master: commit b867281a07addd1eb00f964ff4f8727664e13e19 Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Wed Jan 16 11:59:34 2013 -0600 Utility to run the snow bios in user mode This program lets you test run a snow coreboot image in user mode on a properly equipped arm system (usually an ARM chromebook). This is a real time saver as you don't have to flash each time. We've found and fixed some nasty bugs with this one. Anyway, the instructions on how to use this are in the binary. Change-Id: Ib555ef51fd7e930905a2ee5cbfda1cc6f068278e Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Reviewed-on: http://review.coreboot.org/2159 Reviewed-by: David Hendricks <dhendrix(a)chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Build-Tested: build bot (Jenkins) at Thu Jan 17 23:53:34 2013, giving +1 Reviewed-By: David Hendricks <dhendrix(a)chromium.org> at Thu Jan 17 23:39:26 2013, giving +2 See http://review.coreboot.org/2159 for details. -gerrit

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Re: [coreboot] Big picture of recent ARM patches?
by ron minnich 19 Jan '13

19 Jan '13

I just ordered the development board, 249, plus cable kit, 60. The web site, if you do this, will try your patience but it can be done ;-) So once the board comes in (4 weeks!) we can have a go at that. ron

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Big picture of recent ARM patches?
by Paul Menzel 18 Jan '13

18 Jan '13

Dear coreboot folks, it is great to see the past and current development of coreboot. Even better that hardware/devices with coreboot installed can be bought. Thank you for making that possible. Google’s coreboot developers latest effort seems to be to port coreboot to an ARM system. Unfortunately I am missing the big picture. I just see patches getting pushed to Gerrit and most of them getting approved. This is probably the result of upstreaming work early on so that trees do not diverge. Which is great! So it would be awesome if there would be a public roadmap, so that at least myself can get a small overview. My impression is that only you Google developers know what you are doing and can review the patches. But that might miss valuable comments from the other core coreboot developers regarding certain design decisions. And a nice understandable commit history and overview would make life for possible PowerPC (or other architectures) porters easier. Though that is just another guess from my side. Thanks, Paul

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Patch merged into coreboot/master: db5b893 Add more information to the cbfstool print
by gerrit＠coreboot.org 18 Jan '13

18 Jan '13

the following patch was just integrated into master: commit db5b893569f0b0c17e8faf1905f7da2450984432 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Fri Jan 18 15:53:22 2013 -0800 Add more information to the cbfstool print Show what's in a stage or payload. This will let people better understand what's in a stage or payload. Change-Id: If6d9a877b4aedd5cece76774e41f0daadb20c008 Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Reviewed-on: http://review.coreboot.org/2176 Tested-by: build bot (Jenkins) Build-Tested: build bot (Jenkins) at Sat Jan 19 01:03:37 2013, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Sat Jan 19 02:19:13 2013, giving +2 See http://review.coreboot.org/2176 for details. -gerrit

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coreboot January 2013