coreboot July 2012

coreboot@coreboot.org

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New patch to review for coreboot: c1a45b1 Add support for HM70 and NM70 LPC bridge
by Stefan Reinauer 23 Jul '12

23 Jul '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1300 -gerrit commit c1a45b1d551beee81960b62025725f5436587c0c Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Thu Jun 21 16:05:21 2012 -0700 Add support for HM70 and NM70 LPC bridge This lets the SPI driver and the LPC driver know about HM70 and NM70. Change-Id: Id2f1e0e5586a2f7200b2d24785df3f2be890da98 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/include/device/pci_ids.h | 2 +- .../intel/sandybridge/report_platform.c | 15 +++++++++------ src/southbridge/intel/bd82x6x/lpc.c | 10 ++++++++++ 3 files changed, 20 insertions(+), 7 deletions(-) diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index fd886da..7aac1f7 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -2507,7 +2507,7 @@ #define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MIN 0x1c41 #define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MAX 0x1c5f #define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MIN 0x1e41 -#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MAX 0x1e5d +#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MAX 0x1e5f #define PCI_DEVICE_ID_INTEL_TGP_LPC 0x27bc /* Intel 82801E (C-ICH) */ diff --git a/src/northbridge/intel/sandybridge/report_platform.c b/src/northbridge/intel/sandybridge/report_platform.c index bc88a89..ecd8f18 100644 --- a/src/northbridge/intel/sandybridge/report_platform.c +++ b/src/northbridge/intel/sandybridge/report_platform.c @@ -66,21 +66,24 @@ static struct { const char *dev_name; } pch_table [] = { {0x1E41, "Desktop Sample"}, + {0x1E42, "Mobile Sample"}, + {0x1E43, "SFF Sample"}, + {0x1E44, "Z77"}, + {0x1E45, "H71"}, + {0x1E46, "Z75"}, {0x1E47, "Q77"}, {0x1E48, "Q75"}, {0x1E49, "B75"}, - {0x1E44, "Z77"}, - {0x1E46, "Z75"}, {0x1E4A, "H77"}, {0x1E53, "C216"}, - {0x1E42, "Mobile Sample"}, {0x1E55, "QM77"}, + {0x1E56, "QS77"}, {0x1E58, "UM77"}, {0x1E57, "HM77"}, {0x1E59, "HM76"}, - {0x1E5d, "HM75"}, - {0x1E43, "SFF Sample"}, - {0x1E56, "QS77"}, + {0x1E5D, "HM75"}, + {0x1E5E, "HM70"}, + {0x1E5F, "NM70"}, }; static void report_pch_info(void) diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index dddab6a..703fc8a 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -684,3 +684,13 @@ static const struct pci_driver hm75_lpc __pci_driver = { .vendor = PCI_VENDOR_ID_INTEL, .device = 0x1e5d, }; +static const struct pci_driver hm70_lpc __pci_driver = { + .ops = &device_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x1e5e, +}; +static const struct pci_driver nm70_lpc __pci_driver = { + .ops = &device_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x1e5f, +};

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New patch to review for coreboot: 3d24e00 ifdtool: Use perror for file write errors
by Stefan Reinauer 23 Jul '12

23 Jul '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1299 -gerrit commit 3d24e001d146e96eedd24fe54931116a6ec3070f Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Mon Jun 18 16:02:20 2012 -0700 ifdtool: Use perror for file write errors The "Error while writing." error messages did not output a new line which made the output look weird. With this patch, it should look like this: $ ifdtool -x 3rdparty/mainboard/google/parrot/descriptor.bin File 3rdparty/mainboard/google/parrot/descriptor.bin is 4096 bytes Found Flash Descriptor signature at 0x00000010 Flash Region 0 (Flash Descriptor): 00000000 - 00000fff Flash Region 1 (BIOS): 00200000 - 007fffff Error while writing: Bad address Flash Region 2 (Intel ME): 00001000 - 001fffff Error while writing: Bad address Flash Region 3 (GbE): 00fff000 - 00000fff (unused) Flash Region 4 (Platform Data): 00fff000 - 00000fff (unused) Change-Id: I784ff72d0673f167dbf0bd10921406abd685ce72 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- util/ifdtool/ifdtool.c | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c index e78ac60..1b418d1 100644 --- a/util/ifdtool/ifdtool.c +++ b/util/ifdtool/ifdtool.c @@ -296,7 +296,7 @@ static void write_regions(char *image, int size) O_WRONLY | O_CREAT | O_TRUNC, S_IRUSR | S_IWUSR | S_IRGRP | S_IROTH); if (write(region_fd, image + region.base, region.size) != region.size) - printf("Error while writing."); + perror("Error while writing"); close(region_fd); } } @@ -317,7 +317,7 @@ static void write_image(char *filename, char *image, int size) O_WRONLY | O_CREAT | O_TRUNC, S_IRUSR | S_IWUSR | S_IRGRP | S_IROTH); if (write(new_fd, image, size) != size) - printf("Error while writing."); + perror("Error while writing"); close(new_fd); }

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New patch to review for coreboot: 13b585b Drop leading spaces from CPU name string
by Stefan Reinauer 23 Jul '12

23 Jul '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1298 -gerrit commit 13b585b977fa3e14f3b77a8c7ecdacb4e693b066 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Mon Jun 18 15:48:34 2012 -0700 Drop leading spaces from CPU name string This is as per Intel's suggestion on how to display their name strings. Change-Id: Ie82341305e58baa8041e50a61a11b395fa7d9582 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- .../intel/sandybridge/report_platform.c | 8 ++++++-- 1 files changed, 6 insertions(+), 2 deletions(-) diff --git a/src/northbridge/intel/sandybridge/report_platform.c b/src/northbridge/intel/sandybridge/report_platform.c index 18dffc2..bc88a89 100644 --- a/src/northbridge/intel/sandybridge/report_platform.c +++ b/src/northbridge/intel/sandybridge/report_platform.c @@ -29,7 +29,7 @@ static void report_cpu_info(void) { struct cpuid_result cpuidr; u32 i, index; - char cpu_string[50]; /* 48 bytes are reported */ + char cpu_string[50], *cpu_name = cpu_string; /* 48 bytes are reported */ int vt, txt, aes; const char *mode[] = {"NOT ", ""}; @@ -47,8 +47,12 @@ static void report_cpu_info(void) *p++ = cpuidr.edx; } } + /* Skip leading spaces in CPU name string */ + while (cpu_name[0] == ' ') + cpu_name++; + cpuidr = cpuid(1); - printk(BIOS_DEBUG, "CPU id(%x): %s\n", cpuidr.eax, cpu_string); + printk(BIOS_DEBUG, "CPU id(%x): %s\n", cpuidr.eax, cpu_name); aes = (cpuidr.ecx & (1 << 25)) ? 1 : 0; txt = (cpuidr.ecx & (1 << 6)) ? 1 : 0; vt = (cpuidr.ecx & (1 << 5)) ? 1 : 0;

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New patch to review for coreboot: a9a1fc5 Properly identify ACPI C3 states in _CST table.
by Stefan Reinauer 23 Jul '12

23 Jul '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1297 -gerrit commit a9a1fc5987493575c759af510647836138052a26 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Wed Jun 20 14:38:53 2012 -0700 Properly identify ACPI C3 states in _CST table. Dump and disassemble ACPI tables and look in _CST. In the last entry the state was getting set to 0: Package (0x04) { ResourceTemplate () { Register (FFixedHW, 0x01, // Bit Width 0x02, // Bit Offset 0x0000000000000030, // Address 0x01, // Access Size ) }, 0x00000000, // State 0x0000005A, // Latency 0x000000C8 // Power } Now it is properly identifed as state 3: Package (0x04) { ResourceTemplate () { Register (FFixedHW, 0x01, // Bit Width 0x02, // Bit Offset 0x0000000000000030, // Address 0x01, // Access Size ) }, 0x00000003, // State 0x0000005A, // Latency 0x000000C8 // Power } Change-Id: Ie0a68606c5a43ac5fb5ba7bb9a3fef933ad67b64 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- src/cpu/intel/model_206ax/acpi.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/src/cpu/intel/model_206ax/acpi.c b/src/cpu/intel/model_206ax/acpi.c index dea23e7..5d3f3a0 100644 --- a/src/cpu/intel/model_206ax/acpi.c +++ b/src/cpu/intel/model_206ax/acpi.c @@ -79,7 +79,7 @@ static int generate_cstate_entries(acpi_cstate_t *cstates, length += acpigen_write_CST_package_entry(&cstates[c2]); } if (c3 > 0) { - cstates[c2].ctype = 2; + cstates[c3].ctype = 3; length += acpigen_write_CST_package_entry(&cstates[c3]); }

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New patch to review for coreboot: 23e192d Add code to read Intel microcode from CBFS
by Stefan Reinauer 23 Jul '12

23 Jul '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1296 -gerrit commit 23e192d58ff8112518cf6f5cc01bb3bb173f4660 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Tue Jun 19 12:56:57 2012 -0700 Add code to read Intel microcode from CBFS When CONFIG_MICROCODE_IN_CBFS is enabled, find the microcode blob in CBFS and pass it to intel_update_microcode() instead of using the compiled in array. CBFS accesses in pre-RAM and 'normal' environments are provided through different API. Change-Id: I35c1480edf87e550a7b88c4aadf079cf3ff86b5d Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> --- src/cpu/intel/microcode/microcode.c | 30 ++++++++++++++++++++++++++ src/cpu/intel/model_206ax/bootblock.c | 6 +++++ src/cpu/intel/model_206ax/model_206ax_init.c | 7 +++++- src/include/cpu/intel/microcode.h | 11 ++++++++- 4 files changed, 52 insertions(+), 2 deletions(-) diff --git a/src/cpu/intel/microcode/microcode.c b/src/cpu/intel/microcode/microcode.c index ec42fb9..af83faf 100644 --- a/src/cpu/intel/microcode/microcode.c +++ b/src/cpu/intel/microcode/microcode.c @@ -1,6 +1,7 @@ /* * This file is part of the coreboot project. * + * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved. * Copyright (C) 2000 Ronald G. Minnich * * This program is free software; you can redistribute it and/or modify @@ -27,6 +28,14 @@ #include <cpu/x86/msr.h> #include <cpu/intel/microcode.h> +#if CONFIG_MICROCODE_IN_CBFS +#ifdef __PRE_RAM__ +#include <arch/cbfs.h> +#else +#include <cbfs.h> +#endif +#endif + struct microcode { u32 hdrver; /* Header Version */ u32 rev; /* Update Revision */ @@ -68,6 +77,9 @@ static inline u32 read_microcode_rev(void) return msr.hi; } +#if CONFIG_MICROCODE_IN_CBFS +static +#endif void intel_update_microcode(const void *microcode_updates) { u32 eax; @@ -131,3 +143,21 @@ void intel_update_microcode(const void *microcode_updates) } } } + +#if CONFIG_MICROCODE_IN_CBFS + +#define MICROCODE_CBFS_FILE "microcode_blob.bin" + +void intel_update_microcode_from_cbfs(void) +{ + void *microcode_blob; + +#ifdef __PRE_RAM__ + microcode_blob = walkcbfs((char *) MICROCODE_CBFS_FILE); +#else + microcode_blob = cbfs_find_file(MICROCODE_CBFS_FILE, + CBFS_TYPE_MICROCODE); +#endif + intel_update_microcode(microcode_blob); +} +#endif diff --git a/src/cpu/intel/model_206ax/bootblock.c b/src/cpu/intel/model_206ax/bootblock.c index 62d9b4e..4061bb7 100644 --- a/src/cpu/intel/model_206ax/bootblock.c +++ b/src/cpu/intel/model_206ax/bootblock.c @@ -23,9 +23,11 @@ #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> +#if !CONFIG_MICROCODE_IN_CBFS static const uint32_t microcode_updates[] = { #include "microcode_blob.h" }; +#endif #include <cpu/intel/microcode/microcode.c> @@ -61,5 +63,9 @@ static void enable_rom_caching(void) static void bootblock_cpu_init(void) { enable_rom_caching(); +#if CONFIG_MICROCODE_IN_CBFS + intel_update_microcode_from_cbfs(); +#else intel_update_microcode(microcode_updates); +#endif } diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c index dda7d35..87bc585 100644 --- a/src/cpu/intel/model_206ax/model_206ax_init.c +++ b/src/cpu/intel/model_206ax/model_206ax_init.c @@ -115,9 +115,11 @@ static acpi_cstate_t cstate_map[] = { { 0 } }; +#if !CONFIG_MICROCODE_IN_CBFS static const uint32_t microcode_updates[] = { #include "microcode_blob.h" }; +#endif /* Convert time in seconds to POWER_LIMIT_1_TIME MSR value */ static const u8 power_limit_time_sec_to_msr[] = { @@ -387,8 +389,11 @@ static void model_206ax_init(device_t cpu) /* Turn on caching if we haven't already */ x86_enable_cache(); - /* Update the microcode */ +#if CONFIG_MICROCODE_IN_CBFS + intel_update_microcode_from_cbfs(); +#else intel_update_microcode(microcode_updates); +#endif /* Clear out pending MCEs */ configure_mca(); diff --git a/src/include/cpu/intel/microcode.h b/src/include/cpu/intel/microcode.h index 4139c01..289e919 100644 --- a/src/include/cpu/intel/microcode.h +++ b/src/include/cpu/intel/microcode.h @@ -1,6 +1,7 @@ /* * This file is part of the coreboot project. * + * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved. * Copyright (C) 2000 Ronald G. Minnich * * This program is free software; you can redistribute it and/or modify @@ -16,7 +17,15 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef __CPU__INTEL__MICROCODE__ +#define __CPU__INTEL__MICROCODE__ -#if !defined(__ROMCC__) +#ifndef __PRE_RAM__ +#if CONFIG_MICROCODE_IN_CBFS +void intel_update_microcode_from_cbfs(void); +#else void intel_update_microcode(const void *microcode_updates); #endif +#endif + +#endif

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New patch to review for coreboot: 4199fe3 Add microcode blob processing
by Stefan Reinauer 23 Jul '12

23 Jul '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1295 -gerrit commit 4199fe3d470a2a9e9f87058ede9037307647ca31 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Tue Jun 19 08:34:51 2012 -0700 Add microcode blob processing When microcode storage in CBFS is enabled, the make system is supposed to generate the microcode blob and place it into the generated ROM image as a CBFS component. The microcode source representation does not change: it is still an array of 32 bit constants. This new addition compiles the array into a separate object file and then strips all sections but data. The raw data section is then included into CBFS as a file named 'microcode_blob.bin' of type 0x53, which is assigned to microcode storage. Change-Id: I84ae040be52f520b106e3471c7e391e64d7847d9 Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> --- src/arch/x86/Makefile.inc | 6 ++++++ src/cpu/intel/microcode/Makefile.inc | 14 ++++++++++++++ src/cpu/intel/microcode/microcode_blob.c | 22 ++++++++++++++++++++++ 3 files changed, 42 insertions(+), 0 deletions(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index f498831..306f239 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -34,6 +34,12 @@ cmos_layout.bin-type = 0x01aa OPTION_TABLE_H:=$(obj)/option_table.h endif +ifeq ($(CONFIG_MICROCODE_IN_CBFS),y) +cbfs-files-y += microcode_blob.bin +microcode_blob.bin-file = $(obj)/microcode_blob.bin +microcode_blob.bin-type = 0x53 +endif + ####################################################################### # Build the final rom image COREBOOT_ROM_DEPENDENCIES:= diff --git a/src/cpu/intel/microcode/Makefile.inc b/src/cpu/intel/microcode/Makefile.inc index 6631019..f4d0102 100644 --- a/src/cpu/intel/microcode/Makefile.inc +++ b/src/cpu/intel/microcode/Makefile.inc @@ -1 +1,15 @@ ramstage-y += microcode.c + + +ifeq ($(CONFIG_MICROCODE_IN_CBFS),y) + +SRC_PATH = src/cpu/intel/microcode +FLAGS = -I $(CONFIG_MICROCODE_INCLUDE_PATH) -include $(obj)/config.h +$(obj)/microcode_blob.o: $(SRC_PATH)/microcode_blob.c + $(CC) $(FLAGS) -MMD -c -o $@ $< + +$(obj)/microcode_blob.bin: $(obj)/microcode_blob.o + objcopy -j .data -O binary $< $@ + +-include $(obj)/microcode_blob.d +endif diff --git a/src/cpu/intel/microcode/microcode_blob.c b/src/cpu/intel/microcode/microcode_blob.c new file mode 100644 index 0000000..69238a9 --- /dev/null +++ b/src/cpu/intel/microcode/microcode_blob.c @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +unsigned microcode[] = { +#include <microcode_blob.h> +};

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New patch to review for coreboot: aa33165 Rename microcode include file to be model agnostic
by Stefan Reinauer 23 Jul '12

23 Jul '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1294 -gerrit commit aa331657ff2fbabb32681809b6eab7d7b874deeb Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Tue Jun 19 05:25:41 2012 +0000 Rename microcode include file to be model agnostic In preparation to support CBFS hosted microcode blobs, this change renames the wrapper include file containing the microcode to be independent of CPU model. Change-Id: If1a4963a52e5037a3a3495b90708ffc08b23f4c1 Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> --- src/cpu/intel/model_206ax/bootblock.c | 2 +- src/cpu/intel/model_206ax/microcode_blob.h | 31 ++++++++++++++++++++++++++ src/cpu/intel/model_206ax/model_206ax_init.c | 2 +- src/cpu/intel/model_206ax/x06_microcode.h | 31 -------------------------- 4 files changed, 33 insertions(+), 33 deletions(-) diff --git a/src/cpu/intel/model_206ax/bootblock.c b/src/cpu/intel/model_206ax/bootblock.c index 9549d23..62d9b4e 100644 --- a/src/cpu/intel/model_206ax/bootblock.c +++ b/src/cpu/intel/model_206ax/bootblock.c @@ -24,7 +24,7 @@ #include <cpu/x86/mtrr.h> static const uint32_t microcode_updates[] = { - #include "x06_microcode.h" + #include "microcode_blob.h" }; #include <cpu/intel/microcode/microcode.c> diff --git a/src/cpu/intel/model_206ax/microcode_blob.h b/src/cpu/intel/model_206ax/microcode_blob.h new file mode 100644 index 0000000..d055b2e --- /dev/null +++ b/src/cpu/intel/model_206ax/microcode_blob.h @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +#if CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE + #include "microcode-m12206a7_00000025.h" +#elif CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE +#else +#error "Which microcode to use?" +#endif + /* Dummy terminator */ + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c index b88d7d4..dda7d35 100644 --- a/src/cpu/intel/model_206ax/model_206ax_init.c +++ b/src/cpu/intel/model_206ax/model_206ax_init.c @@ -116,7 +116,7 @@ static acpi_cstate_t cstate_map[] = { }; static const uint32_t microcode_updates[] = { - #include "x06_microcode.h" + #include "microcode_blob.h" }; /* Convert time in seconds to POWER_LIMIT_1_TIME MSR value */ diff --git a/src/cpu/intel/model_206ax/x06_microcode.h b/src/cpu/intel/model_206ax/x06_microcode.h deleted file mode 100644 index d055b2e..0000000 --- a/src/cpu/intel/model_206ax/x06_microcode.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - - -#if CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE - #include "microcode-m12206a7_00000025.h" -#elif CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE -#else -#error "Which microcode to use?" -#endif - /* Dummy terminator */ - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0,

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New patch to review for coreboot: 1bd276a Add standard header to prevent multiple inclusion
by Stefan Reinauer 23 Jul '12

23 Jul '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1293 -gerrit commit 1bd276a9a866c54c1d9ec4dbb00d14be2ef01a49 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Tue Jun 19 04:48:28 2012 +0000 Add standard header to prevent multiple inclusion This include file needs to be prevented from being included multiple times. Change-Id: I42e0cbe38d332b919f22e331eaf7a0251929e1dc Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> --- src/arch/x86/include/arch/cbfs.h | 24 +++++++++++++++++++++++- 1 files changed, 23 insertions(+), 1 deletions(-) diff --git a/src/arch/x86/include/arch/cbfs.h b/src/arch/x86/include/arch/cbfs.h index 635ff10..8a61d6e 100644 --- a/src/arch/x86/include/arch/cbfs.h +++ b/src/arch/x86/include/arch/cbfs.h @@ -1,3 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __INCLUDE_ARCH_CBFS__ +#define __INCLUDE_ARCH_CBFS__ + static void *walkcbfs(char *target) { void *entry; @@ -23,4 +45,4 @@ static inline void call(unsigned long addr, unsigned long bist) { asm volatile ("jmp *%0\n\t" : : "r" (addr), "a" (bist)); } - +#endif

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New patch to review for coreboot: fd2d352 Config changes to support microcode in CBFS
by Stefan Reinauer 23 Jul '12

23 Jul '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1292 -gerrit commit fd2d35281ebb6d59d06fcd53a19f7e7d325dd5a3 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Tue Jun 19 04:20:20 2012 +0000 Config changes to support microcode in CBFS Nothing is yet enabled, this is just a config skeleton change. The MICROCODE_INCLUDE_PATH definition is going to be used by the Makefile building the microcode blob for CBFS inclusion. Change-Id: I7868db3cfd4b181500e361706e5f4dc08ca1c87d Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> --- src/cpu/Kconfig | 9 +++++++++ src/cpu/intel/model_206ax/Kconfig | 6 ++++++ 2 files changed, 15 insertions(+), 0 deletions(-) diff --git a/src/cpu/Kconfig b/src/cpu/Kconfig index 85e83d4..5196e1a 100644 --- a/src/cpu/Kconfig +++ b/src/cpu/Kconfig @@ -61,4 +61,13 @@ config SSE2 streaming SIMD instructions. Some parts of coreboot can be built with more efficient code if SSE2 instructions are available. +if CPU_INTEL_MODEL_206AX || CPU_INTEL_MODEL_306AX + +config MICROCODE_IN_CBFS + bool "Look for microcode in CBFS" + help + Load microcode updates from CBFS instead of compiling them in. + +endif + endif # ARCH_X86 diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig index 6c70993..1d4ff02 100644 --- a/src/cpu/intel/model_206ax/Kconfig +++ b/src/cpu/intel/model_206ax/Kconfig @@ -21,6 +21,12 @@ config SMM_TSEG_SIZE hex default 0x800000 +if MICROCODE_IN_CBFS +config MICROCODE_INCLUDE_PATH + string + default "src/cpu/intel/model_206ax" +endif + endif if CPU_INTEL_MODEL_206AX

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Patch merged into coreboot/master: 696dc0b Fixes to enable RC6 on IvyBridge
by gerrit＠coreboot.org 23 Jul '12

23 Jul '12

the following patch was just integrated into master: commit 696dc0b6d66d34d0c15798f365387ff8f1436e17 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Fri May 25 10:04:17 2012 -0700 Fixes to enable RC6 on IvyBridge - The unneeded poll on non-MT force-wake bit was timing out and causing the gma_pm_init_pre_vbios() function to exit early so it was not preparing PM registers properly. I changed the gtt_poll() calls to not return on timeout unless it can't proceed so we don't see half-initialized registers. - RC6+ (Deep Render Standby) is not working reliably so we can just enable RC6 in the BIOS and let the kernel decide if it wants to enable RC6+ later. This Kernel message is new in kernel 3.4: [drm] Enabling RC6 states: RC6 on, RC6p off, RC6pp off Change-Id: I69d005ba56be8c7684a4ea1133a1d761f7c07acc Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Build-Tested: build bot (Jenkins) at Mon Jul 23 23:40:59 2012, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Tue Jul 24 00:02:18 2012, giving +2 See http://review.coreboot.org/1268 for details. -gerrit

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coreboot July 2012