coreboot July 2012

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New patch to review for coreboot: d07e775 ELOG: Fix boot count increment for non-wake case
by Stefan Reinauer 23 Jul '12

23 Jul '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1328 -gerrit commit d07e775d85806855ce6acf5dda67682325e2952f Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Fri Jun 29 15:38:02 2012 -0700 ELOG: Fix boot count increment for non-wake case The count was only incrementing for a wake from S5 and it was not incrementing in the normal reboot case. Change-Id: I73bc6db6bd02e6c4677f7e44a5c098c6dcb51747 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- src/northbridge/intel/sandybridge/early_init.c | 11 ++++++----- 1 files changed, 6 insertions(+), 5 deletions(-) diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c index 6bd774b..2954bf1 100644 --- a/src/northbridge/intel/sandybridge/early_init.c +++ b/src/northbridge/intel/sandybridge/early_init.c @@ -64,14 +64,15 @@ static void sandybridge_setup_bars(void) pci_write_config8(PCI_DEV(0, 0x00, 0), PAM5, 0x33); pci_write_config8(PCI_DEV(0, 0x00, 0), PAM6, 0x33); + printk(BIOS_DEBUG, " done.\n"); + #if CONFIG_ELOG_BOOT_COUNT - /* Increment Boot Counter for non-S3 resume */ + /* Increment Boot Counter except when resuming from S3 */ if ((inw(DEFAULT_PMBASE + PM1_STS) & WAK_STS) && - ((inl(DEFAULT_PMBASE + PM1_CNT) >> 10) & 7) != SLP_TYP_S3) - boot_count_increment(); + ((inl(DEFAULT_PMBASE + PM1_CNT) >> 10) & 7) == SLP_TYP_S3) + return; + boot_count_increment(); #endif - - printk(BIOS_DEBUG, " done.\n"); } static void sandybridge_setup_graphics(void)

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New patch to review for coreboot: 9befba2 Add BAR address debug information to Oxford PCIe serial driver
by Stefan Reinauer 23 Jul '12

23 Jul '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1327 -gerrit commit 9befba2ae7ce00e230d563622d9460be635247b3 Author: Marc Jones <marc.jones(a)se-eng.com> Date: Mon Jul 2 22:31:22 2012 -0600 Add BAR address debug information to Oxford PCIe serial driver The Oxford PCIE Serial card has a hardcoded address at setup, which may be moved during PCI Init. The driver re-initializes after PCI init. Add a debug print for the new BAR address. Initializing Oxford OXPCIe952 OXPCIe952: Class=70002 Revision ID=0 OXPCIe952: 2 UARTs detected. OXPCIe952: Uart Bar: 0xe0800000 Change-Id: I1858d3eba09749cba3c3869060d00e621dca112a Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> --- src/drivers/oxford/oxpcie/oxpcie.c | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/src/drivers/oxford/oxpcie/oxpcie.c b/src/drivers/oxford/oxpcie/oxpcie.c index 8afdd1f..5ce4f62 100644 --- a/src/drivers/oxford/oxpcie/oxpcie.c +++ b/src/drivers/oxford/oxpcie/oxpcie.c @@ -38,6 +38,7 @@ static void oxford_oxpcie_enable(device_t dev) (read32(res->base) >> 8), (read32(res->base) & 0xff)); printk(BIOS_DEBUG, "OXPCIe952: %d UARTs detected.\n", (read32(res->base + 4) & 3)); + printk(BIOS_DEBUG, "OXPCIe952: UART BAR: 0x%x\n", (u32)res->base); }

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New patch to review for coreboot: 0e8fa37 Add PCIe port disable debug message
by Stefan Reinauer 23 Jul '12

23 Jul '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1326 -gerrit commit 0e8fa37a7a349594407a367bf45d42d2af4a7f55 Author: Marc Jones <marc.jones(a)se-eng.com> Date: Fri Jun 15 23:03:15 2012 -0600 Add PCIe port disable debug message The PCIe device enable function prints when it disables a device. The PCIe ports(bridges) use a different routine that didn't print the message. Add it to be consistent and to provide better debug output. Change-Id: I8462c48e7f4930db68703f0bfb710c01c9643a98 Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> --- src/southbridge/intel/bd82x6x/pch.c | 2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/src/southbridge/intel/bd82x6x/pch.c b/src/southbridge/intel/bd82x6x/pch.c index 0913e1d..3c448de 100644 --- a/src/southbridge/intel/bd82x6x/pch.c +++ b/src/southbridge/intel/bd82x6x/pch.c @@ -297,6 +297,8 @@ static void pch_pcie_enable(device_t dev) } if (!dev->enabled) { + printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev)); + /* * PCIE Power Savings for PantherPoint and CougarPoint/B1+ *

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New patch to review for coreboot: 2c987a6 Make MAX_PHYSICAL_CPUS invisible on non-AMD boards
by Stefan Reinauer 23 Jul '12

23 Jul '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1325 -gerrit commit 2c987a68e57477fadd78c4d1e73469d9447fde53 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Mon Jun 25 14:12:58 2012 -0700 Make MAX_PHYSICAL_CPUS invisible on non-AMD boards It's only used on AMD based boards. Hence drop it, so we don't accidently start using it by mistake instead of MAX_CPUS Change-Id: Id8f522f24283129874d56e70bd00df92abe9c3cf Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/cpu/Kconfig | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/src/cpu/Kconfig b/src/cpu/Kconfig index 5196e1a..f37bbf6 100644 --- a/src/cpu/Kconfig +++ b/src/cpu/Kconfig @@ -23,6 +23,7 @@ config DCACHE_RAM_GLOBAL_VAR_SIZE # yet be dropped completely. config MAX_PHYSICAL_CPUS int + depends on CPU_AMD_MODEL_10XXX || CPU_AMD_MODEL_FXX || CPU_AMD_AGESA default 1 config SMP

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New patch to review for coreboot: 94a7263 bd82x6x: Use CMOS variable if available for power-on on power failure
by Stefan Reinauer 23 Jul '12

23 Jul '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1324 -gerrit commit 94a72631f7e6882633773210e225f56bef4ff354 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Thu Jun 28 12:22:28 2012 -0700 bd82x6x: Use CMOS variable if available for power-on on power failure We used a hard coded value for some reason. Don't do that, but use CMOS instead. Modelled after http://review.coreboot.org/#/c/443 to get bd82x6x in sync. Change-Id: I36d715310157b9f9074f2a1c80710f85833020b4 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/southbridge/intel/bd82x6x/smihandler.c | 14 ++++++++++---- 1 files changed, 10 insertions(+), 4 deletions(-) diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c index 29f1a1e..da5b52b 100644 --- a/src/southbridge/intel/bd82x6x/smihandler.c +++ b/src/southbridge/intel/bd82x6x/smihandler.c @@ -29,6 +29,7 @@ #include <device/pci_def.h> #include <cpu/x86/smm.h> #include <elog.h> +#include <pc80/mc146818rtc.h> #include "pch.h" #include "nvs.h" @@ -324,11 +325,16 @@ static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *stat u8 reg8; u32 reg32; u8 slp_typ; - /* FIXME: the power state on boot should be read from - * CMOS or even better from GNVS. Right now it's hard - * coded at compile time. - */ u8 s5pwr = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; + + // save and recover RTC port values + u8 tmp70, tmp72; + tmp70 = inb(0x70); + tmp72 = inb(0x72); + get_option(&s5pwr, "power_on_after_fail"); + outb(tmp70, 0x70); + outb(tmp72, 0x72); + void (*mainboard_sleep)(u8 slp_typ) = mainboard_smi_sleep; /* First, disable further SMIs */

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New patch to review for coreboot: b933096 bd82x6x: Support power-on-after-power-fail better
by Stefan Reinauer 23 Jul '12

23 Jul '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1323 -gerrit commit b933096316ccc00d7801f06b0e68604bdfaad002 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Thu Jun 28 12:18:41 2012 -0700 bd82x6x: Support power-on-after-power-fail better Changing CMOS value for power-on-after-power-fail was only honored after reboot, which is counter intuitive (set from "enable" to "disable", power-off, replug device -> device turns on; and similar cases). Modelled after http://review.coreboot.org/#/c/444 Change-Id: I2b8461dff1ae085c1ea4b4926084268b4da90321 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/southbridge/intel/bd82x6x/smihandler.c | 14 +++++++------- 1 files changed, 7 insertions(+), 7 deletions(-) diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c index 3716bf1..29f1a1e 100644 --- a/src/southbridge/intel/bd82x6x/smihandler.c +++ b/src/southbridge/intel/bd82x6x/smihandler.c @@ -373,16 +373,16 @@ static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *stat outl(0, pmbase + GPE0_EN); - /* Should we keep the power state after a power loss? - * In case the setting is "ON" or "OFF" we don't have - * to do anything. But if it's "KEEP" we have to switch - * to "OFF" before entering S5. + /* Always set the flag in case CMOS was changed on runtime. For + * "KEEP", switch to "OFF" - KEEP is software emulated */ - if (s5pwr == MAINBOARD_POWER_KEEP) { - reg8 = pcie_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3); + reg8 = pcie_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3); + if (s5pwr == MAINBOARD_POWER_ON) { + reg8 &= ~1; + } else { reg8 |= 1; - pcie_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8); } + pcie_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8); /* also iterates over all bridges on bus 0 */ busmaster_disable_on_bus(0);

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New patch to review for coreboot: 2aa966b Add specific power management init code for PantherPoint
by Stefan Reinauer 23 Jul '12

23 Jul '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1322 -gerrit commit 2aa966bff8d614d703c469021aecfe7eb4033cdd Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Thu Jun 28 13:03:40 2012 -0700 Add specific power management init code for PantherPoint There are enough subtle differences in the magic values that it is easier to make a separate function. This fixes a reset hang with pantherpoint chipset. Change-Id: I02b03cb37e5fd5ee2fd62067644f0a62dc2cd26a Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/southbridge/intel/bd82x6x/lpc.c | 58 +++++++++++++++++++++++++++++++++- 1 files changed, 56 insertions(+), 2 deletions(-) diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 8db30f6..fcc99f4 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -306,8 +306,10 @@ static void pch_rtc_init(struct device *dev) rtc_init(rtc_failed); } -static void pch_pm_init(struct device *dev) +/* CougarPoint PCH Power Management init */ +static void cpt_pm_init(struct device *dev) { + printk(BIOS_DEBUG, "CougarPoint PM init\n"); pci_write_config8(dev, 0xa9, 0x47); RCBA32_AND_OR(0x2238, ~0UL, (1 << 6)|(1 << 0)); RCBA32_AND_OR(0x228c, ~0UL, (1 << 0)); @@ -346,6 +348,49 @@ static void pch_pm_init(struct device *dev) RCBA32_AND_OR(0x21b0, ~0UL, 0xf); } +/* PantherPoint PCH Power Management init */ +static void ppt_pm_init(struct device *dev) +{ + printk(BIOS_DEBUG, "PantherPoint PM init\n"); + pci_write_config8(dev, 0xa9, 0x47); + RCBA32_AND_OR(0x2238, ~0UL, (1 << 0)); + RCBA32_AND_OR(0x228c, ~0UL, (1 << 0)); + RCBA16_AND_OR(0x1100, ~0UL, (1 << 13)|(1 << 14)); + RCBA16_AND_OR(0x0900, ~0UL, (1 << 14)); + RCBA32(0x2304) = 0xc03b8400; + RCBA32_AND_OR(0x2314, ~0UL, (1 << 5)|(1 << 18)); + RCBA32_AND_OR(0x2320, ~0UL, (1 << 15)|(1 << 1)); + RCBA32_AND_OR(0x3314, ~0x1f, 0xf); + RCBA32(0x3318) = 0x054f0000; + RCBA32(0x3324) = 0x04000000; + RCBA32_AND_OR(0x3340, ~0UL, 0xfffff); + RCBA32_AND_OR(0x3344, ~0UL, (1 << 1)|(1 << 0)); + RCBA32(0x3360) = 0x0001c000; + RCBA32(0x3368) = 0x00061100; + RCBA32(0x3378) = 0x7f8fdfff; + RCBA32(0x337c) = 0x000003fd; + RCBA32(0x3388) = 0x00001000; + RCBA32(0x3390) = 0x0001c000; + RCBA32(0x33a0) = 0x00000800; + RCBA32(0x33b0) = 0x00001000; + RCBA32(0x33c0) = 0x00093900; + RCBA32(0x33cc) = 0x24653002; + RCBA32(0x33d0) = 0x067388fe; + RCBA32_AND_OR(0x33d4, 0xf000f000, 0x00670060); + RCBA32(0x3a28) = 0x01010000; + RCBA32(0x3a2c) = 0x01010404; + RCBA32(0x3a80) = 0x01040000; + RCBA32_AND_OR(0x3a84, ~0x0000ffff, 0x00001001); + RCBA32_AND_OR(0x3a84, ~0UL, (1 << 24)); /* SATA 2/3 disabled */ + RCBA32_AND_OR(0x3a88, ~0UL, (1 << 0)); /* SATA 4/5 disabled */ + RCBA32(0x3a6c) = 0x00000001; + RCBA32_AND_OR(0x2344, 0x00ffff00, 0xff00000c); + RCBA32_AND_OR(0x80c, ~(0xff << 20), 0x11 << 20); + RCBA32_AND_OR(0x33a4, ~0UL, (1 << 0)); + RCBA32(0x33c8) = 0; + RCBA32_AND_OR(0x21b0, ~0UL, 0xf); +} + static void enable_hpet(void) { u32 reg32; @@ -504,7 +549,16 @@ static void lpc_init(struct device *dev) pch_power_options(dev); /* Initialize power management */ - pch_pm_init(dev); + switch (pch_silicon_type()) { + case PCH_TYPE_CPT: /* CougarPoint */ + cpt_pm_init(dev); + break; + case PCH_TYPE_PPT: /* PantherPoint */ + ppt_pm_init(dev); + break; + default: + printk(BIOS_ERR, "Unknown Chipset: 0x%04x\n", dev->device); + } /* Set the state of the GPIO lines. */ //gpio_init(dev);

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Patch merged into coreboot/master: 32c4db4 Make memalign print useful messages on failure
by gerrit＠coreboot.org 23 Jul '12

23 Jul '12

the following patch was just integrated into master: commit 32c4db41bfa7a53adfbfcc2a4f1d4baf124c70fc Author: Ronald G. Minnich <rminnich(a)chromium.org> Date: Thu May 31 16:02:26 2012 -0700 Make memalign print useful messages on failure Brevity is the soul of wit, except for error messages; then it's a sign of witlessness. I can say this because this error message may be my fault, although it is lost in the 20th century code base so who knows. Anyway, when memalign dies, it's not a bad idea to have a lot of information about what went wrong. So instead of the terse single bit of "something failed" this patch changes things to be a bit more useful. Change-Id: I8851502297e0ae9773912839ebfdf4f9574c8087 Signed-off-by: Ronald G. Minnich <rminnich(a)chromium.org> Build-Tested: build bot (Jenkins) at Tue Jul 24 00:22:34 2012, giving +1 See http://review.coreboot.org/1270 for details. -gerrit

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New patch to review for coreboot: 7a33471 ELOG: Log events for Chrome OS developer/recovery mode
by Stefan Reinauer 23 Jul '12

23 Jul '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1321 -gerrit commit 7a33471cb4802513b5349967fd5f328a9f491b13 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Sat Jun 23 17:33:30 2012 -0700 ELOG: Log events for Chrome OS developer/recovery mode If a Chrome OS device is in developer mode log an event. When the device is in recovery mode also log an event and provide the recovery reason. Enable developer mode and trigger recovery mode and verify that the events are logged: 238 | 2012-06-23 17:31:56 | Chrome OS Developer Mode 239 | 2012-06-23 17:31:56 | Chrome OS Recovery Mode | User Requested from Developer Screen Change-Id: I14d41f44e04fd91340569617c7314da7e35a154f Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/vendorcode/google/chromeos/gnvs.c | 11 +++++++++++ 1 files changed, 11 insertions(+), 0 deletions(-) diff --git a/src/vendorcode/google/chromeos/gnvs.c b/src/vendorcode/google/chromeos/gnvs.c index aaca95a..c8ccfe4 100644 --- a/src/vendorcode/google/chromeos/gnvs.c +++ b/src/vendorcode/google/chromeos/gnvs.c @@ -21,6 +21,9 @@ #include <string.h> #include <cbfs.h> #include <console/console.h> +#include <elog.h> + +#include "chromeos.h" #include "gnvs.h" chromeos_acpi_t *vboot_data = NULL; @@ -32,6 +35,14 @@ void chromeos_init_vboot(chromeos_acpi_t *chromeos) /* Copy saved ME hash into NVS */ memcpy(vboot_data->mehh, me_hash_saved, sizeof(vboot_data->mehh)); + +#if CONFIG_ELOG + if (developer_mode_enabled()) + elog_add_event(ELOG_TYPE_CROS_DEVELOPER_MODE); + if (recovery_mode_enabled()) + elog_add_event_byte(ELOG_TYPE_CROS_RECOVERY_MODE, + get_recovery_mode_from_vbnv()); +#endif } void chromeos_set_me_hash(u32 *hash, int len)

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New patch to review for coreboot: 85c8a36 ELOG: Log run-time SMI southbridge events
by Stefan Reinauer 23 Jul '12

23 Jul '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1320 -gerrit commit 85c8a36b7d8c2a838fb275eeaa02d60e080e941e Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Sat Jun 23 17:30:19 2012 -0700 ELOG: Log run-time SMI southbridge events Events are logged for SMIs that trigger ACPI sleeps state entry and when the power button press triggers an SMI such as at the developer/recovery screens. Generate ACPI sleep state events and power button events and verify they show up in the log: 153 | 2012-06-23 17:12:59 | ACPI Enter | S5 184 | 2012-06-23 17:15:50 | ACPI Enter | S3 216 | 2012-06-23 17:28:58 | Power Button Change-Id: Iba134d619780e459bce189d36d57844997ffb009 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/southbridge/intel/bd82x6x/smihandler.c | 9 +++++++++ 1 files changed, 9 insertions(+), 0 deletions(-) diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c index 715a82f..3716bf1 100644 --- a/src/southbridge/intel/bd82x6x/smihandler.c +++ b/src/southbridge/intel/bd82x6x/smihandler.c @@ -346,6 +346,12 @@ static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *stat if (mainboard_sleep) mainboard_sleep(slp_typ); +#if CONFIG_ELOG_GSMI + /* Log S3, S4, and S5 entry */ + if (slp_typ >= 5) + elog_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ-2); +#endif + /* Next, do the deed. */ @@ -526,6 +532,9 @@ static void southbridge_smi_pm1(unsigned int node, smm_state_save_area_t *state_ // power button pressed u32 reg32; reg32 = (7 << 10) | (1 << 13); +#if CONFIG_ELOG_GSMI + elog_add_event(ELOG_TYPE_POWER_BUTTON); +#endif outl(reg32, pmbase + PM1_CNT); } }

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coreboot July 2012