coreboot July 2012

coreboot@coreboot.org

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639 discussions

Patch merged into coreboot/master: 13b585b Drop leading spaces from CPU name string
by gerrit＠coreboot.org 24 Jul '12

24 Jul '12

the following patch was just integrated into master: commit 13b585b977fa3e14f3b77a8c7ecdacb4e693b066 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Mon Jun 18 15:48:34 2012 -0700 Drop leading spaces from CPU name string This is as per Intel's suggestion on how to display their name strings. Change-Id: Ie82341305e58baa8041e50a61a11b395fa7d9582 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Tue Jul 24 08:53:01 2012, giving +2 See http://review.coreboot.org/1298 for details. -gerrit

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Patch merged into coreboot/master: a9a1fc5 Properly identify ACPI C3 states in _CST table.
by gerrit＠coreboot.org 24 Jul '12

24 Jul '12

the following patch was just integrated into master: commit a9a1fc5987493575c759af510647836138052a26 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Wed Jun 20 14:38:53 2012 -0700 Properly identify ACPI C3 states in _CST table. Dump and disassemble ACPI tables and look in _CST. In the last entry the state was getting set to 0: Package (0x04) { ResourceTemplate () { Register (FFixedHW, 0x01, // Bit Width 0x02, // Bit Offset 0x0000000000000030, // Address 0x01, // Access Size ) }, 0x00000000, // State 0x0000005A, // Latency 0x000000C8 // Power } Now it is properly identifed as state 3: Package (0x04) { ResourceTemplate () { Register (FFixedHW, 0x01, // Bit Width 0x02, // Bit Offset 0x0000000000000030, // Address 0x01, // Access Size ) }, 0x00000003, // State 0x0000005A, // Latency 0x000000C8 // Power } Change-Id: Ie0a68606c5a43ac5fb5ba7bb9a3fef933ad67b64 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Tue Jul 24 08:53:50 2012, giving +2 See http://review.coreboot.org/1297 for details. -gerrit

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Patch merged into coreboot/master: df4917d Remove unused free() function
by gerrit＠coreboot.org 24 Jul '12

24 Jul '12

the following patch was just integrated into master: commit df4917d5d02ea8636c6c20ee1a312301712e7406 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Wed Jun 6 13:42:09 2012 -0700 Remove unused free() function Since coreboot is running very short, we don't free memory. Hence, drop (dummy) free() Change-Id: I6e2737f07c6b9f73ebfad7d124b97a57cb7454a3 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> See http://review.coreboot.org/1274 for details. -gerrit

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Patch merged into coreboot/master: 1bd276a Add standard header to prevent multiple inclusion
by gerrit＠coreboot.org 24 Jul '12

24 Jul '12

the following patch was just integrated into master: commit 1bd276a9a866c54c1d9ec4dbb00d14be2ef01a49 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Tue Jun 19 04:48:28 2012 +0000 Add standard header to prevent multiple inclusion This include file needs to be prevented from being included multiple times. Change-Id: I42e0cbe38d332b919f22e331eaf7a0251929e1dc Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> See http://review.coreboot.org/1293 for details. -gerrit

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Patch merged into coreboot/master: 428cab4 Move GGL0001 ACPI code to generic ChromeOS code
by gerrit＠coreboot.org 24 Jul '12

24 Jul '12

the following patch was just integrated into master: commit 428cab4ee82c28829af13fad56db22914530ee68 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Thu Jun 7 15:38:44 2012 -0700 Move GGL0001 ACPI code to generic ChromeOS code The only difference in this code on all our platforms is the array describing the GPIOs. Hence, only keep that array in the mainboard ChromeOS directory and move everything else to generic ChromeOS ACPI code. Change-Id: I9fc75842af64530c1255bea1c5f803c5316d6da6 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Tue Jul 24 08:35:25 2012, giving +2 See http://review.coreboot.org/1278 for details. -gerrit

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Patch merged into coreboot/master: 07e941b Fix MRC cache update delays
by gerrit＠coreboot.org 24 Jul '12

24 Jul '12

the following patch was just integrated into master: commit 07e941bfd3b775f6f3f03768d886a6b735d73d2d Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Wed Jun 6 13:24:32 2012 -0700 Fix MRC cache update delays When no valid MRC cache area is found, the mrc_cache data structure was used without prior initialization. This sometimes caused a long delay when booting because compute_ip_checksum would checksum up to 4GB of memory. Change-Id: I6a0ca1aa618838bbc3d042be425700fc34b427f2 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Build-Tested: build bot (Jenkins) at Tue Jul 24 03:31:15 2012, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Tue Jul 24 06:55:35 2012, giving +2 See http://review.coreboot.org/1277 for details. -gerrit

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Patch merged into coreboot/master: 3f49a21 Remove code that enables/disables VMX in coreboot on chromebooks.
by gerrit＠coreboot.org 24 Jul '12

24 Jul '12

the following patch was just integrated into master: commit 3f49a21848c62581852fe5de99a65a094c92c212 Author: Ronald G. Minnich <rminnich(a)chromium.org> Date: Tue Jun 5 14:08:10 2012 -0700 Remove code that enables/disables VMX in coreboot on chromebooks. There are several reasons for this: 1. It's a core setting, not a platform setting, which is bizarre. But, we disable vmx via an SMI, and that only happens on core 0. Hence, the code did not correctly make the same settings on all cores- one had them disabled, the others were in an unknown state. When (e.g.) kvm started on a vmx-enabled core, then moved to a vmx-disabled core, the processor would reset *very* quickly. Changing this would be messy. 2. On the CPU on link, there is something about trying to set the lock bit that is getting a GPF. 3. It's the wrong place and time to set it. Once controlled, they can't be changed in the kernel. The kernel is what should control this feature, not the BIOS, as we have learned time and time again. If somebody is in as root and can start a VM, you have a lot more to worry about than someone starting a guest virtual machine. Change-Id: I4f36093f1b68207251584066ccb9a6bcfeec767e Signed-off-by: Ronald G. Minnich <rminnich(a)chromium.org> Build-Tested: build bot (Jenkins) at Tue Jul 24 02:58:53 2012, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Tue Jul 24 06:54:59 2012, giving +2 See http://review.coreboot.org/1276 for details. -gerrit

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Patch merged into coreboot/master: 104f855 malloc/memalign: Remove unneeded linker check
by gerrit＠coreboot.org 24 Jul '12

24 Jul '12

the following patch was just integrated into master: commit 104f85537f63a2ace2176c70cdc1b6a4ae6f2334 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Wed Jun 6 13:43:52 2012 -0700 malloc/memalign: Remove unneeded linker check This check got in the code when some Linux distros shipped broken linkers around 1999. Since then, the code around that check was changed, and it does not make sense anymore to have this check. Change-Id: I37c6b690d72f55c18ba4c34e8541a6a441e5e67a Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Build-Tested: build bot (Jenkins) at Tue Jul 24 02:35:01 2012, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Tue Jul 24 02:38:38 2012, giving +2 See http://review.coreboot.org/1275 for details. -gerrit

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Patch merged into coreboot/master: 5056b5b SPI flash layer: remove unused function spi_flash_free()
by gerrit＠coreboot.org 24 Jul '12

24 Jul '12

the following patch was just integrated into master: commit 5056b5bb37bc1b86e901fe5738df27ca568c8cb8 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Wed Jun 6 13:40:12 2012 -0700 SPI flash layer: remove unused function spi_flash_free() We don't ever free memory in coreboot, hence drop spi_flash_free() and spi_free_slave() Change-Id: I0ca3f78574ceb4516e7d33c06ab1a58abfb3b0ec Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Build-Tested: build bot (Jenkins) at Tue Jul 24 01:51:10 2012, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Tue Jul 24 02:37:39 2012, giving +2 See http://review.coreboot.org/1273 for details. -gerrit

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Patch merged into coreboot/master: 1989fd3 MTRR: drop repetetive debug message
by gerrit＠coreboot.org 24 Jul '12

24 Jul '12

the following patch was just integrated into master: commit 1989fd38fdd5695c188f3c188b0176d748f70fdd Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Wed Jun 6 13:46:26 2012 -0700 MTRR: drop repetetive debug message It's not really useful anymore I guess, and it makes the log files harder to read. Hence dropping it. Change-Id: If4c3e8b40ae491ca527ef62f8145206960f6579d Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Build-Tested: build bot (Jenkins) at Tue Jul 24 01:33:25 2012, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Tue Jul 24 02:37:06 2012, giving +2 See http://review.coreboot.org/1272 for details. -gerrit

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coreboot July 2012