coreboot July 2012

coreboot@coreboot.org

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639 discussions

Patch merged into coreboot/master: 2f91fad Cougar/Panther Point: Compile in ME7 and ME8 code at the same time
by gerrit＠coreboot.org 24 Jul '12

24 Jul '12

the following patch was just integrated into master: commit 2f91fad6bebbd00b60f1b0fd1d7501a0400e04f1 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Mon Jun 11 15:15:46 2012 -0700 Cougar/Panther Point: Compile in ME7 and ME8 code at the same time In the short term there might be devices with Sandy Bridge CPUs on mainboards with Panther Point PCHes. While this configuration option is perfectly valid, coreboot currently ties Sandy Bridge to Cougar Point and Ivy Bridge to Panther Point. One occurence is in the ME handling code. To make coreboot most flexible, compile both ME handlers into coreboot and decide at runtime which one to use. Change-Id: Icffe2930873f67c99c3f73e37e7a967f4f002b88 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Build-Tested: build bot (Jenkins) at Tue Jul 24 04:15:32 2012, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Tue Jul 24 23:17:17 2012, giving +2 See http://review.coreboot.org/1280 for details. -gerrit

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Patch merged into coreboot/master: a68e3d1 Fix ME hash functions on Panther Point/Cougar Point
by gerrit＠coreboot.org 24 Jul '12

24 Jul '12

the following patch was just integrated into master: commit a68e3d1880817916d1f58413340d672cf8341dd9 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Mon Jun 11 14:13:09 2012 -0700 Fix ME hash functions on Panther Point/Cougar Point - On Cougar Point there may have been stack corruption during the ME hash verification - On Panther Point the ME firmware hash was not passed on to the OS Change-Id: I73fc10db63ecff939833fb856a6da1e394155043 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Build-Tested: build bot (Jenkins) at Tue Jul 24 04:00:51 2012, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Tue Jul 24 23:16:14 2012, giving +2 See http://review.coreboot.org/1279 for details. -gerrit

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Patch merged into coreboot/master: fd2d352 Config changes to support microcode in CBFS
by gerrit＠coreboot.org 24 Jul '12

24 Jul '12

the following patch was just integrated into master: commit fd2d35281ebb6d59d06fcd53a19f7e7d325dd5a3 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Tue Jun 19 04:20:20 2012 +0000 Config changes to support microcode in CBFS Nothing is yet enabled, this is just a config skeleton change. The MICROCODE_INCLUDE_PATH definition is going to be used by the Makefile building the microcode blob for CBFS inclusion. Change-Id: I7868db3cfd4b181500e361706e5f4dc08ca1c87d Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Build-Tested: build bot (Jenkins) at Tue Jul 24 08:05:50 2012, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Tue Jul 24 23:15:34 2012, giving +2 See http://review.coreboot.org/1292 for details. -gerrit

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Patch merged into coreboot/master: 9befba2 Add BAR address debug information to Oxford PCIe serial driver
by gerrit＠coreboot.org 24 Jul '12

24 Jul '12

the following patch was just integrated into master: commit 9befba2ae7ce00e230d563622d9460be635247b3 Author: Marc Jones <marc.jones(a)se-eng.com> Date: Mon Jul 2 22:31:22 2012 -0600 Add BAR address debug information to Oxford PCIe serial driver The Oxford PCIE Serial card has a hardcoded address at setup, which may be moved during PCI Init. The driver re-initializes after PCI init. Add a debug print for the new BAR address. Initializing Oxford OXPCIe952 OXPCIe952: Class=70002 Revision ID=0 OXPCIe952: 2 UARTs detected. OXPCIe952: Uart Bar: 0xe0800000 Change-Id: I1858d3eba09749cba3c3869060d00e621dca112a Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Build-Tested: build bot (Jenkins) at Tue Jul 24 22:10:21 2012, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Tue Jul 24 22:47:52 2012, giving +2 See http://review.coreboot.org/1327 for details. -gerrit

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Patch merged into coreboot/master: 4199fe3 Add microcode blob processing
by gerrit＠coreboot.org 24 Jul '12

24 Jul '12

the following patch was just integrated into master: commit 4199fe3d470a2a9e9f87058ede9037307647ca31 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Tue Jun 19 08:34:51 2012 -0700 Add microcode blob processing When microcode storage in CBFS is enabled, the make system is supposed to generate the microcode blob and place it into the generated ROM image as a CBFS component. The microcode source representation does not change: it is still an array of 32 bit constants. This new addition compiles the array into a separate object file and then strips all sections but data. The raw data section is then included into CBFS as a file named 'microcode_blob.bin' of type 0x53, which is assigned to microcode storage. Change-Id: I84ae040be52f520b106e3471c7e391e64d7847d9 Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Build-Tested: build bot (Jenkins) at Tue Jul 24 08:51:41 2012, giving +1 See http://review.coreboot.org/1295 for details. -gerrit

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Patch merged into coreboot/master: 23e192d Add code to read Intel microcode from CBFS
by gerrit＠coreboot.org 24 Jul '12

24 Jul '12

the following patch was just integrated into master: commit 23e192d58ff8112518cf6f5cc01bb3bb173f4660 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Tue Jun 19 12:56:57 2012 -0700 Add code to read Intel microcode from CBFS When CONFIG_MICROCODE_IN_CBFS is enabled, find the microcode blob in CBFS and pass it to intel_update_microcode() instead of using the compiled in array. CBFS accesses in pre-RAM and 'normal' environments are provided through different API. Change-Id: I35c1480edf87e550a7b88c4aadf079cf3ff86b5d Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Build-Tested: build bot (Jenkins) at Tue Jul 24 09:29:47 2012, giving +1 See http://review.coreboot.org/1296 for details. -gerrit

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Patch merged into coreboot/master: 0e8fa37 Add PCIe port disable debug message
by gerrit＠coreboot.org 24 Jul '12

24 Jul '12

the following patch was just integrated into master: commit 0e8fa37a7a349594407a367bf45d42d2af4a7f55 Author: Marc Jones <marc.jones(a)se-eng.com> Date: Fri Jun 15 23:03:15 2012 -0600 Add PCIe port disable debug message The PCIe device enable function prints when it disables a device. The PCIe ports(bridges) use a different routine that didn't print the message. Add it to be consistent and to provide better debug output. Change-Id: I8462c48e7f4930db68703f0bfb710c01c9643a98 Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Tue Jul 24 08:41:34 2012, giving +2 Build-Tested: build bot (Jenkins) at Tue Jul 24 21:36:45 2012, giving +1 See http://review.coreboot.org/1326 for details. -gerrit

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Patch merged into coreboot/master: 2c987a6 Make MAX_PHYSICAL_CPUS invisible on non-AMD boards
by gerrit＠coreboot.org 24 Jul '12

24 Jul '12

the following patch was just integrated into master: commit 2c987a68e57477fadd78c4d1e73469d9447fde53 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Mon Jun 25 14:12:58 2012 -0700 Make MAX_PHYSICAL_CPUS invisible on non-AMD boards It's only used on AMD based boards. Hence drop it, so we don't accidently start using it by mistake instead of MAX_CPUS Change-Id: Id8f522f24283129874d56e70bd00df92abe9c3cf Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Build-Tested: build bot (Jenkins) at Tue Jul 24 21:01:55 2012, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Tue Jul 24 21:31:28 2012, giving +2 See http://review.coreboot.org/1325 for details. -gerrit

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Patch merged into coreboot/master: b933096 bd82x6x: Support power-on-after-power-fail better
by gerrit＠coreboot.org 24 Jul '12

24 Jul '12

the following patch was just integrated into master: commit b933096316ccc00d7801f06b0e68604bdfaad002 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Thu Jun 28 12:18:41 2012 -0700 bd82x6x: Support power-on-after-power-fail better Changing CMOS value for power-on-after-power-fail was only honored after reboot, which is counter intuitive (set from "enable" to "disable", power-off, replug device -> device turns on; and similar cases). Modelled after http://review.coreboot.org/#/c/444 Change-Id: I2b8461dff1ae085c1ea4b4926084268b4da90321 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Tue Jul 24 20:09:46 2012, giving +2 See http://review.coreboot.org/1323 for details. -gerrit

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Patch merged into coreboot/master: aa33165 Rename microcode include file to be model agnostic
by gerrit＠coreboot.org 24 Jul '12

24 Jul '12

the following patch was just integrated into master: commit aa331657ff2fbabb32681809b6eab7d7b874deeb Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Tue Jun 19 05:25:41 2012 +0000 Rename microcode include file to be model agnostic In preparation to support CBFS hosted microcode blobs, this change renames the wrapper include file containing the microcode to be independent of CPU model. Change-Id: If1a4963a52e5037a3a3495b90708ffc08b23f4c1 Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Build-Tested: build bot (Jenkins) at Tue Jul 24 08:35:00 2012, giving +1 See http://review.coreboot.org/1294 for details. -gerrit

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coreboot July 2012