coreboot July 2012

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Patch set updated for coreboot: 9a8aa1c IEI PM-LX2-800-R10: Added preliminary mainboard support
by Patrick Georgi 25 Jul '12

25 Jul '12

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1152 -gerrit commit 9a8aa1c0a01999a4983b5854afcece8841926e90 Author: Ricardo Martins <rasmartins(a)gmail.com> Date: Sat Jul 7 14:27:03 2012 +0100 IEI PM-LX2-800-R10: Added preliminary mainboard support Details for this board are available at http://usa.ieiworld.com/product_groups/industrial/content.aspx?gid=00001000… Most of the functionality provided by the original BIOS is implemented. The Geode Link Speed is hardcoded to a safe value. I'll add automatic configuration in a later patch. Change-Id: Iaefe47f5ad405a56d230c929e5850156eb0f60ae Signed-off-by: Ricardo Martins <rasmartins(a)gmail.com> --- src/mainboard/iei/Kconfig | 3 + src/mainboard/iei/pm-lx2-800-r10/Kconfig | 58 ++++++++++ src/mainboard/iei/pm-lx2-800-r10/chip.h | 23 ++++ src/mainboard/iei/pm-lx2-800-r10/cmos.layout | 103 ++++++++++++++++++ src/mainboard/iei/pm-lx2-800-r10/devicetree.cb | 87 +++++++++++++++ src/mainboard/iei/pm-lx2-800-r10/irq_tables.c | 134 ++++++++++++++++++++++++ src/mainboard/iei/pm-lx2-800-r10/it8888_io.def | 27 +++++ src/mainboard/iei/pm-lx2-800-r10/mainboard.c | 103 ++++++++++++++++++ src/mainboard/iei/pm-lx2-800-r10/romstage.c | 91 ++++++++++++++++ 9 files changed, 629 insertions(+), 0 deletions(-) diff --git a/src/mainboard/iei/Kconfig b/src/mainboard/iei/Kconfig index ea26922..537252d 100644 --- a/src/mainboard/iei/Kconfig +++ b/src/mainboard/iei/Kconfig @@ -31,6 +31,8 @@ config BOARD_IEI_PCISA_LX_800_R10 bool "PCISA LX-800-R10" config BOARD_IEI_PM_LX_800_R11 bool "PM LX-800-R11" +config BOARD_IEI_PM_LX2_800_R10 + bool "PM-LX2-800-R10" endchoice @@ -39,6 +41,7 @@ source "src/mainboard/iei/kino-780am2-fam10/Kconfig" source "src/mainboard/iei/nova4899r/Kconfig" source "src/mainboard/iei/pcisa-lx-800-r10/Kconfig" source "src/mainboard/iei/pm-lx-800-r11/Kconfig" +source "src/mainboard/iei/pm-lx2-800-r10/Kconfig" config MAINBOARD_VENDOR string diff --git a/src/mainboard/iei/pm-lx2-800-r10/Kconfig b/src/mainboard/iei/pm-lx2-800-r10/Kconfig new file mode 100644 index 0000000..62f8520 --- /dev/null +++ b/src/mainboard/iei/pm-lx2-800-r10/Kconfig @@ -0,0 +1,58 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2012 Ricardo Martins <rasmartins(a)gmail.com> +## +## This program is free software; you can redistribute it and/or +## modify it under the terms of the GNU General Public License as +## published by the Free Software Foundation; version 2 of +## the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +## MA 02110-1301 USA +## + +if BOARD_IEI_PM_LX2_800_R10 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select ARCH_X86 + select CPU_AMD_GEODE_LX + select NORTHBRIDGE_AMD_LX + select SOUTHBRIDGE_AMD_CS5536 + select SUPERIO_SMSC_SMSCSUPERIO + select HAVE_PIRQ_TABLE + select HAVE_OPTION_TABLE + select PIRQ_ROUTE + select BOARD_ROMSIZE_KB_512 + select POWER_BUTTON_FORCE_ENABLE + select PLL_MANUAL_CONFIG + select CORE_GLIU_500_266 + +config MAINBOARD_DIR + string + default iei/pm-lx2-800-r10 + +config MAINBOARD_PART_NUMBER + string + default "PM-LX2-800-R10" + +config IRQ_SLOT_COUNT + int + default 3 + +config SCH3114_COM3_AUTO_DIR + bool "COM3 Automatic Direction Control" + default y + help + If selected, COM3 automatic direction control will + be enabled by default. + +endif # BOARD_IEI_PM_LX2_800_R10 diff --git a/src/mainboard/iei/pm-lx2-800-r10/chip.h b/src/mainboard/iei/pm-lx2-800-r10/chip.h new file mode 100644 index 0000000..d69f9b6 --- /dev/null +++ b/src/mainboard/iei/pm-lx2-800-r10/chip.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Ricardo Martins <rasmartins(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/iei/pm-lx2-800-r10/cmos.layout b/src/mainboard/iei/pm-lx2-800-r10/cmos.layout new file mode 100644 index 0000000..e09cfb6 --- /dev/null +++ b/src/mainboard/iei/pm-lx2-800-r10/cmos.layout @@ -0,0 +1,103 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2012 Ricardo Martins <rasmartins(a)gmail.com> +## +## This program is free software; you can redistribute it and/or +## modify it under the terms of the GNU General Public License as +## published by the Free Software Foundation; version 2 of +## the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +## MA 02110-1301 USA +## + +entries + # RTC + 0 384 r 0 reserved_rtc + # Coreboot + 384 1 e 3 boot_option + 385 1 e 3 last_boot + 386 4 r 0 reboot_bits + 390 3 e 4 baud_rate + 393 4 e 5 debug_level + 397 2 r 0 unused + # PM-LX2-800-R10 + 399 1 e 1 com3_auto_direction + 400 1 e 2 it8888_io_space0 + 401 1 e 2 it8888_io_space1 + 402 1 e 2 it8888_io_space2 + 403 1 e 2 it8888_io_space3 + 404 2 e 6 it8888_io_space0_speed + 406 2 e 6 it8888_io_space1_speed + 408 2 e 6 it8888_io_space2_speed + 410 2 e 6 it8888_io_space3_speed + 412 3 e 7 it8888_io_space0_size + 415 3 e 7 it8888_io_space1_size + 418 3 e 7 it8888_io_space2_size + 421 3 e 7 it8888_io_space3_size + 424 16 h 0 it8888_io_space0_addr + 440 16 h 0 it8888_io_space1_addr + 456 16 h 0 it8888_io_space2_addr + 472 16 h 0 it8888_io_space3_addr + 488 16 h 0 check_sum + +enumerations + # Yes / No + 1 0 No + 1 1 Yes + + # Enabled / Disabled + 2 0 Disabled + 2 1 Enabled + + # Normal / Fallback + 3 0 Fallback + 3 1 Normal + + # Console Baud Rate + 4 0 115200 + 4 1 57600 + 4 2 38400 + 4 3 19200 + 4 4 9600 + 4 5 4800 + 4 6 2400 + 4 7 1200 + + # Console Log Level + 5 0 Emergency + 5 1 Alert + 5 2 Critical + 5 3 Error + 5 4 Warning + 5 5 Notice + 5 6 Info + 5 7 Debug + 5 8 Spew + + # IT8888 Decoding Speeds + 6 0 Subtractive + 6 1 Slow + 6 2 Medium + 6 3 Fast + + # IT8888 Decoding Sizes + 7 0 1 + 7 1 2 + 7 2 4 + 7 3 8 + 7 4 16 + 7 5 32 + 7 6 64 + 7 7 128 + +checksums + checksum 384 487 488 diff --git a/src/mainboard/iei/pm-lx2-800-r10/devicetree.cb b/src/mainboard/iei/pm-lx2-800-r10/devicetree.cb new file mode 100644 index 0000000..f5721a3 --- /dev/null +++ b/src/mainboard/iei/pm-lx2-800-r10/devicetree.cb @@ -0,0 +1,87 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2012 Ricardo Martins <rasmartins(a)gmail.com> +## +## This program is free software; you can redistribute it and/or +## modify it under the terms of the GNU General Public License as +## published by the Free Software Foundation; version 2 of +## the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +## MA 02110-1301 USA +## + +chip northbridge/amd/lx + device pci_domain 0 on + device pci 1.0 on end # Northbridge + device pci 1.1 on end # Video Adapter + device pci 1.2 on end # AES Security Block + chip southbridge/amd/cs5536 + register "lpc_serirq_enable" = "0x000010da" + register "lpc_serirq_polarity" = "0x0000ef25" + register "lpc_serirq_mode" = "1" + register "enable_gpio_int_route" = "0x0d0c0700" + register "enable_ide_nand_flash" = "0" + register "enable_USBP4_device" = "0" # 0:host, 1:device + register "enable_USBP4_overcurrent" = "0" + register "com1_enable" = "0" + register "com2_enable" = "0" + register "unwanted_vpci[0]" = "0" # End of list has a zero + device pci 11.0 on end # IT8888 + device pci e.0 on end # RTL8100C + device pci f.0 on # ISA Bridge + chip superio/smsc/smscsuperio # SMSC SCH3114 + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + + device pnp 2e.3 off # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + end + + device pnp 2e.4 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + + device pnp 2e.5 on # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + + device pnp 2e.7 on # PS/2 keyboard/mouse + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 # Keyboard + irq 0x72 = 12 # Mouse + end + + device pnp 2e.a on # Runtime Register + io 0x60 = 0x400 + end + end + end + device pci f.2 on end # IDE Controller + device pci f.3 on end # Audio + device pci f.4 on end # OHCI + device pci f.5 on end # EHCI + end + end + # APIC cluster is late CPU init. + device lapic_cluster 0 on + chip cpu/amd/geode_lx + device lapic 0 on end + end + end +end diff --git a/src/mainboard/iei/pm-lx2-800-r10/irq_tables.c b/src/mainboard/iei/pm-lx2-800-r10/irq_tables.c new file mode 100644 index 0000000..2bbf218 --- /dev/null +++ b/src/mainboard/iei/pm-lx2-800-r10/irq_tables.c @@ -0,0 +1,134 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Ricardo Martins <rasmartins(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <device/pci_ids.h> +#include <arch/pirq_routing.h> + +/* Platform IRQs */ +#define PIRQA 10 +#define PIRQB 10 +#define PIRQC 11 +#define PIRQD 11 + +/* Links */ +#define L_PIRQN 0 +#define L_PIRQA 1 +#define L_PIRQB 2 +#define L_PIRQC 3 +#define L_PIRQD 4 + +/* Bitmaps */ +#define B_LINKN (0) +#define B_LINK0 (1 << PIRQA) +#define B_LINK1 (1 << PIRQB) +#define B_LINK2 (1 << PIRQC) +#define B_LINK3 (1 << PIRQD) + +const struct irq_routing_table intel_irq_routing_table = { + PIRQ_SIGNATURE, /* u32 signature */ + PIRQ_VERSION, /* u16 version */ + 32 + 16 * CONFIG_IRQ_SLOT_COUNT, /* Max. number of devices on the bus */ + 0x00, /* Interrupt router bus */ + (0x0f << 3) | 0x0, /* Interrupt router dev */ + (B_LINK0 | B_LINK1 | B_LINK2 | B_LINK3),/* IRQs devoted exclusively to PCI usage */ + PCI_VENDOR_ID_AMD, /* Vendor */ + PCI_DEVICE_ID_AMD_CS5536_ISA, /* Device */ + 0, /* Miniport */ + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + 0x27, /* Checksum */ + { + [0] = { /* Host bridge */ + .slot = 0x00, + .bus = 0x00, + .devfn = (0x01 << 3) | 0x0, + .irq = { + [0] = { + .link = L_PIRQA, + .bitmap = B_LINK0 + }, + [1] = { + .link = L_PIRQN, + .bitmap = B_LINKN + }, + [2] = { + .link = L_PIRQN, + .bitmap = B_LINKN + }, + [3] = { + .link = L_PIRQN, + .bitmap = B_LINKN + } + } + }, + + [1] = { /* ISA bridge */ + .slot = 0x00, + .bus = 0x00, + .devfn = (0x0f << 3) | 0x0, + .irq = { + [0] = { + .link = L_PIRQN, + .bitmap = B_LINKN + }, + [1] = { + .link = L_PIRQB, + .bitmap = B_LINK1 + }, + [2] = { + .link = L_PIRQN, + .bitmap = B_LINKN + }, + [3] = { + .link = L_PIRQD, + .bitmap = B_LINK3 + } + } + }, + + [2] = { /* Ethernet */ + .slot = 0x00, + .bus = 0x00, + .devfn = (0x0e << 3) | 0x0, + .irq = { + [0] = { + .link = L_PIRQD, + .bitmap = B_LINK3 + }, + [1] = { + .link = L_PIRQN, + .bitmap = B_LINKN + }, + [2] = { + .link = L_PIRQN, + .bitmap = B_LINKN + }, + [3] = { + .link = L_PIRQN, + .bitmap = B_LINKN + } + } + } + } +}; + +unsigned long write_pirq_routing_table(unsigned long addr) +{ + return copy_pirq_routing_table(addr); +} diff --git a/src/mainboard/iei/pm-lx2-800-r10/it8888_io.def b/src/mainboard/iei/pm-lx2-800-r10/it8888_io.def new file mode 100644 index 0000000..5920abc --- /dev/null +++ b/src/mainboard/iei/pm-lx2-800-r10/it8888_io.def @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Ricardo Martins <rasmartins(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* Name, Register, Enabled/Disabled, Speed, Size, Address. */ +IT8888_IO("it8888_io_space0", 0x58, 0, 0, 0, 0) +IT8888_IO("it8888_io_space1", 0x5c, 0, 0, 0, 0) +IT8888_IO("it8888_io_space2", 0x60, 0, 0, 0, 0) +IT8888_IO("it8888_io_space3", 0x64, 0, 0, 0, 0) +IT8888_IO("it8888_io_space4", 0x68, 0, 0, 0, 0) +IT8888_IO("it8888_io_space5", 0x6c, 0, 0, 0, 0) diff --git a/src/mainboard/iei/pm-lx2-800-r10/mainboard.c b/src/mainboard/iei/pm-lx2-800-r10/mainboard.c new file mode 100644 index 0000000..170a67a --- /dev/null +++ b/src/mainboard/iei/pm-lx2-800-r10/mainboard.c @@ -0,0 +1,103 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Ricardo Martins <rasmartins(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <console/console.h> +#include <device/pci.h> +#include <device/device.h> +#include <boot/tables.h> +#include <pc80/mc146818rtc.h> +#include "chip.h" + +#if CONFIG_USE_OPTION_TABLE +# include "option_table.h" +#endif + +/* SCH3114 runtime register (RTR) address. */ +#define SCH3114_RTR_ADDR (0x400) +/* SP34 option register. */ +#define SCH3114_RTR_SP34_OPT (SCH3114_RTR_ADDR + 0x13) +/* H/W Monitoring register block index. */ +#define SCH3114_RTR_HWM_IDX (SCH3114_RTR_ADDR + 0x70) +/* H/W Monitoring register block data. */ +#define SCH3114_RTR_HWM_DAT (SCH3114_RTR_ADDR + 0x71) +/* H/W Monitoring Ready/Lock/Start register. */ +#define SCH3114_HWM_RLS_REG (0x40) +/* IT8888 PCI Vendor ID. */ +#define IT8888_PCI_VID (0x1283) +/* IT8888 PCI Device ID. */ +#define IT8888_PCI_DID (0x8888) + +static u16 opt(const char* option, u16 def_value) +{ +#if CONFIG_USE_OPTION_TABLE + u16 value = 0; + if (get_option(&value, option) != 0) + value = def_value; + return value; +#else + return def_value; +#endif +} + +static void init(struct device *dev) +{ + /* SCH3114: enable hardware monitor. */ + printk(BIOS_INFO, "Enabling SCH3114 hardware monitor\n"); + outb(SCH3114_HWM_RLS_REG, SCH3114_RTR_HWM_IDX); + outb(inb(SCH3114_RTR_HWM_DAT) | 0x01, SCH3114_RTR_HWM_DAT); + + /* SCH3114: COM3 Automatic Direction Control / nRTS control. */ + if (opt("com3_auto_direction", CONFIG_SCH3114_COM3_AUTO_DIR) != 0) { + printk(BIOS_INFO, "Enabling RS858 Auto Direction Control\n"); + outb(inb(SCH3114_RTR_SP34_OPT) | 0x03, SCH3114_RTR_SP34_OPT); + } + + /* IT8888. */ + device_t it8x = dev_find_device(IT8888_PCI_VID, IT8888_PCI_DID, 0); + if (!it8x) { + printk(BIOS_ERR, "IT8888 not found\n"); + return; + } + + u32 cfg = 0; +#define IT8888_IO(name, reg, dena, dspeed, dsize, daddr) \ + if (opt(name, dena) != 0) { \ + cfg = (1 << 31); \ + cfg |= opt(name "_addr", daddr); \ + cfg |= opt(name "_speed", dspeed) << 29; \ + cfg |= opt(name "_size", dsize) << 24; \ + } else { \ + cfg = 0; \ + } \ + pci_write_config32(it8x, reg, cfg); + +#include "it8888_io.def" +} + +static void enable_dev(struct device *dev) +{ + dev->ops->init = init; +} + +struct chip_operations mainboard_ops = { + CHIP_NAME("IEI PM-LX2-800-R10 Mainboard") + .enable_dev = enable_dev, +}; diff --git a/src/mainboard/iei/pm-lx2-800-r10/romstage.c b/src/mainboard/iei/pm-lx2-800-r10/romstage.c new file mode 100644 index 0000000..fdc8e2d --- /dev/null +++ b/src/mainboard/iei/pm-lx2-800-r10/romstage.c @@ -0,0 +1,91 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Advanced Micro Devices, Inc. + * Copyright (C) 2012 Ricardo Martins <rasmartins(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include <stdlib.h> + +#include <spd.h> +#include <arch/io.h> +#include <arch/hlt.h> +#include <arch/llshell.h> +#include <device/pci_def.h> +#include <device/pnp_def.h> +#include <console/console.h> +#include <cpu/x86/bist.h> +#include <cpu/x86/msr.h> +#include <cpu/amd/lxdef.h> +#include <southbridge/amd/cs5536/cs5536.h> +#include <southbridge/amd/cs5536/early_smbus.c> +#include <southbridge/amd/cs5536/early_setup.c> +#include <superio/smsc/smscsuperio/early_serial.c> + +#define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1) + +static inline int spd_read_byte(unsigned int device, unsigned int address) +{ + /* Only DIMM0 is available. */ + if (device != DIMM0) + return 0xFF; + + return smbus_read_byte(device, address); +} + +#include <northbridge/amd/lx/raminit.h> +#include <northbridge/amd/lx/pll_reset.c> +#include <northbridge/amd/lx/raminit.c> +#include <lib/generic_sdram.c> +#include <cpu/amd/geode_lx/cpureginit.c> +#include <cpu/amd/geode_lx/syspreinit.c> +#include <cpu/amd/geode_lx/msrinit.c> + +void main(unsigned long bist) +{ + static const struct mem_controller memctrl[] = { + {.channel0 = {DIMM0, DIMM1}} + }; + + SystemPreInit(); + msr_init(); + + cs5536_early_setup(); + + smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + console_init(); + + /* Enable COM3. */ + device_t dev = PNP_DEV(0x2e, 0x0b); + u16 port = dev >> 8; + outb(0x55, port); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, 0x3e8); + pnp_set_irq(dev, PNP_IDX_IRQ0, 4); + pnp_set_enable(dev, 1); + outb(0xaa, port); + + report_bist_failure(bist); + + pll_reset(); + + cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED); + + sdram_initialize(1, memctrl); +}

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New patch to review for coreboot: e605f78 Remove useless semicolon
by Patrick Georgi 25 Jul '12

25 Jul '12

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1354 -gerrit commit e605f788a2cc53f6229e826073f2ef842e00868f Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Wed Jul 25 08:55:53 2012 +0200 Remove useless semicolon Change-Id: Idc4d5737f5b49108987ca7fe90410d4e80b723f2 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- src/devices/device.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/src/devices/device.c b/src/devices/device.c index 9753de8..92a4447 100644 --- a/src/devices/device.c +++ b/src/devices/device.c @@ -737,7 +737,7 @@ static void set_vga_bridge_bits(void) /* It isn't safe to enable all VGA cards. */ dev->command &= ~(PCI_COMMAND_MEMORY | PCI_COMMAND_IO); - }; + } if (!vga) vga = vga_onboard;

1 0

Patch set updated for coreboot: ebdbbbd amd/lx: Move configuration from source to Kconfig
by Patrick Georgi 25 Jul '12

25 Jul '12

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1227 -gerrit commit ebdbbbd1eee3e96741d62bffb958a0351e470a72 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Fri Jul 13 19:06:22 2012 +0200 amd/lx: Move configuration from source to Kconfig LX has two values that are usually automatically derived but can be overridden, that were so far defined in each board's romstage. These values, along with the toggle to enable override are now part of LX's Kconfig. For boards that gave values but requested autogeneration, the values are removed. Further improvements: Figure out the various fields in PLLMSRlo and make them sensible Kconfig options (instead of the hex value it is now) Change-Id: I8a17c89e4a3cb1b52aaceef645955ab7817b482d Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- src/mainboard/aaeon/pfm-540i_revb/romstage.c | 6 +--- src/mainboard/amd/db800/romstage.c | 6 +--- src/mainboard/amd/norwich/romstage.c | 6 +--- src/mainboard/artecgroup/dbe61/romstage.c | 8 +----- src/mainboard/bachmann/ot200/Kconfig | 6 ++++ src/mainboard/bachmann/ot200/romstage.c | 6 +--- src/mainboard/digitallogic/msm800sev/romstage.c | 6 +--- src/mainboard/iei/pcisa-lx-800-r10/Kconfig | 6 ++++ src/mainboard/iei/pcisa-lx-800-r10/romstage.c | 10 +------ src/mainboard/iei/pm-lx-800-r11/Kconfig | 19 +++---------- src/mainboard/iei/pm-lx-800-r11/romstage.c | 12 +-------- src/mainboard/lippert/hurricane-lx/Kconfig | 6 ++++ src/mainboard/lippert/hurricane-lx/romstage.c | 6 +--- src/mainboard/lippert/literunner-lx/Kconfig | 6 ++++ src/mainboard/lippert/literunner-lx/romstage.c | 6 +--- src/mainboard/lippert/roadrunner-lx/Kconfig | 6 ++++ src/mainboard/lippert/roadrunner-lx/romstage.c | 6 +--- src/mainboard/lippert/spacerunner-lx/Kconfig | 6 ++++ src/mainboard/lippert/spacerunner-lx/romstage.c | 6 +--- src/mainboard/pcengines/alix1c/romstage.c | 6 +--- src/mainboard/pcengines/alix2d/romstage.c | 6 +--- src/mainboard/traverse/geos/Kconfig | 6 ++++ src/mainboard/traverse/geos/romstage.c | 6 +--- src/mainboard/winent/pl6064/romstage.c | 6 +--- src/northbridge/amd/lx/Kconfig | 31 ++++++++++++++++++++++- src/northbridge/amd/lx/pll_reset.c | 8 +++--- 26 files changed, 97 insertions(+), 111 deletions(-) diff --git a/src/mainboard/aaeon/pfm-540i_revb/romstage.c b/src/mainboard/aaeon/pfm-540i_revb/romstage.c index 4b510a9..2d3b71d 100644 --- a/src/mainboard/aaeon/pfm-540i_revb/romstage.c +++ b/src/mainboard/aaeon/pfm-540i_revb/romstage.c @@ -47,10 +47,6 @@ static inline int spd_read_byte(unsigned int device, unsigned int address) return smbus_read_byte(device, address); } -#define ManualConf 0 /* Do automatic strapped PLL config */ -#define PLLMSRhi 0x000005DD /* Manual settings for the PLL */ -#define PLLMSRlo 0x00DE60EE - #include "northbridge/amd/lx/raminit.h" #include "northbridge/amd/lx/pll_reset.c" #include "northbridge/amd/lx/raminit.c" @@ -79,7 +75,7 @@ void main(unsigned long bist) /* Halt if there was a built in self test failure */ report_bist_failure(bist); - pll_reset(ManualConf); + pll_reset(); cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED); diff --git a/src/mainboard/amd/db800/romstage.c b/src/mainboard/amd/db800/romstage.c index 3590c37..2bb6cd3 100644 --- a/src/mainboard/amd/db800/romstage.c +++ b/src/mainboard/amd/db800/romstage.c @@ -41,10 +41,6 @@ static inline int spd_read_byte(unsigned int device, unsigned int address) return smbus_read_byte(device, address); } -#define ManualConf 0 /* Do automatic strapped PLL config */ -#define PLLMSRhi 0x000005DD /* Manual settings for the PLL */ -#define PLLMSRlo 0x00DE60EE - #include "northbridge/amd/lx/raminit.h" #include "northbridge/amd/lx/pll_reset.c" #include "northbridge/amd/lx/raminit.c" @@ -74,7 +70,7 @@ void main(unsigned long bist) /* Halt if there was a built in self test failure */ report_bist_failure(bist); - pll_reset(ManualConf); + pll_reset(); cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED); diff --git a/src/mainboard/amd/norwich/romstage.c b/src/mainboard/amd/norwich/romstage.c index d8fca5a..c71b31f 100644 --- a/src/mainboard/amd/norwich/romstage.c +++ b/src/mainboard/amd/norwich/romstage.c @@ -38,10 +38,6 @@ static inline int spd_read_byte(unsigned int device, unsigned int address) return smbus_read_byte(device, address); } -#define ManualConf 0 /* Do automatic strapped PLL config */ -#define PLLMSRhi 0x00001490 /* manual settings for the PLL */ -#define PLLMSRlo 0x02000030 - #include "northbridge/amd/lx/raminit.h" #include "northbridge/amd/lx/pll_reset.c" #include "northbridge/amd/lx/raminit.c" @@ -75,7 +71,7 @@ void main(unsigned long bist) /* Halt if there was a built in self test failure */ report_bist_failure(bist); - pll_reset(ManualConf); + pll_reset(); cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED); diff --git a/src/mainboard/artecgroup/dbe61/romstage.c b/src/mainboard/artecgroup/dbe61/romstage.c index f97af92..61bd03e 100644 --- a/src/mainboard/artecgroup/dbe61/romstage.c +++ b/src/mainboard/artecgroup/dbe61/romstage.c @@ -51,12 +51,6 @@ static int spd_read_byte(unsigned device, unsigned address) return 0xFF; } -#define ManualConf 0 /* Do automatic strapped PLL config */ -/* CPU and GLIU mult/div 500/266*/ -#define PLLMSRhi 0x0000039C /* 33MHz PCI, 0x000003DD for 66MHz PCI */ -/* Hold Count - how long we will sit in reset */ -#define PLLMSRlo 0x00DE6000 - #include "northbridge/amd/lx/raminit.h" #include "northbridge/amd/lx/pll_reset.c" #include "northbridge/amd/lx/raminit.c" @@ -94,7 +88,7 @@ void main(unsigned long bist) /* Halt if there was a built in self test failure */ report_bist_failure(bist); - pll_reset(ManualConf); + pll_reset(); cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED); diff --git a/src/mainboard/bachmann/ot200/Kconfig b/src/mainboard/bachmann/ot200/Kconfig index a201bde..5d185c0 100644 --- a/src/mainboard/bachmann/ot200/Kconfig +++ b/src/mainboard/bachmann/ot200/Kconfig @@ -12,6 +12,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy select BOARD_ROMSIZE_KB_2048 select POWER_BUTTON_DEFAULT_DISABLE select DRIVERS_I2C_IDREG + select PLL_MANUAL_CONFIG + select CORE_GLIU_500_266 config MAINBOARD_DIR string @@ -25,4 +27,8 @@ config IRQ_SLOT_COUNT int default 6 +config PLLMSRlo + hex + default 0x07de001e + endif # BOARD_BACHMANN_OT200 diff --git a/src/mainboard/bachmann/ot200/romstage.c b/src/mainboard/bachmann/ot200/romstage.c index 9edd5f7..3a8ecad 100644 --- a/src/mainboard/bachmann/ot200/romstage.c +++ b/src/mainboard/bachmann/ot200/romstage.c @@ -39,10 +39,6 @@ static inline int spd_read_byte(unsigned int device, unsigned int address) return smbus_read_byte(device, address); } -#define ManualConf 1 /* Do automatic strapped PLL config */ -#define PLLMSRhi 0x0000039c /* CPU 500 MHz - GLIU 266 MHz */ -#define PLLMSRlo 0x07de001e - #include "northbridge/amd/lx/raminit.h" #include "northbridge/amd/lx/pll_reset.c" #include "northbridge/amd/lx/raminit.c" @@ -75,7 +71,7 @@ void main(unsigned long bist) /* Halt if there was a built in self test failure */ report_bist_failure(bist); - pll_reset(ManualConf); + pll_reset(); cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED); diff --git a/src/mainboard/digitallogic/msm800sev/romstage.c b/src/mainboard/digitallogic/msm800sev/romstage.c index d30e2b0..caafd2f 100644 --- a/src/mainboard/digitallogic/msm800sev/romstage.c +++ b/src/mainboard/digitallogic/msm800sev/romstage.c @@ -22,10 +22,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) return smbus_read_byte(device, address); } -#define ManualConf 0 /* Do automatic strapped PLL config */ -#define PLLMSRhi 0x00001490 /* manual settings for the PLL */ -#define PLLMSRlo 0x02000030 - #include "northbridge/amd/lx/raminit.h" #include "northbridge/amd/lx/pll_reset.c" #include "northbridge/amd/lx/raminit.c" @@ -57,7 +53,7 @@ void main(unsigned long bist) /* Halt if there was a built in self test failure */ report_bist_failure(bist); - pll_reset(ManualConf); + pll_reset(); cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED); diff --git a/src/mainboard/iei/pcisa-lx-800-r10/Kconfig b/src/mainboard/iei/pcisa-lx-800-r10/Kconfig index eae72ae..69e106e 100644 --- a/src/mainboard/iei/pcisa-lx-800-r10/Kconfig +++ b/src/mainboard/iei/pcisa-lx-800-r10/Kconfig @@ -11,6 +11,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy select PIRQ_ROUTE select BOARD_ROMSIZE_KB_256 select POWER_BUTTON_FORCE_ENABLE + select PLL_MANUAL_CONFIG + select CORE_GLIU_500_266 config MAINBOARD_DIR string @@ -24,4 +26,8 @@ config IRQ_SLOT_COUNT int default 9 +config PLLMSRlo + hex + default 0x00DE6000 + endif # BOARD_IEI_PCISA_LX_800_R10 diff --git a/src/mainboard/iei/pcisa-lx-800-r10/romstage.c b/src/mainboard/iei/pcisa-lx-800-r10/romstage.c index aec9843..7bd1b74 100644 --- a/src/mainboard/iei/pcisa-lx-800-r10/romstage.c +++ b/src/mainboard/iei/pcisa-lx-800-r10/romstage.c @@ -41,14 +41,6 @@ static inline int spd_read_byte(unsigned int device, unsigned int address) return smbus_read_byte(device, address); } -#define ManualConf 1 /* Do automatic strapped PLL config */ -//#define PLLMSRhi 0x0000059C /* CPU and GLIU mult/div 500/400*/ -//#define PLLMSRhi 0x0000049C /* CPU and GLIU mult/div 500/333*/ -#define PLLMSRhi 0x0000039C /* CPU and GLIU mult/div 500/266*/ -//0x0000059C 0000 0000 0000 0000 0000 |0101 1|0|01 110|0 -/* Hold Count - how long we will sit in reset */ -#define PLLMSRlo 0x00DE6000 - #include "northbridge/amd/lx/raminit.h" #include "northbridge/amd/lx/pll_reset.c" #include "northbridge/amd/lx/raminit.c" @@ -78,7 +70,7 @@ void main(unsigned long bist) /* Halt if there was a built in self test failure */ report_bist_failure(bist); - pll_reset(ManualConf); + pll_reset(); cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED); diff --git a/src/mainboard/iei/pm-lx-800-r11/Kconfig b/src/mainboard/iei/pm-lx-800-r11/Kconfig index a897106..e443c6c 100644 --- a/src/mainboard/iei/pm-lx-800-r11/Kconfig +++ b/src/mainboard/iei/pm-lx-800-r11/Kconfig @@ -32,6 +32,8 @@ config BOARD_SPECIFIC_OPTIONS select PIRQ_ROUTE select BOARD_ROMSIZE_KB_512 select POWER_BUTTON_FORCE_ENABLE + select PLL_MANUAL_CONFIG + select CORE_GLIU_500_266 config MAINBOARD_DIR string @@ -45,19 +47,8 @@ config IRQ_SLOT_COUNT int default 7 -choice - prompt "Core/GLIU Frequency" - default CORE_GLIU_500_266 - -config CORE_GLIU_500_266 - bool "500MHz / 266MHz" - -config CORE_GLIU_500_333 - bool "500MHz / 333MHz" - -config CORE_GLIU_500_400 - bool "500MHz / 400MHz" - -endchoice +config PLLMSRlo + hex + default 0x07de0000 endif # BOARD_IEI_PM_LX_800_R11 diff --git a/src/mainboard/iei/pm-lx-800-r11/romstage.c b/src/mainboard/iei/pm-lx-800-r11/romstage.c index f756622..2992f53 100644 --- a/src/mainboard/iei/pm-lx-800-r11/romstage.c +++ b/src/mainboard/iei/pm-lx-800-r11/romstage.c @@ -46,16 +46,6 @@ static inline int spd_read_byte(unsigned int device, unsigned int address) return smbus_read_byte(device, address); } -#if CONFIG_CORE_GLIU_500_400 -# define PLLMSRhi 0x0000059c -#elif CONFIG_CORE_GLIU_500_333 -# define PLLMSRhi 0x0000049c -#else -# define PLLMSRhi 0x0000039c -#endif - -#define PLLMSRlo 0x07de000 - #include <northbridge/amd/lx/raminit.h> #include <northbridge/amd/lx/pll_reset.c> #include <northbridge/amd/lx/raminit.c> @@ -80,7 +70,7 @@ void main(unsigned long bist) report_bist_failure(bist); - pll_reset(1); + pll_reset(); cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED); diff --git a/src/mainboard/lippert/hurricane-lx/Kconfig b/src/mainboard/lippert/hurricane-lx/Kconfig index 118809d..64e1631 100644 --- a/src/mainboard/lippert/hurricane-lx/Kconfig +++ b/src/mainboard/lippert/hurricane-lx/Kconfig @@ -13,6 +13,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy # Board is equipped with a 1 MB SPI flash, however, due to limitations # of the IT8712F Super I/O, only the top 512 KB are directly mapped. select BOARD_ROMSIZE_KB_512 + select PLL_MANUAL_CONFIG + select CORE_GLIU_500_333 config MAINBOARD_DIR string @@ -50,4 +52,8 @@ config ONBOARD_UARTS_RS485 If selected, both on-board serial ports will operate in RS485 mode instead of RS232. +config PLLMSRlo + hex + default 0x00de6001 + endif # BOARD_LIPPERT_HURRICANE_LX diff --git a/src/mainboard/lippert/hurricane-lx/romstage.c b/src/mainboard/lippert/hurricane-lx/romstage.c index 29aa9d1..b2ee033 100644 --- a/src/mainboard/lippert/hurricane-lx/romstage.c +++ b/src/mainboard/lippert/hurricane-lx/romstage.c @@ -40,10 +40,6 @@ /* Bit0 enables Spread Spectrum. */ #define SMC_CONFIG 0x01 -#define ManualConf 1 /* No automatic strapped PLL config */ -#define PLLMSRhi 0x0000049C /* Manual settings for the PLL */ -#define PLLMSRlo 0x00DE6001 - static inline int spd_read_byte(unsigned int device, unsigned int address) { if (device != DIMM0) @@ -138,7 +134,7 @@ void main(unsigned long bist) /* Halt if there was a built in self test failure */ report_bist_failure(bist); - pll_reset(ManualConf); + pll_reset(); cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED); diff --git a/src/mainboard/lippert/literunner-lx/Kconfig b/src/mainboard/lippert/literunner-lx/Kconfig index 12a3ae1..c4684c9 100644 --- a/src/mainboard/lippert/literunner-lx/Kconfig +++ b/src/mainboard/lippert/literunner-lx/Kconfig @@ -15,6 +15,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy # of the IT8712F Super I/O, only the top 512 KB are directly mapped. select BOARD_ROMSIZE_KB_512 select POWER_BUTTON_FORCE_ENABLE + select PLL_MANUAL_CONFIG + select CORE_GLIU_500_400 config MAINBOARD_DIR string @@ -42,4 +44,8 @@ config ONBOARD_IDE_SLAVE If selected, the on-board Compact Flash card socket will act as IDE Slave instead of Master. +config PLLMSRlo + hex + default 0x00de6001 + endif # BOARD_LIPPERT_LITERUNNER_LX diff --git a/src/mainboard/lippert/literunner-lx/romstage.c b/src/mainboard/lippert/literunner-lx/romstage.c index 1e82bdb..77e2d12 100644 --- a/src/mainboard/lippert/literunner-lx/romstage.c +++ b/src/mainboard/lippert/literunner-lx/romstage.c @@ -44,10 +44,6 @@ #define SMC_CONFIG 0x01 #endif -#define ManualConf 1 /* No automatic strapped PLL config */ -#define PLLMSRhi 0x0000059C /* Manual settings for the PLL */ -#define PLLMSRlo 0x00DE6001 - static const unsigned char spdbytes[] = { // 4x Promos V58C2512164SA-J5I 0xFF, 0xFF, // only values used by Geode-LX raminit.c are set [SPD_MEMORY_TYPE] = SPD_MEMORY_TYPE_SDRAM_DDR, // (Fundamental) memory type @@ -181,7 +177,7 @@ void main(unsigned long bist) /* Halt if there was a built in self test failure */ report_bist_failure(bist); - pll_reset(ManualConf); + pll_reset(); cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED); diff --git a/src/mainboard/lippert/roadrunner-lx/Kconfig b/src/mainboard/lippert/roadrunner-lx/Kconfig index 2d11b33..f5ec9b9 100644 --- a/src/mainboard/lippert/roadrunner-lx/Kconfig +++ b/src/mainboard/lippert/roadrunner-lx/Kconfig @@ -14,6 +14,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy # SST 49LF008A is possible. select BOARD_ROMSIZE_KB_512 select POWER_BUTTON_FORCE_ENABLE + select PLL_MANUAL_CONFIG + select CORE_GLIU_500_333 config MAINBOARD_DIR string @@ -34,4 +36,8 @@ config ONBOARD_UARTS_RS485 If selected, both on-board serial ports will operate in RS485 mode instead of RS232. +config PLLMSRlo + hex + default 0x00de6001 + endif # BOARD_LIPPERT_ROADRUNNER_LX diff --git a/src/mainboard/lippert/roadrunner-lx/romstage.c b/src/mainboard/lippert/roadrunner-lx/romstage.c index 20e5b6a..827c41b 100644 --- a/src/mainboard/lippert/roadrunner-lx/romstage.c +++ b/src/mainboard/lippert/roadrunner-lx/romstage.c @@ -37,10 +37,6 @@ #include "southbridge/amd/cs5536/early_setup.c" #include "superio/ite/it8712f/early_serial.c" -#define ManualConf 1 /* No automatic strapped PLL config */ -#define PLLMSRhi 0x0000049C /* Manual settings for the PLL */ -#define PLLMSRlo 0x00DE6001 - static inline int spd_read_byte(unsigned int device, unsigned int address) { if (device != DIMM0) @@ -113,7 +109,7 @@ void main(unsigned long bist) /* Halt if there was a built in self test failure */ report_bist_failure(bist); - pll_reset(ManualConf); + pll_reset(); cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED); diff --git a/src/mainboard/lippert/spacerunner-lx/Kconfig b/src/mainboard/lippert/spacerunner-lx/Kconfig index 99ecf7c..c4a2ce8 100644 --- a/src/mainboard/lippert/spacerunner-lx/Kconfig +++ b/src/mainboard/lippert/spacerunner-lx/Kconfig @@ -15,6 +15,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy # of the IT8712F Super I/O, only the top 512 KB are directly mapped. select BOARD_ROMSIZE_KB_512 select POWER_BUTTON_FORCE_ENABLE + select PLL_MANUAL_CONFIG + select CORE_GLIU_500_400 config MAINBOARD_DIR string @@ -41,4 +43,8 @@ config ONBOARD_IDE_SLAVE help If selected, the on-board SSD will act as IDE Slave instead of Master. +config PLLMSRlo + hex + default 0x00de6001 + endif # BOARD_LIPPERT_SPACERUNNER_LX diff --git a/src/mainboard/lippert/spacerunner-lx/romstage.c b/src/mainboard/lippert/spacerunner-lx/romstage.c index 9dcb37b..d62c039 100644 --- a/src/mainboard/lippert/spacerunner-lx/romstage.c +++ b/src/mainboard/lippert/spacerunner-lx/romstage.c @@ -44,10 +44,6 @@ #define SMC_CONFIG 0x01 #endif -#define ManualConf 1 /* No automatic strapped PLL config */ -#define PLLMSRhi 0x0000059C /* Manual settings for the PLL */ -#define PLLMSRlo 0x00DE6001 - static const unsigned char spdbytes[] = { // 4x Promos V58C2512164SA-J5I 0xFF, 0xFF, // only values used by Geode-LX raminit.c are set [SPD_MEMORY_TYPE] = SPD_MEMORY_TYPE_SDRAM_DDR, // (Fundamental) memory type @@ -178,7 +174,7 @@ void main(unsigned long bist) /* Halt if there was a built in self test failure */ report_bist_failure(bist); - pll_reset(ManualConf); + pll_reset(); cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED); diff --git a/src/mainboard/pcengines/alix1c/romstage.c b/src/mainboard/pcengines/alix1c/romstage.c index f109031..9de3863 100644 --- a/src/mainboard/pcengines/alix1c/romstage.c +++ b/src/mainboard/pcengines/alix1c/romstage.c @@ -99,10 +99,6 @@ static u8 spd_read_byte(u8 device, u8 address) return spdbytes[address]; } -#define ManualConf 0 /* Do automatic strapped PLL config */ -#define PLLMSRhi 0x00001490 /* Manual settings for the PLL */ -#define PLLMSRlo 0x02000030 - #include "northbridge/amd/lx/raminit.h" #include "northbridge/amd/lx/pll_reset.c" #include "northbridge/amd/lx/raminit.c" @@ -132,7 +128,7 @@ void main(unsigned long bist) /* Halt if there was a built in self test failure */ report_bist_failure(bist); - pll_reset(ManualConf); + pll_reset(); cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED); diff --git a/src/mainboard/pcengines/alix2d/romstage.c b/src/mainboard/pcengines/alix2d/romstage.c index 0e8cc63..fd5582d 100644 --- a/src/mainboard/pcengines/alix2d/romstage.c +++ b/src/mainboard/pcengines/alix2d/romstage.c @@ -98,10 +98,6 @@ static u8 spd_read_byte(u8 device, u8 address) return spdbytes[address]; } -#define ManualConf 0 /* Do automatic strapped PLL config */ -#define PLLMSRhi 0x00001490 /* Manual settings for the PLL */ -#define PLLMSRlo 0x02000030 - #include "northbridge/amd/lx/raminit.h" #include "northbridge/amd/lx/pll_reset.c" #include "northbridge/amd/lx/raminit.c" @@ -156,7 +152,7 @@ void main(unsigned long bist) /* Halt if there was a built in self test failure */ report_bist_failure(bist); - pll_reset(ManualConf); + pll_reset(); cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED); diff --git a/src/mainboard/traverse/geos/Kconfig b/src/mainboard/traverse/geos/Kconfig index 40679fe..3139d7d 100644 --- a/src/mainboard/traverse/geos/Kconfig +++ b/src/mainboard/traverse/geos/Kconfig @@ -11,6 +11,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy select UDELAY_TSC select BOARD_ROMSIZE_KB_1024 select POWER_BUTTON_DEFAULT_DISABLE + select PLL_MANUAL_CONFIG + select CORE_GLIU_500_400 config MAINBOARD_DIR string @@ -24,4 +26,8 @@ config IRQ_SLOT_COUNT int default 6 +config PLLMSRlo + hex + default 0x00de602e + endif # BOARD_TRAVERSE_GEOS diff --git a/src/mainboard/traverse/geos/romstage.c b/src/mainboard/traverse/geos/romstage.c index 588681b..0b61d41 100644 --- a/src/mainboard/traverse/geos/romstage.c +++ b/src/mainboard/traverse/geos/romstage.c @@ -39,10 +39,6 @@ static inline int spd_read_byte(unsigned int device, unsigned int address) return smbus_read_byte(device, address); } -#define ManualConf 1 /* Do automatic strapped PLL config */ -#define PLLMSRhi 0x0000059C /* manual settings for the PLL */ -#define PLLMSRlo 0x00DE602E - #include "northbridge/amd/lx/raminit.h" #include "northbridge/amd/lx/pll_reset.c" #include "northbridge/amd/lx/raminit.c" @@ -75,7 +71,7 @@ void main(unsigned long bist) /* Halt if there was a built in self test failure */ report_bist_failure(bist); - pll_reset(ManualConf); + pll_reset(); cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED); diff --git a/src/mainboard/winent/pl6064/romstage.c b/src/mainboard/winent/pl6064/romstage.c index 6651acd..39e4ecf 100644 --- a/src/mainboard/winent/pl6064/romstage.c +++ b/src/mainboard/winent/pl6064/romstage.c @@ -43,10 +43,6 @@ static inline int spd_read_byte(unsigned int device, unsigned int address) return smbus_read_byte(device, address); } -#define ManualConf 0 /* Do automatic strapped PLL config */ -#define PLLMSRhi 0x00001490 /* Manual settings for the PLL */ -#define PLLMSRlo 0x02000030 - #include "northbridge/amd/lx/raminit.h" #include "northbridge/amd/lx/pll_reset.c" #include "northbridge/amd/lx/raminit.c" @@ -77,7 +73,7 @@ void main(unsigned long bist) /* Halt if there was a built in self test failure */ report_bist_failure(bist); - pll_reset(ManualConf); + pll_reset(); cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED); diff --git a/src/northbridge/amd/lx/Kconfig b/src/northbridge/amd/lx/Kconfig index c1fea49..d74d715 100644 --- a/src/northbridge/amd/lx/Kconfig +++ b/src/northbridge/amd/lx/Kconfig @@ -2,7 +2,36 @@ config NORTHBRIDGE_AMD_LX bool select GEODE_VSA +if NORTHBRIDGE_AMD_LX + config VIDEO_MB int default 8 - depends on NORTHBRIDGE_AMD_LX + +config PLL_MANUAL_CONFIG + bool + +if PLL_MANUAL_CONFIG + +# "Core/GLIU Frequency" +config CORE_GLIU_500_266 + bool # "500MHz / 266MHz" + +config CORE_GLIU_500_333 + bool # "500MHz / 333MHz" + +config CORE_GLIU_500_400 + bool # "500MHz / 400MHz" + +config PLLMSRhi + hex + default 0x39c if CORE_GLIU_500_266 + default 0x49c if CORE_GLIU_500_333 + default 0x59c if CORE_GLIU_500_400 + +config PLLMSRlo + hex + +endif + +endif diff --git a/src/northbridge/amd/lx/pll_reset.c b/src/northbridge/amd/lx/pll_reset.c index 3077b61..bf01e54 100644 --- a/src/northbridge/amd/lx/pll_reset.c +++ b/src/northbridge/amd/lx/pll_reset.c @@ -18,7 +18,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -static void pll_reset(char manualconf) +static void pll_reset(void) { msr_t msrGlcpSysRstpll; @@ -31,13 +31,13 @@ static void pll_reset(char manualconf) if (!(msrGlcpSysRstpll.lo & (1 << RSTPLL_LOWER_SWFLAGS_SHIFT))) { printk(BIOS_DEBUG, "Configuring PLL.\n"); - if (manualconf) { + if (CONFIG_PLL_MANUAL_CONFIG) { post_code(POST_PLL_MANUAL); /* CPU and GLIU mult/div (GLMC_CLK = GLIU_CLK / 2) */ - msrGlcpSysRstpll.hi = PLLMSRhi; + msrGlcpSysRstpll.hi = CONFIG_PLLMSRhi; /* Hold Count - how long we will sit in reset */ - msrGlcpSysRstpll.lo = PLLMSRlo; + msrGlcpSysRstpll.lo = CONFIG_PLLMSRlo; } else { /*automatic configuration (straps) */ post_code(POST_PLL_STRAP);

1 0

Patch set updated for coreboot: cec022a IEI PM-LX2-800-R10: Added preliminary mainboard support
by Patrick Georgi 25 Jul '12

25 Jul '12

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1152 -gerrit commit cec022acf29e6c1b70ff4b5795894c101af994eb Author: Ricardo Martins <rasmartins(a)gmail.com> Date: Sat Jul 7 14:27:03 2012 +0100 IEI PM-LX2-800-R10: Added preliminary mainboard support Details for this board are available at http://usa.ieiworld.com/product_groups/industrial/content.aspx?gid=00001000… Most of the functionality provided by the original BIOS is implemented. The Geode Link Speed is hardcoded to a safe value. I'll add automatic configuration in a later patch. Change-Id: Iaefe47f5ad405a56d230c929e5850156eb0f60ae Signed-off-by: Ricardo Martins <rasmartins(a)gmail.com> --- src/mainboard/iei/Kconfig | 3 + src/mainboard/iei/pm-lx2-800-r10/Kconfig | 58 ++++++++++ src/mainboard/iei/pm-lx2-800-r10/chip.h | 23 ++++ src/mainboard/iei/pm-lx2-800-r10/cmos.layout | 103 ++++++++++++++++++ src/mainboard/iei/pm-lx2-800-r10/devicetree.cb | 87 +++++++++++++++ src/mainboard/iei/pm-lx2-800-r10/irq_tables.c | 134 ++++++++++++++++++++++++ src/mainboard/iei/pm-lx2-800-r10/it8888_io.def | 27 +++++ src/mainboard/iei/pm-lx2-800-r10/mainboard.c | 103 ++++++++++++++++++ src/mainboard/iei/pm-lx2-800-r10/romstage.c | 91 ++++++++++++++++ 9 files changed, 629 insertions(+), 0 deletions(-) diff --git a/src/mainboard/iei/Kconfig b/src/mainboard/iei/Kconfig index ea26922..537252d 100644 --- a/src/mainboard/iei/Kconfig +++ b/src/mainboard/iei/Kconfig @@ -31,6 +31,8 @@ config BOARD_IEI_PCISA_LX_800_R10 bool "PCISA LX-800-R10" config BOARD_IEI_PM_LX_800_R11 bool "PM LX-800-R11" +config BOARD_IEI_PM_LX2_800_R10 + bool "PM-LX2-800-R10" endchoice @@ -39,6 +41,7 @@ source "src/mainboard/iei/kino-780am2-fam10/Kconfig" source "src/mainboard/iei/nova4899r/Kconfig" source "src/mainboard/iei/pcisa-lx-800-r10/Kconfig" source "src/mainboard/iei/pm-lx-800-r11/Kconfig" +source "src/mainboard/iei/pm-lx2-800-r10/Kconfig" config MAINBOARD_VENDOR string diff --git a/src/mainboard/iei/pm-lx2-800-r10/Kconfig b/src/mainboard/iei/pm-lx2-800-r10/Kconfig new file mode 100644 index 0000000..62f8520 --- /dev/null +++ b/src/mainboard/iei/pm-lx2-800-r10/Kconfig @@ -0,0 +1,58 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2012 Ricardo Martins <rasmartins(a)gmail.com> +## +## This program is free software; you can redistribute it and/or +## modify it under the terms of the GNU General Public License as +## published by the Free Software Foundation; version 2 of +## the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +## MA 02110-1301 USA +## + +if BOARD_IEI_PM_LX2_800_R10 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select ARCH_X86 + select CPU_AMD_GEODE_LX + select NORTHBRIDGE_AMD_LX + select SOUTHBRIDGE_AMD_CS5536 + select SUPERIO_SMSC_SMSCSUPERIO + select HAVE_PIRQ_TABLE + select HAVE_OPTION_TABLE + select PIRQ_ROUTE + select BOARD_ROMSIZE_KB_512 + select POWER_BUTTON_FORCE_ENABLE + select PLL_MANUAL_CONFIG + select CORE_GLIU_500_266 + +config MAINBOARD_DIR + string + default iei/pm-lx2-800-r10 + +config MAINBOARD_PART_NUMBER + string + default "PM-LX2-800-R10" + +config IRQ_SLOT_COUNT + int + default 3 + +config SCH3114_COM3_AUTO_DIR + bool "COM3 Automatic Direction Control" + default y + help + If selected, COM3 automatic direction control will + be enabled by default. + +endif # BOARD_IEI_PM_LX2_800_R10 diff --git a/src/mainboard/iei/pm-lx2-800-r10/chip.h b/src/mainboard/iei/pm-lx2-800-r10/chip.h new file mode 100644 index 0000000..d69f9b6 --- /dev/null +++ b/src/mainboard/iei/pm-lx2-800-r10/chip.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Ricardo Martins <rasmartins(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/iei/pm-lx2-800-r10/cmos.layout b/src/mainboard/iei/pm-lx2-800-r10/cmos.layout new file mode 100644 index 0000000..e09cfb6 --- /dev/null +++ b/src/mainboard/iei/pm-lx2-800-r10/cmos.layout @@ -0,0 +1,103 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2012 Ricardo Martins <rasmartins(a)gmail.com> +## +## This program is free software; you can redistribute it and/or +## modify it under the terms of the GNU General Public License as +## published by the Free Software Foundation; version 2 of +## the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +## MA 02110-1301 USA +## + +entries + # RTC + 0 384 r 0 reserved_rtc + # Coreboot + 384 1 e 3 boot_option + 385 1 e 3 last_boot + 386 4 r 0 reboot_bits + 390 3 e 4 baud_rate + 393 4 e 5 debug_level + 397 2 r 0 unused + # PM-LX2-800-R10 + 399 1 e 1 com3_auto_direction + 400 1 e 2 it8888_io_space0 + 401 1 e 2 it8888_io_space1 + 402 1 e 2 it8888_io_space2 + 403 1 e 2 it8888_io_space3 + 404 2 e 6 it8888_io_space0_speed + 406 2 e 6 it8888_io_space1_speed + 408 2 e 6 it8888_io_space2_speed + 410 2 e 6 it8888_io_space3_speed + 412 3 e 7 it8888_io_space0_size + 415 3 e 7 it8888_io_space1_size + 418 3 e 7 it8888_io_space2_size + 421 3 e 7 it8888_io_space3_size + 424 16 h 0 it8888_io_space0_addr + 440 16 h 0 it8888_io_space1_addr + 456 16 h 0 it8888_io_space2_addr + 472 16 h 0 it8888_io_space3_addr + 488 16 h 0 check_sum + +enumerations + # Yes / No + 1 0 No + 1 1 Yes + + # Enabled / Disabled + 2 0 Disabled + 2 1 Enabled + + # Normal / Fallback + 3 0 Fallback + 3 1 Normal + + # Console Baud Rate + 4 0 115200 + 4 1 57600 + 4 2 38400 + 4 3 19200 + 4 4 9600 + 4 5 4800 + 4 6 2400 + 4 7 1200 + + # Console Log Level + 5 0 Emergency + 5 1 Alert + 5 2 Critical + 5 3 Error + 5 4 Warning + 5 5 Notice + 5 6 Info + 5 7 Debug + 5 8 Spew + + # IT8888 Decoding Speeds + 6 0 Subtractive + 6 1 Slow + 6 2 Medium + 6 3 Fast + + # IT8888 Decoding Sizes + 7 0 1 + 7 1 2 + 7 2 4 + 7 3 8 + 7 4 16 + 7 5 32 + 7 6 64 + 7 7 128 + +checksums + checksum 384 487 488 diff --git a/src/mainboard/iei/pm-lx2-800-r10/devicetree.cb b/src/mainboard/iei/pm-lx2-800-r10/devicetree.cb new file mode 100644 index 0000000..f5721a3 --- /dev/null +++ b/src/mainboard/iei/pm-lx2-800-r10/devicetree.cb @@ -0,0 +1,87 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2012 Ricardo Martins <rasmartins(a)gmail.com> +## +## This program is free software; you can redistribute it and/or +## modify it under the terms of the GNU General Public License as +## published by the Free Software Foundation; version 2 of +## the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +## MA 02110-1301 USA +## + +chip northbridge/amd/lx + device pci_domain 0 on + device pci 1.0 on end # Northbridge + device pci 1.1 on end # Video Adapter + device pci 1.2 on end # AES Security Block + chip southbridge/amd/cs5536 + register "lpc_serirq_enable" = "0x000010da" + register "lpc_serirq_polarity" = "0x0000ef25" + register "lpc_serirq_mode" = "1" + register "enable_gpio_int_route" = "0x0d0c0700" + register "enable_ide_nand_flash" = "0" + register "enable_USBP4_device" = "0" # 0:host, 1:device + register "enable_USBP4_overcurrent" = "0" + register "com1_enable" = "0" + register "com2_enable" = "0" + register "unwanted_vpci[0]" = "0" # End of list has a zero + device pci 11.0 on end # IT8888 + device pci e.0 on end # RTL8100C + device pci f.0 on # ISA Bridge + chip superio/smsc/smscsuperio # SMSC SCH3114 + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + + device pnp 2e.3 off # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + end + + device pnp 2e.4 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + + device pnp 2e.5 on # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + + device pnp 2e.7 on # PS/2 keyboard/mouse + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 # Keyboard + irq 0x72 = 12 # Mouse + end + + device pnp 2e.a on # Runtime Register + io 0x60 = 0x400 + end + end + end + device pci f.2 on end # IDE Controller + device pci f.3 on end # Audio + device pci f.4 on end # OHCI + device pci f.5 on end # EHCI + end + end + # APIC cluster is late CPU init. + device lapic_cluster 0 on + chip cpu/amd/geode_lx + device lapic 0 on end + end + end +end diff --git a/src/mainboard/iei/pm-lx2-800-r10/irq_tables.c b/src/mainboard/iei/pm-lx2-800-r10/irq_tables.c new file mode 100644 index 0000000..2bbf218 --- /dev/null +++ b/src/mainboard/iei/pm-lx2-800-r10/irq_tables.c @@ -0,0 +1,134 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Ricardo Martins <rasmartins(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <device/pci_ids.h> +#include <arch/pirq_routing.h> + +/* Platform IRQs */ +#define PIRQA 10 +#define PIRQB 10 +#define PIRQC 11 +#define PIRQD 11 + +/* Links */ +#define L_PIRQN 0 +#define L_PIRQA 1 +#define L_PIRQB 2 +#define L_PIRQC 3 +#define L_PIRQD 4 + +/* Bitmaps */ +#define B_LINKN (0) +#define B_LINK0 (1 << PIRQA) +#define B_LINK1 (1 << PIRQB) +#define B_LINK2 (1 << PIRQC) +#define B_LINK3 (1 << PIRQD) + +const struct irq_routing_table intel_irq_routing_table = { + PIRQ_SIGNATURE, /* u32 signature */ + PIRQ_VERSION, /* u16 version */ + 32 + 16 * CONFIG_IRQ_SLOT_COUNT, /* Max. number of devices on the bus */ + 0x00, /* Interrupt router bus */ + (0x0f << 3) | 0x0, /* Interrupt router dev */ + (B_LINK0 | B_LINK1 | B_LINK2 | B_LINK3),/* IRQs devoted exclusively to PCI usage */ + PCI_VENDOR_ID_AMD, /* Vendor */ + PCI_DEVICE_ID_AMD_CS5536_ISA, /* Device */ + 0, /* Miniport */ + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + 0x27, /* Checksum */ + { + [0] = { /* Host bridge */ + .slot = 0x00, + .bus = 0x00, + .devfn = (0x01 << 3) | 0x0, + .irq = { + [0] = { + .link = L_PIRQA, + .bitmap = B_LINK0 + }, + [1] = { + .link = L_PIRQN, + .bitmap = B_LINKN + }, + [2] = { + .link = L_PIRQN, + .bitmap = B_LINKN + }, + [3] = { + .link = L_PIRQN, + .bitmap = B_LINKN + } + } + }, + + [1] = { /* ISA bridge */ + .slot = 0x00, + .bus = 0x00, + .devfn = (0x0f << 3) | 0x0, + .irq = { + [0] = { + .link = L_PIRQN, + .bitmap = B_LINKN + }, + [1] = { + .link = L_PIRQB, + .bitmap = B_LINK1 + }, + [2] = { + .link = L_PIRQN, + .bitmap = B_LINKN + }, + [3] = { + .link = L_PIRQD, + .bitmap = B_LINK3 + } + } + }, + + [2] = { /* Ethernet */ + .slot = 0x00, + .bus = 0x00, + .devfn = (0x0e << 3) | 0x0, + .irq = { + [0] = { + .link = L_PIRQD, + .bitmap = B_LINK3 + }, + [1] = { + .link = L_PIRQN, + .bitmap = B_LINKN + }, + [2] = { + .link = L_PIRQN, + .bitmap = B_LINKN + }, + [3] = { + .link = L_PIRQN, + .bitmap = B_LINKN + } + } + } + } +}; + +unsigned long write_pirq_routing_table(unsigned long addr) +{ + return copy_pirq_routing_table(addr); +} diff --git a/src/mainboard/iei/pm-lx2-800-r10/it8888_io.def b/src/mainboard/iei/pm-lx2-800-r10/it8888_io.def new file mode 100644 index 0000000..5920abc --- /dev/null +++ b/src/mainboard/iei/pm-lx2-800-r10/it8888_io.def @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Ricardo Martins <rasmartins(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* Name, Register, Enabled/Disabled, Speed, Size, Address. */ +IT8888_IO("it8888_io_space0", 0x58, 0, 0, 0, 0) +IT8888_IO("it8888_io_space1", 0x5c, 0, 0, 0, 0) +IT8888_IO("it8888_io_space2", 0x60, 0, 0, 0, 0) +IT8888_IO("it8888_io_space3", 0x64, 0, 0, 0, 0) +IT8888_IO("it8888_io_space4", 0x68, 0, 0, 0, 0) +IT8888_IO("it8888_io_space5", 0x6c, 0, 0, 0, 0) diff --git a/src/mainboard/iei/pm-lx2-800-r10/mainboard.c b/src/mainboard/iei/pm-lx2-800-r10/mainboard.c new file mode 100644 index 0000000..170a67a --- /dev/null +++ b/src/mainboard/iei/pm-lx2-800-r10/mainboard.c @@ -0,0 +1,103 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Ricardo Martins <rasmartins(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <console/console.h> +#include <device/pci.h> +#include <device/device.h> +#include <boot/tables.h> +#include <pc80/mc146818rtc.h> +#include "chip.h" + +#if CONFIG_USE_OPTION_TABLE +# include "option_table.h" +#endif + +/* SCH3114 runtime register (RTR) address. */ +#define SCH3114_RTR_ADDR (0x400) +/* SP34 option register. */ +#define SCH3114_RTR_SP34_OPT (SCH3114_RTR_ADDR + 0x13) +/* H/W Monitoring register block index. */ +#define SCH3114_RTR_HWM_IDX (SCH3114_RTR_ADDR + 0x70) +/* H/W Monitoring register block data. */ +#define SCH3114_RTR_HWM_DAT (SCH3114_RTR_ADDR + 0x71) +/* H/W Monitoring Ready/Lock/Start register. */ +#define SCH3114_HWM_RLS_REG (0x40) +/* IT8888 PCI Vendor ID. */ +#define IT8888_PCI_VID (0x1283) +/* IT8888 PCI Device ID. */ +#define IT8888_PCI_DID (0x8888) + +static u16 opt(const char* option, u16 def_value) +{ +#if CONFIG_USE_OPTION_TABLE + u16 value = 0; + if (get_option(&value, option) != 0) + value = def_value; + return value; +#else + return def_value; +#endif +} + +static void init(struct device *dev) +{ + /* SCH3114: enable hardware monitor. */ + printk(BIOS_INFO, "Enabling SCH3114 hardware monitor\n"); + outb(SCH3114_HWM_RLS_REG, SCH3114_RTR_HWM_IDX); + outb(inb(SCH3114_RTR_HWM_DAT) | 0x01, SCH3114_RTR_HWM_DAT); + + /* SCH3114: COM3 Automatic Direction Control / nRTS control. */ + if (opt("com3_auto_direction", CONFIG_SCH3114_COM3_AUTO_DIR) != 0) { + printk(BIOS_INFO, "Enabling RS858 Auto Direction Control\n"); + outb(inb(SCH3114_RTR_SP34_OPT) | 0x03, SCH3114_RTR_SP34_OPT); + } + + /* IT8888. */ + device_t it8x = dev_find_device(IT8888_PCI_VID, IT8888_PCI_DID, 0); + if (!it8x) { + printk(BIOS_ERR, "IT8888 not found\n"); + return; + } + + u32 cfg = 0; +#define IT8888_IO(name, reg, dena, dspeed, dsize, daddr) \ + if (opt(name, dena) != 0) { \ + cfg = (1 << 31); \ + cfg |= opt(name "_addr", daddr); \ + cfg |= opt(name "_speed", dspeed) << 29; \ + cfg |= opt(name "_size", dsize) << 24; \ + } else { \ + cfg = 0; \ + } \ + pci_write_config32(it8x, reg, cfg); + +#include "it8888_io.def" +} + +static void enable_dev(struct device *dev) +{ + dev->ops->init = init; +} + +struct chip_operations mainboard_ops = { + CHIP_NAME("IEI PM-LX2-800-R10 Mainboard") + .enable_dev = enable_dev, +}; diff --git a/src/mainboard/iei/pm-lx2-800-r10/romstage.c b/src/mainboard/iei/pm-lx2-800-r10/romstage.c new file mode 100644 index 0000000..8bc55f4 --- /dev/null +++ b/src/mainboard/iei/pm-lx2-800-r10/romstage.c @@ -0,0 +1,91 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Advanced Micro Devices, Inc. + * Copyright (C) 2012 Ricardo Martins <rasmartins(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include <stdlib.h> + +#include <spd.h> +#include <arch/io.h> +#include <arch/hlt.h> +#include <arch/llshell.h> +#include <device/pci_def.h> +#include <device/pnp_def.h> +#include <console/console.h> +#include <cpu/x86/bist.h> +#include <cpu/x86/msr.h> +#include <cpu/amd/lxdef.h> +#include <southbridge/amd/cs5536/cs5536.h> +#include <southbridge/amd/cs5536/early_smbus.c> +#include <southbridge/amd/cs5536/early_setup.c> +#include <superio/smsc/smscsuperio/early_serial.c> + +#define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1) + +static inline int spd_read_byte(unsigned int device, unsigned int address) +{ + /* Only DIMM0 is available. */ + if (device != DIMM0) + return 0xFF; + + return smbus_read_byte(device, address); +} + +#include <northbridge/amd/lx/raminit.h> +#include <northbridge/amd/lx/pll_reset.c> +#include <northbridge/amd/lx/raminit.c> +#include <lib/generic_sdram.c> +#include <cpu/amd/geode_lx/cpureginit.c> +#include <cpu/amd/geode_lx/syspreinit.c> +#include <cpu/amd/geode_lx/msrinit.c> + +void main(unsigned long bist) +{ + static const struct mem_controller memctrl[] = { + {.channel0 = {DIMM0, DIMM1}} + }; + + SystemPreInit(); + msr_init(); + + cs5536_early_setup(); + + smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + console_init(); + + /* Enable COM3. */ + device_t dev = PNP_DEV(0x2e, 0x0b); + u16 port = dev >> 8; + outb(0x55, port); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, 0x3e8); + pnp_set_irq(dev, PNP_IDX_IRQ0, 4); + pnp_set_enable(dev, 1); + outb(0xaa, port); + + report_bist_failure(bist); + + pll_reset(1); + + cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED); + + sdram_initialize(1, memctrl); +}

1 0

Patch merged into coreboot/master: ac9c349 chromeos: Pass pointer to ChromeOS ACPI structure instead of VB Shared Data
by gerrit＠coreboot.org 25 Jul '12

25 Jul '12

the following patch was just integrated into master: commit ac9c349576511d4c8e67a4964fe777a9658c9534 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Wed Jun 13 13:12:19 2012 -0700 chromeos: Pass pointer to ChromeOS ACPI structure instead of VB Shared Data coreboot used to pass some information to u-boot in the coreboot table and other information in a modified flat device tree. Since the FDT code was never upstreamed and removed from our tree, u-boot was changed to get the information it needs from the coreboot table alone. However, in the process of this change only the vboot shared data structure was passed on by coreboot, so when u-boot tried to update the ChromeOS specific ACPI entries, it would accidently overwrite the vboot data. This patch passes on the ChromeOS specific ACPI data structure instead of the vboot shared data. Another change to u-boot will teach it how to get to the vboot shared data from there. Change-Id: Ifbb64eafc0d9967887b4cdeebf97d0c4ce019290 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Wed Jul 25 08:31:39 2012, giving +2 See http://review.coreboot.org/1282 for details. -gerrit

1 0

Patch set updated for coreboot: f2e2f19 amd/lx: Move configuration from source to Kconfig
by Patrick Georgi 25 Jul '12

25 Jul '12

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1227 -gerrit commit f2e2f1997b502906ba5961babcde4c4728b16872 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Fri Jul 13 19:06:22 2012 +0200 amd/lx: Move configuration from source to Kconfig LX has two values that are usually automatically derived but can be overridden, that were so far defined in each board's romstage. These values, along with the toggle to enable override are now part of LX's Kconfig. For boards that gave values but requested autogeneration, the values are removed. Further improvements: Figure out the various fields in PLLMSRlo and make them sensible Kconfig options (instead of the hex value it is now) Change-Id: I8a17c89e4a3cb1b52aaceef645955ab7817b482d Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- src/mainboard/aaeon/pfm-540i_revb/romstage.c | 6 +--- src/mainboard/amd/db800/romstage.c | 6 +--- src/mainboard/amd/norwich/romstage.c | 6 +--- src/mainboard/artecgroup/dbe61/romstage.c | 8 +----- src/mainboard/bachmann/ot200/Kconfig | 6 ++++ src/mainboard/bachmann/ot200/romstage.c | 6 +--- src/mainboard/digitallogic/msm800sev/romstage.c | 6 +--- src/mainboard/iei/pcisa-lx-800-r10/Kconfig | 6 ++++ src/mainboard/iei/pcisa-lx-800-r10/romstage.c | 10 +------ src/mainboard/iei/pm-lx-800-r11/Kconfig | 19 +++---------- src/mainboard/iei/pm-lx-800-r11/romstage.c | 12 +-------- src/mainboard/lippert/hurricane-lx/Kconfig | 6 ++++ src/mainboard/lippert/hurricane-lx/romstage.c | 6 +--- src/mainboard/lippert/literunner-lx/Kconfig | 6 ++++ src/mainboard/lippert/literunner-lx/romstage.c | 6 +--- src/mainboard/lippert/roadrunner-lx/Kconfig | 6 ++++ src/mainboard/lippert/roadrunner-lx/romstage.c | 6 +--- src/mainboard/lippert/spacerunner-lx/Kconfig | 6 ++++ src/mainboard/lippert/spacerunner-lx/romstage.c | 6 +--- src/mainboard/pcengines/alix1c/romstage.c | 6 +--- src/mainboard/pcengines/alix2d/romstage.c | 6 +--- src/mainboard/traverse/geos/Kconfig | 6 ++++ src/mainboard/traverse/geos/romstage.c | 6 +--- src/mainboard/winent/pl6064/romstage.c | 6 +--- src/northbridge/amd/lx/Kconfig | 31 ++++++++++++++++++++++- src/northbridge/amd/lx/pll_reset.c | 8 +++--- 26 files changed, 97 insertions(+), 111 deletions(-) diff --git a/src/mainboard/aaeon/pfm-540i_revb/romstage.c b/src/mainboard/aaeon/pfm-540i_revb/romstage.c index 4b510a9..2d3b71d 100644 --- a/src/mainboard/aaeon/pfm-540i_revb/romstage.c +++ b/src/mainboard/aaeon/pfm-540i_revb/romstage.c @@ -47,10 +47,6 @@ static inline int spd_read_byte(unsigned int device, unsigned int address) return smbus_read_byte(device, address); } -#define ManualConf 0 /* Do automatic strapped PLL config */ -#define PLLMSRhi 0x000005DD /* Manual settings for the PLL */ -#define PLLMSRlo 0x00DE60EE - #include "northbridge/amd/lx/raminit.h" #include "northbridge/amd/lx/pll_reset.c" #include "northbridge/amd/lx/raminit.c" @@ -79,7 +75,7 @@ void main(unsigned long bist) /* Halt if there was a built in self test failure */ report_bist_failure(bist); - pll_reset(ManualConf); + pll_reset(); cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED); diff --git a/src/mainboard/amd/db800/romstage.c b/src/mainboard/amd/db800/romstage.c index 3590c37..2bb6cd3 100644 --- a/src/mainboard/amd/db800/romstage.c +++ b/src/mainboard/amd/db800/romstage.c @@ -41,10 +41,6 @@ static inline int spd_read_byte(unsigned int device, unsigned int address) return smbus_read_byte(device, address); } -#define ManualConf 0 /* Do automatic strapped PLL config */ -#define PLLMSRhi 0x000005DD /* Manual settings for the PLL */ -#define PLLMSRlo 0x00DE60EE - #include "northbridge/amd/lx/raminit.h" #include "northbridge/amd/lx/pll_reset.c" #include "northbridge/amd/lx/raminit.c" @@ -74,7 +70,7 @@ void main(unsigned long bist) /* Halt if there was a built in self test failure */ report_bist_failure(bist); - pll_reset(ManualConf); + pll_reset(); cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED); diff --git a/src/mainboard/amd/norwich/romstage.c b/src/mainboard/amd/norwich/romstage.c index d8fca5a..c71b31f 100644 --- a/src/mainboard/amd/norwich/romstage.c +++ b/src/mainboard/amd/norwich/romstage.c @@ -38,10 +38,6 @@ static inline int spd_read_byte(unsigned int device, unsigned int address) return smbus_read_byte(device, address); } -#define ManualConf 0 /* Do automatic strapped PLL config */ -#define PLLMSRhi 0x00001490 /* manual settings for the PLL */ -#define PLLMSRlo 0x02000030 - #include "northbridge/amd/lx/raminit.h" #include "northbridge/amd/lx/pll_reset.c" #include "northbridge/amd/lx/raminit.c" @@ -75,7 +71,7 @@ void main(unsigned long bist) /* Halt if there was a built in self test failure */ report_bist_failure(bist); - pll_reset(ManualConf); + pll_reset(); cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED); diff --git a/src/mainboard/artecgroup/dbe61/romstage.c b/src/mainboard/artecgroup/dbe61/romstage.c index f97af92..61bd03e 100644 --- a/src/mainboard/artecgroup/dbe61/romstage.c +++ b/src/mainboard/artecgroup/dbe61/romstage.c @@ -51,12 +51,6 @@ static int spd_read_byte(unsigned device, unsigned address) return 0xFF; } -#define ManualConf 0 /* Do automatic strapped PLL config */ -/* CPU and GLIU mult/div 500/266*/ -#define PLLMSRhi 0x0000039C /* 33MHz PCI, 0x000003DD for 66MHz PCI */ -/* Hold Count - how long we will sit in reset */ -#define PLLMSRlo 0x00DE6000 - #include "northbridge/amd/lx/raminit.h" #include "northbridge/amd/lx/pll_reset.c" #include "northbridge/amd/lx/raminit.c" @@ -94,7 +88,7 @@ void main(unsigned long bist) /* Halt if there was a built in self test failure */ report_bist_failure(bist); - pll_reset(ManualConf); + pll_reset(); cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED); diff --git a/src/mainboard/bachmann/ot200/Kconfig b/src/mainboard/bachmann/ot200/Kconfig index a201bde..5d185c0 100644 --- a/src/mainboard/bachmann/ot200/Kconfig +++ b/src/mainboard/bachmann/ot200/Kconfig @@ -12,6 +12,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy select BOARD_ROMSIZE_KB_2048 select POWER_BUTTON_DEFAULT_DISABLE select DRIVERS_I2C_IDREG + select PLL_MANUAL_CONFIG + select CORE_GLIU_500_266 config MAINBOARD_DIR string @@ -25,4 +27,8 @@ config IRQ_SLOT_COUNT int default 6 +config PLLMSRlo + hex + default 0x07de001e + endif # BOARD_BACHMANN_OT200 diff --git a/src/mainboard/bachmann/ot200/romstage.c b/src/mainboard/bachmann/ot200/romstage.c index 9edd5f7..3a8ecad 100644 --- a/src/mainboard/bachmann/ot200/romstage.c +++ b/src/mainboard/bachmann/ot200/romstage.c @@ -39,10 +39,6 @@ static inline int spd_read_byte(unsigned int device, unsigned int address) return smbus_read_byte(device, address); } -#define ManualConf 1 /* Do automatic strapped PLL config */ -#define PLLMSRhi 0x0000039c /* CPU 500 MHz - GLIU 266 MHz */ -#define PLLMSRlo 0x07de001e - #include "northbridge/amd/lx/raminit.h" #include "northbridge/amd/lx/pll_reset.c" #include "northbridge/amd/lx/raminit.c" @@ -75,7 +71,7 @@ void main(unsigned long bist) /* Halt if there was a built in self test failure */ report_bist_failure(bist); - pll_reset(ManualConf); + pll_reset(); cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED); diff --git a/src/mainboard/digitallogic/msm800sev/romstage.c b/src/mainboard/digitallogic/msm800sev/romstage.c index d30e2b0..caafd2f 100644 --- a/src/mainboard/digitallogic/msm800sev/romstage.c +++ b/src/mainboard/digitallogic/msm800sev/romstage.c @@ -22,10 +22,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) return smbus_read_byte(device, address); } -#define ManualConf 0 /* Do automatic strapped PLL config */ -#define PLLMSRhi 0x00001490 /* manual settings for the PLL */ -#define PLLMSRlo 0x02000030 - #include "northbridge/amd/lx/raminit.h" #include "northbridge/amd/lx/pll_reset.c" #include "northbridge/amd/lx/raminit.c" @@ -57,7 +53,7 @@ void main(unsigned long bist) /* Halt if there was a built in self test failure */ report_bist_failure(bist); - pll_reset(ManualConf); + pll_reset(); cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED); diff --git a/src/mainboard/iei/pcisa-lx-800-r10/Kconfig b/src/mainboard/iei/pcisa-lx-800-r10/Kconfig index eae72ae..69e106e 100644 --- a/src/mainboard/iei/pcisa-lx-800-r10/Kconfig +++ b/src/mainboard/iei/pcisa-lx-800-r10/Kconfig @@ -11,6 +11,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy select PIRQ_ROUTE select BOARD_ROMSIZE_KB_256 select POWER_BUTTON_FORCE_ENABLE + select PLL_MANUAL_CONFIG + select CORE_GLIU_500_266 config MAINBOARD_DIR string @@ -24,4 +26,8 @@ config IRQ_SLOT_COUNT int default 9 +config PLLMSRlo + hex + default 0x00DE6000 + endif # BOARD_IEI_PCISA_LX_800_R10 diff --git a/src/mainboard/iei/pcisa-lx-800-r10/romstage.c b/src/mainboard/iei/pcisa-lx-800-r10/romstage.c index aec9843..7bd1b74 100644 --- a/src/mainboard/iei/pcisa-lx-800-r10/romstage.c +++ b/src/mainboard/iei/pcisa-lx-800-r10/romstage.c @@ -41,14 +41,6 @@ static inline int spd_read_byte(unsigned int device, unsigned int address) return smbus_read_byte(device, address); } -#define ManualConf 1 /* Do automatic strapped PLL config */ -//#define PLLMSRhi 0x0000059C /* CPU and GLIU mult/div 500/400*/ -//#define PLLMSRhi 0x0000049C /* CPU and GLIU mult/div 500/333*/ -#define PLLMSRhi 0x0000039C /* CPU and GLIU mult/div 500/266*/ -//0x0000059C 0000 0000 0000 0000 0000 |0101 1|0|01 110|0 -/* Hold Count - how long we will sit in reset */ -#define PLLMSRlo 0x00DE6000 - #include "northbridge/amd/lx/raminit.h" #include "northbridge/amd/lx/pll_reset.c" #include "northbridge/amd/lx/raminit.c" @@ -78,7 +70,7 @@ void main(unsigned long bist) /* Halt if there was a built in self test failure */ report_bist_failure(bist); - pll_reset(ManualConf); + pll_reset(); cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED); diff --git a/src/mainboard/iei/pm-lx-800-r11/Kconfig b/src/mainboard/iei/pm-lx-800-r11/Kconfig index a897106..e443c6c 100644 --- a/src/mainboard/iei/pm-lx-800-r11/Kconfig +++ b/src/mainboard/iei/pm-lx-800-r11/Kconfig @@ -32,6 +32,8 @@ config BOARD_SPECIFIC_OPTIONS select PIRQ_ROUTE select BOARD_ROMSIZE_KB_512 select POWER_BUTTON_FORCE_ENABLE + select PLL_MANUAL_CONFIG + select CORE_GLIU_500_266 config MAINBOARD_DIR string @@ -45,19 +47,8 @@ config IRQ_SLOT_COUNT int default 7 -choice - prompt "Core/GLIU Frequency" - default CORE_GLIU_500_266 - -config CORE_GLIU_500_266 - bool "500MHz / 266MHz" - -config CORE_GLIU_500_333 - bool "500MHz / 333MHz" - -config CORE_GLIU_500_400 - bool "500MHz / 400MHz" - -endchoice +config PLLMSRlo + hex + default 0x07de0000 endif # BOARD_IEI_PM_LX_800_R11 diff --git a/src/mainboard/iei/pm-lx-800-r11/romstage.c b/src/mainboard/iei/pm-lx-800-r11/romstage.c index f756622..2992f53 100644 --- a/src/mainboard/iei/pm-lx-800-r11/romstage.c +++ b/src/mainboard/iei/pm-lx-800-r11/romstage.c @@ -46,16 +46,6 @@ static inline int spd_read_byte(unsigned int device, unsigned int address) return smbus_read_byte(device, address); } -#if CONFIG_CORE_GLIU_500_400 -# define PLLMSRhi 0x0000059c -#elif CONFIG_CORE_GLIU_500_333 -# define PLLMSRhi 0x0000049c -#else -# define PLLMSRhi 0x0000039c -#endif - -#define PLLMSRlo 0x07de000 - #include <northbridge/amd/lx/raminit.h> #include <northbridge/amd/lx/pll_reset.c> #include <northbridge/amd/lx/raminit.c> @@ -80,7 +70,7 @@ void main(unsigned long bist) report_bist_failure(bist); - pll_reset(1); + pll_reset(); cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED); diff --git a/src/mainboard/lippert/hurricane-lx/Kconfig b/src/mainboard/lippert/hurricane-lx/Kconfig index 118809d..64e1631 100644 --- a/src/mainboard/lippert/hurricane-lx/Kconfig +++ b/src/mainboard/lippert/hurricane-lx/Kconfig @@ -13,6 +13,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy # Board is equipped with a 1 MB SPI flash, however, due to limitations # of the IT8712F Super I/O, only the top 512 KB are directly mapped. select BOARD_ROMSIZE_KB_512 + select PLL_MANUAL_CONFIG + select CORE_GLIU_500_333 config MAINBOARD_DIR string @@ -50,4 +52,8 @@ config ONBOARD_UARTS_RS485 If selected, both on-board serial ports will operate in RS485 mode instead of RS232. +config PLLMSRlo + hex + default 0x00de6001 + endif # BOARD_LIPPERT_HURRICANE_LX diff --git a/src/mainboard/lippert/hurricane-lx/romstage.c b/src/mainboard/lippert/hurricane-lx/romstage.c index 29aa9d1..b2ee033 100644 --- a/src/mainboard/lippert/hurricane-lx/romstage.c +++ b/src/mainboard/lippert/hurricane-lx/romstage.c @@ -40,10 +40,6 @@ /* Bit0 enables Spread Spectrum. */ #define SMC_CONFIG 0x01 -#define ManualConf 1 /* No automatic strapped PLL config */ -#define PLLMSRhi 0x0000049C /* Manual settings for the PLL */ -#define PLLMSRlo 0x00DE6001 - static inline int spd_read_byte(unsigned int device, unsigned int address) { if (device != DIMM0) @@ -138,7 +134,7 @@ void main(unsigned long bist) /* Halt if there was a built in self test failure */ report_bist_failure(bist); - pll_reset(ManualConf); + pll_reset(); cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED); diff --git a/src/mainboard/lippert/literunner-lx/Kconfig b/src/mainboard/lippert/literunner-lx/Kconfig index 12a3ae1..c4684c9 100644 --- a/src/mainboard/lippert/literunner-lx/Kconfig +++ b/src/mainboard/lippert/literunner-lx/Kconfig @@ -15,6 +15,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy # of the IT8712F Super I/O, only the top 512 KB are directly mapped. select BOARD_ROMSIZE_KB_512 select POWER_BUTTON_FORCE_ENABLE + select PLL_MANUAL_CONFIG + select CORE_GLIU_500_400 config MAINBOARD_DIR string @@ -42,4 +44,8 @@ config ONBOARD_IDE_SLAVE If selected, the on-board Compact Flash card socket will act as IDE Slave instead of Master. +config PLLMSRlo + hex + default 0x00de6001 + endif # BOARD_LIPPERT_LITERUNNER_LX diff --git a/src/mainboard/lippert/literunner-lx/romstage.c b/src/mainboard/lippert/literunner-lx/romstage.c index 1e82bdb..77e2d12 100644 --- a/src/mainboard/lippert/literunner-lx/romstage.c +++ b/src/mainboard/lippert/literunner-lx/romstage.c @@ -44,10 +44,6 @@ #define SMC_CONFIG 0x01 #endif -#define ManualConf 1 /* No automatic strapped PLL config */ -#define PLLMSRhi 0x0000059C /* Manual settings for the PLL */ -#define PLLMSRlo 0x00DE6001 - static const unsigned char spdbytes[] = { // 4x Promos V58C2512164SA-J5I 0xFF, 0xFF, // only values used by Geode-LX raminit.c are set [SPD_MEMORY_TYPE] = SPD_MEMORY_TYPE_SDRAM_DDR, // (Fundamental) memory type @@ -181,7 +177,7 @@ void main(unsigned long bist) /* Halt if there was a built in self test failure */ report_bist_failure(bist); - pll_reset(ManualConf); + pll_reset(); cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED); diff --git a/src/mainboard/lippert/roadrunner-lx/Kconfig b/src/mainboard/lippert/roadrunner-lx/Kconfig index 2d11b33..f5ec9b9 100644 --- a/src/mainboard/lippert/roadrunner-lx/Kconfig +++ b/src/mainboard/lippert/roadrunner-lx/Kconfig @@ -14,6 +14,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy # SST 49LF008A is possible. select BOARD_ROMSIZE_KB_512 select POWER_BUTTON_FORCE_ENABLE + select PLL_MANUAL_CONFIG + select CORE_GLIU_500_333 config MAINBOARD_DIR string @@ -34,4 +36,8 @@ config ONBOARD_UARTS_RS485 If selected, both on-board serial ports will operate in RS485 mode instead of RS232. +config PLLMSRlo + hex + default 0x00de6001 + endif # BOARD_LIPPERT_ROADRUNNER_LX diff --git a/src/mainboard/lippert/roadrunner-lx/romstage.c b/src/mainboard/lippert/roadrunner-lx/romstage.c index 20e5b6a..827c41b 100644 --- a/src/mainboard/lippert/roadrunner-lx/romstage.c +++ b/src/mainboard/lippert/roadrunner-lx/romstage.c @@ -37,10 +37,6 @@ #include "southbridge/amd/cs5536/early_setup.c" #include "superio/ite/it8712f/early_serial.c" -#define ManualConf 1 /* No automatic strapped PLL config */ -#define PLLMSRhi 0x0000049C /* Manual settings for the PLL */ -#define PLLMSRlo 0x00DE6001 - static inline int spd_read_byte(unsigned int device, unsigned int address) { if (device != DIMM0) @@ -113,7 +109,7 @@ void main(unsigned long bist) /* Halt if there was a built in self test failure */ report_bist_failure(bist); - pll_reset(ManualConf); + pll_reset(); cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED); diff --git a/src/mainboard/lippert/spacerunner-lx/Kconfig b/src/mainboard/lippert/spacerunner-lx/Kconfig index 99ecf7c..c4a2ce8 100644 --- a/src/mainboard/lippert/spacerunner-lx/Kconfig +++ b/src/mainboard/lippert/spacerunner-lx/Kconfig @@ -15,6 +15,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy # of the IT8712F Super I/O, only the top 512 KB are directly mapped. select BOARD_ROMSIZE_KB_512 select POWER_BUTTON_FORCE_ENABLE + select PLL_MANUAL_CONFIG + select CORE_GLIU_500_400 config MAINBOARD_DIR string @@ -41,4 +43,8 @@ config ONBOARD_IDE_SLAVE help If selected, the on-board SSD will act as IDE Slave instead of Master. +config PLLMSRlo + hex + default 0x00de6001 + endif # BOARD_LIPPERT_SPACERUNNER_LX diff --git a/src/mainboard/lippert/spacerunner-lx/romstage.c b/src/mainboard/lippert/spacerunner-lx/romstage.c index 9dcb37b..d62c039 100644 --- a/src/mainboard/lippert/spacerunner-lx/romstage.c +++ b/src/mainboard/lippert/spacerunner-lx/romstage.c @@ -44,10 +44,6 @@ #define SMC_CONFIG 0x01 #endif -#define ManualConf 1 /* No automatic strapped PLL config */ -#define PLLMSRhi 0x0000059C /* Manual settings for the PLL */ -#define PLLMSRlo 0x00DE6001 - static const unsigned char spdbytes[] = { // 4x Promos V58C2512164SA-J5I 0xFF, 0xFF, // only values used by Geode-LX raminit.c are set [SPD_MEMORY_TYPE] = SPD_MEMORY_TYPE_SDRAM_DDR, // (Fundamental) memory type @@ -178,7 +174,7 @@ void main(unsigned long bist) /* Halt if there was a built in self test failure */ report_bist_failure(bist); - pll_reset(ManualConf); + pll_reset(); cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED); diff --git a/src/mainboard/pcengines/alix1c/romstage.c b/src/mainboard/pcengines/alix1c/romstage.c index f109031..9de3863 100644 --- a/src/mainboard/pcengines/alix1c/romstage.c +++ b/src/mainboard/pcengines/alix1c/romstage.c @@ -99,10 +99,6 @@ static u8 spd_read_byte(u8 device, u8 address) return spdbytes[address]; } -#define ManualConf 0 /* Do automatic strapped PLL config */ -#define PLLMSRhi 0x00001490 /* Manual settings for the PLL */ -#define PLLMSRlo 0x02000030 - #include "northbridge/amd/lx/raminit.h" #include "northbridge/amd/lx/pll_reset.c" #include "northbridge/amd/lx/raminit.c" @@ -132,7 +128,7 @@ void main(unsigned long bist) /* Halt if there was a built in self test failure */ report_bist_failure(bist); - pll_reset(ManualConf); + pll_reset(); cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED); diff --git a/src/mainboard/pcengines/alix2d/romstage.c b/src/mainboard/pcengines/alix2d/romstage.c index 0e8cc63..fd5582d 100644 --- a/src/mainboard/pcengines/alix2d/romstage.c +++ b/src/mainboard/pcengines/alix2d/romstage.c @@ -98,10 +98,6 @@ static u8 spd_read_byte(u8 device, u8 address) return spdbytes[address]; } -#define ManualConf 0 /* Do automatic strapped PLL config */ -#define PLLMSRhi 0x00001490 /* Manual settings for the PLL */ -#define PLLMSRlo 0x02000030 - #include "northbridge/amd/lx/raminit.h" #include "northbridge/amd/lx/pll_reset.c" #include "northbridge/amd/lx/raminit.c" @@ -156,7 +152,7 @@ void main(unsigned long bist) /* Halt if there was a built in self test failure */ report_bist_failure(bist); - pll_reset(ManualConf); + pll_reset(); cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED); diff --git a/src/mainboard/traverse/geos/Kconfig b/src/mainboard/traverse/geos/Kconfig index 40679fe..3139d7d 100644 --- a/src/mainboard/traverse/geos/Kconfig +++ b/src/mainboard/traverse/geos/Kconfig @@ -11,6 +11,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy select UDELAY_TSC select BOARD_ROMSIZE_KB_1024 select POWER_BUTTON_DEFAULT_DISABLE + select PLL_MANUAL_CONFIG + select CORE_GLIU_500_400 config MAINBOARD_DIR string @@ -24,4 +26,8 @@ config IRQ_SLOT_COUNT int default 6 +config PLLMSRlo + hex + default 0x00de602e + endif # BOARD_TRAVERSE_GEOS diff --git a/src/mainboard/traverse/geos/romstage.c b/src/mainboard/traverse/geos/romstage.c index 588681b..0b61d41 100644 --- a/src/mainboard/traverse/geos/romstage.c +++ b/src/mainboard/traverse/geos/romstage.c @@ -39,10 +39,6 @@ static inline int spd_read_byte(unsigned int device, unsigned int address) return smbus_read_byte(device, address); } -#define ManualConf 1 /* Do automatic strapped PLL config */ -#define PLLMSRhi 0x0000059C /* manual settings for the PLL */ -#define PLLMSRlo 0x00DE602E - #include "northbridge/amd/lx/raminit.h" #include "northbridge/amd/lx/pll_reset.c" #include "northbridge/amd/lx/raminit.c" @@ -75,7 +71,7 @@ void main(unsigned long bist) /* Halt if there was a built in self test failure */ report_bist_failure(bist); - pll_reset(ManualConf); + pll_reset(); cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED); diff --git a/src/mainboard/winent/pl6064/romstage.c b/src/mainboard/winent/pl6064/romstage.c index 6651acd..39e4ecf 100644 --- a/src/mainboard/winent/pl6064/romstage.c +++ b/src/mainboard/winent/pl6064/romstage.c @@ -43,10 +43,6 @@ static inline int spd_read_byte(unsigned int device, unsigned int address) return smbus_read_byte(device, address); } -#define ManualConf 0 /* Do automatic strapped PLL config */ -#define PLLMSRhi 0x00001490 /* Manual settings for the PLL */ -#define PLLMSRlo 0x02000030 - #include "northbridge/amd/lx/raminit.h" #include "northbridge/amd/lx/pll_reset.c" #include "northbridge/amd/lx/raminit.c" @@ -77,7 +73,7 @@ void main(unsigned long bist) /* Halt if there was a built in self test failure */ report_bist_failure(bist); - pll_reset(ManualConf); + pll_reset(); cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED); diff --git a/src/northbridge/amd/lx/Kconfig b/src/northbridge/amd/lx/Kconfig index c1fea49..d74d715 100644 --- a/src/northbridge/amd/lx/Kconfig +++ b/src/northbridge/amd/lx/Kconfig @@ -2,7 +2,36 @@ config NORTHBRIDGE_AMD_LX bool select GEODE_VSA +if NORTHBRIDGE_AMD_LX + config VIDEO_MB int default 8 - depends on NORTHBRIDGE_AMD_LX + +config PLL_MANUAL_CONFIG + bool + +if PLL_MANUAL_CONFIG + +# "Core/GLIU Frequency" +config CORE_GLIU_500_266 + bool # "500MHz / 266MHz" + +config CORE_GLIU_500_333 + bool # "500MHz / 333MHz" + +config CORE_GLIU_500_400 + bool # "500MHz / 400MHz" + +config PLLMSRhi + hex + default 0x39c if CORE_GLIU_500_266 + default 0x49c if CORE_GLIU_500_333 + default 0x59c if CORE_GLIU_500_400 + +config PLLMSRlo + hex + +endif + +endif diff --git a/src/northbridge/amd/lx/pll_reset.c b/src/northbridge/amd/lx/pll_reset.c index 3077b61..bf01e54 100644 --- a/src/northbridge/amd/lx/pll_reset.c +++ b/src/northbridge/amd/lx/pll_reset.c @@ -18,7 +18,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -static void pll_reset(char manualconf) +static void pll_reset(void) { msr_t msrGlcpSysRstpll; @@ -31,13 +31,13 @@ static void pll_reset(char manualconf) if (!(msrGlcpSysRstpll.lo & (1 << RSTPLL_LOWER_SWFLAGS_SHIFT))) { printk(BIOS_DEBUG, "Configuring PLL.\n"); - if (manualconf) { + if (CONFIG_PLL_MANUAL_CONFIG) { post_code(POST_PLL_MANUAL); /* CPU and GLIU mult/div (GLMC_CLK = GLIU_CLK / 2) */ - msrGlcpSysRstpll.hi = PLLMSRhi; + msrGlcpSysRstpll.hi = CONFIG_PLLMSRhi; /* Hold Count - how long we will sit in reset */ - msrGlcpSysRstpll.lo = PLLMSRlo; + msrGlcpSysRstpll.lo = CONFIG_PLLMSRlo; } else { /*automatic configuration (straps) */ post_code(POST_PLL_STRAP);

1 0

Patch set updated for coreboot: d2f2f57 IEI PM-LX2-800-R10: Added preliminary mainboard support
by Patrick Georgi 25 Jul '12

25 Jul '12

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1152 -gerrit commit d2f2f572e0ba6aea12565f7e006445aff9cfae44 Author: Ricardo Martins <rasmartins(a)gmail.com> Date: Sat Jul 7 14:27:03 2012 +0100 IEI PM-LX2-800-R10: Added preliminary mainboard support Details for this board are available at http://usa.ieiworld.com/product_groups/industrial/content.aspx?gid=00001000… Most of the functionality provided by the original BIOS is implemented. The Geode Link Speed is hardcoded to a safe value. I'll add automatic configuration in a later patch. Change-Id: Iaefe47f5ad405a56d230c929e5850156eb0f60ae Signed-off-by: Ricardo Martins <rasmartins(a)gmail.com> --- src/mainboard/iei/Kconfig | 3 + src/mainboard/iei/pm-lx2-800-r10/Kconfig | 58 ++++++++++ src/mainboard/iei/pm-lx2-800-r10/chip.h | 23 ++++ src/mainboard/iei/pm-lx2-800-r10/cmos.layout | 103 ++++++++++++++++++ src/mainboard/iei/pm-lx2-800-r10/devicetree.cb | 87 +++++++++++++++ src/mainboard/iei/pm-lx2-800-r10/irq_tables.c | 134 ++++++++++++++++++++++++ src/mainboard/iei/pm-lx2-800-r10/it8888_io.def | 27 +++++ src/mainboard/iei/pm-lx2-800-r10/mainboard.c | 103 ++++++++++++++++++ src/mainboard/iei/pm-lx2-800-r10/romstage.c | 91 ++++++++++++++++ 9 files changed, 629 insertions(+), 0 deletions(-) diff --git a/src/mainboard/iei/Kconfig b/src/mainboard/iei/Kconfig index ea26922..537252d 100644 --- a/src/mainboard/iei/Kconfig +++ b/src/mainboard/iei/Kconfig @@ -31,6 +31,8 @@ config BOARD_IEI_PCISA_LX_800_R10 bool "PCISA LX-800-R10" config BOARD_IEI_PM_LX_800_R11 bool "PM LX-800-R11" +config BOARD_IEI_PM_LX2_800_R10 + bool "PM-LX2-800-R10" endchoice @@ -39,6 +41,7 @@ source "src/mainboard/iei/kino-780am2-fam10/Kconfig" source "src/mainboard/iei/nova4899r/Kconfig" source "src/mainboard/iei/pcisa-lx-800-r10/Kconfig" source "src/mainboard/iei/pm-lx-800-r11/Kconfig" +source "src/mainboard/iei/pm-lx2-800-r10/Kconfig" config MAINBOARD_VENDOR string diff --git a/src/mainboard/iei/pm-lx2-800-r10/Kconfig b/src/mainboard/iei/pm-lx2-800-r10/Kconfig new file mode 100644 index 0000000..62f8520 --- /dev/null +++ b/src/mainboard/iei/pm-lx2-800-r10/Kconfig @@ -0,0 +1,58 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2012 Ricardo Martins <rasmartins(a)gmail.com> +## +## This program is free software; you can redistribute it and/or +## modify it under the terms of the GNU General Public License as +## published by the Free Software Foundation; version 2 of +## the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +## MA 02110-1301 USA +## + +if BOARD_IEI_PM_LX2_800_R10 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select ARCH_X86 + select CPU_AMD_GEODE_LX + select NORTHBRIDGE_AMD_LX + select SOUTHBRIDGE_AMD_CS5536 + select SUPERIO_SMSC_SMSCSUPERIO + select HAVE_PIRQ_TABLE + select HAVE_OPTION_TABLE + select PIRQ_ROUTE + select BOARD_ROMSIZE_KB_512 + select POWER_BUTTON_FORCE_ENABLE + select PLL_MANUAL_CONFIG + select CORE_GLIU_500_266 + +config MAINBOARD_DIR + string + default iei/pm-lx2-800-r10 + +config MAINBOARD_PART_NUMBER + string + default "PM-LX2-800-R10" + +config IRQ_SLOT_COUNT + int + default 3 + +config SCH3114_COM3_AUTO_DIR + bool "COM3 Automatic Direction Control" + default y + help + If selected, COM3 automatic direction control will + be enabled by default. + +endif # BOARD_IEI_PM_LX2_800_R10 diff --git a/src/mainboard/iei/pm-lx2-800-r10/chip.h b/src/mainboard/iei/pm-lx2-800-r10/chip.h new file mode 100644 index 0000000..d69f9b6 --- /dev/null +++ b/src/mainboard/iei/pm-lx2-800-r10/chip.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Ricardo Martins <rasmartins(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/iei/pm-lx2-800-r10/cmos.layout b/src/mainboard/iei/pm-lx2-800-r10/cmos.layout new file mode 100644 index 0000000..e09cfb6 --- /dev/null +++ b/src/mainboard/iei/pm-lx2-800-r10/cmos.layout @@ -0,0 +1,103 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2012 Ricardo Martins <rasmartins(a)gmail.com> +## +## This program is free software; you can redistribute it and/or +## modify it under the terms of the GNU General Public License as +## published by the Free Software Foundation; version 2 of +## the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +## MA 02110-1301 USA +## + +entries + # RTC + 0 384 r 0 reserved_rtc + # Coreboot + 384 1 e 3 boot_option + 385 1 e 3 last_boot + 386 4 r 0 reboot_bits + 390 3 e 4 baud_rate + 393 4 e 5 debug_level + 397 2 r 0 unused + # PM-LX2-800-R10 + 399 1 e 1 com3_auto_direction + 400 1 e 2 it8888_io_space0 + 401 1 e 2 it8888_io_space1 + 402 1 e 2 it8888_io_space2 + 403 1 e 2 it8888_io_space3 + 404 2 e 6 it8888_io_space0_speed + 406 2 e 6 it8888_io_space1_speed + 408 2 e 6 it8888_io_space2_speed + 410 2 e 6 it8888_io_space3_speed + 412 3 e 7 it8888_io_space0_size + 415 3 e 7 it8888_io_space1_size + 418 3 e 7 it8888_io_space2_size + 421 3 e 7 it8888_io_space3_size + 424 16 h 0 it8888_io_space0_addr + 440 16 h 0 it8888_io_space1_addr + 456 16 h 0 it8888_io_space2_addr + 472 16 h 0 it8888_io_space3_addr + 488 16 h 0 check_sum + +enumerations + # Yes / No + 1 0 No + 1 1 Yes + + # Enabled / Disabled + 2 0 Disabled + 2 1 Enabled + + # Normal / Fallback + 3 0 Fallback + 3 1 Normal + + # Console Baud Rate + 4 0 115200 + 4 1 57600 + 4 2 38400 + 4 3 19200 + 4 4 9600 + 4 5 4800 + 4 6 2400 + 4 7 1200 + + # Console Log Level + 5 0 Emergency + 5 1 Alert + 5 2 Critical + 5 3 Error + 5 4 Warning + 5 5 Notice + 5 6 Info + 5 7 Debug + 5 8 Spew + + # IT8888 Decoding Speeds + 6 0 Subtractive + 6 1 Slow + 6 2 Medium + 6 3 Fast + + # IT8888 Decoding Sizes + 7 0 1 + 7 1 2 + 7 2 4 + 7 3 8 + 7 4 16 + 7 5 32 + 7 6 64 + 7 7 128 + +checksums + checksum 384 487 488 diff --git a/src/mainboard/iei/pm-lx2-800-r10/devicetree.cb b/src/mainboard/iei/pm-lx2-800-r10/devicetree.cb new file mode 100644 index 0000000..f5721a3 --- /dev/null +++ b/src/mainboard/iei/pm-lx2-800-r10/devicetree.cb @@ -0,0 +1,87 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2012 Ricardo Martins <rasmartins(a)gmail.com> +## +## This program is free software; you can redistribute it and/or +## modify it under the terms of the GNU General Public License as +## published by the Free Software Foundation; version 2 of +## the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +## MA 02110-1301 USA +## + +chip northbridge/amd/lx + device pci_domain 0 on + device pci 1.0 on end # Northbridge + device pci 1.1 on end # Video Adapter + device pci 1.2 on end # AES Security Block + chip southbridge/amd/cs5536 + register "lpc_serirq_enable" = "0x000010da" + register "lpc_serirq_polarity" = "0x0000ef25" + register "lpc_serirq_mode" = "1" + register "enable_gpio_int_route" = "0x0d0c0700" + register "enable_ide_nand_flash" = "0" + register "enable_USBP4_device" = "0" # 0:host, 1:device + register "enable_USBP4_overcurrent" = "0" + register "com1_enable" = "0" + register "com2_enable" = "0" + register "unwanted_vpci[0]" = "0" # End of list has a zero + device pci 11.0 on end # IT8888 + device pci e.0 on end # RTL8100C + device pci f.0 on # ISA Bridge + chip superio/smsc/smscsuperio # SMSC SCH3114 + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + + device pnp 2e.3 off # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + end + + device pnp 2e.4 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + + device pnp 2e.5 on # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + + device pnp 2e.7 on # PS/2 keyboard/mouse + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 # Keyboard + irq 0x72 = 12 # Mouse + end + + device pnp 2e.a on # Runtime Register + io 0x60 = 0x400 + end + end + end + device pci f.2 on end # IDE Controller + device pci f.3 on end # Audio + device pci f.4 on end # OHCI + device pci f.5 on end # EHCI + end + end + # APIC cluster is late CPU init. + device lapic_cluster 0 on + chip cpu/amd/geode_lx + device lapic 0 on end + end + end +end diff --git a/src/mainboard/iei/pm-lx2-800-r10/irq_tables.c b/src/mainboard/iei/pm-lx2-800-r10/irq_tables.c new file mode 100644 index 0000000..2bbf218 --- /dev/null +++ b/src/mainboard/iei/pm-lx2-800-r10/irq_tables.c @@ -0,0 +1,134 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Ricardo Martins <rasmartins(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <device/pci_ids.h> +#include <arch/pirq_routing.h> + +/* Platform IRQs */ +#define PIRQA 10 +#define PIRQB 10 +#define PIRQC 11 +#define PIRQD 11 + +/* Links */ +#define L_PIRQN 0 +#define L_PIRQA 1 +#define L_PIRQB 2 +#define L_PIRQC 3 +#define L_PIRQD 4 + +/* Bitmaps */ +#define B_LINKN (0) +#define B_LINK0 (1 << PIRQA) +#define B_LINK1 (1 << PIRQB) +#define B_LINK2 (1 << PIRQC) +#define B_LINK3 (1 << PIRQD) + +const struct irq_routing_table intel_irq_routing_table = { + PIRQ_SIGNATURE, /* u32 signature */ + PIRQ_VERSION, /* u16 version */ + 32 + 16 * CONFIG_IRQ_SLOT_COUNT, /* Max. number of devices on the bus */ + 0x00, /* Interrupt router bus */ + (0x0f << 3) | 0x0, /* Interrupt router dev */ + (B_LINK0 | B_LINK1 | B_LINK2 | B_LINK3),/* IRQs devoted exclusively to PCI usage */ + PCI_VENDOR_ID_AMD, /* Vendor */ + PCI_DEVICE_ID_AMD_CS5536_ISA, /* Device */ + 0, /* Miniport */ + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + 0x27, /* Checksum */ + { + [0] = { /* Host bridge */ + .slot = 0x00, + .bus = 0x00, + .devfn = (0x01 << 3) | 0x0, + .irq = { + [0] = { + .link = L_PIRQA, + .bitmap = B_LINK0 + }, + [1] = { + .link = L_PIRQN, + .bitmap = B_LINKN + }, + [2] = { + .link = L_PIRQN, + .bitmap = B_LINKN + }, + [3] = { + .link = L_PIRQN, + .bitmap = B_LINKN + } + } + }, + + [1] = { /* ISA bridge */ + .slot = 0x00, + .bus = 0x00, + .devfn = (0x0f << 3) | 0x0, + .irq = { + [0] = { + .link = L_PIRQN, + .bitmap = B_LINKN + }, + [1] = { + .link = L_PIRQB, + .bitmap = B_LINK1 + }, + [2] = { + .link = L_PIRQN, + .bitmap = B_LINKN + }, + [3] = { + .link = L_PIRQD, + .bitmap = B_LINK3 + } + } + }, + + [2] = { /* Ethernet */ + .slot = 0x00, + .bus = 0x00, + .devfn = (0x0e << 3) | 0x0, + .irq = { + [0] = { + .link = L_PIRQD, + .bitmap = B_LINK3 + }, + [1] = { + .link = L_PIRQN, + .bitmap = B_LINKN + }, + [2] = { + .link = L_PIRQN, + .bitmap = B_LINKN + }, + [3] = { + .link = L_PIRQN, + .bitmap = B_LINKN + } + } + } + } +}; + +unsigned long write_pirq_routing_table(unsigned long addr) +{ + return copy_pirq_routing_table(addr); +} diff --git a/src/mainboard/iei/pm-lx2-800-r10/it8888_io.def b/src/mainboard/iei/pm-lx2-800-r10/it8888_io.def new file mode 100644 index 0000000..5920abc --- /dev/null +++ b/src/mainboard/iei/pm-lx2-800-r10/it8888_io.def @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Ricardo Martins <rasmartins(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* Name, Register, Enabled/Disabled, Speed, Size, Address. */ +IT8888_IO("it8888_io_space0", 0x58, 0, 0, 0, 0) +IT8888_IO("it8888_io_space1", 0x5c, 0, 0, 0, 0) +IT8888_IO("it8888_io_space2", 0x60, 0, 0, 0, 0) +IT8888_IO("it8888_io_space3", 0x64, 0, 0, 0, 0) +IT8888_IO("it8888_io_space4", 0x68, 0, 0, 0, 0) +IT8888_IO("it8888_io_space5", 0x6c, 0, 0, 0, 0) diff --git a/src/mainboard/iei/pm-lx2-800-r10/mainboard.c b/src/mainboard/iei/pm-lx2-800-r10/mainboard.c new file mode 100644 index 0000000..170a67a --- /dev/null +++ b/src/mainboard/iei/pm-lx2-800-r10/mainboard.c @@ -0,0 +1,103 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Ricardo Martins <rasmartins(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <console/console.h> +#include <device/pci.h> +#include <device/device.h> +#include <boot/tables.h> +#include <pc80/mc146818rtc.h> +#include "chip.h" + +#if CONFIG_USE_OPTION_TABLE +# include "option_table.h" +#endif + +/* SCH3114 runtime register (RTR) address. */ +#define SCH3114_RTR_ADDR (0x400) +/* SP34 option register. */ +#define SCH3114_RTR_SP34_OPT (SCH3114_RTR_ADDR + 0x13) +/* H/W Monitoring register block index. */ +#define SCH3114_RTR_HWM_IDX (SCH3114_RTR_ADDR + 0x70) +/* H/W Monitoring register block data. */ +#define SCH3114_RTR_HWM_DAT (SCH3114_RTR_ADDR + 0x71) +/* H/W Monitoring Ready/Lock/Start register. */ +#define SCH3114_HWM_RLS_REG (0x40) +/* IT8888 PCI Vendor ID. */ +#define IT8888_PCI_VID (0x1283) +/* IT8888 PCI Device ID. */ +#define IT8888_PCI_DID (0x8888) + +static u16 opt(const char* option, u16 def_value) +{ +#if CONFIG_USE_OPTION_TABLE + u16 value = 0; + if (get_option(&value, option) != 0) + value = def_value; + return value; +#else + return def_value; +#endif +} + +static void init(struct device *dev) +{ + /* SCH3114: enable hardware monitor. */ + printk(BIOS_INFO, "Enabling SCH3114 hardware monitor\n"); + outb(SCH3114_HWM_RLS_REG, SCH3114_RTR_HWM_IDX); + outb(inb(SCH3114_RTR_HWM_DAT) | 0x01, SCH3114_RTR_HWM_DAT); + + /* SCH3114: COM3 Automatic Direction Control / nRTS control. */ + if (opt("com3_auto_direction", CONFIG_SCH3114_COM3_AUTO_DIR) != 0) { + printk(BIOS_INFO, "Enabling RS858 Auto Direction Control\n"); + outb(inb(SCH3114_RTR_SP34_OPT) | 0x03, SCH3114_RTR_SP34_OPT); + } + + /* IT8888. */ + device_t it8x = dev_find_device(IT8888_PCI_VID, IT8888_PCI_DID, 0); + if (!it8x) { + printk(BIOS_ERR, "IT8888 not found\n"); + return; + } + + u32 cfg = 0; +#define IT8888_IO(name, reg, dena, dspeed, dsize, daddr) \ + if (opt(name, dena) != 0) { \ + cfg = (1 << 31); \ + cfg |= opt(name "_addr", daddr); \ + cfg |= opt(name "_speed", dspeed) << 29; \ + cfg |= opt(name "_size", dsize) << 24; \ + } else { \ + cfg = 0; \ + } \ + pci_write_config32(it8x, reg, cfg); + +#include "it8888_io.def" +} + +static void enable_dev(struct device *dev) +{ + dev->ops->init = init; +} + +struct chip_operations mainboard_ops = { + CHIP_NAME("IEI PM-LX2-800-R10 Mainboard") + .enable_dev = enable_dev, +}; diff --git a/src/mainboard/iei/pm-lx2-800-r10/romstage.c b/src/mainboard/iei/pm-lx2-800-r10/romstage.c new file mode 100644 index 0000000..8bc55f4 --- /dev/null +++ b/src/mainboard/iei/pm-lx2-800-r10/romstage.c @@ -0,0 +1,91 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Advanced Micro Devices, Inc. + * Copyright (C) 2012 Ricardo Martins <rasmartins(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include <stdlib.h> + +#include <spd.h> +#include <arch/io.h> +#include <arch/hlt.h> +#include <arch/llshell.h> +#include <device/pci_def.h> +#include <device/pnp_def.h> +#include <console/console.h> +#include <cpu/x86/bist.h> +#include <cpu/x86/msr.h> +#include <cpu/amd/lxdef.h> +#include <southbridge/amd/cs5536/cs5536.h> +#include <southbridge/amd/cs5536/early_smbus.c> +#include <southbridge/amd/cs5536/early_setup.c> +#include <superio/smsc/smscsuperio/early_serial.c> + +#define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1) + +static inline int spd_read_byte(unsigned int device, unsigned int address) +{ + /* Only DIMM0 is available. */ + if (device != DIMM0) + return 0xFF; + + return smbus_read_byte(device, address); +} + +#include <northbridge/amd/lx/raminit.h> +#include <northbridge/amd/lx/pll_reset.c> +#include <northbridge/amd/lx/raminit.c> +#include <lib/generic_sdram.c> +#include <cpu/amd/geode_lx/cpureginit.c> +#include <cpu/amd/geode_lx/syspreinit.c> +#include <cpu/amd/geode_lx/msrinit.c> + +void main(unsigned long bist) +{ + static const struct mem_controller memctrl[] = { + {.channel0 = {DIMM0, DIMM1}} + }; + + SystemPreInit(); + msr_init(); + + cs5536_early_setup(); + + smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + console_init(); + + /* Enable COM3. */ + device_t dev = PNP_DEV(0x2e, 0x0b); + u16 port = dev >> 8; + outb(0x55, port); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, 0x3e8); + pnp_set_irq(dev, PNP_IDX_IRQ0, 4); + pnp_set_enable(dev, 1); + outb(0xaa, port); + + report_bist_failure(bist); + + pll_reset(1); + + cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED); + + sdram_initialize(1, memctrl); +}

1 0

Accessing Repository via http fails
by Bao, Zheng 25 Jul '12

25 Jul '12

Hi, Stefan & folks, Is it just me or do you guys have the same problem when clone the code via http? #git clone http://[<username>:<password>@]review.coreboot.org/p/coreboot.git Initialized empty Git repository in /home/baozheng/LinuxBIOS/temp/coreboot/.git/ error: The requested URL returned error: 503 while accessing http://zbao:nDK8YdCIeF6v@review.coreboot.org/p/coreboot.git/info/refs fatal: HTTP request failed Any thing wrong? Zheng

1 0

Patch merged into coreboot/master: c3b4a5e sync the northbridge.c with other family.
by gerrit＠coreboot.org 25 Jul '12

25 Jul '12

the following patch was just integrated into master: commit c3b4a5e90ef23b10d37fa89d0a633982d5a329cd Author: zbao <fishbaozi(a)gmail.com> Date: Mon Jul 23 19:41:03 2012 +0800 sync the northbridge.c with other family. Change-Id: Ice4d0202590fca0169dcda2770ca6add166b5c13 Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: zbao <fishbaozi(a)gmail.com> Build-Tested: build bot (Jenkins) at Mon Jul 23 12:32:35 2012, giving +1 See http://review.coreboot.org/1262 for details. -gerrit

1 0

Patch merged into coreboot/master: 93f232d Fix LAPIC timer on Ivy Bridge systems
by gerrit＠coreboot.org 25 Jul '12

25 Jul '12

the following patch was just integrated into master: commit 93f232dad8f8e544153c14b6d57cb66395adb960 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Tue Jul 10 13:24:29 2012 -0700 Fix LAPIC timer on Ivy Bridge systems The LAPIC timer is running at BCLK (100MHz) on Sandy Bridge and Ivy Bridge systems. However, the current timer code assumed that the clock would run at 200MHz instead. This made all delays twice as long as needed. Change-Id: I41b1186daee11cfd9a25b3a9d5ebdeeb271293c7 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Tue Jul 24 08:48:48 2012, giving +2 Build-Tested: build bot (Jenkins) at Tue Jul 24 23:41:21 2012, giving +1 See http://review.coreboot.org/1330 for details. -gerrit

1 0

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coreboot July 2012