coreboot July 2012

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Patch set updated for coreboot: ac9c349 chromeos: Pass pointer to ChromeOS ACPI structure instead of VB Shared Data
by Stefan Reinauer 25 Jul '12

25 Jul '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1282 -gerrit commit ac9c349576511d4c8e67a4964fe777a9658c9534 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Wed Jun 13 13:12:19 2012 -0700 chromeos: Pass pointer to ChromeOS ACPI structure instead of VB Shared Data coreboot used to pass some information to u-boot in the coreboot table and other information in a modified flat device tree. Since the FDT code was never upstreamed and removed from our tree, u-boot was changed to get the information it needs from the coreboot table alone. However, in the process of this change only the vboot shared data structure was passed on by coreboot, so when u-boot tried to update the ChromeOS specific ACPI entries, it would accidently overwrite the vboot data. This patch passes on the ChromeOS specific ACPI data structure instead of the vboot shared data. Another change to u-boot will teach it how to get to the vboot shared data from there. Change-Id: Ifbb64eafc0d9967887b4cdeebf97d0c4ce019290 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/arch/x86/include/arch/acpi.h | 4 ---- src/vendorcode/google/chromeos/gnvs.c | 9 ++++++++- src/vendorcode/google/chromeos/gnvs.h | 1 + 3 files changed, 9 insertions(+), 5 deletions(-) diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index 8c8106d..0b2cbf4 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -523,8 +523,4 @@ void generate_cpu_entries(void); #endif /* CONFIG_GENERATE_ACPI_TABLES */ -#if CONFIG_CHROMEOS -void acpi_get_vdat_info(void **vdat_addr, uint32_t *vdat_size); -#endif /* CONFIG_CHROMEOS */ - #endif /* __ASM_ACPI_H */ diff --git a/src/vendorcode/google/chromeos/gnvs.c b/src/vendorcode/google/chromeos/gnvs.c index 024dbf8..aaca95a 100644 --- a/src/vendorcode/google/chromeos/gnvs.c +++ b/src/vendorcode/google/chromeos/gnvs.c @@ -23,7 +23,7 @@ #include <console/console.h> #include "gnvs.h" -chromeos_acpi_t *vboot_data; +chromeos_acpi_t *vboot_data = NULL; static u32 me_hash_saved[8]; void chromeos_init_vboot(chromeos_acpi_t *chromeos) @@ -41,7 +41,14 @@ void chromeos_set_me_hash(u32 *hash, int len) /* Copy to NVS or save until it is ready */ if (vboot_data) + /* This does never happen! */ memcpy(vboot_data->mehh, hash, len*sizeof(u32)); else memcpy(me_hash_saved, hash, len*sizeof(u32)); } + +void acpi_get_vdat_info(void **vdat_addr, uint32_t *vdat_size) +{ + *vdat_addr = vboot_data; + *vdat_size = sizeof(*vboot_data); +} diff --git a/src/vendorcode/google/chromeos/gnvs.h b/src/vendorcode/google/chromeos/gnvs.h index 6dd740f..4067494 100644 --- a/src/vendorcode/google/chromeos/gnvs.h +++ b/src/vendorcode/google/chromeos/gnvs.h @@ -64,5 +64,6 @@ typedef struct { extern chromeos_acpi_t *vboot_data; void chromeos_init_vboot(chromeos_acpi_t *chromeos); void chromeos_set_me_hash(u32*, int); +void acpi_get_vdat_info(void **vdat_addr, uint32_t *vdat_size); #endif

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Patch merged into coreboot/master: 4f4dda8 ELOG: Add support for a monotonic boot counter in CMOS
by gerrit＠coreboot.org 25 Jul '12

25 Jul '12

the following patch was just integrated into master: commit 4f4dda816d74613c463838fde8a4abb1da19c4e8 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Sat Jun 23 16:37:45 2012 -0700 ELOG: Add support for a monotonic boot counter in CMOS This maintains a 32bit monotonically increasing boot counter that is stored in CMOS and logged on every non-S3 boot when the event log is initialized. In CMOS the count is prefixed with a 16bit signature and appended with a 16bit checksum. This counter is incremented in sandybridge early_init which is called by romstage. It is incremented early in order notice when reboots happen after memory init. The counter is then logged when ELOG is initialized and will store the boot count as part of a 'System boot; event. Reboot a few times and look for 'System boot' events in the event log and check that they are increasing. Also verify that the counter does NOT increase when resuming from S3. 171 | 2012-06-23 16:02:55 | System boot | 285 176 | 2012-06-23 16:26:00 | System boot | 286 182 | 2012-06-23 16:27:04 | System boot | 287 189 | 2012-06-23 16:31:10 | System boot | 288 Change-Id: I23faeafcf155edfd10aa6882598b3883575f8a33 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Build-Tested: build bot (Jenkins) at Tue Jul 24 17:01:03 2012, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Wed Jul 25 00:47:08 2012, giving +2 See http://review.coreboot.org/1315 for details. -gerrit

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Patch merged into coreboot/master: 57a75b6 ELOG: Add support for generating SMBIOS type15 table
by gerrit＠coreboot.org 25 Jul '12

25 Jul '12

the following patch was just integrated into master: commit 57a75b64ce14f968a4ea251da53fef3b4c3983f3 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Sat Jun 23 16:13:42 2012 -0700 ELOG: Add support for generating SMBIOS type15 table This standared SMBIOS 0able describes the location and format of the event log to the OS and applications. In this case the pointer is a 32bit physical address pointer to the log in memory mapped flash. Look for SMBIOS type15 entry with 'dmidecode -t 15' Handle 0x0004, DMI type 15, 23 bytes System Event Log Area Length: 4095 bytes Header Start Offset: 0x0000 Header Length: 8 bytes Data Start Offset: 0x0008 Access Method: Memory-mapped physical 32-bit address Access Address: 0xFFB6F000 Status: Valid, Not Full Change Token: 0x00000000 Header Format: OEM-specific Supported Log Type Descriptors: 0 Change-Id: I1e7729e604000f197e26e69991a2867e869197a6 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Build-Tested: build bot (Jenkins) at Tue Jul 24 16:39:18 2012, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Wed Jul 25 00:46:55 2012, giving +2 See http://review.coreboot.org/1314 for details. -gerrit

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Patch merged into coreboot/master: f135193 More descriptive error messages in Sandybridge raminit code
by gerrit＠coreboot.org 25 Jul '12

25 Jul '12

the following patch was just integrated into master: commit f1351932d41879cf8b71e8586667ba1ab5ac70c7 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Mon Jun 18 14:38:40 2012 -0700 More descriptive error messages in Sandybridge raminit code MRC returns specific error codes; print the according error message if we know what it means. Change-Id: Iaaf1512b9d577d4291fccfb94d879043ab5b11b5 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Build-Tested: build bot (Jenkins) at Tue Jul 24 06:43:07 2012, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Wed Jul 25 00:35:42 2012, giving +2 See http://review.coreboot.org/1289 for details. -gerrit

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Patch merged into coreboot/master: f207abb bd82x6x: Drop unneeded pci_dev_t
by gerrit＠coreboot.org 25 Jul '12

25 Jul '12

the following patch was just integrated into master: commit f207abb3c727ebb80f0398d3a44e5defe93fed99 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Tue Jul 10 13:26:59 2012 -0700 bd82x6x: Drop unneeded pci_dev_t This was introduced when porting the SPI driver over from u-boot but it is not needed. Hence drop the extra typedef and use device_t instead. Change-Id: I3ab797a8e482d1c9aa1d004e488e99aeaffcdd8b Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Tue Jul 24 08:46:21 2012, giving +2 Build-Tested: build bot (Jenkins) at Wed Jul 25 00:18:55 2012, giving +1 See http://review.coreboot.org/1331 for details. -gerrit

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New patch to review for coreboot: fad6d0b SMM: Fix state table for Intel Core2 CPUs
by Stefan Reinauer 24 Jul '12

24 Jul '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1353 -gerrit commit fad6d0bbfd2152af48bc4648e72afe839f306d3d Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Tue Jul 24 14:53:15 2012 -0700 SMM: Fix state table for Intel Core2 CPUs When fixing the SMM state table for SandyBridge/IvyBridge CPUs the wrong table was used for older 64bit capable CPUs. Change-Id: Ia7dff21aa3f0e5aa61575634fc839777de6bef10 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/cpu/x86/smm/smihandler.c | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/src/cpu/x86/smm/smihandler.c b/src/cpu/x86/smm/smihandler.c index 83ebaf9..10f38f9 100644 --- a/src/cpu/x86/smm/smihandler.c +++ b/src/cpu/x86/smm/smihandler.c @@ -158,6 +158,7 @@ void smi_handler(u32 smm_revision) state_save.type = EM64T; state_save.em64t_state_save = (em64t_smm_state_save_area_t *) (smm_base + 0x7d00 - (node * 0x400)); + break; case 0x00030101: /* SandyBridge/IvyBridge */ state_save.type = EM64T101; state_save.em64t101_state_save =

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Patch merged into coreboot/master: d07e775 ELOG: Fix boot count increment for non-wake case
by gerrit＠coreboot.org 24 Jul '12

24 Jul '12

the following patch was just integrated into master: commit d07e775d85806855ce6acf5dda67682325e2952f Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Fri Jun 29 15:38:02 2012 -0700 ELOG: Fix boot count increment for non-wake case The count was only incrementing for a wake from S5 and it was not incrementing in the normal reboot case. Change-Id: I73bc6db6bd02e6c4677f7e44a5c098c6dcb51747 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> Build-Tested: build bot (Jenkins) at Tue Jul 24 22:40:17 2012, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Tue Jul 24 23:52:29 2012, giving +2 See http://review.coreboot.org/1328 for details. -gerrit

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Patch merged into coreboot/master: 2d3a5c5 Ivybridge: fix workaround and enable PAIR
by gerrit＠coreboot.org 24 Jul '12

24 Jul '12

the following patch was just integrated into master: commit 2d3a5c5dc15508b84883af8071870e743653a562 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Sat Jun 23 20:14:07 2012 -0700 Ivybridge: fix workaround and enable PAIR MCHBAR 0x5f10[7:0] should be set to 0x30 for ivybridge and 0x20 for sandybridge. Move this code to ramstage and set it per-chipset. Power Aware Interrupt Routing is supported in ivybridge, enable it and set fixed priority. Boot on ivybridge device and read MCHBAR 0x5f10: mmio_read8 0xfed15f10 0x30 And verify PAIR is enabled (bit4=1): mmio_read8 0xfed15418 0x24 Change-Id: If017d5ce2bd5ab5092c86f657434f2b645ee6613 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Build-Tested: build bot (Jenkins) at Tue Jul 24 12:22:49 2012, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Tue Jul 24 23:50:20 2012, giving +2 See http://review.coreboot.org/1303 for details. -gerrit

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Patch merged into coreboot/master: 538ad1f CPU: Set flex ratio to nominal TDP ratio in bootblock
by gerrit＠coreboot.org 24 Jul '12

24 Jul '12

the following patch was just integrated into master: commit 538ad1f6c7fcba133931d2d2673c0bf50b5f9aad Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Jul 9 09:58:35 2012 -0700 CPU: Set flex ratio to nominal TDP ratio in bootblock CPUs with configurable TDP will run the TSC at the max non-turbo ratio for the maximum TDP value, which can cause issues if another TDP is desired. To deal with this we set the flex ratio to the nominal TDP ratio early in the boot and then configure the Soft Reset Data registers so the PCH can tell the CPU what frequency to run at after a reset. This is done very early in the bootblock because it is necessary to reset the system after setting a flex ratio. The end result is that the TSC will now increment at the max non-turbo frequency for the nominal TDP. On some system with 1.8GHz CPU ensure that the kernel detects the CPU speed as ~1800mhz rather than ~2300mhz: > dmesg | grep "MHz processor" [ 0.004000] Detected 1795.801 MHz processor. Change-Id: I8436dced9199003b6423186a2b041e3f7b84ab8c Signed-off-by: Duncan Laurie <dlaurie(a)google.com> Build-Tested: build bot (Jenkins) at Tue Jul 24 23:10:06 2012, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Tue Jul 24 23:49:46 2012, giving +2 See http://review.coreboot.org/1329 for details. -gerrit

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Patch merged into coreboot/master: fe5a554 SMM: Fix state save map for sandybridge and TSEG
by gerrit＠coreboot.org 24 Jul '12

24 Jul '12

the following patch was just integrated into master: commit fe5a5548bd833818ec15d2fa6ad121794dd29d62 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Sat Jun 23 15:22:43 2012 -0700 SMM: Fix state save map for sandybridge and TSEG There are enough differences that it is worth defining the proper map for the sandybridge/ivybridge CPUs. The state save map was not being addressed properly for TSEG and needs to use the right offset instead of pointing in ASEG. To do this properly add a required southbridge export to return the TSEG base and use that where appropriate. Change-Id: Idad153ed6c07d2633cb3d53eddd433a3df490834 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Build-Tested: build bot (Jenkins) at Tue Jul 24 14:31:46 2012, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Tue Jul 24 23:49:28 2012, giving +2 See http://review.coreboot.org/1309 for details. -gerrit

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coreboot July 2012