coreboot July 2012

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Patch merged into coreboot/master: 857f723 SMM: Add option for SPI driver to be available in SMM
by gerrit＠coreboot.org 24 Jul '12

24 Jul '12

the following patch was just integrated into master: commit 857f723d69b14fa52a3ab3c1c515d2303e75c8cb Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Sat Jun 23 16:53:57 2012 -0700 SMM: Add option for SPI driver to be available in SMM - add Kconfig option for CONFIG_SPI_FLASH_SMM - compile subsystem and chip drivers for smm if enabled - change mdelay(1) to udelay(500) since mdelay is not defined in SMM and a 1ms delay is worth avoiding - make flash chip structure non-const so the probe function pointers can be relocated for use in TSEG - Make SMM PCI access possible in southbridge SPI code Change-Id: Icfcbbe8e4e56658769d46af0b5bf6c79a6432641 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Build-Tested: build bot (Jenkins) at Tue Jul 24 16:04:19 2012, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Tue Jul 24 23:44:40 2012, giving +2 See http://review.coreboot.org/1313 for details. -gerrit

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Patch merged into coreboot/master: c3c95f4 SMM: Add support for malloc in SMM if using TSEG
by gerrit＠coreboot.org 24 Jul '12

24 Jul '12

the following patch was just integrated into master: commit c3c95f4dd8516b21a68193072f21418517a8a06f Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Sat Jun 23 13:33:32 2012 -0700 SMM: Add support for malloc in SMM if using TSEG This is used by the SPI driver and ELOG. It requires SMM TSEG and a _heap/_eheap region defined in the linker script. The first time malloc is called in SMM the start and end pointers to the heap region will be relocated for the TSEG region. Enable SPI flash and ELOG in SMM and successfully allocate memory. The allocated addresses are verified to be sure they are within the TSEG heap region: smm.elf:00014000 B _eheap smm.elf:00010000 B _heap TSEG base is 0xad000000 Memory allocated in ELOG: ELOG: MEM @0xad018030 Change-Id: I5cca38e4888d597cbbfcd9983cd6a7ae3600c2a3 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Build-Tested: build bot (Jenkins) at Tue Jul 24 15:42:15 2012, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Tue Jul 24 23:44:19 2012, giving +2 See http://review.coreboot.org/1312 for details. -gerrit

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Patch merged into coreboot/master: 55e6e71 ELOG: Add support for flash based event log
by gerrit＠coreboot.org 24 Jul '12

24 Jul '12

the following patch was just integrated into master: commit 55e6e71a6cfa49480e2789aa74746c530d578e10 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Sat Jun 23 16:08:47 2012 -0700 ELOG: Add support for flash based event log This is based around the SMBIOS event log specification but expanded with OEM event types to support more specific and relevant system events. It requires flash storage and a minimum 4K block (or flash block size) that should be allocated in the FMAP. A copy of the event log is maintained in memory for convenience and speed and the in-memory copy is written to flash at specific points. The log is automatically shunk when it reaches a configurable full threshold in order to not get stuck with a full log that needs OS help to clear. ELOG implements the specification published here: http://code.google.com/p/firmware-event-log/wiki/FirmwareEventLogDesign And is similar to what we use in other firmware at Google. This implementation does not support double-buffered flash regions. This is done because speed is valued over the log reliability and it keeps the code simpler for the first version. This is a large commit and by itself it just provides a new driver that is made available to coreboot. Without additional patches it is not very useful, but the end result is an event log that will contain entries like this: 171 | 2012-06-23 16:02:55 | System boot | 285 172 | 2012-06-23 16:02:55 | EC Event | Power Button 173 | 2012-06-23 16:02:55 | SUS Power Fail 174 | 2012-06-23 16:02:55 | System Reset 175 | 2012-06-23 16:02:55 | ACPI Wake | S5 Change-Id: I985524c67f525c8a268eccbd856c1a4c2a426889 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Build-Tested: build bot (Jenkins) at Tue Jul 24 15:08:55 2012, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Tue Jul 24 23:43:38 2012, giving +2 See http://review.coreboot.org/1311 for details. -gerrit

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Patch merged into coreboot/master: 83a49f7 SMM: Add heap region and move C handler higher in region
by gerrit＠coreboot.org 24 Jul '12

24 Jul '12

the following patch was just integrated into master: commit 83a49f79e7339b011063e346b9f96765b2805160 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Sat Jun 23 15:09:34 2012 -0700 SMM: Add heap region and move C handler higher in region In order to support SPI and ELOG drivers the SMM region needs to be able to be larger than the previous allocation below 0x7400. Now that we have support for 4M TSEG we do not need to live in this region. This change adds a 16KB heap region abofe the save state area at TSEG+64KB and moves the C handler above this. The heap region is then available for malloc and the C handler can grow to support flash and event log features. While updating the memory map comment in assembly stub I also added a pause instruction to the cpu spin lock as this was added to the C code in latest upstream rebase. Dump sympbols from smm.elf binary to see the new regions: 00010000 B _heap 00014000 B _eheap 00014000 T _smm_c_handler_start 0001b240 T _smm_c_handler_end Change-Id: I45f0ab4df1fdef3b626f877094a58587476ac634 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Build-Tested: build bot (Jenkins) at Tue Jul 24 14:16:21 2012, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Tue Jul 24 23:40:54 2012, giving +2 See http://review.coreboot.org/1308 for details. -gerrit

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Patch merged into coreboot/master: 29b3a4c CPU: Update ivybridge PP1 current limit value
by gerrit＠coreboot.org 24 Jul '12

24 Jul '12

the following patch was just integrated into master: commit 29b3a4cf5ecef85ccfee7981427173f5b3b6edf2 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Jun 25 09:53:58 2012 -0700 CPU: Update ivybridge PP1 current limit value The BWG says ivybridge current limit for PP1 is 50A. Verify the PP1 current limit value on link device: > echo $(( ( $(rdmsr 0 0x602) & 0x1fff ) >> 3 )) 50 Change-Id: I946269d21ef605f2525fe03993f569d69128294b Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Build-Tested: build bot (Jenkins) at Tue Jul 24 13:30:21 2012, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Tue Jul 24 23:39:55 2012, giving +2 See http://review.coreboot.org/1305 for details. -gerrit

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Patch merged into coreboot/master: 364dbdd CPU: Add basic support for Nominal Configurable TDP
by gerrit＠coreboot.org 24 Jul '12

24 Jul '12

the following patch was just integrated into master: commit 364dbdd0177ff1fb5bbf398217fcae01ef296d1e Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Jun 25 09:51:59 2012 -0700 CPU: Add basic support for Nominal Configurable TDP Ivybridge B0+ CPUs are capable of supporting multiple TDP levels. This complicates the default case because now the registers that were reporting max non-turbo ratio are reporting that value for the highest possible TDP level. For now this change just forces everything to use the Nominal TDP values instead of the higher (or lower) levels. - When building P-state tables, determine the P[1] (max non turbo) ratio based on the Nominal ratio if available. - Set the turbo activation ratio to the Nominal max ratio. - Mirror the power level settings in new MCHBAR register after they are written, which happens after BIOS_RESET_CPL is set. - Set the current ratio to Nominal ratio at boot. 1) Verify that P-state table is generated properly with P[0]=1801MHz (ratio 0x1C) and P[1]=1800MHz (ratio 0x12) PSS: 1801MHz power 17000 control 0x1c00 status 0x1c00 PSS: 1800MHz power 17000 control 0x1200 status 0x1200 2) Verify power limits in MCHBAR match PKG_POWER_LIMIT: > rdmsr 0 0x610 0x800080aa00dc8088 > mmio_read32 0xfed159a4 0x000080aa > mmio_read32 0xfed159a0 0x00dc8088 3) Verify turbo activation ratio is set to nominal ratio: > rdmsr 0 0x64c 0x0000000000000012 4) Check that proper ratio was set at boot on one core only: > grep 'frequency set to' /sys/firmware/log model_x06ax: frequency set to 1800 model_x06ax: frequency set to 1800 model_x06ax: frequency set to 1800 model_x06ax: frequency set to 1800 Change-Id: I592e60a7740f31b140986a8269dca91b4adbb270 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Build-Tested: build bot (Jenkins) at Tue Jul 24 12:57:13 2012, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Tue Jul 24 23:39:44 2012, giving +2 See http://review.coreboot.org/1304 for details. -gerrit

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Patch merged into coreboot/master: f1a5f90 Rename cache_lbmem() to cache_ramstage()
by gerrit＠coreboot.org 24 Jul '12

24 Jul '12

the following patch was just integrated into master: commit f1a5f90801465fde0dd0e556767249a244378ab9 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Fri Jun 15 15:34:24 2012 -0700 Rename cache_lbmem() to cache_ramstage() ... and don't require it to specify a cache type. This function is only used on romcc boards, and should go away (because all boards should be switched to CAR) Change-Id: Ic32ca3be1afffc773c72c140e88b338d48a0c8ca Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Build-Tested: build bot (Jenkins) at Tue Jul 24 06:28:48 2012, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Tue Jul 24 23:29:40 2012, giving +2 See http://review.coreboot.org/1288 for details. -gerrit

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Patch merged into coreboot/master: 831243e Implement stack overflow checking for the BSP
by gerrit＠coreboot.org 24 Jul '12

24 Jul '12

the following patch was just integrated into master: commit 831243ee6459d48974caa0adc739eef740377122 Author: Ronald G. Minnich <rminnich(a)chromium.org> Date: Tue Jun 12 16:29:32 2012 -0700 Implement stack overflow checking for the BSP Previous patches implemented stack overflow checking for the APs. This patch builds on the BSP stack poisoning patch to implement stack overflow checking for the BSP, and also prints out maximum stack usage. It reveals that our 32K stack is ridiculously oversized, especially now that the lzma decoder doesn't use a giant 16K on-stack array. Break the stack checking out into a separate function, which we will later use for the APs. CPU0: stack from 00180000 to 00188000:Lowest stack address 00187ad8 To test failure, change the DEADBEEF stack poison value in c_start.S to something else. Then we should get an error like this: Stack overrun on BSP.Increase stack from current 32768 bytes CPU0: stack from 00180000 to 00188000:Lowest stack address 00180000 Separate the act of loading from the act of starting the payload. This allows us better error management and reporting of stack use. Now we see: CPU0: stack from 00180000 to 00188000:Lowest stack address 00187ad8 Tested for both success and failure on Link. At the same time, feel free to carefully check my manipulation of _estack. Change-Id: Ibb09738b15ec6a5510ac81e45dd82756bfa5aac2 Signed-off-by: Ronald G. Minnich <rminnich(a)chromium.org> Build-Tested: build bot (Jenkins) at Tue Jul 24 06:00:15 2012, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Tue Jul 24 23:29:11 2012, giving +2 See http://review.coreboot.org/1286 for details. -gerrit

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Patch merged into coreboot/master: 8d5a1dd Fix automatic ME detection in finalize
by gerrit＠coreboot.org 24 Jul '12

24 Jul '12

the following patch was just integrated into master: commit 8d5a1ddb04733d2094ea934bec72005497b46b94 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Wed Jun 13 16:31:50 2012 -0700 Fix automatic ME detection in finalize The ME needs to be talked to through the PCIe memory mapped config space. Change-Id: Ic2c5a572a126722a08a82d95df13d11507586c6b Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Build-Tested: build bot (Jenkins) at Tue Jul 24 05:11:52 2012, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Tue Jul 24 23:28:47 2012, giving +2 See http://review.coreboot.org/1284 for details. -gerrit

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Patch merged into coreboot/master: d58843d ChromeOS: Remove board specific acpi_get_vdat_info()
by gerrit＠coreboot.org 24 Jul '12

24 Jul '12

the following patch was just integrated into master: commit d58843d71be629039188456cb256c96de1cc5499 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Wed Jun 13 13:17:03 2012 -0700 ChromeOS: Remove board specific acpi_get_vdat_info() The function acpi_get_vdat_info() was moved to the ChromeOS vendor code, and is no longer required to be present for each board. Hence, remove it. Change-Id: I3dc8dbb6119ceffa057373bad7c0058ac0d40eb8 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Build-Tested: build bot (Jenkins) at Tue Jul 24 04:58:18 2012, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Tue Jul 24 23:17:56 2012, giving +2 See http://review.coreboot.org/1283 for details. -gerrit

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coreboot July 2012