coreboot July 2012

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Patch merged into coreboot/master: c1a45b1 Add support for HM70 and NM70 LPC bridge
by gerrit＠coreboot.org 24 Jul '12

24 Jul '12

the following patch was just integrated into master: commit c1a45b1d551beee81960b62025725f5436587c0c Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Thu Jun 21 16:05:21 2012 -0700 Add support for HM70 and NM70 LPC bridge This lets the SPI driver and the LPC driver know about HM70 and NM70. Change-Id: Id2f1e0e5586a2f7200b2d24785df3f2be890da98 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Tue Jul 24 12:26:25 2012, giving +2 See http://review.coreboot.org/1300 for details. -gerrit

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Patch merged into coreboot/master: d9c108e cs5536: add smbus support in ramstage
by gerrit＠coreboot.org 24 Jul '12

24 Jul '12

the following patch was just integrated into master: commit d9c108eef717bc1de1b86b8120267b4c3a00f06d Author: Christian Gmeiner <christian.gmeiner(a)gmail.com> Date: Fri Jul 20 10:21:29 2012 +0200 cs5536: add smbus support in ramstage With this patch it is possible to use the smbus in ramstage. The biggest part of the patch is a simple code split into a general part (smbus.h) and the concrete users (early_smbus.c and cs5536.c). After the switch from romstage to ramstage the smb base address has changed, but that is no problem as the new base address is stored in bar0 of the ISA bridge. It could also be read via msr, but via PCI it is simpler. I used the following patch as reference on how to readout the new base address: http://lists.laptop.org/pipermail/commits-kernel/2006-November/000178.html Change-Id: I9f86a1e474368c62f9ed3a95edfb3e63117aa156 Signed-off-by: Christian Gmeiner <christian.gmeiner(a)gmail.com> Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Tue Jul 24 12:18:28 2012, giving +2 See http://review.coreboot.org/1243 for details. -gerrit

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Patch merged into coreboot/master: f67f26f Add uartmem_init prototype.
by gerrit＠coreboot.org 24 Jul '12

24 Jul '12

the following patch was just integrated into master: commit f67f26faa266db1314055283d10791f024b1018a Author: Marc Jones <marc.jones(a)se-eng.com> Date: Wed Jun 13 20:48:36 2012 -0600 Add uartmem_init prototype. The oxpcie ramstage code calls uartmem_init after the PCI memory allocation, but hte function was static and didn't have a prototype. Change-Id: Iabc1a3d248aeaed29aaaa22504defac97c572326 Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Tue Jul 24 12:17:21 2012, giving +2 See http://review.coreboot.org/1285 for details. -gerrit

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Patch merged into coreboot/master: 0bcdec8 RTC: Add defines for standard clock offsets
by gerrit＠coreboot.org 24 Jul '12

24 Jul '12

the following patch was just integrated into master: commit 0bcdec8a18ce4061710fa212adabc4fdc63b2f4b Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Sat Jun 23 13:22:25 2012 -0700 RTC: Add defines for standard clock offsets ELOG reads from RTC to build timestamp structure, the resulting timestamp is decoded when printing events. Change-Id: If26552074f18de5095b967b875a0ac1d815a5b31 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Tue Jul 24 08:54:25 2012, giving +2 See http://review.coreboot.org/1302 for details. -gerrit

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Patch merged into coreboot/master: 8e599ec Print PCI ID of PCH during boot up
by gerrit＠coreboot.org 24 Jul '12

24 Jul '12

the following patch was just integrated into master: commit 8e599ec930891a7d93a0830b466f15a3d4d084fe Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Mon Jun 18 11:26:25 2012 -0700 Print PCI ID of PCH during boot up Right now, if we have an unknown PCH, coreboot will print something like this: PCH type: Unknown rev id 4 Instead, it should also print the PCI ID of the device, so we can add it to the list of known PCHes. Change-Id: Ib0b96e287c36d2895d1287b1734ca13d75e7985a Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Tue Jul 24 11:34:56 2012, giving +2 See http://review.coreboot.org/1287 for details. -gerrit

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New patch to review for coreboot: decc049 AMD parmer: Set correct azalia code verb table
by Zheng Bao 24 Jul '12

24 Jul '12

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1352 -gerrit commit decc049c17ecd3d06f3c6b31f69a5d462fee6a80 Author: zbao <fishbaozi(a)gmail.com> Date: Tue Jul 24 19:03:03 2012 +0800 AMD parmer: Set correct azalia code verb table Change-Id: I0b10080deb971cdefa4d3916fabd40f5a81b11f4 Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: zbao <fishbaozi(a)gmail.com> --- src/mainboard/amd/parmer/BiosCallOuts.c | 18 +++++++++--------- 1 files changed, 9 insertions(+), 9 deletions(-) diff --git a/src/mainboard/amd/parmer/BiosCallOuts.c b/src/mainboard/amd/parmer/BiosCallOuts.c index a4898ea..a5e274a 100644 --- a/src/mainboard/amd/parmer/BiosCallOuts.c +++ b/src/mainboard/amd/parmer/BiosCallOuts.c @@ -506,7 +506,7 @@ AGESA_STATUS BiosHookBeforeExitSelfRefresh (UINT32 Func, UINT32 Data, VOID *Conf /** * AMD Parmer Platform ALC272 Verb Table */ -const CODEC_ENTRY Pumori_Alc272_VerbTbl[] = { +const CODEC_ENTRY Parmer_Alc272_VerbTbl[] = { {0x11, 0x411111F0}, {0x12, 0x411111F0}, {0x13, 0x411111F0}, @@ -514,19 +514,19 @@ const CODEC_ENTRY Pumori_Alc272_VerbTbl[] = { {0x15, 0x411111F0}, {0x16, 0x411111F0}, {0x17, 0x411111F0}, - {0x18, 0x01a19830}, + {0x18, 0x01a19840}, {0x19, 0x411111F0}, - {0x1a, 0x01813020}, + {0x1a, 0x01813030}, {0x1b, 0x411111F0}, - {0x1d, 0x40151e05}, - {0x1e, 0x411111F0}, - {0x21, 0x01214010}, + {0x1d, 0x40130605}, + {0x1e, 0x01441120}, + {0x21, 0x01211010}, {0xff, 0xffffffff} }; -const CODEC_TBL_LIST PumoriCodecTableList[] = +const CODEC_TBL_LIST ParmerCodecTableList[] = { - {0x10ec0272, (CODEC_ENTRY*)&Pumori_Alc272_VerbTbl[0]}, + {0x10ec0272, (CODEC_ENTRY*)&Parmer_Alc272_VerbTbl[0]}, {(UINT32)0x0FFFFFFFF, (CODEC_ENTRY*)0x0FFFFFFFFUL} }; @@ -725,7 +725,7 @@ AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr) printk(BIOS_DEBUG, "Fch OEM config in INIT ENV "); /* Azalia Controller OEM Codec Table Pointer */ - FchParams_env->Azalia.AzaliaOemCodecTablePtr = (CODEC_TBL_LIST *)(&PumoriCodecTableList[0]); + FchParams_env->Azalia.AzaliaOemCodecTablePtr = (CODEC_TBL_LIST *)(&ParmerCodecTableList[0]); /* Azalia Controller Front Panel OEM Table Pointer */ /* Fan Control */

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New patch to review for coreboot: b4a40ce AMD family15tn: Add BIOS callback hook for getting VBIOS Image
by Zheng Bao 24 Jul '12

24 Jul '12

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1351 -gerrit commit b4a40ce9ff8b73f485723ba87553bbe63f260e77 Author: zbao <fishbaozi(a)gmail.com> Date: Tue Jul 24 17:59:43 2012 +0800 AMD family15tn: Add BIOS callback hook for getting VBIOS Image This is for GfxInitSview(GnbSview.c). It would create warning message if it could not get VBIOS image. Change-Id: I3b2726f612b4b7a237644a4b63b56efad52b7ab5 Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: zbao <fishbaozi(a)gmail.com> --- src/mainboard/amd/parmer/BiosCallOuts.c | 12 ++++++++++++ src/mainboard/amd/parmer/BiosCallOuts.h | 2 ++ 2 files changed, 14 insertions(+), 0 deletions(-) diff --git a/src/mainboard/amd/parmer/BiosCallOuts.c b/src/mainboard/amd/parmer/BiosCallOuts.c index a50e532..a4898ea 100644 --- a/src/mainboard/amd/parmer/BiosCallOuts.c +++ b/src/mainboard/amd/parmer/BiosCallOuts.c @@ -25,6 +25,7 @@ #include "OptionsIds.h" #include "heapManager.h" #include "FchPlatform.h" +#include "cbfs.h" STATIC CONST BIOS_CALLOUT_STRUCT BiosCallouts[] = { @@ -71,6 +72,9 @@ STATIC CONST BIOS_CALLOUT_STRUCT BiosCallouts[] = {AGESA_FCH_OEM_CALLOUT, Fch_Oem_config }, + {AGESA_GNB_GFX_GET_VBIOS_IMAGE, + BiosHookGfxGetVbiosImage + } }; AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr) @@ -733,3 +737,11 @@ AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr) return AGESA_SUCCESS; } + +AGESA_STATUS BiosHookGfxGetVbiosImage(UINT32 Func, UINT32 FchData, VOID *ConfigPrt) +{ + GFX_VBIOS_IMAGE_INFO *pVbiosImageInfo = (GFX_VBIOS_IMAGE_INFO *)ConfigPrt; + pVbiosImageInfo->ImagePtr = cbfs_find_file("pci"CONFIG_VGA_BIOS_ID".rom", CBFS_TYPE_OPTIONROM); + /* printk(BIOS_DEBUG, "IMGptr=%x\n", pVbiosImageInfo->ImagePtr); */ + return pVbiosImageInfo->ImagePtr == NULL ? AGESA_WARNING : AGESA_SUCCESS; +} diff --git a/src/mainboard/amd/parmer/BiosCallOuts.h b/src/mainboard/amd/parmer/BiosCallOuts.h index 1993c64..b7b9eaf 100644 --- a/src/mainboard/amd/parmer/BiosCallOuts.h +++ b/src/mainboard/amd/parmer/BiosCallOuts.h @@ -71,6 +71,8 @@ AGESA_STATUS BiosHookBeforeExitSelfRefresh (UINT32 Func, UINT32 Data, VOID *Conf AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr); /* FCH OEM Config*/ AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr); +/* Get Vbios Image */ +AGESA_STATUS BiosHookGfxGetVbiosImage(UINT32 Func, UINT32 FchData, VOID *ConfigPrt); #define SB_GPIO_REG02 2 #define SB_GPIO_REG09 9 #define SB_GPIO_REG10 10

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New patch to review for coreboot: 96e5b66 AMD Family 15tn: Set the default return value as AGESA_SUCCESS instead of TRUE
by Zheng Bao 24 Jul '12

24 Jul '12

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1350 -gerrit commit 96e5b66538e4ab0e38057212e25002070d77531e Author: zbao <fishbaozi(a)gmail.com> Date: Tue Jul 24 17:58:30 2012 +0800 AMD Family 15tn: Set the default return value as AGESA_SUCCESS instead of TRUE The default return value should be AGESA_SUCCESS, which is zero. If it was set as TRUE, the AGESA wrapper would think it was AGESA_UNSUPPORTED. That would make no sense. And it would produce ASSERT warning in AGESA wrapper. On my parmer board, with Engine sample processor, it can not create the correct DMI table. Routine initlate will return AGESS_ERROR. ------Serial message--------- ASSERTION FAILED: file 'src/mainboard/amd/parmer/agesawrapper.c', line 427 DmiTable:100123c3, AcpiPstatein: 10010126, AcpiSrat:0,AcpiSlit:0, Mce:100111ba, Cmc:1001127c,Alib:1001ccd4, AcpiIvrs:0 in agesawrapper_amdinitlate agesawrapper_amdinitlate failed: 5 ----------------------------- I believe the processor with acceptable name string will create the right DMI. Change-Id: Ie86955cf9affffc964a7c9f4a2c63077ef2030de Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: zbao <fishbaozi(a)gmail.com> --- .../amd/agesa/f15tn/Proc/CPU/Feature/cpuDmi.c | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuDmi.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuDmi.c index 23fd79f..2e7d905 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuDmi.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuDmi.c @@ -245,7 +245,7 @@ GetDmiInfoMain ( CPU_GET_MEM_INFO CpuGetMemInfo; MsrData = 0; - Flag = TRUE; + Flag = AGESA_SUCCESS; ProcData = NULL; MemInfo = NULL; DmiBufferPtr = *DmiTable; @@ -473,7 +473,7 @@ GetType4Type7Info ( PROC_FAMILY_TABLE *ProcData; CPU_LOGICAL_ID LogicalID; - Flag = TRUE; + Flag = AGESA_SUCCESS; DmiBufferPtr = (DMI_INFO *) ApExeParams->RelatedDataBlock; GetLogicalIdOfCurrentCore (&LogicalID, &ApExeParams->StdHeader);

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New patch to review for coreboot: dddbbed AMD Family15tn: Set the mask of MTRR to 0000FFFXX0000800
by Zheng Bao 24 Jul '12

24 Jul '12

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1349 -gerrit commit dddbbed1725ae8a781c3cecd39d3cf5e354d33ff Author: zbao <fishbaozi(a)gmail.com> Date: Tue Jul 24 17:56:48 2012 +0800 AMD Family15tn: Set the mask of MTRR to 0000FFFXX0000800 Remove the warning message from linux dmesg, mtrr: your BIOS has configured as incorrect mask, fixing it. Change-Id: I355509db12ab10c33b7c1c23e2c7c4783f30e67e Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: zbao <fishbaozi(a)gmail.com> --- src/mainboard/amd/dinar/agesawrapper.c | 2 +- src/mainboard/amd/parmer/agesawrapper.c | 2 +- src/mainboard/amd/torpedo/agesawrapper.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src/mainboard/amd/dinar/agesawrapper.c b/src/mainboard/amd/dinar/agesawrapper.c index 171deb8..a8ec917 100644 --- a/src/mainboard/amd/dinar/agesawrapper.c +++ b/src/mainboard/amd/dinar/agesawrapper.c @@ -270,7 +270,7 @@ agesawrapper_amdinitmmio ( /* Set ROM cache onto WP to decrease post time */ MsrReg = (0x0100000000 - CONFIG_ROM_SIZE) | 5; LibAmdMsrWrite (0x20E, &MsrReg, &StdHeader); - MsrReg = (0x1000000000 - CONFIG_ROM_SIZE) | 0x800; + MsrReg = (0x1000000000000ull - CONFIG_ROM_SIZE) | 0x800; LibAmdMsrWrite (0x20F, &MsrReg, &StdHeader); Status = AGESA_SUCCESS; diff --git a/src/mainboard/amd/parmer/agesawrapper.c b/src/mainboard/amd/parmer/agesawrapper.c index 6f44d46..b82c1c1 100644 --- a/src/mainboard/amd/parmer/agesawrapper.c +++ b/src/mainboard/amd/parmer/agesawrapper.c @@ -166,7 +166,7 @@ agesawrapper_amdinitmmio ( /* Set ROM cache onto WP to decrease post time */ MsrReg = (0x0100000000ull - CONFIG_ROM_SIZE) | 5ull; LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader); - MsrReg = (0x1000000000ull - CONFIG_ROM_SIZE) | 0x800ull; + MsrReg = (0x1000000000000ull - CONFIG_ROM_SIZE) | 0x800ull; LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader); Status = AGESA_SUCCESS; diff --git a/src/mainboard/amd/torpedo/agesawrapper.c b/src/mainboard/amd/torpedo/agesawrapper.c index 2995856..2bd1725 100644 --- a/src/mainboard/amd/torpedo/agesawrapper.c +++ b/src/mainboard/amd/torpedo/agesawrapper.c @@ -281,7 +281,7 @@ agesawrapper_amdinitmmio ( /* Set ROM cache onto WP to decrease post time */ MsrReg = (0x0100000000ull - CONFIG_ROM_SIZE) | 5ull; LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader); - MsrReg = (0x1000000000ull - CONFIG_ROM_SIZE) | 0x800ull; + MsrReg = (0x1000000000000ull - CONFIG_ROM_SIZE) | 0x800ull; LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader); /* Clear all pending SMI. On S3 clear power button enable so it wll not generate an SMI */

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Patch merged into coreboot/master: 3d24e00 ifdtool: Use perror for file write errors
by gerrit＠coreboot.org 24 Jul '12

24 Jul '12

the following patch was just integrated into master: commit 3d24e001d146e96eedd24fe54931116a6ec3070f Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Mon Jun 18 16:02:20 2012 -0700 ifdtool: Use perror for file write errors The "Error while writing." error messages did not output a new line which made the output look weird. With this patch, it should look like this: $ ifdtool -x 3rdparty/mainboard/google/parrot/descriptor.bin File 3rdparty/mainboard/google/parrot/descriptor.bin is 4096 bytes Found Flash Descriptor signature at 0x00000010 Flash Region 0 (Flash Descriptor): 00000000 - 00000fff Flash Region 1 (BIOS): 00200000 - 007fffff Error while writing: Bad address Flash Region 2 (Intel ME): 00001000 - 001fffff Error while writing: Bad address Flash Region 3 (GbE): 00fff000 - 00000fff (unused) Flash Region 4 (Platform Data): 00fff000 - 00000fff (unused) Change-Id: I784ff72d0673f167dbf0bd10921406abd685ce72 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Tue Jul 24 08:52:22 2012, giving +2 See http://review.coreboot.org/1299 for details. -gerrit

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coreboot July 2012