coreboot July 2012

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New patch to review for coreboot: 4c11d71 CTDP: Only do TDP down/nominal change from TNP0
by Stefan Reinauer 23 Jul '12

23 Jul '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1348 -gerrit commit 4c11d714adf9a09677a358bea44e86f753b3d45f Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Wed Jul 18 15:33:45 2012 -0700 CTDP: Only do TDP down/nominal change from TNP0 Otherwise there is a flurry of TDP changes with suspend/resume as the kernel powers devices off on suspend and brings them back online in resume. This also adds a mutex around the TDP operations since it is split across two methods and can't just rely on being Serialized. Change-Id: I7757d3ddad34ac985a9c8ce2fc202e2b2dcb2527 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- .../intel/sandybridge/acpi/hostbridge.asl | 30 ++++++++++++++++---- 1 files changed, 24 insertions(+), 6 deletions(-) diff --git a/src/northbridge/intel/sandybridge/acpi/hostbridge.asl b/src/northbridge/intel/sandybridge/acpi/hostbridge.asl index 8dd1de6..93db98d 100644 --- a/src/northbridge/intel/sandybridge/acpi/hostbridge.asl +++ b/src/northbridge/intel/sandybridge/acpi/hostbridge.asl @@ -101,6 +101,8 @@ Device (MCHC) TLUD, 32, } + Mutex (CTCM, 1) /* CTDP Switch Mutex (sync level 1) */ + Name (CTCC, 0) /* CTDP Current Selection */ Name (CTCN, 0) /* CTDP Nominal Select */ Name (CTCD, 1) /* CTDP Down Select */ Name (CTCU, 2) /* CTDP Up Select */ @@ -167,12 +169,16 @@ Device (MCHC) /* Set TDP Down */ Method (STND, 0, Serialized) { - Store ("Set TDP Down", Debug) - - If (LEqual (CTCD, CTCS)) { + If (Acquire (CTCM, 100)) { + Return (0) + } + If (LEqual (CTCD, CTCC)) { + Release (CTCM) Return (0) } + Store ("Set TDP Down", Debug) + /* Set CTC */ Store (CTCD, CTCS) @@ -189,18 +195,26 @@ Device (MCHC) /* Set PL1 */ Store (CTDD, PL1V) + /* Store the new TDP Down setting */ + Store (CTCD, CTCC) + + Release (CTCM) Return (1) } /* Set TDP Nominal from Down */ Method (STDN, 0, Serialized) { - Store ("Set TDP Nominal", Debug) - - If (LEqual (CTCN, CTCS)) { + If (Acquire (CTCM, 100)) { + Return (0) + } + If (LEqual (CTCN, CTCC)) { + Release (CTCM) Return (0) } + Store ("Set TDP Nominal", Debug) + /* Set PL1 */ Store (CTDN, PL1V) @@ -217,6 +231,10 @@ Device (MCHC) /* Set CTC */ Store (CTCN, CTCS) + /* Store the new TDP Nominal setting */ + Store (CTCN, CTCC) + + Release (CTCM) Return (1) } }

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New patch to review for coreboot: 99d48b5 SATA: Add option to configure gen3 transmitter
by Stefan Reinauer 23 Jul '12

23 Jul '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1347 -gerrit commit 99d48b5837f2ce45a6bdb918542815fa39b7de11 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Jul 16 16:16:31 2012 -0700 SATA: Add option to configure gen3 transmitter Unfortunately the drive strength values are very much board specific and different between mobile and desktop so we don't try to do any fancy detection here but let it be specified directly in the devicetree. Change-Id: I66674bff0de04ecd088fb09afad1cf801a374df2 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- src/southbridge/intel/bd82x6x/chip.h | 2 ++ src/southbridge/intel/bd82x6x/pch.h | 4 ++++ src/southbridge/intel/bd82x6x/sata.c | 9 +++++++++ 3 files changed, 15 insertions(+), 0 deletions(-) diff --git a/src/southbridge/intel/bd82x6x/chip.h b/src/southbridge/intel/bd82x6x/chip.h index 880244b..07a2af7 100644 --- a/src/southbridge/intel/bd82x6x/chip.h +++ b/src/southbridge/intel/bd82x6x/chip.h @@ -67,6 +67,8 @@ struct southbridge_intel_bd82x6x_config { uint32_t ide_legacy_combined; uint32_t sata_ahci; uint8_t sata_port_map; + uint32_t sata_port0_gen3_tx; + uint32_t sata_port1_gen3_tx; uint32_t gen1_dec; uint32_t gen2_dec; diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index 0a16308..beed63a 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -198,6 +198,10 @@ int smbus_read_byte(unsigned device, unsigned address); #define SATA_SP 0xd0 /* Scratchpad */ +/* SATA IOBP Registers */ +#define SATA_IOBP_SP0G3IR 0xea000151 +#define SATA_IOBP_SP1G3IR 0xea000051 + /* PCI Configuration Space (D31:F3): SMBus */ #define PCH_SMBUS_DEV PCI_DEV(0, 0x1f, 3) #define SMB_BASE 0x20 diff --git a/src/southbridge/intel/bd82x6x/sata.c b/src/southbridge/intel/bd82x6x/sata.c index c0eb232..2e41158 100644 --- a/src/southbridge/intel/bd82x6x/sata.c +++ b/src/southbridge/intel/bd82x6x/sata.c @@ -182,6 +182,15 @@ static void sata_init(struct device *dev) pci_write_config32(dev, 0x94, ((config->sata_port_map ^ 0x3f) << 24) | 0x183); } + + /* Set Gen3 Transmitter settings if needed */ + if (config->sata_port0_gen3_tx) + pch_iobp_update(SATA_IOBP_SP0G3IR, 0, + config->sata_port0_gen3_tx); + + if (config->sata_port1_gen3_tx) + pch_iobp_update(SATA_IOBP_SP1G3IR, 0, + config->sata_port1_gen3_tx); } static void sata_enable(device_t dev)

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New patch to review for coreboot: a8d447a ELOG: Fix reporting of developer/recovery modes
by Stefan Reinauer 23 Jul '12

23 Jul '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1346 -gerrit commit a8d447a324ef126fab9dce1d1f8268fb97d24b72 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Jul 16 12:47:45 2012 -0700 ELOG: Fix reporting of developer/recovery modes Recent changes in EC/Vboot/U-boot have completely broken the logging of developer and recovery modes. Recovery mode may not be in VBNV, so if that is zero and yet we are in recovery mode then assume it is there because the button/key was pressed. Since there may not be any actual developer mode switch we look if option rom is loaded and the system is not in recovery mode and consider that as developer mode. Change-Id: I70104877b24de477217e1ff5b3a019aef22343ec Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/include/elog.h | 1 + src/vendorcode/google/chromeos/gnvs.c | 9 ++++++--- 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/src/include/elog.h b/src/include/elog.h index 5a84c75..488549e 100644 --- a/src/include/elog.h +++ b/src/include/elog.h @@ -104,6 +104,7 @@ struct elog_event_data_wake { /* Chrome OS related events */ #define ELOG_TYPE_CROS_DEVELOPER_MODE 0xa0 #define ELOG_TYPE_CROS_RECOVERY_MODE 0xa1 +#define ELOG_CROS_RECOVERY_MODE_BUTTON 0x02 /* Management Engine Events */ #define ELOG_TYPE_MANAGEMENT_ENGINE 0xa2 diff --git a/src/vendorcode/google/chromeos/gnvs.c b/src/vendorcode/google/chromeos/gnvs.c index c8ccfe4..2e9975c 100644 --- a/src/vendorcode/google/chromeos/gnvs.c +++ b/src/vendorcode/google/chromeos/gnvs.c @@ -37,11 +37,14 @@ void chromeos_init_vboot(chromeos_acpi_t *chromeos) memcpy(vboot_data->mehh, me_hash_saved, sizeof(vboot_data->mehh)); #if CONFIG_ELOG - if (developer_mode_enabled()) + if (developer_mode_enabled() || + (vboot_wants_oprom() && !recovery_mode_enabled())) elog_add_event(ELOG_TYPE_CROS_DEVELOPER_MODE); - if (recovery_mode_enabled()) + if (recovery_mode_enabled()) { + int reason = get_recovery_mode_from_vbnv(); elog_add_event_byte(ELOG_TYPE_CROS_RECOVERY_MODE, - get_recovery_mode_from_vbnv()); + reason ? reason : ELOG_CROS_RECOVERY_MODE_BUTTON); + } #endif }

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New patch to review for coreboot: 369ab60 Log event for abnormal management engine status
by Stefan Reinauer 23 Jul '12

23 Jul '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1345 -gerrit commit 369ab60207dd36c3072ed86939143809bc7d6bae Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Fri Jul 13 10:11:54 2012 -0700 Log event for abnormal management engine status This will log if the ME is disabled or has an error. 1) disable ME via EC console: gpioset PCH_HDA_SDO 1 2) boot the device 3) read eventlog with "mosys eventlog list" 71 | 2012-07-13 10:10:55 | Management Engine | Disabled Change-Id: I9f6ee452d2aea76e6a5ea2cd50a50ff36245692a Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/include/elog.h | 3 +++ src/southbridge/intel/bd82x6x/me.c | 7 ++++--- src/southbridge/intel/bd82x6x/me_8.x.c | 7 ++++--- 3 files changed, 11 insertions(+), 6 deletions(-) diff --git a/src/include/elog.h b/src/include/elog.h index 7d89f45..5a84c75 100644 --- a/src/include/elog.h +++ b/src/include/elog.h @@ -105,6 +105,9 @@ struct elog_event_data_wake { #define ELOG_TYPE_CROS_DEVELOPER_MODE 0xa0 #define ELOG_TYPE_CROS_RECOVERY_MODE 0xa1 +/* Management Engine Events */ +#define ELOG_TYPE_MANAGEMENT_ENGINE 0xa2 + extern int elog_init(void); extern int elog_clear(void); extern void elog_add_event_raw(u8 event_type, void *data, u8 data_size); diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c index 464d0fd..3b7f342 100644 --- a/src/southbridge/intel/bd82x6x/me.c +++ b/src/southbridge/intel/bd82x6x/me.c @@ -35,6 +35,7 @@ #include <device/pci_def.h> #include <string.h> #include <delay.h> +#include <elog.h> #ifdef __SMM__ # include <arch/romcc_io.h> @@ -727,9 +728,9 @@ static void intel_me_init(device_t dev) case ME_RECOVERY_BIOS_PATH: case ME_DISABLE_BIOS_PATH: case ME_FIRMWARE_UPDATE_BIOS_PATH: - /* - * TODO(dlaurie) Force recovery mode if ME is unhappy? - */ +#if CONFIG_ELOG + elog_add_event_byte(ELOG_TYPE_MANAGEMENT_ENGINE, path); +#endif break; } } diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c index 74bf1ae..9461d61 100644 --- a/src/southbridge/intel/bd82x6x/me_8.x.c +++ b/src/southbridge/intel/bd82x6x/me_8.x.c @@ -35,6 +35,7 @@ #include <device/pci_def.h> #include <string.h> #include <delay.h> +#include <elog.h> #ifdef __SMM__ # include <arch/romcc_io.h> @@ -730,9 +731,9 @@ static void intel_me_init(device_t dev) case ME_RECOVERY_BIOS_PATH: case ME_DISABLE_BIOS_PATH: case ME_FIRMWARE_UPDATE_BIOS_PATH: - /* - * TODO(dlaurie) Force recovery mode if ME is unhappy? - */ +#if CONFIG_ELOG + elog_add_event_byte(ELOG_TYPE_MANAGEMENT_ENGINE, path); +#endif break; } }

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New patch to review for coreboot: 8b58555 ACPI: Add support for runtime config TDP down
by Stefan Reinauer 23 Jul '12

23 Jul '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1344 -gerrit commit 8b58555a396576d2ab85e0e724ca8cfd679bddfd Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Jul 16 12:27:42 2012 -0700 ACPI: Add support for runtime config TDP down The required power MSRs are mirrored in MCHBAR so it is possible to configure TDP at runtime via ASL. This adds the required fields and a set of methods to configure "TDP down" and "TDP nominal". It explicitly does not support "TDP up" at the moment. PSSS: method is added to assist in searching the _PSS table for the appropriate entry that corresponds to the desired max non-turbo ratio. STND: Set TDP Down from Nominal. This will limit CPU to the TDP down configuration by sequencing the required changes in the right order. STDN: Set TDP Nominal from Down. This will set the CPU back to nominal configuration by sequencing the required changes in the correct (reverse) order. This does not introduce any functional changes and must be paired with additional changes to be useful. The current configured TDP can be checked to see that the transition to/from a desired level is successful. > mmio_read8 0xfed15f50 0x00 # TDP-Nominal > mmio_read8 0xfed15f50 0x01 # TDP-Down Change-Id: I31a2f30cc9d134cc5eee980ae9288ae45e71c6e6 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- .../intel/sandybridge/acpi/hostbridge.asl | 119 +++++++++++++++++++- .../intel/sandybridge/acpi/sandybridge.asl | 2 +- 2 files changed, 119 insertions(+), 2 deletions(-) diff --git a/src/northbridge/intel/sandybridge/acpi/hostbridge.asl b/src/northbridge/intel/sandybridge/acpi/hostbridge.asl index 592c4c6..8dd1de6 100644 --- a/src/northbridge/intel/sandybridge/acpi/hostbridge.asl +++ b/src/northbridge/intel/sandybridge/acpi/hostbridge.asl @@ -101,8 +101,125 @@ Device (MCHC) TLUD, 32, } -} + Name (CTCN, 0) /* CTDP Nominal Select */ + Name (CTCD, 1) /* CTDP Down Select */ + Name (CTCU, 2) /* CTDP Up Select */ + + OperationRegion (MCHB, SystemMemory, DEFAULT_MCHBAR, 0x8000) + Field (MCHB, DWordAcc, Lock, Preserve) + { + Offset (0x5930), + CTDN, 15, /* CTDP Nominal PL1 */ + Offset (0x59a0), + PL1V, 15, /* Power Limit 1 Value */ + PL1E, 1, /* Power Limit 1 Enable */ + PL1C, 1, /* Power Limit 1 Clamp */ + PL1T, 7, /* Power Limit 1 Time */ + Offset (0x59a4), + PL2V, 15, /* Power Limit 2 Value */ + PL2E, 1, /* Power Limit 2 Enable */ + PL2C, 1, /* Power Limit 2 Clamp */ + PL2T, 7, /* Power Limit 2 Time */ + Offset (0x5f3c), + TARN, 8, /* CTDP Nominal Turbo Activation Ratio */ + Offset (0x5f40), + CTDD, 15, /* CTDP Down PL1 */ + , 1, + TARD, 8, /* CTDP Down Turbo Activation Ratio */ + Offset (0x5f48), + CTDU, 15, /* CTDP Up PL1 */ + , 1, + TARU, 8, /* CTDP Up Turbo Activation Ratio */ + Offset (0x5f50), + CTCS, 2, /* CTDP Select */ + Offset (0x5f54), + TARS, 8, /* Turbo Activation Ratio Select */ + } + + /* + * Search CPU0 _PSS looking for control=arg0 and then + * return previous P-state entry number for new _PPC + * + * Format of _PSS: + * Name (_PSS, Package () { + * Package (6) { freq, power, tlat, blat, control, status } + * } + */ + External (\_PR.CPU0._PSS) + Method (PSSS, 1, NotSerialized) + { + Store (One, Local0) /* Start at P1 */ + Store (SizeOf (\_PR.CPU0._PSS), Local1) + + While (LLess (Local0, Local1)) { + /* Store _PSS entry Control value to Local2 */ + ShiftRight (DeRefOf (Index (DeRefOf (Index + (\_PR.CPU0._PSS, Local0)), 4)), 8, Local2) + If (LEqual (Local2, Arg0)) { + Return (Subtract (Local0, 1)) + } + Increment (Local0) + } + + Return (0) + } + + /* Set TDP Down */ + Method (STND, 0, Serialized) + { + Store ("Set TDP Down", Debug) + + If (LEqual (CTCD, CTCS)) { + Return (0) + } + + /* Set CTC */ + Store (CTCD, CTCS) + + /* Set TAR */ + Store (TARD, TARS) + + /* Set PPC limit and notify OS */ + Store (PSSS (TARD), PPCM) + PPCN () + + /* Set PL2 to 1.25 * PL1 */ + Divide (Multiply (CTDD, 125), 100, Local0, PL2V) + /* Set PL1 */ + Store (CTDD, PL1V) + + Return (1) + } + + /* Set TDP Nominal from Down */ + Method (STDN, 0, Serialized) + { + Store ("Set TDP Nominal", Debug) + + If (LEqual (CTCN, CTCS)) { + Return (0) + } + + /* Set PL1 */ + Store (CTDN, PL1V) + + /* Set PL2 to 1.25 * PL1 */ + Divide (Multiply (CTDN, 125), 100, Local0, PL2V) + + /* Set PPC limit and notify OS */ + Store (PSSS (TARN), PPCM) + PPCN () + + /* Set TAR */ + Store (TARN, TARS) + + /* Set CTC */ + Store (CTCN, CTCS) + + Return (1) + } +} // Current Resource Settings diff --git a/src/northbridge/intel/sandybridge/acpi/sandybridge.asl b/src/northbridge/intel/sandybridge/acpi/sandybridge.asl index 64b5d8f..6708e27 100644 --- a/src/northbridge/intel/sandybridge/acpi/sandybridge.asl +++ b/src/northbridge/intel/sandybridge/acpi/sandybridge.asl @@ -19,8 +19,8 @@ * MA 02110-1301 USA */ -#include "hostbridge.asl" #include "../sandybridge.h" +#include "hostbridge.asl" /* PCI Device Resource Consumption */ Device (PDRC)

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New patch to review for coreboot: fa4e269 CPU: Add option to set TCC activation offset
by Stefan Reinauer 23 Jul '12

23 Jul '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1343 -gerrit commit fa4e269220a4c7d1ec5b03da23420bb7fc744646 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Jul 16 12:19:00 2012 -0700 CPU: Add option to set TCC activation offset The default TCC activation offset is 0, which means TCC activation starts at Tj_max. For devices with limited cooling ability it may be desired to lower TCC activation. This adds an option that can be declared in the devicetree to set the TCC activation to a non-zero value. Enable tcc_offset=15 in devicetree.cb and build/boot the BIOS and check that the value is set in the MSR: > and $(shr $(rdmsr 0 0x1a2) 24) 0xf 0xf Change-Id: I88f6857b40fd354f70fa9d5d9c1d8ceaea6dfcd1 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/cpu/intel/model_206ax/chip.h | 2 ++ src/cpu/intel/model_206ax/model_206ax.h | 1 + src/cpu/intel/model_206ax/model_206ax_init.c | 26 ++++++++++++++++++++++++++ 3 files changed, 29 insertions(+), 0 deletions(-) diff --git a/src/cpu/intel/model_206ax/chip.h b/src/cpu/intel/model_206ax/chip.h index 48e0c89..96b4c5d 100644 --- a/src/cpu/intel/model_206ax/chip.h +++ b/src/cpu/intel/model_206ax/chip.h @@ -34,4 +34,6 @@ struct cpu_intel_model_206ax_config { int c1_acpower; /* ACPI C1 on AC Power */ int c2_acpower; /* ACPI C2 on AC Power */ int c3_acpower; /* ACPI C3 on AC Power */ + + int tcc_offset; /* TCC Activation Offset */ }; diff --git a/src/cpu/intel/model_206ax/model_206ax.h b/src/cpu/intel/model_206ax/model_206ax.h index cdcc233..a7ca04a 100644 --- a/src/cpu/intel/model_206ax/model_206ax.h +++ b/src/cpu/intel/model_206ax/model_206ax.h @@ -34,6 +34,7 @@ #define FLEX_RATIO_EN (1 << 16) #define IA32_PLATFORM_DCA_CAP 0x1f8 #define IA32_MISC_ENABLE 0x1a0 +#define MSR_TEMPERATURE_TARGET 0x1a2 #define IA32_PERF_CTL 0x199 #define IA32_THERM_INTERRUPT 0x19b #define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0 diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c index 70a655a..2ad8012 100644 --- a/src/cpu/intel/model_206ax/model_206ax_init.c +++ b/src/cpu/intel/model_206ax/model_206ax_init.c @@ -37,6 +37,7 @@ #include <pc80/mc146818rtc.h> #include <usbdebug.h> #include "model_206ax.h" +#include "chip.h" /* * List of suported C-states in this processor @@ -312,6 +313,28 @@ static void configure_c_states(void) wrmsr(MSR_PP1_CURRENT_CONFIG, msr); } +static void configure_thermal_target(void) +{ + struct cpu_intel_model_206ax_config *conf; + device_t lapic; + msr_t msr; + + /* Find pointer to CPU configuration */ + lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC); + if (!lapic || !lapic->chip_info) + return; + conf = lapic->chip_info; + + /* Set TCC activaiton offset if supported */ + msr = rdmsr(MSR_PLATFORM_INFO); + if ((msr.lo & (1 << 30)) && conf->tcc_offset) { + msr = rdmsr(MSR_TEMPERATURE_TARGET); + msr.lo &= ~(0xf << 24); /* Bits 27:24 */ + msr.lo |= (conf->tcc_offset & 0xf) << 24; + wrmsr(MSR_TEMPERATURE_TARGET, msr); + } +} + static void configure_misc(void) { msr_t msr; @@ -454,6 +477,9 @@ static void model_206ax_init(device_t cpu) /* Configure Enhanced SpeedStep and Thermal Sensors */ configure_misc(); + /* Thermal throttle activation offset */ + configure_thermal_target(); + /* Enable Direct Cache Access */ configure_dca_cap();

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New patch to review for coreboot: b69c7c9 ACPI: Add a method to notify OS to re-read _PPC
by Stefan Reinauer 23 Jul '12

23 Jul '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1342 -gerrit commit b69c7c9ecf211352131ab37172cf7e9ebddc9af3 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Jul 16 12:14:49 2012 -0700 ACPI: Add a method to notify OS to re-read _PPC Split this behavior out from PNOT() so the OS can update _PPC limit without re-reading C-state tables. Change-Id: I81b9111a4866f6b9916f74ac57a3caefaa77c565 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/cpu/intel/model_206ax/acpi/cpu.asl | 27 +++++++++++++++++++-------- 1 files changed, 19 insertions(+), 8 deletions(-) diff --git a/src/cpu/intel/model_206ax/acpi/cpu.asl b/src/cpu/intel/model_206ax/acpi/cpu.asl index a9d5eeb..558a9d3 100644 --- a/src/cpu/intel/model_206ax/acpi/cpu.asl +++ b/src/cpu/intel/model_206ax/acpi/cpu.asl @@ -33,29 +33,40 @@ External (\_PR.CPU7, DeviceObj) Method (PNOT) { If (LGreaterEqual (\PCNT, 2)) { - Notify (\_PR.CPU0, 0x80) // _PPC Notify (\_PR.CPU0, 0x81) // _CST - Notify (\_PR.CPU1, 0x80) // _PPC Notify (\_PR.CPU1, 0x81) // _CST } If (LGreaterEqual (\PCNT, 4)) { - Notify (\_PR.CPU2, 0x80) // _PPC Notify (\_PR.CPU2, 0x81) // _CST - Notify (\_PR.CPU3, 0x80) // _PPC Notify (\_PR.CPU3, 0x81) // _CST } If (LGreaterEqual (\PCNT, 8)) { - Notify (\_PR.CPU4, 0x80) // _PPC Notify (\_PR.CPU4, 0x81) // _CST - Notify (\_PR.CPU5, 0x80) // _PPC Notify (\_PR.CPU5, 0x81) // _CST - Notify (\_PR.CPU6, 0x80) // _PPC Notify (\_PR.CPU6, 0x81) // _CST - Notify (\_PR.CPU7, 0x80) // _PPC Notify (\_PR.CPU7, 0x81) // _CST } } +/* Notify OS to re-read CPU _PPC limit, assuming ^2 CPU count */ +Method (PPCN) +{ + If (LGreaterEqual (\PCNT, 2)) { + Notify (\_PR.CPU0, 0x80) // _PPC + Notify (\_PR.CPU1, 0x80) // _PPC + } + If (LGreaterEqual (\PCNT, 4)) { + Notify (\_PR.CPU2, 0x80) // _PPC + Notify (\_PR.CPU3, 0x80) // _PPC + } + If (LGreaterEqual (\PCNT, 8)) { + Notify (\_PR.CPU4, 0x80) // _PPC + Notify (\_PR.CPU5, 0x80) // _PPC + Notify (\_PR.CPU6, 0x80) // _PPC + Notify (\_PR.CPU7, 0x80) // _PPC + } +} + /* Notify OS to re-read Throttle Limit tables, assuming ^2 CPU count */ Method (TNOT) {

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New patch to review for coreboot: 1eb5629 ACPI: Add function to write _PPC using NVS
by Stefan Reinauer 23 Jul '12

23 Jul '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1341 -gerrit commit 1eb5629e24af2b52941848d57ae251565b5dc207 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Jul 16 12:11:53 2012 -0700 ACPI: Add function to write _PPC using NVS The existing NVS variable for PPCM will be used to select a dynamic max P-state. By itself this does not change existing behavior because the NVS PPCM variable is initialized to zero. PPCM can be tested by building and booting a modified BIOS that sets gnvs->ppcm to a value greater than 1 and checking from the OS that the P-state is limited to that value. Change-Id: Ia7b3bbc6b84c1aa42349bb236abee5cc92486561 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/arch/x86/boot/acpigen.c | 26 ++++++++++++++++++++++++++ src/arch/x86/include/arch/acpigen.h | 1 + src/cpu/intel/model_206ax/acpi.c | 2 +- 3 files changed, 28 insertions(+), 1 deletions(-) diff --git a/src/arch/x86/boot/acpigen.c b/src/arch/x86/boot/acpigen.c index 71aa10c..47845a0 100644 --- a/src/arch/x86/boot/acpigen.c +++ b/src/arch/x86/boot/acpigen.c @@ -396,6 +396,32 @@ int acpigen_write_PPC(u8 nr) return len; } +/* generates a func with max supported P states */ +int acpigen_write_PPC_NVS(void) +{ +/* + Method (_PPC, 0, NotSerialized) + { + Return (PPCM) + } +*/ + int len; + /* method op */ + acpigen_emit_byte(0x14); + len = acpigen_write_len_f(); + len += acpigen_emit_namestring("_PPC"); + /* no fnarg */ + acpigen_emit_byte(0x00); + /* return */ + acpigen_emit_byte(0xa4); + /* arg */ + len += acpigen_emit_namestring("PPCM"); + /* add all single bytes */ + len += 3; + acpigen_patch_len(len - 1); + return len; +} + int acpigen_write_TPC(const char *gnvs_tpc_limit) { /* diff --git a/src/arch/x86/include/arch/acpigen.h b/src/arch/x86/include/arch/acpigen.h index aebf508..5297aff 100644 --- a/src/arch/x86/include/arch/acpigen.h +++ b/src/arch/x86/include/arch/acpigen.h @@ -42,6 +42,7 @@ int acpigen_write_name_qword(const char *name, uint64_t val); int acpigen_write_name_byte(const char *name, uint8_t val); int acpigen_write_scope(const char *name); int acpigen_write_PPC(u8 nr); +int acpigen_write_PPC_NVS(void); int acpigen_write_empty_PCT(void); int acpigen_write_empty_PTC(void); int acpigen_write_TPC(const char *gnvs_tpc_limit); diff --git a/src/cpu/intel/model_206ax/acpi.c b/src/cpu/intel/model_206ax/acpi.c index 9784c47..f66df51 100644 --- a/src/cpu/intel/model_206ax/acpi.c +++ b/src/cpu/intel/model_206ax/acpi.c @@ -251,7 +251,7 @@ static int generate_P_state_entries(int core, int cores_per_package) len = acpigen_write_empty_PCT(); /* Write _PPC with no limit on supported P-state */ - len += acpigen_write_PPC(0); + len += acpigen_write_PPC_NVS(); /* Write PSD indicating configured coordination type */ len += acpigen_write_PSD_package(core, cores_per_package, coord_type);

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New patch to review for coreboot: 13b6519 NVS: Add a temp sensor ID and an ACPI Method to set it
by Stefan Reinauer 23 Jul '12

23 Jul '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1340 -gerrit commit 13b65191bbcc97e2526c74cec03eba5f8e50d5fd Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Jul 16 11:28:52 2012 -0700 NVS: Add a temp sensor ID and an ACPI Method to set it This will allow various teams to select which thermal sensor will control the thermal zones. Also add a method to notify the thermalzones of a change so these threshold/sensor methods take effect. Needs a modified BIOS that uses the NVS TMPS value in the thermalzone to read a different sensor. Then, use a kernel driver that contains the following: /* Adjust temperature sensor id to 2 */ union acpi_object param; struct acpi_object_list input; param.type = ACPI_TYPE_INTEGER param.integer.value = 2 input.count = 1; input.pointer = &param; acpi_evaluate_object(NULL, "\\TMPU", &input, NULL); And ensure that the temperature sensor that is being monitored switches to ID 2. Change-Id: I6319741358ba31eb8a3dc635d64f3f0acf683386 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/southbridge/intel/bd82x6x/acpi/globalnvs.asl | 33 ++++++++++++++++++++- src/southbridge/intel/bd82x6x/nvs.h | 3 +- 2 files changed, 33 insertions(+), 3 deletions(-) diff --git a/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl b/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl index df450e3..7aeb32b 100644 --- a/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl +++ b/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl @@ -71,6 +71,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve) F4OF, 8, // 0x22 - FAN 4 OFF Threshold F4ON, 8, // 0x23 - FAN 4 ON Threshold F4PW, 8, // 0x24 - FAN 4 PWM value + TMPS, 8, // 0x25 - Temperature Sensor ID /* Processor Identification */ Offset (0x28), APIC, 8, // 0x28 - APIC Enabled by coreboot @@ -82,8 +83,8 @@ Field (GNVS, ByteAcc, NoLock, Preserve) /* Super I/O & CMOS config */ Offset (0x32), NATP, 8, // 0x32 - - S5U0, 8, // 0x32 - Enable USB0 in S5 - S5U1, 8, // 0x33 - Enable USB1 in S5 + S5U0, 8, // 0x33 - Enable USB0 in S5 + S5U1, 8, // 0x34 - Enable USB1 in S5 S3U0, 8, // 0x35 - Enable USB0 in S3 S3U1, 8, // 0x36 - Enable USB1 in S3 S33G, 8, // 0x37 - Enable 3G in S3 @@ -208,11 +209,28 @@ Method (S3GD) Store (Zero, \S33G) } +External (\_TZ.THRM) +External (\_TZ.SKIN) + +Method (TZUP) +{ + /* Update Primary Thermal Zone */ + If (CondRefOf (\_TZ.THRM, Local0)) { + Notify (\_TZ.THRM, 0x81) + } + + /* Update Secondary Thermal Zone */ + If (CondRefOf (\_TZ.SKIN, Local0)) { + Notify (\_TZ.SKIN, 0x81) + } +} + /* Update Fan 0 thresholds */ Method (F0UT, 2) { Store (Arg0, \F0OF) Store (Arg1, \F0ON) + TZUP () } /* Update Fan 1 thresholds */ @@ -220,6 +238,7 @@ Method (F1UT, 2) { Store (Arg0, \F1OF) Store (Arg1, \F1ON) + TZUP () } /* Update Fan 2 thresholds */ @@ -227,6 +246,7 @@ Method (F2UT, 2) { Store (Arg0, \F2OF) Store (Arg1, \F2ON) + TZUP () } /* Update Fan 3 thresholds */ @@ -234,6 +254,7 @@ Method (F3UT, 2) { Store (Arg0, \F3OF) Store (Arg1, \F3ON) + TZUP () } /* Update Fan 4 thresholds */ @@ -241,4 +262,12 @@ Method (F4UT, 2) { Store (Arg0, \F4OF) Store (Arg1, \F4ON) + TZUP () +} + +/* Update Temperature Sensor ID */ +Method (TMPU, 1) +{ + Store (Arg0, \TMPS) + TZUP () } diff --git a/src/southbridge/intel/bd82x6x/nvs.h b/src/southbridge/intel/bd82x6x/nvs.h index 3928804..2d94a64 100644 --- a/src/southbridge/intel/bd82x6x/nvs.h +++ b/src/southbridge/intel/bd82x6x/nvs.h @@ -55,7 +55,8 @@ typedef struct { u8 f4of; /* 0x22 - FAN 4 OFF Threshold */ u8 f4on; /* 0x23 - FAN 4 ON Threshold */ u8 f4pw; /* 0x24 - FAN 4 PWM value */ - u8 rsvd3[3]; + u8 tmps; /* 0x25 - Temperature Sensor ID */ + u8 rsvd3[2]; /* Processor Identification */ u8 apic; /* 0x28 - APIC enabled */ u8 mpen; /* 0x29 - MP capable/enabled */

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New patch to review for coreboot: 9fbef93 CougarPoint/PantherPoint: Add HM77 device ID to table
by Stefan Reinauer 23 Jul '12

23 Jul '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1339 -gerrit commit 9fbef93160491577bd30c3e835c6c8684b0d505f Author: Kimarie Hoot <kimarie.hoot(a)se-eng.com> Date: Sat Jul 14 08:26:08 2012 -0600 CougarPoint/PantherPoint: Add HM77 device ID to table Change-Id: Ic5aada423d8e61abbebfcaaf5cb02ede80dfae02 Signed-off-by: Kimarie Hoot <kimarie.hoot(a)se-eng.com> --- src/southbridge/intel/bd82x6x/lpc.c | 9 ++++----- 1 files changed, 4 insertions(+), 5 deletions(-) diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index bf51501..592f5de 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -692,16 +692,15 @@ static struct device_operations device_ops = { }; -/* IDs for LPC device of Intel 6 series Chipset and - * Intel C200 Series Chipset according to specification - * update from August 2011 +/* IDs for LPC device of Intel 6 Series Chipset, Intel 7 Series Chipset, and + * Intel C200 Series Chipset */ static const unsigned short pci_device_ids[] = { 0x1c46, 0x1c47, 0x1c49, 0x1c4a, 0x1c4b, 0x1c4c, 0x1c4d, 0x1c4e, 0x1c4f, 0x1c50, 0x1c52, 0x1c54, - 0x1e55, 0x1c56, 0x1c5c, 0x1e5d, - 0x1e5e, 0x1e5f, + 0x1e55, 0x1c56, 0x1e57, 0x1c5c, + 0x1e5d, 0x1e5e, 0x1e5f, 0 }; static const struct pci_driver pch_lpc __pci_driver = {

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coreboot July 2012