coreboot July 2012

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New patch to review for coreboot: c939c3d ME: Move ME v8 lockdown to finalize step
by Stefan Reinauer 23 Jul '12

23 Jul '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1338 -gerrit commit c939c3d9957c2a3c7a6619815374520226f7f78d Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Tue Jul 10 15:15:41 2012 -0700 ME: Move ME v8 lockdown to finalize step The ME device was being sent EOP and the PCI device hidden during coreboot so it was not available in the SMI finalize step. This also flips the PCI vendor/device dword around for the match. Boot on Panther Point with serial and SMI debugging enabled and see that ME EOP message is sent and the device is hidden at end of U-boot and before the kernel loads. Finalizing Coreboot SMI# #0 ME: mkhi_end_of_post ME: END OF POST message successful (0) PM1_STS: TMROF PM1_EN: 120 Starting kernel ... Change-Id: I230038c62c50db2a1c94078c0a2a67bdc232440e Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/southbridge/intel/bd82x6x/me.c | 4 +- src/southbridge/intel/bd82x6x/me_8.x.c | 63 ++++++++++++++++---------------- 2 files changed, 34 insertions(+), 33 deletions(-) diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c index 25b88b9..464d0fd 100644 --- a/src/southbridge/intel/bd82x6x/me.c +++ b/src/southbridge/intel/bd82x6x/me.c @@ -535,10 +535,10 @@ void intel_me_finalize_smm(void) { u32 did = pcie_read_config32(PCH_ME_DEV, PCI_VENDOR_ID); switch (did) { - case 0x80861c3a: + case 0x1c3a8086: intel_me7_finalize_smm(); break; - case 0x80861e3a: + case 0x1e3a8086: intel_me8_finalize_smm(); break; default: diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c index 32f660e..74bf1ae 100644 --- a/src/southbridge/intel/bd82x6x/me_8.x.c +++ b/src/southbridge/intel/bd82x6x/me_8.x.c @@ -356,33 +356,6 @@ static inline int mei_sendrecv(struct mei_header *mei, struct mkhi_header *mkhi, return 0; } -/* Send END OF POST message to the ME */ -static int mkhi_end_of_post(void) -{ - struct mkhi_header mkhi = { - .group_id = MKHI_GROUP_ID_GEN, - .command = MKHI_END_OF_POST, - }; - struct mei_header mei = { - .is_complete = 1, - .host_address = MEI_HOST_ADDRESS, - .client_address = MEI_ADDRESS_MKHI, - .length = sizeof(mkhi), - }; - - u32 eop_ack; - - /* Send request and wait for response */ - printk(BIOS_NOTICE, "ME: %s\n", __FUNCTION__); - if (mei_sendrecv(&mei, &mkhi, NULL, &eop_ack, sizeof(eop_ack)) < 0) { - printk(BIOS_ERR, "ME: END OF POST message failed\n"); - return -1; - } - - printk(BIOS_INFO, "ME: END OF POST message successful (%d)\n", eop_ack); - return 0; -} - #if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) && !defined(__SMM__) static inline void print_cap(const char *name, int state) { @@ -491,6 +464,33 @@ static int mkhi_global_reset(void) #ifdef __SMM__ +/* Send END OF POST message to the ME */ +static int mkhi_end_of_post(void) +{ + struct mkhi_header mkhi = { + .group_id = MKHI_GROUP_ID_GEN, + .command = MKHI_END_OF_POST, + }; + struct mei_header mei = { + .is_complete = 1, + .host_address = MEI_HOST_ADDRESS, + .client_address = MEI_ADDRESS_MKHI, + .length = sizeof(mkhi), + }; + + u32 eop_ack; + + /* Send request and wait for response */ + printk(BIOS_NOTICE, "ME: %s\n", __FUNCTION__); + if (mei_sendrecv(&mei, &mkhi, NULL, &eop_ack, sizeof(eop_ack)) < 0) { + printk(BIOS_ERR, "ME: END OF POST message failed\n"); + return -1; + } + + printk(BIOS_INFO, "ME: END OF POST message successful (%d)\n", eop_ack); + return 0; +} + void intel_me8_finalize_smm(void) { struct me_hfs hfs; @@ -719,10 +719,11 @@ static void intel_me_init(device_t dev) me_print_fw_version(&mbp_data.fw_version_name); me_print_fwcaps(&mbp_data.fw_caps_sku); #endif - /* Tell ME that BIOS is done */ - mkhi_end_of_post(); - /* Hide the virtual PCI device */ - intel_me_hide(dev); + + /* + * Leave the ME unlocked in this path. + * It will be locked via SMI command later. + */ break; case ME_ERROR_BIOS_PATH:

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New patch to review for coreboot: 035c331 Reserve bd82x6x LPC decode ranges in the resource allocator
by Stefan Reinauer 23 Jul '12

23 Jul '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1337 -gerrit commit 035c331b3e4a344f7c04b4074e958544bc46ef9a Author: Marc Jones <marc.jones(a)se-eng.com> Date: Fri Jul 13 14:14:34 2012 -0600 Reserve bd82x6x LPC decode ranges in the resource allocator The LPC bus normally allocates the range for legacy devices, 0-0x1000. Some devices on LPC are above that range and need to be accounted for. Check the decode range settings for addresses > 0x1000 and reserve them. Change-Id: Idba800d7cee3185296f29dd237ba306f3de8de55 Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> --- src/southbridge/intel/bd82x6x/lpc.c | 39 +++++++++++++++++++++++++++++++++- 1 files changed, 37 insertions(+), 2 deletions(-) diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index fcc99f4..bf51501 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -593,18 +593,20 @@ static void lpc_init(struct device *dev) static void pch_lpc_read_resources(device_t dev) { struct resource *res; + config_t *config = dev->chip_info; + u8 io_index = 0; /* Get the normal PCI resources of this device. */ pci_dev_read_resources(dev); /* Add an extra subtractive resource for both memory and I/O. */ - res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); + res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0)); res->base = 0; res->size = 0x1000; res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; - res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); + res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0)); res->base = 0xff800000; res->size = 0x00800000; /* 8 MB for flash */ res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | @@ -614,6 +616,39 @@ static void pch_lpc_read_resources(device_t dev) res->base = IO_APIC_ADDR; res->size = 0x00001000; res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + + /* Set PCH IO decode ranges if required.*/ + if ((config->gen1_dec & 0xFFFC) > 0x1000) { + res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0)); + res->base = config->gen1_dec & 0xFFFC; + res->size = (config->gen1_dec >> 16) & 0xFC; + res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | + IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + } + + if ((config->gen2_dec & 0xFFFC) > 0x1000) { + res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0)); + res->base = config->gen2_dec & 0xFFFC; + res->size = (config->gen2_dec >> 16) & 0xFC; + res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | + IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + } + + if ((config->gen3_dec & 0xFFFC) > 0x1000) { + res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0)); + res->base = config->gen3_dec & 0xFFFC; + res->size = (config->gen3_dec >> 16) & 0xFC; + res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | + IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + } + + if ((config->gen4_dec & 0xFFFC) > 0x1000) { + res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0)); + res->base = config->gen4_dec & 0xFFFC; + res->size = (config->gen4_dec >> 16) & 0xFC; + res->flags = IORESOURCE_IO| IORESOURCE_SUBTRACTIVE | + IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + } } static void pch_lpc_enable_resources(device_t dev)

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New patch to review for coreboot: d95d46c Fix comment to reference IvyBridge, too
by Stefan Reinauer 23 Jul '12

23 Jul '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1336 -gerrit commit d95d46c972a6a150e11cfc61bde2830545ad61d3 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Tue Jul 10 17:16:10 2012 -0700 Fix comment to reference IvyBridge, too On both SandyBridge and IvyBridge BCLK is fixed at 100MHz. Have the comment reflect that. Change-Id: Ia81c3501dc3e68cf3143c3bc864dfbf88901f9f9 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/cpu/intel/model_206ax/model_206ax.h | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/src/cpu/intel/model_206ax/model_206ax.h b/src/cpu/intel/model_206ax/model_206ax.h index 8259d89..cdcc233 100644 --- a/src/cpu/intel/model_206ax/model_206ax.h +++ b/src/cpu/intel/model_206ax/model_206ax.h @@ -22,7 +22,7 @@ #ifndef _CPU_INTEL_MODEL_206AX_H #define _CPU_INTEL_MODEL_206AX_H -/* SandyBridge bus clock is fixed at 100MHz */ +/* SandyBridge/IvyBridge bus clock is fixed at 100MHz */ #define SANDYBRIDGE_BCLK 100 #define IA32_FEATURE_CONTROL 0x3a

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New patch to review for coreboot: 8de89aa Drop CONFIG_CPU_MODEL_NAME and fix CPU name displayed in logs
by Stefan Reinauer 23 Jul '12

23 Jul '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1335 -gerrit commit 8de89aa8148c36dd405839458e59886b8973e5d6 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Tue Jul 10 17:13:04 2012 -0700 Drop CONFIG_CPU_MODEL_NAME and fix CPU name displayed in logs On SandyBridge systems configured to work with Panther Point the CPU would wrongly be described as IvyBridge. Fix this issue and drop an unneeded Kconfig variable at the same time. Change-Id: I501a4fa00613e589cd315cfee61b2f9561dfcb4d Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/cpu/intel/model_206ax/Kconfig | 12 ------------ src/cpu/intel/model_206ax/acpi.c | 2 +- 2 files changed, 1 insertions(+), 13 deletions(-) diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig index 071683e..effcdd1 100644 --- a/src/cpu/intel/model_206ax/Kconfig +++ b/src/cpu/intel/model_206ax/Kconfig @@ -26,15 +26,3 @@ config MICROCODE_INCLUDE_PATH string default "src/cpu/intel/model_206ax" endif - -if CPU_INTEL_MODEL_206AX - config CPU_MODEL_NAME - string - default "Intel SandyBridge CPU" -endif - -if CPU_INTEL_MODEL_306AX - config CPU_MODEL_NAME - string - default "Intel IvyBridge CPU" -endif diff --git a/src/cpu/intel/model_206ax/acpi.c b/src/cpu/intel/model_206ax/acpi.c index 7b49555..9784c47 100644 --- a/src/cpu/intel/model_206ax/acpi.c +++ b/src/cpu/intel/model_206ax/acpi.c @@ -362,5 +362,5 @@ void generate_cpu_entries(void) } struct chip_operations cpu_intel_model_206ax_ops = { - CHIP_NAME(CONFIG_CPU_MODEL_NAME) + CHIP_NAME("Intel SandyBridge/IvyBridge CPU") };

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New patch to review for coreboot: 7b18455 Fix date output in Microcode update
by Stefan Reinauer 23 Jul '12

23 Jul '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1334 -gerrit commit 7b18455d9f55f9248ddf8fb60fb051cc1f214522 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Tue Jul 10 17:06:22 2012 -0700 Fix date output in Microcode update Date and time are mixed up: microcode: updated to revision 0x12 date=2012-12-04 should be microcode: updated to revision 0x12 date=2012-04-12 Change-Id: I85f9100f31d88bb831bef07131f361c92c7ef34e Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/cpu/intel/microcode/microcode.c | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/cpu/intel/microcode/microcode.c b/src/cpu/intel/microcode/microcode.c index af83faf..e84bad9 100644 --- a/src/cpu/intel/microcode/microcode.c +++ b/src/cpu/intel/microcode/microcode.c @@ -127,8 +127,8 @@ void intel_update_microcode(const void *microcode_updates) #if !defined(__ROMCC__) printk(BIOS_DEBUG, "microcode: updated to revision " "0x%x date=%04x-%02x-%02x\n", new_rev, - m->date & 0xffff, (m->date >> 16) & 0xff, - (m->date >> 24) & 0xff); + m->date & 0xffff, (m->date >> 24) & 0xff, + (m->date >> 16) & 0xff); #endif break; }

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New patch to review for coreboot: f7bf0c3 Include SandyBridge Microcode when IvyBridge is enabled
by Stefan Reinauer 23 Jul '12

23 Jul '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1333 -gerrit commit f7bf0c3ba600c4ffb9a11bea6ab7b049cfe732c7 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Mon Jul 23 16:12:52 2012 -0700 Include SandyBridge Microcode when IvyBridge is enabled .. in case the system has pluggable CPUs or might come in different SKUs. Change-Id: I7a7cd95b4de5dd78370355f448688e8d000434c1 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/cpu/intel/model_206ax/microcode_blob.h | 6 ------ 1 files changed, 0 insertions(+), 6 deletions(-) diff --git a/src/cpu/intel/model_206ax/microcode_blob.h b/src/cpu/intel/model_206ax/microcode_blob.h index d055b2e..66e893b 100644 --- a/src/cpu/intel/model_206ax/microcode_blob.h +++ b/src/cpu/intel/model_206ax/microcode_blob.h @@ -17,13 +17,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ - -#if CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE #include "microcode-m12206a7_00000025.h" -#elif CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE -#else -#error "Which microcode to use?" -#endif /* Dummy terminator */ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,

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New patch to review for coreboot: 369708b Enable Microcode in CBFS for all SandyBridge/IvyBridge systems
by Stefan Reinauer 23 Jul '12

23 Jul '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1332 -gerrit commit 369708b9bce3a905f26dbb41d6b4f38dd29b25d0 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Tue Jul 10 17:02:21 2012 -0700 Enable Microcode in CBFS for all SandyBridge/IvyBridge systems Change-Id: Idee4facc18e0be60906d2a2f0e99bd39de8d7247 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/cpu/Kconfig | 5 +---- src/cpu/intel/model_206ax/Kconfig | 4 +--- src/cpu/intel/model_206ax/bootblock.c | 10 ---------- src/cpu/intel/model_206ax/model_206ax_init.c | 10 ---------- 4 files changed, 2 insertions(+), 27 deletions(-) diff --git a/src/cpu/Kconfig b/src/cpu/Kconfig index f37bbf6..baf686e 100644 --- a/src/cpu/Kconfig +++ b/src/cpu/Kconfig @@ -62,13 +62,10 @@ config SSE2 streaming SIMD instructions. Some parts of coreboot can be built with more efficient code if SSE2 instructions are available. -if CPU_INTEL_MODEL_206AX || CPU_INTEL_MODEL_306AX - config MICROCODE_IN_CBFS bool "Look for microcode in CBFS" + default n help Load microcode updates from CBFS instead of compiling them in. -endif - endif # ARCH_X86 diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig index 1d4ff02..071683e 100644 --- a/src/cpu/intel/model_206ax/Kconfig +++ b/src/cpu/intel/model_206ax/Kconfig @@ -12,6 +12,7 @@ config CPU_SPECIFIC_OPTIONS select SSE2 select UDELAY_LAPIC select SMM_TSEG + select MICROCODE_IN_CBFS config BOOTBLOCK_CPU_INIT string @@ -21,14 +22,11 @@ config SMM_TSEG_SIZE hex default 0x800000 -if MICROCODE_IN_CBFS config MICROCODE_INCLUDE_PATH string default "src/cpu/intel/model_206ax" endif -endif - if CPU_INTEL_MODEL_206AX config CPU_MODEL_NAME string diff --git a/src/cpu/intel/model_206ax/bootblock.c b/src/cpu/intel/model_206ax/bootblock.c index dbc3591..02958bb 100644 --- a/src/cpu/intel/model_206ax/bootblock.c +++ b/src/cpu/intel/model_206ax/bootblock.c @@ -25,12 +25,6 @@ #include <arch/io.h> #include <arch/romcc_io.h> -#if !CONFIG_MICROCODE_IN_CBFS -static const uint32_t microcode_updates[] = { - #include "microcode_blob.h" -}; -#endif - #include <cpu/intel/microcode/microcode.c> #include "model_206ax.h" @@ -125,9 +119,5 @@ static void bootblock_cpu_init(void) /* Set flex ratio and reset if needed */ set_flex_ratio_to_tdp_nominal(); enable_rom_caching(); -#if CONFIG_MICROCODE_IN_CBFS intel_update_microcode_from_cbfs(); -#else - intel_update_microcode(microcode_updates); -#endif } diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c index 08757d1..70a655a 100644 --- a/src/cpu/intel/model_206ax/model_206ax_init.c +++ b/src/cpu/intel/model_206ax/model_206ax_init.c @@ -115,12 +115,6 @@ static acpi_cstate_t cstate_map[] = { { 0 } }; -#if !CONFIG_MICROCODE_IN_CBFS -static const uint32_t microcode_updates[] = { - #include "microcode_blob.h" -}; -#endif - /* Convert time in seconds to POWER_LIMIT_1_TIME MSR value */ static const u8 power_limit_time_sec_to_msr[] = { [0] = 0x00, @@ -421,11 +415,7 @@ static void model_206ax_init(device_t cpu) /* Turn on caching if we haven't already */ x86_enable_cache(); -#if CONFIG_MICROCODE_IN_CBFS intel_update_microcode_from_cbfs(); -#else - intel_update_microcode(microcode_updates); -#endif /* Clear out pending MCEs */ configure_mca();

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New patch to review for coreboot: f207abb bd82x6x: Drop unneeded pci_dev_t
by Stefan Reinauer 23 Jul '12

23 Jul '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1331 -gerrit commit f207abb3c727ebb80f0398d3a44e5defe93fed99 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Tue Jul 10 13:26:59 2012 -0700 bd82x6x: Drop unneeded pci_dev_t This was introduced when porting the SPI driver over from u-boot but it is not needed. Hence drop the extra typedef and use device_t instead. Change-Id: I3ab797a8e482d1c9aa1d004e488e99aeaffcdd8b Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/southbridge/intel/bd82x6x/spi.c | 4 +--- 1 files changed, 1 insertions(+), 3 deletions(-) diff --git a/src/southbridge/intel/bd82x6x/spi.c b/src/southbridge/intel/bd82x6x/spi.c index 6b39571..5903fd8 100644 --- a/src/southbridge/intel/bd82x6x/spi.c +++ b/src/southbridge/intel/bd82x6x/spi.c @@ -36,7 +36,6 @@ #ifdef __SMM__ #include <arch/romcc_io.h> #include <northbridge/intel/sandybridge/pcie_config.c> -typedef device_t pci_dev_t; #define pci_read_config_byte(dev, reg, targ)\ *(targ) = pcie_read_config8(dev, reg) #define pci_read_config_word(dev, reg, targ)\ @@ -52,7 +51,6 @@ typedef device_t pci_dev_t; #else /* !__SMM__ */ #include <device/device.h> #include <device/pci.h> -typedef device_t pci_dev_t; #define pci_read_config_byte(dev, reg, targ)\ *(targ) = pci_read_config8(dev, reg) #define pci_read_config_word(dev, reg, targ)\ @@ -331,7 +329,7 @@ void spi_init(void) uint8_t *rcrb; /* Root Complex Register Block */ uint32_t rcba; /* Root Complex Base Address */ uint8_t bios_cntl; - pci_dev_t dev; + device_t dev; uint32_t ids; uint16_t vendor_id, device_id;

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New patch to review for coreboot: 93f232d Fix LAPIC timer on Ivy Bridge systems
by Stefan Reinauer 23 Jul '12

23 Jul '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1330 -gerrit commit 93f232dad8f8e544153c14b6d57cb66395adb960 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Tue Jul 10 13:24:29 2012 -0700 Fix LAPIC timer on Ivy Bridge systems The LAPIC timer is running at BCLK (100MHz) on Sandy Bridge and Ivy Bridge systems. However, the current timer code assumed that the clock would run at 200MHz instead. This made all delays twice as long as needed. Change-Id: I41b1186daee11cfd9a25b3a9d5ebdeeb271293c7 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/cpu/x86/lapic/apic_timer.c | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/src/cpu/x86/lapic/apic_timer.c b/src/cpu/x86/lapic/apic_timer.c index 1fd0c60..562c79c 100644 --- a/src/cpu/x86/lapic/apic_timer.c +++ b/src/cpu/x86/lapic/apic_timer.c @@ -50,6 +50,7 @@ static int set_timer_fsb(void) timer_fsb = core2_fsb[rdmsr(0xcd).lo & 7]; break; case 0x2a: /* SandyBridge BCLK fixed at 100MHz*/ + case 0x3a: /* IvyBridge BCLK fixed at 100MHz*/ timer_fsb = 100; break; default:

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New patch to review for coreboot: 538ad1f CPU: Set flex ratio to nominal TDP ratio in bootblock
by Stefan Reinauer 23 Jul '12

23 Jul '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1329 -gerrit commit 538ad1f6c7fcba133931d2d2673c0bf50b5f9aad Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Jul 9 09:58:35 2012 -0700 CPU: Set flex ratio to nominal TDP ratio in bootblock CPUs with configurable TDP will run the TSC at the max non-turbo ratio for the maximum TDP value, which can cause issues if another TDP is desired. To deal with this we set the flex ratio to the nominal TDP ratio early in the boot and then configure the Soft Reset Data registers so the PCH can tell the CPU what frequency to run at after a reset. This is done very early in the bootblock because it is necessary to reset the system after setting a flex ratio. The end result is that the TSC will now increment at the max non-turbo frequency for the nominal TDP. On some system with 1.8GHz CPU ensure that the kernel detects the CPU speed as ~1800mhz rather than ~2300mhz: > dmesg | grep "MHz processor" [ 0.004000] Detected 1795.801 MHz processor. Change-Id: I8436dced9199003b6423186a2b041e3f7b84ab8c Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- src/cpu/intel/model_206ax/bootblock.c | 62 +++++++++++++++++++++++++++++++ src/cpu/intel/model_206ax/model_206ax.h | 5 ++ src/southbridge/intel/bd82x6x/pch.h | 2 + 3 files changed, 69 insertions(+), 0 deletions(-) diff --git a/src/cpu/intel/model_206ax/bootblock.c b/src/cpu/intel/model_206ax/bootblock.c index 4061bb7..dbc3591 100644 --- a/src/cpu/intel/model_206ax/bootblock.c +++ b/src/cpu/intel/model_206ax/bootblock.c @@ -22,6 +22,8 @@ #include <cpu/x86/cache.h> #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> +#include <arch/io.h> +#include <arch/romcc_io.h> #if !CONFIG_MICROCODE_IN_CBFS static const uint32_t microcode_updates[] = { @@ -30,6 +32,14 @@ static const uint32_t microcode_updates[] = { #endif #include <cpu/intel/microcode/microcode.c> +#include "model_206ax.h" + +#if CONFIG_SOUTHBRIDGE_INTEL_BD82X6X || CONFIG_SOUTHBRIDGE_INTEL_C216 +/* Needed for RCBA access to set Soft Reset Data register */ +#include <southbridge/intel/bd82x6x/pch.h> +#else +#error "CPU must be paired with Intel BD82X6X or C216 southbridge" +#endif static void set_var_mtrr( unsigned reg, unsigned base, unsigned size, unsigned type) @@ -60,8 +70,60 @@ static void enable_rom_caching(void) wrmsr(MTRRdefType_MSR, msr); } +static void set_flex_ratio_to_tdp_nominal(void) +{ + msr_t flex_ratio, msr; + u32 soft_reset; + u8 nominal_ratio; + + /* Minimum CPU revision for configurable TDP support */ + if (cpuid_eax(1) < IVB_CONFIG_TDP_MIN_CPUID) + return; + + /* Check for Flex Ratio support */ + flex_ratio = rdmsr(MSR_FLEX_RATIO); + if (!(flex_ratio.lo & FLEX_RATIO_EN)) + return; + + /* Check for >0 configurable TDPs */ + msr = rdmsr(MSR_PLATFORM_INFO); + if (((msr.hi >> 1) & 3) == 0) + return; + + /* Use nominal TDP ratio for flex ratio */ + msr = rdmsr(MSR_CONFIG_TDP_NOMINAL); + nominal_ratio = msr.lo & 0xff; + + /* See if flex ratio is already set to nominal TDP ratio */ + if (((flex_ratio.lo >> 8) & 0xff) == nominal_ratio) + return; + + /* Set flex ratio to nominal TDP ratio */ + flex_ratio.lo &= ~0xff00; + flex_ratio.lo |= nominal_ratio << 8; + flex_ratio.lo |= FLEX_RATIO_LOCK; + wrmsr(MSR_FLEX_RATIO, flex_ratio); + + /* Set flex ratio in soft reset data register bits 11:6. + * RCBA region is enabled in southbridge bootblock */ + soft_reset = RCBA32(SOFT_RESET_DATA); + soft_reset &= ~(0x3f << 6); + soft_reset |= (nominal_ratio & 0x3f) << 6; + RCBA32(SOFT_RESET_DATA) = soft_reset; + + /* Set soft reset control to use register value */ + RCBA32_OR(SOFT_RESET_CTRL, 1); + + /* Issue warm reset, will be "CPU only" due to soft reset data */ + outb(0x0, 0xcf9); + outb(0x6, 0xcf9); + asm("hlt"); +} + static void bootblock_cpu_init(void) { + /* Set flex ratio and reset if needed */ + set_flex_ratio_to_tdp_nominal(); enable_rom_caching(); #if CONFIG_MICROCODE_IN_CBFS intel_update_microcode_from_cbfs(); diff --git a/src/cpu/intel/model_206ax/model_206ax.h b/src/cpu/intel/model_206ax/model_206ax.h index fbd57a5..8259d89 100644 --- a/src/cpu/intel/model_206ax/model_206ax.h +++ b/src/cpu/intel/model_206ax/model_206ax.h @@ -29,6 +29,9 @@ #define CPUID_VMX (1 << 5) #define CPUID_SMX (1 << 6) #define MSR_FEATURE_CONFIG 0x13c +#define MSR_FLEX_RATIO 0x194 +#define FLEX_RATIO_LOCK (1 << 20) +#define FLEX_RATIO_EN (1 << 16) #define IA32_PLATFORM_DCA_CAP 0x1f8 #define IA32_MISC_ENABLE 0x1a0 #define IA32_PERF_CTL 0x199 @@ -95,6 +98,7 @@ #define PSS_LATENCY_TRANSITION 10 #define PSS_LATENCY_BUSMASTER 10 +#ifndef __ROMCC__ #ifdef __SMM__ /* Lock MSRs */ void intel_model_206ax_finalize_smm(void); @@ -103,5 +107,6 @@ void intel_model_206ax_finalize_smm(void); void set_power_limits(u8 power_limit_1_time); int cpu_config_tdp_levels(void); #endif +#endif #endif diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index d6dd5f0..0a16308 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -368,6 +368,8 @@ int smbus_read_byte(unsigned device, unsigned address); #define D25IR 0x3150 /* 16bit */ #define D22IR 0x315c /* 16bit */ #define OIC 0x31fe /* 16bit */ +#define SOFT_RESET_CTRL 0x38f4 +#define SOFT_RESET_DATA 0x38f8 #define DIR_ROUTE(x,a,b,c,d) \ RCBA32(x) = (((d) << DIR_IDR) | ((c) << DIR_ICR) | \

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coreboot July 2012