coreboot July 2012

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New patch to review for coreboot: 7cf8522 SMM: rename tseg_fixup to tseg_relocate and export
by Stefan Reinauer 23 Jul '12

23 Jul '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1310 -gerrit commit 7cf85225010e340e9afef275ac1fdc0627e8e2fd Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Sat Jun 23 15:29:59 2012 -0700 SMM: rename tseg_fixup to tseg_relocate and export This function is exported so it can be used in other places that need similar relocation due to TSEG. Change-Id: I68b78ca32d58d1a414965404e38d71977c3da347 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/include/cpu/x86/smm.h | 3 +++ src/southbridge/intel/bd82x6x/smihandler.c | 12 +++++------- 2 files changed, 8 insertions(+), 7 deletions(-) diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h index ccce2cb..82a5a1a 100644 --- a/src/include/cpu/x86/smm.h +++ b/src/include/cpu/x86/smm.h @@ -376,9 +376,12 @@ void __attribute__((weak)) mainboard_smi_sleep(u8 slp_typ); #if !CONFIG_SMM_TSEG void smi_release_lock(void); +#define tseg_relocate(ptr) #else /* Return address of TSEG base */ u32 smi_get_tseg_base(void); +/* Adjust pointer with TSEG base */ +void tseg_relocate(void **ptr); #endif #endif diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c index f5780cd..2c3bf67 100644 --- a/src/southbridge/intel/bd82x6x/smihandler.c +++ b/src/southbridge/intel/bd82x6x/smihandler.c @@ -60,14 +60,12 @@ u32 smi_get_tseg_base(void) tseg_base = pcie_read_config32(PCI_DEV(0, 0, 0), TSEG) & ~1; return tseg_base; } -static inline void tseg_fixup(void **ptr) +void tseg_relocate(void **ptr) { /* Adjust pointer with TSEG base */ if (*ptr) - *ptr = (void *)(((u8*)*ptr) + tseg_base); + *ptr = (void *)(((u8*)*ptr) + smi_get_tseg_base()); } -#else -#define tseg_fixup(x) do {} while(0) #endif /** @@ -343,7 +341,7 @@ static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *stat slp_typ = (reg32 >> 10) & 7; /* Do any mainboard sleep handling */ - tseg_fixup((void **)&mainboard_sleep); + tseg_relocate((void **)&mainboard_sleep); if (mainboard_sleep) mainboard_sleep(slp_typ); @@ -456,7 +454,7 @@ static void southbridge_smi_apmc(unsigned int node, smm_state_save_area_t *state break; } - tseg_fixup((void **)&mainboard_apmc); + tseg_relocate((void **)&mainboard_apmc); if (mainboard_apmc) mainboard_apmc(reg8); } @@ -496,7 +494,7 @@ static void southbridge_smi_gpi(unsigned int node, smm_state_save_area_t *state_ reg16 &= inw(pmbase + ALT_GP_SMI_EN); - tseg_fixup((void **)&mainboard_gpi); + tseg_relocate((void **)&mainboard_gpi); if (mainboard_gpi) { mainboard_gpi(reg16); } else {

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New patch to review for coreboot: fe5a554 SMM: Fix state save map for sandybridge and TSEG
by Stefan Reinauer 23 Jul '12

23 Jul '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1309 -gerrit commit fe5a5548bd833818ec15d2fa6ad121794dd29d62 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Sat Jun 23 15:22:43 2012 -0700 SMM: Fix state save map for sandybridge and TSEG There are enough differences that it is worth defining the proper map for the sandybridge/ivybridge CPUs. The state save map was not being addressed properly for TSEG and needs to use the right offset instead of pointing in ASEG. To do this properly add a required southbridge export to return the TSEG base and use that where appropriate. Change-Id: Idad153ed6c07d2633cb3d53eddd433a3df490834 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/cpu/x86/smm/smihandler.c | 20 +++++-- src/include/cpu/x86/smm.h | 95 ++++++++++++++++++++++++++++ src/southbridge/intel/bd82x6x/smihandler.c | 28 +++++---- 3 files changed, 125 insertions(+), 18 deletions(-) diff --git a/src/cpu/x86/smm/smihandler.c b/src/cpu/x86/smm/smihandler.c index bbed0f1..83ebaf9 100644 --- a/src/cpu/x86/smm/smihandler.c +++ b/src/cpu/x86/smm/smihandler.c @@ -117,8 +117,14 @@ void smi_handler(u32 smm_revision) { unsigned int node; smm_state_save_area_t state_save; + u32 smm_base = 0xa8000; /* ASEG */ -#if !CONFIG_SMM_TSEG +#if CONFIG_SMM_TSEG + /* Update global variable TSEG base */ + if (!smi_get_tseg_base()) + return; + smm_base = smi_get_tseg_base() + 0x8000; +#else /* Are we ok to execute the handler? */ if (!smi_obtain_lock()) { /* For security reasons we don't release the other CPUs @@ -146,18 +152,22 @@ void smi_handler(u32 smm_revision) case 0x00030007: state_save.type = LEGACY; state_save.legacy_state_save = (legacy_smm_state_save_area_t *) - (0xa8000 + 0x7e00 - (node * 0x400)); + (smm_base + 0x7e00 - (node * 0x400)); break; case 0x00030100: - case 0x00030101: /* SandyBridge */ state_save.type = EM64T; state_save.em64t_state_save = (em64t_smm_state_save_area_t *) - (0xa8000 + 0x7d00 - (node * 0x400)); + (smm_base + 0x7d00 - (node * 0x400)); + case 0x00030101: /* SandyBridge/IvyBridge */ + state_save.type = EM64T101; + state_save.em64t101_state_save = + (em64t101_smm_state_save_area_t *) + (smm_base + 0x7d00 - (node * 0x400)); break; case 0x00030064: state_save.type = AMD64; state_save.amd64_state_save = (amd64_smm_state_save_area_t *) - (0xa8000 + 0x7e00 - (node * 0x400)); + (smm_base + 0x7e00 - (node * 0x400)); break; default: printk(BIOS_DEBUG, "smm_revision: 0x%08x\n", smm_revision); diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h index 89257e5..ccce2cb 100644 --- a/src/include/cpu/x86/smm.h +++ b/src/include/cpu/x86/smm.h @@ -201,6 +201,96 @@ typedef struct { } __attribute__((packed)) em64t_smm_state_save_area_t; +/* Intel Revision 30101 SMM State-Save Area + * Used in SandyBridge/IvyBridge architecture + * starts @ 0x7d00 + */ +typedef struct { + u8 reserved0[208]; + + u32 gdtr_upper_base; + u32 ldtr_upper_base; + u32 idtr_upper_base; + + u32 io_cf8; + + u64 io_rdi; + u64 io_rip; + u64 io_rcx; + u64 io_rsi; + + u8 reserved1[52]; + u32 shutdown_auto_restart; + u8 reserved2[8]; + u32 cr4; + + u8 reserved3[72]; + + u32 gdtr_base; + u8 reserved4[4]; + u32 idtr_base; + u8 reserved5[4]; + u32 ldtr_base; + + u8 reserved6[68]; + u32 cs_base; + u8 reserved7[4]; + u32 iedbase; + + u8 reserved8[8]; + + u32 smbase; + u32 smm_revision; + + u16 io_restart; + u16 autohalt_restart; + + u8 reserved9[24]; + + u64 r15; + u64 r14; + u64 r13; + u64 r12; + u64 r11; + u64 r10; + u64 r9; + u64 r8; + + u64 rax; + u64 rcx; + u64 rdx; + u64 rbx; + + u64 rsp; + u64 rbp; + u64 rsi; + u64 rdi; + + + u64 io_mem_addr; + u32 io_misc_info; + + u32 es_sel; + u32 cs_sel; + u32 ss_sel; + u32 ds_sel; + u32 fs_sel; + u32 gs_sel; + + u32 ldtr_sel; + u32 tr_sel; + + u64 dr7; + u64 dr6; + u64 rip; + u64 efer; + u64 rflags; + + u64 cr3; + u64 cr0; +} __attribute__((packed)) em64t101_smm_state_save_area_t; + + /* Legacy x86 SMM State-Save Area * starts @ 0x7e00 */ @@ -243,6 +333,7 @@ typedef struct { typedef enum { AMD64, EM64T, + EM64T101, LEGACY } save_state_type_t; @@ -252,6 +343,7 @@ typedef struct { union { amd64_smm_state_save_area_t *amd64_state_save; em64t_smm_state_save_area_t *em64t_state_save; + em64t101_smm_state_save_area_t *em64t101_state_save; legacy_smm_state_save_area_t *legacy_state_save; }; } smm_state_save_area_t; @@ -284,6 +376,9 @@ void __attribute__((weak)) mainboard_smi_sleep(u8 slp_typ); #if !CONFIG_SMM_TSEG void smi_release_lock(void); +#else +/* Return address of TSEG base */ +u32 smi_get_tseg_base(void); #endif #endif diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c index d7690ba..f5780cd 100644 --- a/src/southbridge/intel/bd82x6x/smihandler.c +++ b/src/southbridge/intel/bd82x6x/smihandler.c @@ -32,6 +32,13 @@ #include "nvs.h" +/* We are using PCIe accesses for now + * 1. the chipset can do it + * 2. we don't need to worry about how we leave 0xcf8/0xcfc behind + */ +#include <northbridge/intel/sandybridge/sandybridge.h> +#include <northbridge/intel/sandybridge/pcie_config.c> + /* While we read PMBASE dynamically in case it changed, let's * initialize it with a sane value */ @@ -47,6 +54,12 @@ void *smi1 = (void *)0x0; #if CONFIG_SMM_TSEG static u32 tseg_base = 0; +u32 smi_get_tseg_base(void) +{ + if (!tseg_base) + tseg_base = pcie_read_config32(PCI_DEV(0, 0, 0), TSEG) & ~1; + return tseg_base; +} static inline void tseg_fixup(void **ptr) { /* Adjust pointer with TSEG base */ @@ -208,13 +221,6 @@ static void dump_tco_status(u32 tco_sts) printk(BIOS_DEBUG, "\n"); } -/* We are using PCIe accesses for now - * 1. the chipset can do it - * 2. we don't need to worry about how we leave 0xcf8/0xcfc behind - */ -#include <northbridge/intel/sandybridge/sandybridge.h> -#include <northbridge/intel/sandybridge/pcie_config.c> - int southbridge_io_trap_handler(int smif) { switch (smif) { @@ -672,11 +678,6 @@ void southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_sav /* Update global variable pmbase */ pmbase = pcie_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc; -#if CONFIG_SMM_TSEG - /* Update global variable TSEG base */ - tseg_base = pcie_read_config32(PCI_DEV(0, 0, 0), TSEG) & ~1; -#endif - /* We need to clear the SMI status registers, or we won't see what's * happening in the following calls. */ @@ -688,7 +689,8 @@ void southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_sav if (southbridge_smi[i]) { #if CONFIG_SMM_TSEG smi_handler_t handler = (smi_handler_t) - ((u8*)southbridge_smi[i] + tseg_base); + ((u8*)southbridge_smi[i] + + smi_get_tseg_base()); if (handler) handler(node, state_save); #else

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New patch to review for coreboot: 83a49f7 SMM: Add heap region and move C handler higher in region
by Stefan Reinauer 23 Jul '12

23 Jul '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1308 -gerrit commit 83a49f79e7339b011063e346b9f96765b2805160 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Sat Jun 23 15:09:34 2012 -0700 SMM: Add heap region and move C handler higher in region In order to support SPI and ELOG drivers the SMM region needs to be able to be larger than the previous allocation below 0x7400. Now that we have support for 4M TSEG we do not need to live in this region. This change adds a 16KB heap region abofe the save state area at TSEG+64KB and moves the C handler above this. The heap region is then available for malloc and the C handler can grow to support flash and event log features. While updating the memory map comment in assembly stub I also added a pause instruction to the cpu spin lock as this was added to the C code in latest upstream rebase. Dump sympbols from smm.elf binary to see the new regions: 00010000 B _heap 00014000 B _eheap 00014000 T _smm_c_handler_start 0001b240 T _smm_c_handler_end Change-Id: I45f0ab4df1fdef3b626f877094a58587476ac634 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/cpu/x86/smm/smm_tseg.ld | 45 +++++++++++++++++++++++------------- src/cpu/x86/smm/smmhandler_tseg.S | 9 +++++- 2 files changed, 36 insertions(+), 18 deletions(-) diff --git a/src/cpu/x86/smm/smm_tseg.ld b/src/cpu/x86/smm/smm_tseg.ld index 016b5a0..6def972 100644 --- a/src/cpu/x86/smm/smm_tseg.ld +++ b/src/cpu/x86/smm/smm_tseg.ld @@ -10,6 +10,34 @@ SECTIONS .handler (.): { /* Assembler stub */ *(.handler) + } + + /* We are using the TSEG interleaved to stuff the SMM handlers + * for all CPU cores in there. The jump table redirects the execution + * to the actual SMM handler + */ + . = 0x8000 - (( CPUS - 1) * 0x400); + .jumptable : { + *(.jumptable) + } + + /* Data used in early SMM TSEG handler. */ + . = 0x8400; + .earlydata : { + *(.earlydata) + } + + /* 16KB for the heap at 64KB */ + . = 0x10000; + .heap : { + _heap = .; + . = 0x4000; + _eheap = .; + } + + . = ALIGN(0x4000); + .smm_c_handler : { + _smm_c_handler_start = .; /* C code of the SMM handler */ *(.text); @@ -29,25 +57,10 @@ SECTIONS . = ALIGN(4); *(.bss) *(.sbss) - - /* What is this? */ *(COMMON) . = ALIGN(4); - } - /* We are using the TSEG interleaved to stuff the SMM handlers - * for all CPU cores in there. The jump table redirects the execution - * to the actual SMM handler - */ - . = 0x8000 - (( CPUS - 1) * 0x400); - .jumptable : { - *(.jumptable) - } - - /* Data used in early SMM TSEG handler. */ - . = 0x8400; - .earlydata : { - *(.earlydata) + _smm_c_handler_end = .; } /DISCARD/ : { diff --git a/src/cpu/x86/smm/smmhandler_tseg.S b/src/cpu/x86/smm/smmhandler_tseg.S index 8fdd75f..c61a611 100644 --- a/src/cpu/x86/smm/smmhandler_tseg.S +++ b/src/cpu/x86/smm/smmhandler_tseg.S @@ -20,7 +20,11 @@ */ /* - * +--------------------------------+ 0xffff + * +--------------------------------+ + * | SMM Handler C Code | + * +--------------------------------+ 0x14000 + * | SMM Handler Heap | + * +--------------------------------+ 0x10000 * | Save State Map Node 0 | * | Save State Map Node 1 | * | Save State Map Node 2 | @@ -39,7 +43,7 @@ * | ... | * +--------------------------------+ 0x7400 * | | - * | SMM Handler | + * | SMM Handler Assembly Stub | * | | * +--------------------------------+ TSEG * @@ -91,6 +95,7 @@ smm_handler_start: /* If we did not get the lock, wait for release */ wait_for_unlock: + pause addr32 movw (%ebx), %ax cmpw $SMI_LOCKED, %ax je wait_for_unlock

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New patch to review for coreboot: 6fd9d3d Remove CMOS Extended range enable from romstage
by Stefan Reinauer 23 Jul '12

23 Jul '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1307 -gerrit commit 6fd9d3d47fb049b5a6004af399177e6c17782265 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Jun 25 10:39:21 2012 -0700 Remove CMOS Extended range enable from romstage This enable step has been moved to the bd82x6x bootblock. For Samsung Stumpy and Lumpy mainboards and the Intel EmeraldLake2 reference board. Change-Id: I5ce54f57b8e1dd732c8a5ae71d7511703de91a0e Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/mainboard/intel/emeraldlake2/romstage.c | 3 --- src/mainboard/samsung/lumpy/romstage.c | 3 --- src/mainboard/samsung/stumpy/romstage.c | 3 --- 3 files changed, 0 insertions(+), 9 deletions(-) diff --git a/src/mainboard/intel/emeraldlake2/romstage.c b/src/mainboard/intel/emeraldlake2/romstage.c index f8ef17d..7a31242 100644 --- a/src/mainboard/intel/emeraldlake2/romstage.c +++ b/src/mainboard/intel/emeraldlake2/romstage.c @@ -113,9 +113,6 @@ static void rcba_config(void) /* PCH BWG says to read back the IOAPIC enable register */ (void) RCBA16(OIC); - /* Enable upper 128bytes of CMOS (generic) */ - RCBA32(RC) = (1 << 2); - /* Disable unused devices (board specific) */ reg32 = RCBA32(FD); reg32 |= PCH_DISABLE_ALWAYS; diff --git a/src/mainboard/samsung/lumpy/romstage.c b/src/mainboard/samsung/lumpy/romstage.c index 09cbd2a..4bba76e 100644 --- a/src/mainboard/samsung/lumpy/romstage.c +++ b/src/mainboard/samsung/lumpy/romstage.c @@ -114,9 +114,6 @@ static void rcba_config(void) /* PCH BWG says to read back the IOAPIC enable register */ (void) RCBA16(OIC); - /* Enable upper 128bytes of CMOS (generic) */ - RCBA32(RC) = (1 << 2); - /* Disable unused devices (board specific) */ reg32 = RCBA32(FD); reg32 |= PCH_DISABLE_ALWAYS; diff --git a/src/mainboard/samsung/stumpy/romstage.c b/src/mainboard/samsung/stumpy/romstage.c index 68f6260..58305c8 100644 --- a/src/mainboard/samsung/stumpy/romstage.c +++ b/src/mainboard/samsung/stumpy/romstage.c @@ -119,9 +119,6 @@ static void rcba_config(void) /* PCH BWG says to read back the IOAPIC enable register */ (void) RCBA16(OIC); - /* Enable upper 128bytes of CMOS (generic) */ - RCBA32(RC) = (1 << 2); - /* Disable unused devices (board specific) */ reg32 = RCBA32(FD); reg32 |= PCH_DISABLE_ALWAYS;

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New patch to review for coreboot: e6f8608 RTC: Enable extended CMOS in the bootblock
by Stefan Reinauer 23 Jul '12

23 Jul '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1306 -gerrit commit e6f8608ce93f8b923a65ff2378174c3587b1236e Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Sat Jun 23 15:43:41 2012 -0700 RTC: Enable extended CMOS in the bootblock This makes it available early in romstage without having to worry when the different romstagse enable it. Check for extended CMOS to be enabled in early romstage. This is used by a later commit which uses the extended CMOS region for stoage. Change-Id: I9e026d48499c63d6503c2b020d4cc3047126fa93 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/southbridge/intel/bd82x6x/bootblock.c | 3 +++ 1 files changed, 3 insertions(+), 0 deletions(-) diff --git a/src/southbridge/intel/bd82x6x/bootblock.c b/src/southbridge/intel/bd82x6x/bootblock.c index d6cba5f..0191bbf 100644 --- a/src/southbridge/intel/bd82x6x/bootblock.c +++ b/src/southbridge/intel/bd82x6x/bootblock.c @@ -72,4 +72,7 @@ static void bootblock_southbridge_init(void) #endif enable_spi_prefetch(); enable_port80_on_lpc(); + + /* Enable upper 128bytes of CMOS */ + RCBA32(RC) = (1 << 2); }

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New patch to review for coreboot: 29b3a4c CPU: Update ivybridge PP1 current limit value
by Stefan Reinauer 23 Jul '12

23 Jul '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1305 -gerrit commit 29b3a4cf5ecef85ccfee7981427173f5b3b6edf2 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Jun 25 09:53:58 2012 -0700 CPU: Update ivybridge PP1 current limit value The BWG says ivybridge current limit for PP1 is 50A. Verify the PP1 current limit value on link device: > echo $(( ( $(rdmsr 0 0x602) & 0x1fff ) >> 3 )) 50 Change-Id: I946269d21ef605f2525fe03993f569d69128294b Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/cpu/intel/model_206ax/model_206ax.h | 3 ++- src/cpu/intel/model_206ax/model_206ax_init.c | 5 ++++- 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/src/cpu/intel/model_206ax/model_206ax.h b/src/cpu/intel/model_206ax/model_206ax.h index d482ff0..fbd57a5 100644 --- a/src/cpu/intel/model_206ax/model_206ax.h +++ b/src/cpu/intel/model_206ax/model_206ax.h @@ -75,7 +75,8 @@ #define MSR_PP0_CURRENT_CONFIG 0x601 #define PP0_CURRENT_LIMIT (112 << 3) /* 112 A */ #define MSR_PP1_CURRENT_CONFIG 0x602 -#define PP1_CURRENT_LIMIT (35 << 3) /* 35 A */ +#define PP1_CURRENT_LIMIT_SNB (35 << 3) /* 35 A */ +#define PP1_CURRENT_LIMIT_IVB (50 << 3) /* 50 A */ #define MSR_PKG_POWER_SKU_UNIT 0x606 #define MSR_PKG_POWER_SKU 0x614 #define MSR_PP0_POWER_LIMIT 0x638 diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c index 0958fe3..08757d1 100644 --- a/src/cpu/intel/model_206ax/model_206ax_init.c +++ b/src/cpu/intel/model_206ax/model_206ax_init.c @@ -311,7 +311,10 @@ static void configure_c_states(void) /* Secondary Plane Current Limit */ msr = rdmsr(MSR_PP1_CURRENT_CONFIG); msr.lo &= ~0x1fff; - msr.lo |= PP1_CURRENT_LIMIT; + if (cpuid_eax(1) >= 0x30600) + msr.lo |= PP1_CURRENT_LIMIT_IVB; + else + msr.lo |= PP1_CURRENT_LIMIT_SNB; wrmsr(MSR_PP1_CURRENT_CONFIG, msr); }

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New patch to review for coreboot: 364dbdd CPU: Add basic support for Nominal Configurable TDP
by Stefan Reinauer 23 Jul '12

23 Jul '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1304 -gerrit commit 364dbdd0177ff1fb5bbf398217fcae01ef296d1e Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Jun 25 09:51:59 2012 -0700 CPU: Add basic support for Nominal Configurable TDP Ivybridge B0+ CPUs are capable of supporting multiple TDP levels. This complicates the default case because now the registers that were reporting max non-turbo ratio are reporting that value for the highest possible TDP level. For now this change just forces everything to use the Nominal TDP values instead of the higher (or lower) levels. - When building P-state tables, determine the P[1] (max non turbo) ratio based on the Nominal ratio if available. - Set the turbo activation ratio to the Nominal max ratio. - Mirror the power level settings in new MCHBAR register after they are written, which happens after BIOS_RESET_CPL is set. - Set the current ratio to Nominal ratio at boot. 1) Verify that P-state table is generated properly with P[0]=1801MHz (ratio 0x1C) and P[1]=1800MHz (ratio 0x12) PSS: 1801MHz power 17000 control 0x1c00 status 0x1c00 PSS: 1800MHz power 17000 control 0x1200 status 0x1200 2) Verify power limits in MCHBAR match PKG_POWER_LIMIT: > rdmsr 0 0x610 0x800080aa00dc8088 > mmio_read32 0xfed159a4 0x000080aa > mmio_read32 0xfed159a0 0x00dc8088 3) Verify turbo activation ratio is set to nominal ratio: > rdmsr 0 0x64c 0x0000000000000012 4) Check that proper ratio was set at boot on one core only: > grep 'frequency set to' /sys/firmware/log model_x06ax: frequency set to 1800 model_x06ax: frequency set to 1800 model_x06ax: frequency set to 1800 model_x06ax: frequency set to 1800 Change-Id: I592e60a7740f31b140986a8269dca91b4adbb270 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/cpu/intel/model_206ax/acpi.c | 11 +++++- src/cpu/intel/model_206ax/model_206ax.h | 8 ++++ src/cpu/intel/model_206ax/model_206ax_init.c | 45 +++++++++++++++++++---- src/northbridge/intel/sandybridge/northbridge.c | 11 ++++++ 4 files changed, 66 insertions(+), 9 deletions(-) diff --git a/src/cpu/intel/model_206ax/acpi.c b/src/cpu/intel/model_206ax/acpi.c index 5d3f3a0..7b49555 100644 --- a/src/cpu/intel/model_206ax/acpi.c +++ b/src/cpu/intel/model_206ax/acpi.c @@ -229,7 +229,16 @@ static int generate_P_state_entries(int core, int cores_per_package) /* Get bus ratio limits and calculate clock speeds */ msr = rdmsr(MSR_PLATFORM_INFO); ratio_min = (msr.hi >> (40-32)) & 0xff; /* Max Efficiency Ratio */ - ratio_max = (msr.lo >> 8) & 0xff; /* Max Non-Turbo Ratio */ + + /* Determine if this CPU has configurable TDP */ + if (cpu_config_tdp_levels()) { + /* Set max ratio to nominal TDP ratio */ + msr = rdmsr(MSR_CONFIG_TDP_NOMINAL); + ratio_max = msr.lo & 0xff; + } else { + /* Max Non-Turbo Ratio */ + ratio_max = (msr.lo >> 8) & 0xff; + } clock_max = ratio_max * SANDYBRIDGE_BCLK; /* Calculate CPU TDP in mW */ diff --git a/src/cpu/intel/model_206ax/model_206ax.h b/src/cpu/intel/model_206ax/model_206ax.h index 3343d11..d482ff0 100644 --- a/src/cpu/intel/model_206ax/model_206ax.h +++ b/src/cpu/intel/model_206ax/model_206ax.h @@ -81,6 +81,13 @@ #define MSR_PP0_POWER_LIMIT 0x638 #define MSR_PP1_POWER_LIMIT 0x640 +#define IVB_CONFIG_TDP_MIN_CPUID 0x306a2 +#define MSR_CONFIG_TDP_NOMINAL 0x648 +#define MSR_CONFIG_TDP_LEVEL1 0x649 +#define MSR_CONFIG_TDP_LEVEL2 0x64a +#define MSR_CONFIG_TDP_CONTROL 0x64b +#define MSR_TURBO_ACTIVATION_RATIO 0x64c + /* P-state configuration */ #define PSS_MAX_ENTRIES 8 #define PSS_RATIO_STEP 2 @@ -93,6 +100,7 @@ void intel_model_206ax_finalize_smm(void); #else /* Configure power limits for turbo mode */ void set_power_limits(u8 power_limit_1_time); +int cpu_config_tdp_levels(void); #endif #endif diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c index 87bc585..0958fe3 100644 --- a/src/cpu/intel/model_206ax/model_206ax_init.c +++ b/src/cpu/intel/model_206ax/model_206ax_init.c @@ -179,6 +179,19 @@ static const u8 power_limit_time_msr_to_sec[] = { [0x11] = 128, }; +int cpu_config_tdp_levels(void) +{ + msr_t platform_info; + + /* Minimum CPU revision */ + if (cpuid_eax(1) < IVB_CONFIG_TDP_MIN_CPUID) + return 0; + + /* Bits 34:33 indicate how many levels supported */ + platform_info = rdmsr(MSR_PLATFORM_INFO); + return (platform_info.hi >> 1) & 3; +} + /* * Configure processor power limits if possible * This must be done AFTER set of BIOS_RESET_CPL @@ -235,6 +248,14 @@ void set_power_limits(u8 power_limit_1_time) /* Power limit 2 time is only programmable on SNB EP/EX */ wrmsr(MSR_PKG_POWER_LIMIT, limit); + + /* Use nominal TDP values for CPUs with configurable TDP */ + if (cpu_config_tdp_levels()) { + msr = rdmsr(MSR_CONFIG_TDP_NOMINAL); + limit.hi = 0; + limit.lo = msr.lo & 0xff; + wrmsr(MSR_TURBO_ACTIVATION_RATIO, limit); + } } static void configure_c_states(void) @@ -340,16 +361,24 @@ static void configure_dca_cap(void) static void set_max_ratio(void) { - msr_t msr; - - /* Platform Info bits 15:8 give max ratio */ - msr = rdmsr(MSR_PLATFORM_INFO); - msr.hi = 0; - msr.lo &= 0xff00; - wrmsr(IA32_PERF_CTL, msr); + msr_t msr, perf_ctl; + + perf_ctl.hi = 0; + + /* Check for configurable TDP option */ + if (cpu_config_tdp_levels()) { + /* Set to nominal TDP ratio */ + msr = rdmsr(MSR_CONFIG_TDP_NOMINAL); + perf_ctl.lo = (msr.lo & 0xff) << 8; + } else { + /* Platform Info bits 15:8 give max ratio */ + msr = rdmsr(MSR_PLATFORM_INFO); + perf_ctl.lo = msr.lo & 0xff00; + } + wrmsr(IA32_PERF_CTL, perf_ctl); printk(BIOS_DEBUG, "model_x06ax: frequency set to %d\n", - ((msr.lo >> 8) & 0xff) * 100); + ((perf_ctl.lo >> 8) & 0xff) * SANDYBRIDGE_BCLK); } static void set_energy_perf_bias(u8 policy) diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index 2fa3504..bfb2166 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -24,6 +24,7 @@ #include <stdint.h> #include <delay.h> #include <cpu/intel/model_206ax/model_206ax.h> +#include <cpu/x86/msr.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> @@ -422,6 +423,16 @@ static void northbridge_init(struct device *dev) mdelay(1); set_power_limits(28); + /* + * CPUs with configurable TDP also need power limits set + * in MCHBAR. Use same values from MSR_PKG_POWER_LIMIT. + */ + if (cpu_config_tdp_levels()) { + msr_t msr = rdmsr(MSR_PKG_POWER_LIMIT); + MCHBAR32(0x59A0) = msr.lo; + MCHBAR32(0x59A4) = msr.hi; + } + /* Set here before graphics PM init */ MCHBAR32(0x5500) = 0x00100001; }

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New patch to review for coreboot: 2d3a5c5 Ivybridge: fix workaround and enable PAIR
by Stefan Reinauer 23 Jul '12

23 Jul '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1303 -gerrit commit 2d3a5c5dc15508b84883af8071870e743653a562 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Sat Jun 23 20:14:07 2012 -0700 Ivybridge: fix workaround and enable PAIR MCHBAR 0x5f10[7:0] should be set to 0x30 for ivybridge and 0x20 for sandybridge. Move this code to ramstage and set it per-chipset. Power Aware Interrupt Routing is supported in ivybridge, enable it and set fixed priority. Boot on ivybridge device and read MCHBAR 0x5f10: mmio_read8 0xfed15f10 0x30 And verify PAIR is enabled (bit4=1): mmio_read8 0xfed15418 0x24 Change-Id: If017d5ce2bd5ab5092c86f657434f2b645ee6613 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/northbridge/intel/sandybridge/early_init.c | 2 -- src/northbridge/intel/sandybridge/northbridge.c | 19 +++++++++++++++++++ 2 files changed, 19 insertions(+), 2 deletions(-) diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c index 48faf5f..c7afa11 100644 --- a/src/northbridge/intel/sandybridge/early_init.c +++ b/src/northbridge/intel/sandybridge/early_init.c @@ -108,8 +108,6 @@ static void sandybridge_setup_graphics(void) pci_write_config8(PCI_DEV(0, 2, 0), MSAC, reg8); /* Erratum workarounds */ - MCHBAR8(0x5f10) = 0x20; - reg32 = MCHBAR32(0x5f00); reg32 |= (1 << 9)|(1 << 10); MCHBAR32(0x5f00) = reg32; diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index 756aacf..2fa3504 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -387,9 +387,28 @@ static void northbridge_dmi_init(struct device *dev) static void northbridge_init(struct device *dev) { u8 bios_reset_cpl; + u32 bridge_type; northbridge_dmi_init(dev); + bridge_type = MCHBAR32(0x5f10); + bridge_type &= ~0xff; + + if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_IVB) { + /* Enable Power Aware Interrupt Routing */ + u8 pair = MCHBAR8(0x5418); + pair &= ~0xf; /* Clear 3:0 */ + pair |= 0x4; /* Fixed Priority */ + MCHBAR8(0x5418) = pair; + + /* 30h for IvyBridge */ + bridge_type |= 0x30; + } else { + /* 20h for Sandybridge */ + bridge_type |= 0x20; + } + MCHBAR32(0x5f10) = bridge_type; + /* * Set bit 0 of BIOS_RESET_CPL to indicate to the CPU * that BIOS has initialized memory and power management

1 0

New patch to review for coreboot: 0bcdec8 RTC: Add defines for standard clock offsets
by Stefan Reinauer 23 Jul '12

23 Jul '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1302 -gerrit commit 0bcdec8a18ce4061710fa212adabc4fdc63b2f4b Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Sat Jun 23 13:22:25 2012 -0700 RTC: Add defines for standard clock offsets ELOG reads from RTC to build timestamp structure, the resulting timestamp is decoded when printing events. Change-Id: If26552074f18de5095b967b875a0ac1d815a5b31 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/include/pc80/mc146818rtc.h | 12 ++++++++++++ 1 files changed, 12 insertions(+), 0 deletions(-) diff --git a/src/include/pc80/mc146818rtc.h b/src/include/pc80/mc146818rtc.h index a1f06e7..9f18ba4 100644 --- a/src/include/pc80/mc146818rtc.h +++ b/src/include/pc80/mc146818rtc.h @@ -76,6 +76,18 @@ # define RTC_VRT 0x80 /* valid RAM and time */ /**********************************************************************/ +/* Date and Time in RTC CMOS */ +#define RTC_CLK_SECOND 0 +#define RTC_CLK_SECOND_ALARM 1 +#define RTC_CLK_MINUTE 2 +#define RTC_CLK_MINUTE_ALARM 3 +#define RTC_CLK_HOUR 4 +#define RTC_CLK_HOUR_ALARM 5 +#define RTC_CLK_DAYOFWEEK 6 +#define RTC_CLK_DAYOFMONTH 7 +#define RTC_CLK_MONTH 8 +#define RTC_CLK_YEAR 9 + /* On PCs, the checksum is built only over bytes 16..45 */ #define PC_CKS_RANGE_START 16 #define PC_CKS_RANGE_END 45

1 0

New patch to review for coreboot: 4adfa20 bd82x6x: Convert all PCI ID lists to new scheme
by Stefan Reinauer 23 Jul '12

23 Jul '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1301 -gerrit commit 4adfa20442e1379e39ab3e449f82867939a8fbf3 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Fri Jun 22 13:16:11 2012 -0700 bd82x6x: Convert all PCI ID lists to new scheme - Convert all PCI ID lists to new scheme - Unify code (variable names) - add missing PCI IDs for Panther Point PCIe root ports. Change-Id: I6357f6ebce7ddffe45a3ec642b0c594147f6134c Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/southbridge/intel/bd82x6x/azalia.c | 14 ++--- src/southbridge/intel/bd82x6x/lpc.c | 102 ++++-------------------------- src/southbridge/intel/bd82x6x/pch.c | 2 +- src/southbridge/intel/bd82x6x/pcie.c | 74 +++------------------- src/southbridge/intel/bd82x6x/sata.c | 16 +++--- src/southbridge/intel/bd82x6x/smbus.c | 14 ++--- src/southbridge/intel/bd82x6x/usb_ehci.c | 26 ++------ 7 files changed, 49 insertions(+), 199 deletions(-) diff --git a/src/southbridge/intel/bd82x6x/azalia.c b/src/southbridge/intel/bd82x6x/azalia.c index 5a83e38..e40bbe3 100644 --- a/src/southbridge/intel/bd82x6x/azalia.c +++ b/src/southbridge/intel/bd82x6x/azalia.c @@ -353,15 +353,11 @@ static struct device_operations azalia_ops = { .ops_pci = &azalia_pci_ops, }; -static const struct pci_driver azalia_0 __pci_driver = { - .ops = &azalia_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x1c20, -}; +static const unsigned short pci_device_ids[] = { 0x1c20, 0x1e20, 0 }; -static const struct pci_driver azalia_1 __pci_driver = { - .ops = &azalia_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x1e20, +static const struct pci_driver pch_azalia __pci_driver = { + .ops = &azalia_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .devices = pci_device_ids, }; diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 703fc8a..37f9290 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -604,93 +604,17 @@ static struct device_operations device_ops = { * update from August 2011 */ -static const struct pci_driver q67_lpc __pci_driver = { - .ops = &device_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x1c4e, -}; -static const struct pci_driver q65_lpc __pci_driver = { - .ops = &device_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x1c4c, -}; -static const struct pci_driver b65_lpc __pci_driver = { - .ops = &device_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x1c50, -}; -static const struct pci_driver h67_lpc __pci_driver = { - .ops = &device_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x1c4a, -}; -static const struct pci_driver z68_lpc __pci_driver = { - .ops = &device_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x1c46, -}; -static const struct pci_driver h61_lpc __pci_driver = { - .ops = &device_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x1c5c, -}; -static const struct pci_driver c202_lpc __pci_driver = { - .ops = &device_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x1c52, -}; -static const struct pci_driver c204_lpc __pci_driver = { - .ops = &device_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x1c54, -}; -static const struct pci_driver c206_lpc __pci_driver = { - .ops = &device_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x1c56, -}; -static const struct pci_driver qm67_lpc __pci_driver = { - .ops = &device_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x1c4f, -}; -static const struct pci_driver um67_lpc __pci_driver = { - .ops = &device_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x1c47, -}; -static const struct pci_driver hm67_lpc __pci_driver = { - .ops = &device_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x1c4b, -}; -static const struct pci_driver hm65_lpc __pci_driver = { - .ops = &device_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x1c49, -}; -static const struct pci_driver qs67_lpc __pci_driver = { - .ops = &device_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x1c4d, -}; -static const struct pci_driver c216_lpc __pci_driver = { - .ops = &device_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x1e55, -}; -static const struct pci_driver hm75_lpc __pci_driver = { - .ops = &device_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x1e5d, -}; -static const struct pci_driver hm70_lpc __pci_driver = { - .ops = &device_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x1e5e, -}; -static const struct pci_driver nm70_lpc __pci_driver = { - .ops = &device_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x1e5f, +static const unsigned short pci_device_ids[] = { 0x1c46, 0x1c47, 0x1c49, 0x1c4a, + 0x1c4b, 0x1c4c, 0x1c4d, 0x1c4e, + 0x1c4f, 0x1c50, 0x1c52, 0x1c54, + 0x1e55, 0x1c56, 0x1c5c, 0x1e5d, + 0x1e5e, 0x1e5f, + 0 }; + +static const struct pci_driver pch_lpc __pci_driver = { + .ops = &device_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .devices = pci_device_ids, }; + + diff --git a/src/southbridge/intel/bd82x6x/pch.c b/src/southbridge/intel/bd82x6x/pch.c index 5f440e6..0913e1d 100644 --- a/src/southbridge/intel/bd82x6x/pch.c +++ b/src/southbridge/intel/bd82x6x/pch.c @@ -403,6 +403,6 @@ void pch_enable(device_t dev) } struct chip_operations southbridge_intel_bd82x6x_ops = { - CHIP_NAME("Intel Series 6 (" CONFIG_PCH_CHIP_NAME ") Southbridge") + CHIP_NAME("Intel Series 6/7 (" CONFIG_PCH_CHIP_NAME ") Southbridge") .enable_dev = pch_enable, }; diff --git a/src/southbridge/intel/bd82x6x/pcie.c b/src/southbridge/intel/bd82x6x/pcie.c index 5ab18f6..00d1de2 100644 --- a/src/southbridge/intel/bd82x6x/pcie.c +++ b/src/southbridge/intel/bd82x6x/pcie.c @@ -257,68 +257,14 @@ static struct device_operations device_ops = { .ops_pci = &pci_ops, }; -static const struct pci_driver pch_pcie_port1 __pci_driver = { - .ops = &device_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x1c10, /* D28:F0 */ -}; - -static const struct pci_driver pch_pcie_port1_a __pci_driver = { - .ops = &device_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x1e10, /* D28:F0 */ -}; - -static const struct pci_driver pch_pcie_port2 __pci_driver = { - .ops = &device_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x1c12, /* D28:F1 */ -}; - -static const struct pci_driver pch_pcie_port3 __pci_driver = { - .ops = &device_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x1c14, /* D28:F2 */ -}; - -static const struct pci_driver pch_pcie_port3_a __pci_driver = { - .ops = &device_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x1e14, /* D28:F2 */ -}; - -static const struct pci_driver pch_pcie_port4 __pci_driver = { - .ops = &device_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x1c16, /* D28:F3 */ -}; - -static const struct pci_driver pch_pcie_port4_a __pci_driver = { - .ops = &device_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x1e16, /* D28:F3 */ -}; - -static const struct pci_driver pch_pcie_port5 __pci_driver = { - .ops = &device_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x1c18, /* D28:F4 */ -}; - -static const struct pci_driver pch_pcie_port6 __pci_driver = { - .ops = &device_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x1c1a, /* D28:F5 */ -}; - -static const struct pci_driver pch_pcie_port7 __pci_driver = { - .ops = &device_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x1c1c, /* D28:F6 */ -}; - -static const struct pci_driver pch_pcie_port8 __pci_driver = { - .ops = &device_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x1c1e, /* D28:F7 */ +static const unsigned short pci_device_ids[] = { 0x1c10, 0x1c12, 0x1c14, 0x1c16, + 0x1c18, 0x1c1a, 0x1c1c, 0x1c1e, + 0x1e10, 0x1e12, 0x1e14, 0x1e16, + 0x1e18, 0x1e1a, 0x1e1c, 0x1e1e, + 0 }; + +static const struct pci_driver pch_pcie __pci_driver = { + .ops = &device_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .devices = pci_device_ids, }; diff --git a/src/southbridge/intel/bd82x6x/sata.c b/src/southbridge/intel/bd82x6x/sata.c index 431a29b..c0eb232 100644 --- a/src/southbridge/intel/bd82x6x/sata.c +++ b/src/southbridge/intel/bd82x6x/sata.c @@ -230,13 +230,13 @@ static struct device_operations sata_ops = { .ops_pci = &sata_pci_ops, }; -static const unsigned short all_dev_ids[] = { 0x1c00, 0x1c01, 0x1c02, 0x1c03, - 0x1e00, 0x1e01, 0x1e02, 0x1e03, - 0 }; -/* Non-AHCI and Non-RAID Mode */ -static const struct pci_driver pch_sata_normal_driver __pci_driver = { - .ops = &sata_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .devices = all_dev_ids, +static const unsigned short pci_device_ids[] = { 0x1c00, 0x1c01, 0x1c02, 0x1c03, + 0x1e00, 0x1e01, 0x1e02, 0x1e03, + 0 }; + +static const struct pci_driver pch_sata __pci_driver = { + .ops = &sata_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .devices = pci_device_ids, }; diff --git a/src/southbridge/intel/bd82x6x/smbus.c b/src/southbridge/intel/bd82x6x/smbus.c index baa3cfb..4930685 100644 --- a/src/southbridge/intel/bd82x6x/smbus.c +++ b/src/southbridge/intel/bd82x6x/smbus.c @@ -100,14 +100,10 @@ static struct device_operations smbus_ops = { .ops_pci = &smbus_pci_ops, }; -static const struct pci_driver pch_smbus __pci_driver = { - .ops = &smbus_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x1c22, -}; +static const unsigned short pci_device_ids[] = { 0x1c22, 0x1e22, 0 }; -static const struct pci_driver pch_smbus_a __pci_driver = { - .ops = &smbus_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x1e22, +static const struct pci_driver pch_smbus __pci_driver = { + .ops = &smbus_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .devices = pci_device_ids, }; diff --git a/src/southbridge/intel/bd82x6x/usb_ehci.c b/src/southbridge/intel/bd82x6x/usb_ehci.c index c299535..76e8338 100644 --- a/src/southbridge/intel/bd82x6x/usb_ehci.c +++ b/src/southbridge/intel/bd82x6x/usb_ehci.c @@ -102,23 +102,11 @@ static struct device_operations usb_ehci_ops = { .ops_pci = &lops_pci, }; -static const struct pci_driver pch_usb_ehci1 __pci_driver = { - .ops = &usb_ehci_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x1c26, -}; -static const struct pci_driver pch_usb_ehci2 __pci_driver = { - .ops = &usb_ehci_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x1c2d, -}; -static const struct pci_driver pch_usb_ehci3 __pci_driver = { - .ops = &usb_ehci_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x1e26, -}; -static const struct pci_driver pch_usb_ehci4 __pci_driver = { - .ops = &usb_ehci_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x1e2d, +static const unsigned short pci_device_ids[] = { 0x1c26, 0x1c2d, 0x1e26, 0x1e2d, + 0 }; + +static const struct pci_driver pch_usb_ehci __pci_driver = { + .ops = &usb_ehci_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .devices = pci_device_ids, };

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coreboot July 2012