coreboot July 2012

coreboot@coreboot.org

35 participants
639 discussions

New patch to review for coreboot: 5b88dbb ELOG: Log boot-time events found in southbridge
by Stefan Reinauer 23 Jul '12

23 Jul '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1319 -gerrit commit 5b88dbbbe84baa481d07cab23e8034e01685f1a6 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Sat Jun 23 17:06:47 2012 -0700 ELOG: Log boot-time events found in southbridge This is called from the SMI handler install because those setup functions clear many of these registers. Ensure that these events show up in the log as appropriate. Example log output: 159 | 2012-06-23 14:31:54 | SUS Power Fail 160 | 2012-06-23 14:31:54 | System Reset 161 | 2012-06-23 14:31:54 | ACPI Wake | S5 Change-Id: I48c423c10ee7e6c2829bcc95f6cfabb4979c25a9 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/southbridge/intel/bd82x6x/Makefile.inc | 1 + src/southbridge/intel/bd82x6x/elog.c | 114 ++++++++++++++++++++++++++++ src/southbridge/intel/bd82x6x/lpc.c | 4 + src/southbridge/intel/bd82x6x/pch.h | 5 + src/southbridge/intel/bd82x6x/smi.c | 5 + 5 files changed, 129 insertions(+), 0 deletions(-) diff --git a/src/southbridge/intel/bd82x6x/Makefile.inc b/src/southbridge/intel/bd82x6x/Makefile.inc index 3de2bd0..f9aade8 100644 --- a/src/southbridge/intel/bd82x6x/Makefile.inc +++ b/src/southbridge/intel/bd82x6x/Makefile.inc @@ -32,6 +32,7 @@ ramstage-y += me_status.c ramstage-y += reset.c ramstage-y += watchdog.c +ramstage-$(CONFIG_ELOG) += elog.c ramstage-y += spi.c smm-$(CONFIG_SPI_FLASH_SMM) += spi.c diff --git a/src/southbridge/intel/bd82x6x/elog.c b/src/southbridge/intel/bd82x6x/elog.c new file mode 100644 index 0000000..09dfcdb --- /dev/null +++ b/src/southbridge/intel/bd82x6x/elog.c @@ -0,0 +1,114 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA + */ + +#include <arch/io.h> +#include <arch/acpi.h> +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ops.h> +#include <stdint.h> +#include <string.h> +#include <elog.h> +#include "pch.h" + +void pch_log_state(void) +{ + u16 pm1_sts, gen_pmcon_3, tco2_sts; + u32 gpe0_sts, gpe0_en; + u8 gen_pmcon_2; + int i; + struct device *lpc = dev_find_slot(0, PCI_DEVFN(0x1f, 0)); + if (!lpc) + return; + + pm1_sts = inw(DEFAULT_PMBASE + PM1_STS); + gpe0_sts = inl(DEFAULT_PMBASE + GPE0_STS); + gpe0_en = inl(DEFAULT_PMBASE + GPE0_EN); + tco2_sts = inw(DEFAULT_PMBASE + TCO2_STS); + gen_pmcon_2 = pci_read_config8(lpc, GEN_PMCON_2); + gen_pmcon_3 = pci_read_config16(lpc, GEN_PMCON_3); + + /* PWR_FLR Power Failure */ + if (gen_pmcon_2 & (1 << 0)) + elog_add_event(ELOG_TYPE_POWER_FAIL); + + /* SUS Well Power Failure */ + if (gen_pmcon_3 & (1 << 14)) + elog_add_event(ELOG_TYPE_SUS_POWER_FAIL); + + /* SYS_PWROK Failure */ + if (gen_pmcon_2 & (1 << 1)) + elog_add_event(ELOG_TYPE_SYS_PWROK_FAIL); + + /* PWROK Failure */ + if (gen_pmcon_2 & (1 << 0)) + elog_add_event(ELOG_TYPE_PWROK_FAIL); + + /* Second TCO Timeout */ + if (tco2_sts & (1 << 1)) + elog_add_event(ELOG_TYPE_TCO_RESET); + + /* Power Button Override */ + if (pm1_sts & (1 << 11)) + elog_add_event(ELOG_TYPE_POWER_BUTTON_OVERRIDE); + + /* System Reset Status (reset button pushed) */ + if (gen_pmcon_2 & (1 << 4)) + elog_add_event(ELOG_TYPE_RESET_BUTTON); + + /* General Reset Status */ + if (gen_pmcon_3 & (1 << 9)) + elog_add_event(ELOG_TYPE_SYSTEM_RESET); + + /* ACPI Wake */ + if (pm1_sts & (1 << 15)) + elog_add_event_byte(ELOG_TYPE_ACPI_WAKE, + acpi_slp_type == 3 ? 3 : 5); + + /* + * Wake sources + */ + + /* RTC */ + if (pm1_sts & (1 << 10)) + elog_add_event_wake(ELOG_WAKE_SOURCE_RTC, 0); + + /* PCI Express (TODO: determine wake device) */ + if (pm1_sts & (1 << 14)) + elog_add_event_wake(ELOG_WAKE_SOURCE_PCIE, 0); + + /* PME (TODO: determine wake device) */ + if (gpe0_sts & (1 << 13)) + elog_add_event_wake(ELOG_WAKE_SOURCE_PME, 0); + + /* Internal PME (TODO: determine wake device) */ + if (gpe0_sts & (1 << 13)) + elog_add_event_wake(ELOG_WAKE_SOURCE_PME_INTERNAL, 0); + + /* GPIO 0-15 */ + for (i = 0; i < 16; i++) { + if ((gpe0_sts & (1 << (16+i))) && (gpe0_en & (1 << (16+i)))) + elog_add_event_wake(ELOG_WAKE_SOURCE_GPIO, i); + } + + /* SMBUS Wake */ + if (gpe0_sts & (1 << 7)) + elog_add_event_wake(ELOG_WAKE_SOURCE_SMBUS, 0); +} diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 37f9290..8db30f6 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -29,6 +29,7 @@ #include <arch/ioapic.h> #include <arch/acpi.h> #include <cpu/cpu.h> +#include <elog.h> #include "pch.h" #define NMI_OFF 0 @@ -296,6 +297,9 @@ static void pch_rtc_init(struct device *dev) if (rtc_failed) { reg8 &= ~RTC_BATTERY_DEAD; pci_write_config8(dev, GEN_PMCON_3, reg8); +#if CONFIG_ELOG + elog_add_event(ELOG_TYPE_RTC_RESET); +#endif } printk(BIOS_DEBUG, "rtc_failed = 0x%x\n", rtc_failed); diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index 7b646f3..d6dd5f0 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -65,6 +65,9 @@ int pch_silicon_type(void); int pch_silicon_supported(int type, int rev); void pch_enable(device_t dev); void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); +#if CONFIG_ELOG +void pch_log_state(void); +#endif #else void enable_smbus(void); void enable_usb_bar(void); @@ -483,6 +486,8 @@ int smbus_read_byte(unsigned device, unsigned address); #define DEVACT_STS 0x44 #define SS_CNT 0x50 #define C3_RES 0x54 +#define TCO1_STS 0x64 +#define TCO2_STS 0x66 /* * SPI Opcode Menu setup for SPIBAR lockdown diff --git a/src/southbridge/intel/bd82x6x/smi.c b/src/southbridge/intel/bd82x6x/smi.c index da10840..bd4d32c 100644 --- a/src/southbridge/intel/bd82x6x/smi.c +++ b/src/southbridge/intel/bd82x6x/smi.c @@ -370,6 +370,11 @@ static void smm_install(void) void smm_init(void) { +#if CONFIG_ELOG + /* Log events from chipset before clearing */ + pch_log_state(); +#endif + /* Put SMM code to 0xa0000 */ smm_install();

1 0

New patch to review for coreboot: 81a02a1 SMM: Skip locking SPI registers in finalize step
by Stefan Reinauer 23 Jul '12

23 Jul '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1318 -gerrit commit 81a02a12b1f4a1fb9be6217f3249debb34ed7043 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Sat Jun 23 17:02:29 2012 -0700 SMM: Skip locking SPI registers in finalize step This is a temporary workaround so the SPI bus can be accessed at runtime in SMM code until the SPI opcode menu is used properly. Change-Id: I93d188c55b66d8dce49fa91a1de53ee195944b30 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/southbridge/intel/bd82x6x/finalize.c | 3 +++ 1 files changed, 3 insertions(+), 0 deletions(-) diff --git a/src/southbridge/intel/bd82x6x/finalize.c b/src/southbridge/intel/bd82x6x/finalize.c index ed1ebf7..d62600f 100644 --- a/src/southbridge/intel/bd82x6x/finalize.c +++ b/src/southbridge/intel/bd82x6x/finalize.c @@ -31,8 +31,11 @@ void intel_pch_finalize_smm(void) RCBA32(0x3898) = SPI_OPMENU_LOWER; RCBA32(0x389c) = SPI_OPMENU_UPPER; +/* Need to fix SMI driver use of opcode menu */ +#if !CONFIG_ELOG_GSMI /* Lock SPIBAR */ RCBA32_OR(0x3804, (1 << 15)); +#endif /* TCLOCKDN: TC Lockdown */ RCBA32_OR(0x0050, (1 << 31));

1 0

New patch to review for coreboot: d66dc4e ELOG: Support GSMI in CPT/PPT southbridge SMI handler
by Stefan Reinauer 23 Jul '12

23 Jul '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1317 -gerrit commit d66dc4e5e6d8b4c227a78a973ba3b057824fbb22 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Sat Jun 23 17:25:29 2012 -0700 ELOG: Support GSMI in CPT/PPT southbridge SMI handler In order to support the GSMI interface the SMI handler needs to find and use the state save area from the same CPU that initiated the SMI. In this case it is a synchronous SMI resulting form an IO write to port 0xB2. To find the right CPU state save area iterate over the region until the "IO Misc Info" field reports the expected value and then proceed to use that state save area. This is needed because the coreboot SMI handler only executes on one core, and that core is non-deterministic. It is likely that the core executing the C SMM handler is not the same one that actually did the IO write to 0xB2 and generated the SMI. The GSMI parameter buffer is passed as a pointer to EBX in the tate save area, and the GSMI command is extracted from EAX before it is used as the return value. This interface is tested by enabling CONFIG_GOOGLE_GSMI in the kernel and generating events and verifying that they end up in the event log. 159 | 2012-06-23 16:22:45 | Kernl Event | Clean Shutdown 184 | 2012-06-23 17:14:05 | Kernl Event | Oops 185 | 2012-06-23 17:14:05 | Kernl Event | Panic Change-Id: Ic121ea69e9f50c88467c435e095c3e3629989806 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/southbridge/intel/bd82x6x/smihandler.c | 53 ++++++++++++++++++++++++++++ 1 files changed, 53 insertions(+), 0 deletions(-) diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c index 2c3bf67..715a82f 100644 --- a/src/southbridge/intel/bd82x6x/smihandler.c +++ b/src/southbridge/intel/bd82x6x/smihandler.c @@ -28,6 +28,7 @@ #include <cpu/x86/smm.h> #include <device/pci_def.h> #include <cpu/x86/smm.h> +#include <elog.h> #include "pch.h" #include "nvs.h" @@ -405,6 +406,53 @@ static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *stat } } +#if CONFIG_ELOG_GSMI +static void southbridge_smi_gsmi(void) +{ + em64t101_smm_state_save_area_t *io_smi; + u32 base = smi_get_tseg_base() + 0x8000; + u32 *ret, *param; + u8 sub_command, node; + + /* + * Check for Synchronous IO SMI and use save state from that + * core in case we are not running on the same core that + * initiated the IO transaction. + */ + for (node = 0; node < CONFIG_MAX_CPUS; node++) { + /* + * Look for IO Misc Info: + * Synchronous bit[0]=1 + * Byte bit[3:1]=1 + * Output bit[7:4]=0 + * APMC port bit[31:16]=0xb2 + * RAX[7:0] == 0xEF + */ + u32 io_want_info = (APM_CNT << 16) | 0x3; + io_smi = (em64t101_smm_state_save_area_t *) + (base + 0x7d00 - (node * 0x400)); + + if (io_smi->io_misc_info == io_want_info && + ((u8)io_smi->rax == ELOG_GSMI_APM_CNT)) + break; + } + + /* Did not find matching CPU Save State */ + if (node == CONFIG_MAX_CPUS) + return; + + /* Command and return value in EAX */ + ret = (u32*)&io_smi->rax; + sub_command = (u8)(*ret >> 8); + + /* Parameter buffer in EBX */ + param = (u32*)&io_smi->rbx; + + /* drivers/elog/gsmi.c */ + *ret = gsmi_exec(sub_command, param); +} +#endif + static void southbridge_smi_apmc(unsigned int node, smm_state_save_area_t *state_save) { u32 pmctrl; @@ -452,6 +500,11 @@ static void southbridge_smi_apmc(unsigned int node, smm_state_save_area_t *state smm_initialized = 1; printk(BIOS_DEBUG, "SMI#: Setting up structures to %p, %p, %p\n", gnvs, tcg, smi1); break; +#if CONFIG_ELOG_GSMI + case ELOG_GSMI_APM_CNT: + southbridge_smi_gsmi(); + break; +#endif } tseg_relocate((void **)&mainboard_apmc);

1 0

New patch to review for coreboot: e5b0852 ELOG: Add support for SMM and kernel GSMI driver
by Stefan Reinauer 23 Jul '12

23 Jul '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1316 -gerrit commit e5b0852cb546d30252dbec1f323f2ce3292a6c89 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Sat Jun 23 16:48:38 2012 -0700 ELOG: Add support for SMM and kernel GSMI driver The linux kernel contains an SMI driver that was written by me (Duncan) and upstreamed a couple years ago called GSMI. This driver will format a parameter buffer and pass pointers to this parameter buffer to the SMI handler. It uses this to generate events for kernel shutdown reasons: Clean, Panic, Oops, etc. This function expects to be passed pointers into the SMM state save area that correspond to the prameter buffer and the return code, which are typically EAX and EBX. The format of the parameter buffer is defined in the kernel driver so we implement the same interface here in order to be compatible. GSMI_CMD_HANDSHAKE: this is an early call that it does to try and detect what kind of BIOS is running. GSMI_CMD_SET_EVENT_LOG: this contains a parameter buffer that has event type and data. The kernel-specific events are translated here and raw events are passed through as well which allows any run-time event to be added for testing. GSMI_CMD_CLEAR_EVENT_LOG: this command clears the event log. First the gsmi driver must be enabled in the kernel with CONFIG_GOOGLE_GSMI and then events can be added via sysfs and events are automatically generated for various kernel shutdown reasons. These can be seen in the event log as the 'Kernel Event' type: 169 | 2012-06-23 15:03:04 | Kernl Event | Clean Shutdown 181 | 2012-06-23 16:26:32 | Kernl Event | Oops 181 | 2012-06-23 16:26:32 | Kernl Event | Panic Change-Id: Ic0a3916401f0d9811e4aa8b2c560657dccc920c1 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/drivers/elog/Kconfig | 9 +++ src/drivers/elog/Makefile.inc | 2 + src/drivers/elog/gsmi.c | 117 +++++++++++++++++++++++++++++++++++++++++ src/include/elog.h | 4 ++ 4 files changed, 132 insertions(+), 0 deletions(-) diff --git a/src/drivers/elog/Kconfig b/src/drivers/elog/Kconfig index 867416c..7912ab8 100644 --- a/src/drivers/elog/Kconfig +++ b/src/drivers/elog/Kconfig @@ -68,6 +68,15 @@ config ELOG_SHRINK_SIZE endif +config ELOG_GSMI + depends on ELOG && SPI_FLASH_SMM && SMM_TSEG + bool "SMI interface to write and clear event log" + default n + help + This interface is compatible with the linux kernel driver + available with CONFIG_GOOGLE_GSMI and can be used to write + kernel reset/shutdown messages to the event log. + config ELOG_BOOT_COUNT depends on ELOG bool "Maintain a monotonic boot number in CMOS" diff --git a/src/drivers/elog/Makefile.inc b/src/drivers/elog/Makefile.inc index 32509c8..79a7cc0 100644 --- a/src/drivers/elog/Makefile.inc +++ b/src/drivers/elog/Makefile.inc @@ -1,4 +1,6 @@ ramstage-$(CONFIG_ELOG) += elog.c +smm-$(CONFIG_ELOG_GSMI) += elog.c gsmi.c + romstage-$(CONFIG_ELOG_BOOT_COUNT) += boot_count.c ramstage-$(CONFIG_ELOG_BOOT_COUNT) += boot_count.c diff --git a/src/drivers/elog/gsmi.c b/src/drivers/elog/gsmi.c new file mode 100644 index 0000000..dac1af4 --- /dev/null +++ b/src/drivers/elog/gsmi.c @@ -0,0 +1,117 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA + */ + +#include <arch/io.h> +#include <console/console.h> +#include <cpu/x86/smm.h> +#include <elog.h> + +#define GSMI_RET_SUCCESS 0x00 +#define GSMI_RET_INVALID_PARAMETER 0x82 +#define GSMI_RET_UNSUPPORTED 0x83 + +#define GSMI_CMD_SET_EVENT_LOG 0x08 +#define GSMI_CMD_CLEAR_EVENT_LOG 0x09 +#define GSMI_CMD_HANDSHAKE_TYPE 0xc1 + +#define GSMI_HANDSHAKE_NONE 0x7f +#define GSMI_LOG_ENTRY_TYPE_KERNEL 0xDEAD + +struct gsmi_set_eventlog_param { + u32 data_ptr; + u32 data_len; + u32 type; +} __attribute__ ((packed)); + +struct gsmi_set_eventlog_type1 { + u16 type; + u32 instance; +} __attribute__ ((packed)); + +struct gsmi_clear_eventlog_param { + u32 percentage; + u32 data_type; +} __attribute__ ((packed)); + +/* Param is usually EBX, ret in EAX */ +u32 gsmi_exec(u8 command, u32 *param) +{ + struct gsmi_set_eventlog_param *sel; + struct gsmi_set_eventlog_type1 *type1; + struct gsmi_clear_eventlog_param *cel; + u32 ret = GSMI_RET_UNSUPPORTED; + + switch (command) { + case GSMI_CMD_HANDSHAKE_TYPE: + /* Used by kernel to verify basic SMI functionality */ + printk(BIOS_DEBUG, "GSMI Handshake\n"); + ret = GSMI_HANDSHAKE_NONE; + break; + + case GSMI_CMD_SET_EVENT_LOG: + /* Look for a type1 event */ + sel = (struct gsmi_set_eventlog_param *)(*param); + if (!sel) + break; + + /* Make sure the input is usable */ + if (sel->type != 1 && sel->data_ptr != 0 && + sel->data_len != sizeof(struct gsmi_set_eventlog_type1)) + break; + + /* Event structure within the data buffer */ + type1 = (struct gsmi_set_eventlog_type1 *)(sel->data_ptr); + if (!type1) + break; + + printk(BIOS_DEBUG, "GSMI Set Event Log " + "(type=0x%x instance=0x%x)\n", + type1->type, type1->instance); + + if (type1->type == GSMI_LOG_ENTRY_TYPE_KERNEL) { + /* Special case for linux kernel shutdown reason */ + elog_add_event_dword(ELOG_TYPE_OS_EVENT, + type1->instance); + } else { + /* Add other events that may be used for testing */ + elog_add_event_dword(type1->type, type1->instance); + } + ret = GSMI_RET_SUCCESS; + break; + + case GSMI_CMD_CLEAR_EVENT_LOG: + /* Get paramter buffer even though we don't use it */ + cel = (struct gsmi_clear_eventlog_param *)(*param); + if (!cel) + break; + + printk(BIOS_DEBUG, "GSMI Clear Event Log (%u%% type=%u)\n", + cel->percentage, cel->data_type); + + if (elog_clear() == 0) + ret = GSMI_RET_SUCCESS; + break; + + default: + printk(BIOS_DEBUG, "GSMI Unknown: 0x%02x\n", command); + break; + } + + return ret; +} diff --git a/src/include/elog.h b/src/include/elog.h index 0542f68..7d89f45 100644 --- a/src/include/elog.h +++ b/src/include/elog.h @@ -115,6 +115,10 @@ extern void elog_add_event_dword(u8 event_type, u32 data); extern void elog_add_event_wake(u8 source, u32 instance); extern int elog_smbios_write_type15(unsigned long *current, int handle); +#if CONFIG_ELOG_GSMI +extern u32 gsmi_exec(u8 command, u32 *param); +#endif + #if CONFIG_ELOG_BOOT_COUNT u32 boot_count_read(void); u32 boot_count_increment(void);

1 0

New patch to review for coreboot: 4f4dda8 ELOG: Add support for a monotonic boot counter in CMOS
by Stefan Reinauer 23 Jul '12

23 Jul '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1315 -gerrit commit 4f4dda816d74613c463838fde8a4abb1da19c4e8 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Sat Jun 23 16:37:45 2012 -0700 ELOG: Add support for a monotonic boot counter in CMOS This maintains a 32bit monotonically increasing boot counter that is stored in CMOS and logged on every non-S3 boot when the event log is initialized. In CMOS the count is prefixed with a 16bit signature and appended with a 16bit checksum. This counter is incremented in sandybridge early_init which is called by romstage. It is incremented early in order notice when reboots happen after memory init. The counter is then logged when ELOG is initialized and will store the boot count as part of a 'System boot; event. Reboot a few times and look for 'System boot' events in the event log and check that they are increasing. Also verify that the counter does NOT increase when resuming from S3. 171 | 2012-06-23 16:02:55 | System boot | 285 176 | 2012-06-23 16:26:00 | System boot | 286 182 | 2012-06-23 16:27:04 | System boot | 287 189 | 2012-06-23 16:31:10 | System boot | 288 Change-Id: I23faeafcf155edfd10aa6882598b3883575f8a33 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/drivers/elog/Kconfig | 17 ++++ src/drivers/elog/Makefile.inc | 3 + src/drivers/elog/boot_count.c | 122 ++++++++++++++++++++++++ src/drivers/elog/elog.c | 6 + src/include/elog.h | 5 + src/northbridge/intel/sandybridge/early_init.c | 8 ++ 6 files changed, 161 insertions(+), 0 deletions(-) diff --git a/src/drivers/elog/Kconfig b/src/drivers/elog/Kconfig index d61dd10..867416c 100644 --- a/src/drivers/elog/Kconfig +++ b/src/drivers/elog/Kconfig @@ -67,3 +67,20 @@ config ELOG_SHRINK_SIZE Default is 1K. endif + +config ELOG_BOOT_COUNT + depends on ELOG + bool "Maintain a monotonic boot number in CMOS" + default n + help + Store a monotonic boot number in CMOS and provide an interface + to read the current value and increment the counter. This boot + counter will be logged as part of the System Boot event. + +config ELOG_BOOT_COUNT_CMOS_OFFSET + depends on ELOG && ELOG_BOOT_COUNT && !USE_OPTION_TABLE + int "Offset in CMOS to store the boot count" + default 0 + help + This value must be greater than 16 bytes so as not to interfere + with the standard RTC region. Requires 8 bytes. diff --git a/src/drivers/elog/Makefile.inc b/src/drivers/elog/Makefile.inc index a01841d..32509c8 100644 --- a/src/drivers/elog/Makefile.inc +++ b/src/drivers/elog/Makefile.inc @@ -1 +1,4 @@ ramstage-$(CONFIG_ELOG) += elog.c + +romstage-$(CONFIG_ELOG_BOOT_COUNT) += boot_count.c +ramstage-$(CONFIG_ELOG_BOOT_COUNT) += boot_count.c diff --git a/src/drivers/elog/boot_count.c b/src/drivers/elog/boot_count.c new file mode 100644 index 0000000..9ea828d --- /dev/null +++ b/src/drivers/elog/boot_count.c @@ -0,0 +1,122 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA + */ + +#include <console/console.h> +#include <ip_checksum.h> +#include <pc80/mc146818rtc.h> +#include <stddef.h> +#include <stdint.h> +#include <elog.h> + +/* + * We need a region in CMOS to store the boot counter. + * + * This can either be declared as part of the option + * table or statically defined in the board config. + */ +#if CONFIG_USE_OPTION_TABLE +# include "option_table.h" +# define BOOT_COUNT_CMOS_OFFSET (CMOS_VSTART_boot_count_offset >> 3) +#else +# if defined(CONFIG_ELOG_BOOT_COUNT_CMOS_OFFSET) +# define BOOT_COUNT_CMOS_OFFSET CONFIG_ELOG_BOOT_COUNT_CMOS_OFFSET +# else +# error "Must define CONFIG_ELOG_BOOT_COUNT_CMOS_OFFSET" +# endif +#endif + +#define BOOT_COUNT_SIGNATURE 0x4342 /* 'BC' */ + +struct boot_count { + u16 signature; + u32 count; + u16 checksum; +} __attribute__ ((packed)); + +/* Read and validate boot count structure from CMOS */ +static int boot_count_cmos_read(struct boot_count *bc) +{ + u8 i, *p; + u16 csum; + + for (p = (u8*)bc, i = 0; i < sizeof(*bc); i++, p++) + *p = cmos_read(BOOT_COUNT_CMOS_OFFSET + i); + + /* Verify signature */ + if (bc->signature != BOOT_COUNT_SIGNATURE) { + printk(BIOS_DEBUG, "Boot Count invalid signature\n"); + return -1; + } + + /* Verify checksum over signature and counter only */ + csum = compute_ip_checksum(bc, offsetof(struct boot_count, checksum)); + + if (csum != bc->checksum) { + printk(BIOS_DEBUG, "Boot Count checksum mismatch\n"); + return -1; + } + + return 0; +} + +/* Write boot count structure to CMOS */ +static void boot_count_cmos_write(struct boot_count *bc) +{ + u8 i, *p; + + /* Checksum over signature and counter only */ + bc->checksum = compute_ip_checksum( + bc, offsetof(struct boot_count, checksum)); + + for (p = (u8*)bc, i = 0; i < sizeof(*bc); i++, p++) + cmos_write(*p, BOOT_COUNT_CMOS_OFFSET + i); +} + +/* Increment boot count and return the new value */ +u32 boot_count_increment(void) +{ + struct boot_count bc; + + /* Read and increment boot count */ + if (boot_count_cmos_read(&bc) < 0) { + /* Structure invalid, re-initialize */ + bc.signature = BOOT_COUNT_SIGNATURE; + bc.count = 0; + } + + /* Increment boot counter */ + bc.count++; + + /* Write the new count to CMOS */ + boot_count_cmos_write(&bc); + + printk(BIOS_DEBUG, "Boot Count incremented to %u\n", bc.count); + return bc.count; +} + +/* Return the current boot count */ +u32 boot_count_read(void) +{ + struct boot_count bc; + + if (boot_count_cmos_read(&bc) < 0) + return 0; + + return bc.count; +} diff --git a/src/drivers/elog/elog.c b/src/drivers/elog/elog.c index 9c0fa93..1219883 100644 --- a/src/drivers/elog/elog.c +++ b/src/drivers/elog/elog.c @@ -780,6 +780,12 @@ int elog_init(void) elog_add_event_word(ELOG_TYPE_LOG_CLEAR, elog_get_flash()->total_size); +#if CONFIG_ELOG_BOOT_COUNT && !defined(__SMM__) + /* Log boot count event except in S3 resume */ + if (acpi_slp_type != 3) + elog_add_event_dword(ELOG_TYPE_BOOT, boot_count_read()); +#endif + return 0; } diff --git a/src/include/elog.h b/src/include/elog.h index 897a90b..0542f68 100644 --- a/src/include/elog.h +++ b/src/include/elog.h @@ -115,6 +115,11 @@ extern void elog_add_event_dword(u8 event_type, u32 data); extern void elog_add_event_wake(u8 source, u32 instance); extern int elog_smbios_write_type15(unsigned long *current, int handle); +#if CONFIG_ELOG_BOOT_COUNT +u32 boot_count_read(void); +u32 boot_count_increment(void); +#endif + #endif /* !CONFIG_ELOG */ #endif /* ELOG_H_ */ diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c index c7afa11..6bd774b 100644 --- a/src/northbridge/intel/sandybridge/early_init.c +++ b/src/northbridge/intel/sandybridge/early_init.c @@ -24,6 +24,7 @@ #include <arch/io.h> #include <arch/romcc_io.h> #include <device/pci_def.h> +#include <elog.h> #include "sandybridge.h" #include "pcie_config.c" @@ -63,6 +64,13 @@ static void sandybridge_setup_bars(void) pci_write_config8(PCI_DEV(0, 0x00, 0), PAM5, 0x33); pci_write_config8(PCI_DEV(0, 0x00, 0), PAM6, 0x33); +#if CONFIG_ELOG_BOOT_COUNT + /* Increment Boot Counter for non-S3 resume */ + if ((inw(DEFAULT_PMBASE + PM1_STS) & WAK_STS) && + ((inl(DEFAULT_PMBASE + PM1_CNT) >> 10) & 7) != SLP_TYP_S3) + boot_count_increment(); +#endif + printk(BIOS_DEBUG, " done.\n"); }

1 0

New patch to review for coreboot: 57a75b6 ELOG: Add support for generating SMBIOS type15 table
by Stefan Reinauer 23 Jul '12

23 Jul '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1314 -gerrit commit 57a75b64ce14f968a4ea251da53fef3b4c3983f3 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Sat Jun 23 16:13:42 2012 -0700 ELOG: Add support for generating SMBIOS type15 table This standared SMBIOS 0able describes the location and format of the event log to the OS and applications. In this case the pointer is a 32bit physical address pointer to the log in memory mapped flash. Look for SMBIOS type15 entry with 'dmidecode -t 15' Handle 0x0004, DMI type 15, 23 bytes System Event Log Area Length: 4095 bytes Header Start Offset: 0x0000 Header Length: 8 bytes Data Start Offset: 0x0008 Access Method: Memory-mapped physical 32-bit address Access Address: 0xFFB6F000 Status: Valid, Not Full Change Token: 0x00000000 Header Format: OEM-specific Supported Log Type Descriptors: 0 Change-Id: I1e7729e604000f197e26e69991a2867e869197a6 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/arch/x86/boot/smbios.c | 4 ++++ src/drivers/elog/elog.c | 29 +++++++++++++++++++++++++++++ src/drivers/elog/elog_internal.h | 15 +++++++++++++++ src/include/elog.h | 1 + src/include/smbios.h | 31 +++++++++++++++++++++++++++++++ 5 files changed, 80 insertions(+), 0 deletions(-) diff --git a/src/arch/x86/boot/smbios.c b/src/arch/x86/boot/smbios.c index 3b9e5a1..9c61e28 100644 --- a/src/arch/x86/boot/smbios.c +++ b/src/arch/x86/boot/smbios.c @@ -29,6 +29,7 @@ #include <cpu/x86/name.h> #include <cbfs_core.h> #include <arch/byteorder.h> +#include <elog.h> #if CONFIG_CHROMEOS #include <vendorcode/google/chromeos/gnvs.h> #endif @@ -296,6 +297,9 @@ unsigned long smbios_write_tables(unsigned long current) len += smbios_write_type1(&current, handle++); len += smbios_write_type3(&current, handle++); len += smbios_write_type4(&current, handle++); +#if CONFIG_ELOG + len += elog_smbios_write_type15(&current, handle++); +#endif len += smbios_write_type32(&current, handle++); len += smbios_walk_device_tree(all_devices, &handle, &current); diff --git a/src/drivers/elog/elog.c b/src/drivers/elog/elog.c index 8e56b85..9c0fa93 100644 --- a/src/drivers/elog/elog.c +++ b/src/drivers/elog/elog.c @@ -20,6 +20,7 @@ #include <arch/acpi.h> #include <console/console.h> #include <pc80/mc146818rtc.h> +#include <smbios.h> #include <spi.h> #include <spi_flash.h> #include <stdint.h> @@ -677,6 +678,34 @@ static int elog_spi_init(void) } /* + * Fill out SMBIOS Type 15 table entry so the + * event log can be discovered at runtime. + */ +int elog_smbios_write_type15(unsigned long *current, int handle) +{ + struct smbios_type15 *t = (struct smbios_type15 *)*current; + int len = sizeof(struct smbios_type15); + + memset(t, 0, len); + t->type = SMBIOS_EVENT_LOG; + t->length = len - 2; + t->handle = handle; + t->area_length = elog_get_flash()->total_size - 1; + t->header_offset = 0; + t->data_offset = sizeof(struct elog_header); + t->access_method = SMBIOS_EVENTLOG_ACCESS_METHOD_MMIO32; + t->log_status = SMBIOS_EVENTLOG_STATUS_VALID; + t->change_token = 0; + t->address = (u32)elog_get_flash()->backing_store; + t->header_format = ELOG_HEADER_TYPE_OEM; + t->log_type_descriptors = 0; + t->log_type_descriptor_length = 2; + + *current += len; + return len; +} + +/* * Clear the entire event log */ int elog_clear(void) diff --git a/src/drivers/elog/elog_internal.h b/src/drivers/elog/elog_internal.h index 2a6a0b7..6d9a0d4 100644 --- a/src/drivers/elog/elog_internal.h +++ b/src/drivers/elog/elog_internal.h @@ -32,6 +32,21 @@ struct elog_header { #define ELOG_SIGNATURE 0x474f4c45 /* 'ELOG' */ #define ELOG_VERSION 1 +/* SMBIOS event log header */ +struct event_header { + u8 type; + u8 length; + u8 year; + u8 month; + u8 day; + u8 hour; + u8 minute; + u8 second; +} __attribute__ ((packed)); + +/* SMBIOS Type 15 related constants */ +#define ELOG_HEADER_TYPE_OEM 0x88 + typedef enum elog_descriptor_type { ELOG_DESCRIPTOR_UNKNOWN, ELOG_DESCRIPTOR_MEMORY, diff --git a/src/include/elog.h b/src/include/elog.h index c6599a2..897a90b 100644 --- a/src/include/elog.h +++ b/src/include/elog.h @@ -113,6 +113,7 @@ extern void elog_add_event_byte(u8 event_type, u8 data); extern void elog_add_event_word(u8 event_type, u16 data); extern void elog_add_event_dword(u8 event_type, u32 data); extern void elog_add_event_wake(u8 source, u32 instance); +extern int elog_smbios_write_type15(unsigned long *current, int handle); #endif /* !CONFIG_ELOG */ diff --git a/src/include/smbios.h b/src/include/smbios.h index 7912ba1..c658515 100644 --- a/src/include/smbios.h +++ b/src/include/smbios.h @@ -28,6 +28,7 @@ typedef enum { SMBIOS_PROCESSOR_INFORMATION=4, SMBIOS_CACHE_INFORMATION=7, SMBIOS_SYSTEM_SLOTS=9, + SMBIOS_EVENT_LOG=15, SMBIOS_PHYS_MEMORY_ARRAY=16, SMBIOS_MEMORY_DEVICE=17, SMBIOS_MEMORY_ARRAY_MAPPED_ADDRESS=19, @@ -138,6 +139,36 @@ struct smbios_type4 { char eos[2]; } __attribute__((packed)); +struct smbios_type15 { + u8 type; + u8 length; + u16 handle; + u16 area_length; + u16 header_offset; + u16 data_offset; + u8 access_method; + u8 log_status; + u32 change_token; + u32 address; + u8 header_format; + u8 log_type_descriptors; + u8 log_type_descriptor_length; + char eos[2]; +} __attribute__((packed)); + +enum { + SMBIOS_EVENTLOG_ACCESS_METHOD_IO8 = 0, + SMBIOS_EVENTLOG_ACCESS_METHOD_IO8X2, + SMBIOS_EVENTLOG_ACCESS_METHOD_IO16, + SMBIOS_EVENTLOG_ACCESS_METHOD_MMIO32, + SMBIOS_EVENTLOG_ACCESS_METHOD_GPNV, +}; + +enum { + SMBIOS_EVENTLOG_STATUS_VALID = 1, /* Bit 0 */ + SMBIOS_EVENTLOG_STATUS_FULL = 2, /* Bit 1 */ +}; + struct smbios_type16 { u8 type; u8 length;

1 0

New patch to review for coreboot: 857f723 SMM: Add option for SPI driver to be available in SMM
by Stefan Reinauer 23 Jul '12

23 Jul '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1313 -gerrit commit 857f723d69b14fa52a3ab3c1c515d2303e75c8cb Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Sat Jun 23 16:53:57 2012 -0700 SMM: Add option for SPI driver to be available in SMM - add Kconfig option for CONFIG_SPI_FLASH_SMM - compile subsystem and chip drivers for smm if enabled - change mdelay(1) to udelay(500) since mdelay is not defined in SMM and a 1ms delay is worth avoiding - make flash chip structure non-const so the probe function pointers can be relocated for use in TSEG - Make SMM PCI access possible in southbridge SPI code Change-Id: Icfcbbe8e4e56658769d46af0b5bf6c79a6432641 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/drivers/spi/Kconfig | 7 ++++ src/drivers/spi/Makefile.inc | 13 ++++++++ src/drivers/spi/spi_flash.c | 11 ++++++- src/southbridge/intel/bd82x6x/Makefile.inc | 1 + src/southbridge/intel/bd82x6x/spi.c | 43 +++++++++++++++++++++++---- 5 files changed, 66 insertions(+), 9 deletions(-) diff --git a/src/drivers/spi/Kconfig b/src/drivers/spi/Kconfig index ee7584c..e022290 100644 --- a/src/drivers/spi/Kconfig +++ b/src/drivers/spi/Kconfig @@ -24,6 +24,13 @@ config SPI_FLASH Select this option if your chipset driver needs to store certain data in the SPI flash. +config SPI_FLASH_SMM + bool "SPI flash driver support in SMM" + default n + depends on SPI_FLASH && HAVE_SMI_HANDLER + help + Select this option if you want SPI flash support in SMM. + config SPI_FLASH_EON bool default y diff --git a/src/drivers/spi/Makefile.inc b/src/drivers/spi/Makefile.inc index 1814e80..7f94abd 100644 --- a/src/drivers/spi/Makefile.inc +++ b/src/drivers/spi/Makefile.inc @@ -10,3 +10,16 @@ ramstage-$(CONFIG_SPI_FLASH_STMICRO) += stmicro.c ramstage-$(CONFIG_SPI_FLASH_WINBOND) += winbond.c ramstage-$(CONFIG_SPI_FRAM_RAMTRON) += ramtron.c +ifeq ($(CONFIG_SPI_FLASH_SMM),y) +# SPI flash driver interface +smm-$(CONFIG_SPI_FLASH) += spi_flash.c + +# drivers +smm-$(CONFIG_SPI_FLASH_EON) += eon.c +smm-$(CONFIG_SPI_FLASH_MACRONIX) += macronix.c +smm-$(CONFIG_SPI_FLASH_SPANSION) += spansion.c +smm-$(CONFIG_SPI_FLASH_SST) += sst.c +smm-$(CONFIG_SPI_FLASH_STMICRO) += stmicro.c +smm-$(CONFIG_SPI_FLASH_WINBOND) += winbond.c +smm-$(CONFIG_SPI_FRAM_RAMTRON) += ramtron.c +endif \ No newline at end of file diff --git a/src/drivers/spi/spi_flash.c b/src/drivers/spi/spi_flash.c index 6cec611..78c209d 100644 --- a/src/drivers/spi/spi_flash.c +++ b/src/drivers/spi/spi_flash.c @@ -12,6 +12,9 @@ #include <spi.h> #include <spi_flash.h> #include <delay.h> +#ifdef __SMM__ +#include <cpu/x86/smm.h> +#endif #include "spi_flash_internal.h" static void spi_flash_addr(u32 addr, u8 *cmd) @@ -115,7 +118,7 @@ int spi_flash_cmd_poll_bit(struct spi_flash *flash, unsigned long timeout, if ((status & poll_bit) == 0) break; - mdelay(1); + udelay(500); } while (timebase--); if ((status & poll_bit) == 0) @@ -206,7 +209,7 @@ out: */ #define IDCODE_CONT_LEN 0 #define IDCODE_PART_LEN 5 -static const struct { +static struct { const u8 shift; const u8 idcode; struct spi_flash *(*probe) (struct spi_slave *spi, u8 *idcode); @@ -275,6 +278,10 @@ struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs, /* search the table for matches in shift and id */ for (i = 0; i < ARRAY_SIZE(flashes); ++i) if (flashes[i].shift == shift && flashes[i].idcode == *idp) { +#ifdef __SMM__ + /* Need to relocate this function */ + tseg_relocate((void **)&flashes[i].probe); +#endif /* we have a match, call probe */ flash = flashes[i].probe(spi, idp); if (flash) diff --git a/src/southbridge/intel/bd82x6x/Makefile.inc b/src/southbridge/intel/bd82x6x/Makefile.inc index 11a6b08..3de2bd0 100644 --- a/src/southbridge/intel/bd82x6x/Makefile.inc +++ b/src/southbridge/intel/bd82x6x/Makefile.inc @@ -33,6 +33,7 @@ ramstage-y += reset.c ramstage-y += watchdog.c ramstage-y += spi.c +smm-$(CONFIG_SPI_FLASH_SMM) += spi.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c me.c me_8.x.c finalize.c diff --git a/src/southbridge/intel/bd82x6x/spi.c b/src/southbridge/intel/bd82x6x/spi.c index 4cd9af0..6b39571 100644 --- a/src/southbridge/intel/bd82x6x/spi.c +++ b/src/southbridge/intel/bd82x6x/spi.c @@ -27,20 +27,45 @@ #include <delay.h> #include <arch/io.h> #include <console/console.h> -#include <device/pci.h> #include <device/pci_ids.h> #include <spi.h> #define min(a, b) ((a)<(b)?(a):(b)) +#ifdef __SMM__ +#include <arch/romcc_io.h> +#include <northbridge/intel/sandybridge/pcie_config.c> +typedef device_t pci_dev_t; +#define pci_read_config_byte(dev, reg, targ)\ + *(targ) = pcie_read_config8(dev, reg) +#define pci_read_config_word(dev, reg, targ)\ + *(targ) = pcie_read_config16(dev, reg) +#define pci_read_config_dword(dev, reg, targ)\ + *(targ) = pcie_read_config32(dev, reg) +#define pci_write_config_byte(dev, reg, val)\ + pcie_write_config8(dev, reg, val) +#define pci_write_config_word(dev, reg, val)\ + pcie_write_config16(dev, reg, val) +#define pci_write_config_dword(dev, reg, val)\ + pcie_write_config32(dev, reg, val) +#else /* !__SMM__ */ +#include <device/device.h> +#include <device/pci.h> typedef device_t pci_dev_t; -#define pci_read_config_byte(dev, reg, targ) *(targ) = pci_read_config8(dev, reg) -#define pci_read_config_word(dev, reg, targ) *(targ) = pci_read_config16(dev, reg) -#define pci_read_config_dword(dev, reg, targ) *(targ) = pci_read_config32(dev, reg) -#define pci_write_config_byte(dev, reg, val) pci_write_config8(dev, reg, val) -#define pci_write_config_word(dev, reg, val) pci_write_config16(dev, reg, val) -#define pci_write_config_dword(dev, reg, val) pci_write_config32(dev, reg, val) +#define pci_read_config_byte(dev, reg, targ)\ + *(targ) = pci_read_config8(dev, reg) +#define pci_read_config_word(dev, reg, targ)\ + *(targ) = pci_read_config16(dev, reg) +#define pci_read_config_dword(dev, reg, targ)\ + *(targ) = pci_read_config32(dev, reg) +#define pci_write_config_byte(dev, reg, val)\ + pci_write_config8(dev, reg, val) +#define pci_write_config_word(dev, reg, val)\ + pci_write_config16(dev, reg, val) +#define pci_write_config_dword(dev, reg, val)\ + pci_write_config32(dev, reg, val) +#endif /* !__SMM__ */ typedef struct spi_slave ich_spi_slave; @@ -310,7 +335,11 @@ void spi_init(void) uint32_t ids; uint16_t vendor_id, device_id; +#ifdef __SMM__ + dev = PCI_DEV(0, 31, 0); +#else dev = dev_find_slot(0, PCI_DEVFN(31, 0)); +#endif pci_read_config_dword(dev, 0, &ids); vendor_id = ids; device_id = (ids >> 16);

1 0

New patch to review for coreboot: c3c95f4 SMM: Add support for malloc in SMM if using TSEG
by Stefan Reinauer 23 Jul '12

23 Jul '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1312 -gerrit commit c3c95f4dd8516b21a68193072f21418517a8a06f Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Sat Jun 23 13:33:32 2012 -0700 SMM: Add support for malloc in SMM if using TSEG This is used by the SPI driver and ELOG. It requires SMM TSEG and a _heap/_eheap region defined in the linker script. The first time malloc is called in SMM the start and end pointers to the heap region will be relocated for the TSEG region. Enable SPI flash and ELOG in SMM and successfully allocate memory. The allocated addresses are verified to be sure they are within the TSEG heap region: smm.elf:00014000 B _eheap smm.elf:00010000 B _heap TSEG base is 0xad000000 Memory allocated in ELOG: ELOG: MEM @0xad018030 Change-Id: I5cca38e4888d597cbbfcd9983cd6a7ae3600c2a3 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/console/Makefile.inc | 1 + src/lib/Makefile.inc | 1 + src/lib/malloc.c | 9 +++++++++ 3 files changed, 11 insertions(+), 0 deletions(-) diff --git a/src/console/Makefile.inc b/src/console/Makefile.inc index f3b8758..f8928ad 100644 --- a/src/console/Makefile.inc +++ b/src/console/Makefile.inc @@ -7,6 +7,7 @@ ramstage-y += die.c smm-y += printk.c smm-y += vtxprintf.c +smm-$(CONFIG_SMM_TSEG) += die.c romstage-y += vtxprintf.c romstage-$(CONFIG_CACHE_AS_RAM) += console.c diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index a3235a2..ec57bc2 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -32,6 +32,7 @@ endif ramstage-y += memcmp.c ramstage-y += memmove.c ramstage-y += malloc.c +smm-$(CONFIG_SMM_TSEG) += malloc.c ramstage-y += delay.c ramstage-y += fallback_boot.c ramstage-y += compute_ip_checksum.c diff --git a/src/lib/malloc.c b/src/lib/malloc.c index d2011a1..43e514a 100644 --- a/src/lib/malloc.c +++ b/src/lib/malloc.c @@ -1,5 +1,8 @@ #include <stdlib.h> #include <console/console.h> +#ifdef __SMM__ +#include <cpu/x86/smm.h> +#endif #if CONFIG_DEBUG_MALLOC #define MALLOCDBG(x...) printk(BIOS_SPEW, x) @@ -43,5 +46,11 @@ void *memalign(size_t boundary, size_t size) void *malloc(size_t size) { +#if CONFIG_SMM_TSEG && defined(__SMM__) + if (!free_mem_ptr) { + free_mem_ptr = &_heap + smi_get_tseg_base(); + free_mem_end_ptr = &_eheap + smi_get_tseg_base(); + } +#endif return memalign(sizeof(u64), size); }

1 0

New patch to review for coreboot: 55e6e71 ELOG: Add support for flash based event log
by Stefan Reinauer 23 Jul '12

23 Jul '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1311 -gerrit commit 55e6e71a6cfa49480e2789aa74746c530d578e10 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Sat Jun 23 16:08:47 2012 -0700 ELOG: Add support for flash based event log This is based around the SMBIOS event log specification but expanded with OEM event types to support more specific and relevant system events. It requires flash storage and a minimum 4K block (or flash block size) that should be allocated in the FMAP. A copy of the event log is maintained in memory for convenience and speed and the in-memory copy is written to flash at specific points. The log is automatically shunk when it reaches a configurable full threshold in order to not get stuck with a full log that needs OS help to clear. ELOG implements the specification published here: http://code.google.com/p/firmware-event-log/wiki/FirmwareEventLogDesign And is similar to what we use in other firmware at Google. This implementation does not support double-buffered flash regions. This is done because speed is valued over the log reliability and it keeps the code simpler for the first version. This is a large commit and by itself it just provides a new driver that is made available to coreboot. Without additional patches it is not very useful, but the end result is an event log that will contain entries like this: 171 | 2012-06-23 16:02:55 | System boot | 285 172 | 2012-06-23 16:02:55 | EC Event | Power Button 173 | 2012-06-23 16:02:55 | SUS Power Fail 174 | 2012-06-23 16:02:55 | System Reset 175 | 2012-06-23 16:02:55 | ACPI Wake | S5 Change-Id: I985524c67f525c8a268eccbd856c1a4c2a426889 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/drivers/Kconfig | 1 + src/drivers/Makefile.inc | 1 + src/drivers/elog/Kconfig | 69 +++ src/drivers/elog/Makefile.inc | 1 + src/drivers/elog/elog.c | 880 ++++++++++++++++++++++++++++++++++++++ src/drivers/elog/elog_internal.h | 76 ++++ src/include/elog.h | 119 +++++ 7 files changed, 1147 insertions(+), 0 deletions(-) diff --git a/src/drivers/Kconfig b/src/drivers/Kconfig index 89cdf6a..da90a03 100644 --- a/src/drivers/Kconfig +++ b/src/drivers/Kconfig @@ -28,3 +28,4 @@ source src/drivers/trident/Kconfig source src/drivers/ics/Kconfig source src/drivers/spi/Kconfig source src/drivers/ipmi/Kconfig +source src/drivers/elog/Kconfig diff --git a/src/drivers/Makefile.inc b/src/drivers/Makefile.inc index 6c63a6a..e10e685 100644 --- a/src/drivers/Makefile.inc +++ b/src/drivers/Makefile.inc @@ -28,4 +28,5 @@ subdirs-y += trident subdirs-y += ics subdirs-y += spi subdirs-y += ipmi +subdirs-y += elog subdirs-$(CONFIG_ARCH_X86) += pc80 diff --git a/src/drivers/elog/Kconfig b/src/drivers/elog/Kconfig new file mode 100644 index 0000000..d61dd10 --- /dev/null +++ b/src/drivers/elog/Kconfig @@ -0,0 +1,69 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2012 The Chromium OS Authors. All rights reserved. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +config ELOG + depends on SPI_FLASH + bool "Support for flash based event log" + default n + help + Enable support for flash based event logging. + +if ELOG + +config ELOG_DEBUG + bool "Enable debug output for event logging" + default n + +config ELOG_FLASH_BASE + hex "Event log offset into flash" + default 0 + help + Offset into the flash chip for the ELOG block. + This should be allocated in the FMAP. + +config ELOG_AREA_SIZE + hex "Size of Event Log area in flash" + default 0x1000 + help + This should be a multiple of flash block size. + + Default is 4K. + +config ELOG_FULL_THRESHOLD + hex "Threshold at which flash is considered full" + default 0xC00 + help + When the Event Log size is larger than this it will be shrunk + to ELOG_SHRINK_SIZE. Must be greater than ELOG_AREA_SIZE, and + ELOG_AREA_SIZE - ELOG_FULL_THRESHOLD must be greater than the + maximum event size of 128. + + Default is 75% of the log, or 3K. + +config ELOG_SHRINK_SIZE + hex "Resulting size when the event log is shrunk" + default 0x400 + help + When the Event Log is shrunk it will go to this size. + ELOG_AREA_SIZE - ELOG_SHRINK_SIZE must be less than + CONFIG_ELOG_FULL_THRESHOLD. + + Default is 1K. + +endif diff --git a/src/drivers/elog/Makefile.inc b/src/drivers/elog/Makefile.inc new file mode 100644 index 0000000..a01841d --- /dev/null +++ b/src/drivers/elog/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_ELOG) += elog.c diff --git a/src/drivers/elog/elog.c b/src/drivers/elog/elog.c new file mode 100644 index 0000000..8e56b85 --- /dev/null +++ b/src/drivers/elog/elog.c @@ -0,0 +1,880 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA + */ + +#include <arch/acpi.h> +#include <console/console.h> +#include <pc80/mc146818rtc.h> +#include <spi.h> +#include <spi_flash.h> +#include <stdint.h> +#include <string.h> +#include <elog.h> +#include "elog_internal.h" + +#if CONFIG_ELOG_FLASH_BASE == 0 +#error "CONFIG_ELOG_FLASH_BASE is invalid" +#endif +#if CONFIG_ELOG_FULL_THRESHOLD >= CONFIG_ELOG_AREA_SIZE +#error "CONFIG_ELOG_FULL_THRESHOLD is larger than CONFIG_ELOG_AREA_SIZE" +#endif +#if (CONFIG_ELOG_AREA_SIZE - CONFIG_ELOG_FULL_THRESHOLD) < (MAX_EVENT_SIZE + 1) +#error "CONFIG_ELOG_FULL_THRESHOLD is too small" +#endif +#if CONFIG_ELOG_SHRINK_SIZE >= CONFIG_ELOG_AREA_SIZE +#error "CONFIG_ELOG_SHRINK_SIZE is larger than CONFIG_ELOG_AREA_SIZE" +#endif +#if (CONFIG_ELOG_AREA_SIZE - CONFIG_ELOG_SHRINK_SIZE) > \ + CONFIG_ELOG_FULL_THRESHOLD +#error "CONFIG_ELOG_SHRINK_SIZE is too large" +#endif + +#if CONFIG_ELOG_DEBUG +#define elog_debug(STR...) printk(BIOS_DEBUG, STR) +#else +#define elog_debug(STR...) +#endif + +/* + * Static variables for ELOG state + */ +static int elog_initialized; +static struct spi_flash *elog_spi; +static struct elog_descriptor elog_flash_area; +static struct elog_descriptor elog_mem_area; + +static inline struct elog_descriptor* elog_get_mem(void) +{ + return &elog_mem_area; +} + +static inline struct elog_descriptor* elog_get_flash(void) +{ + return &elog_flash_area; +} + +/* + * Convert a memory mapped flash address into a flash offset + */ +static inline u32 elog_flash_address_to_offset(u8 *address) +{ + if (!elog_spi) + return 0; + return (u32)address - ((u32)~0UL - elog_spi->size + 1); +} + +/* + * Convert a flash offset into a memory mapped flash address + */ +static inline u8* elog_flash_offset_to_address(u32 offset) +{ + if (!elog_spi) + return NULL; + return (u8*)((u32)~0UL - elog_spi->size + 1 + offset); +} + +/* + * The ELOG header is at the very beginning of the area + */ +static inline struct elog_header* +elog_get_header(struct elog_descriptor *elog) +{ + return elog->backing_store; +} + +/* + * Pointer to an event log header in the event data area + */ +static inline struct event_header* +elog_get_event_base(struct elog_descriptor *elog, u32 offset) +{ + return (struct event_header *)&elog->data[offset]; +} + +/* + * Pointer to where the next event should be stored + */ +static inline struct event_header* +elog_get_next_event_base(struct elog_descriptor *elog) +{ + return elog_get_event_base(elog, elog->next_event_offset); +} + +/* + * Pointer to the last logged event + */ +static inline struct event_header* +elog_get_last_event_base(struct elog_descriptor *elog) +{ + return elog_get_event_base(elog, elog->last_event_offset); +} + +/* + * Update the checksum at the last byte + */ +static void elog_update_checksum(struct event_header *event, u8 checksum) +{ + u8 *event_data = (u8*)event; + event_data[event->length - 1] = checksum; +} + +/* + * Simple byte checksum for events + */ +static u8 elog_checksum_event(struct event_header *event) +{ + u8 index, checksum = 0; + u8 *data = (u8*)event; + + for (index = 0; index < event->length; index++) + checksum += data[index]; + return checksum; +} + +/* + * Check if a raw buffer is filled with ELOG_TYPE_EOL byte + */ +static int elog_is_buffer_clear(u8 *base, u32 size) +{ + u8 *current = base; + u8 *end = current + size; + + elog_debug("elog_is_buffer_clear(base=0x%p size=%u)\n", base, size); + + for (; current != end; current++) { + if (*current != ELOG_TYPE_EOL) + return 0; + } + return 1; +} + +/* + * Verify whether ELOG area is filled with ELOG_TYPE_EOL byte + */ +static int elog_is_area_clear(struct elog_descriptor *elog) +{ + return elog_is_buffer_clear(elog->backing_store, elog->total_size); +} + +/* + * Check that the ELOG area has been initialized and is valid. + */ +static int elog_is_area_valid(struct elog_descriptor *elog) +{ + elog_debug("elog_is_area_valid()\n"); + + if (elog->area_state != ELOG_AREA_HAS_CONTENT) + return 0; + if (elog->header_state != ELOG_HEADER_VALID) + return 0; + if (elog->event_buffer_state != ELOG_EVENT_BUFFER_OK) + return 0; + return 1; +} + +/* + * Verify the contents of an ELOG Header structure + * Returns 1 if the header is valid, 0 otherwise + */ +static int elog_is_header_valid(struct elog_header *header) +{ + elog_debug("elog_is_header_valid()\n"); + + if (header->magic != ELOG_SIGNATURE) { + printk(BIOS_ERR, "ELOG: header magic 0x%X != 0x%X\n", + header->magic, ELOG_SIGNATURE); + return 0; + } + if (header->version != ELOG_VERSION) { + printk(BIOS_ERR, "ELOG: header version %u != %u\n", + header->version, ELOG_VERSION); + return 0; + } + if (header->header_size != sizeof(*header)) { + printk(BIOS_ERR, "ELOG: header size mismatch %u != %u\n", + header->header_size, sizeof(*header)); + return 0; + } + return 1; +} + +/* + * Validate the event header and data. + */ +static int elog_is_event_valid(struct elog_descriptor *elog, u32 offset) +{ + struct event_header *event; + + event = elog_get_event_base(elog, offset); + if (!event) + return 0; + + /* Validate event length */ + if ((offsetof(struct event_header, type) + + sizeof(event->type) - 1 + offset) >= elog->data_size) + return 0; + + /* End of event marker has been found */ + if (event->type == ELOG_TYPE_EOL) + return 0; + + /* Check if event fits in area */ + if ((offsetof(struct event_header, length) + + sizeof(event->length) - 1 + offset) >= elog->data_size) + return 0; + + /* + * If the current event length + the current offset exceeds + * the area size then the event area is corrupt. + */ + if ((event->length + offset) >= elog->data_size) + return 0; + + /* Event length must be at least header size + checksum */ + if (event->length < (sizeof(*event) + 1)) + return 0; + + /* If event checksum is invalid the area is corrupt */ + if (elog_checksum_event(event) != 0) + return 0; + + /* Event is valid */ + return 1; +} + +/* + * Write 'size' bytes of data provided in 'buffer' into flash + * device at offset 'offset'. This will not erase the flash and + * it assumes the flash area is erased appropriately. + */ +static void elog_flash_write(u8 *address, u8 *buffer, u32 size) +{ + u32 offset; + + if (!address || !buffer || !size || !elog_spi) + return; + + offset = elog_flash_address_to_offset(address); + + elog_debug("elog_flash_write(address=0x%p offset=0x%08x buffer=0x%p " + "size=%u)\n", address, offset, buffer, size); + + /* Write the data to flash */ + elog_spi->write(elog_spi, offset, size, buffer); +} + +/* + * Erase the first block specified in the address. + * Only handles flash area within a single flash block. + */ +static void elog_flash_erase(u8 *address, u32 size) +{ + u32 offset; + + if (!address || !size || !elog_spi) + return; + + offset = elog_flash_address_to_offset(address); + + elog_debug("elog_flash_erase(address=0x%p offset=0x%08x size=%u)\n", + address, offset, size); + + /* Erase the sectors in this region */ + elog_spi->erase(elog_spi, offset, size); +} + +/* + * Scan the event area and validate each entry and + * update the ELOG descriptor state. + */ +static void elog_update_event_buffer_state(struct elog_descriptor *elog) +{ + u32 count = 0; + u32 offset = 0; + u32 last_offset = 0; + u32 last_event_size = 0; + struct event_header *event; + + elog_debug("elog_update_event_buffer_state()\n"); + + /* Go through each event and validate it */ + while (1) { + event = elog_get_event_base(elog, offset); + + /* Do not de-reference anything past the area length */ + if ((offsetof(struct event_header, type) + + sizeof(event->type) - 1 + offset) >= elog->data_size) { + elog->event_buffer_state = ELOG_EVENT_BUFFER_CORRUPTED; + break; + } + + /* The end of the event marker has been found */ + if (event->type == ELOG_TYPE_EOL) + break; + + /* Validate the event */ + if (!elog_is_event_valid(elog, offset)) { + elog->event_buffer_state = ELOG_EVENT_BUFFER_CORRUPTED; + break; + } + + /* Move to the next event */ + count++; + last_offset = offset; + last_event_size = event->length; + offset += event->length; + } + + /* Ensure the remaining buffer is empty */ + if (!elog_is_buffer_clear(&elog->data[offset], + elog->data_size - offset)) + elog->event_buffer_state = ELOG_EVENT_BUFFER_CORRUPTED; + + /* Update data into elog descriptor */ + elog->event_count = count; + elog->next_event_offset = offset; + elog->last_event_offset = last_offset; + elog->last_event_size = last_event_size; +} + +static void elog_validate_and_fill(struct elog_descriptor *elog) +{ + elog_debug("elog_validate_and_fill()\n"); + + /* Check if the area is empty or not */ + if (elog_is_area_clear(elog)) { + elog->area_state = ELOG_AREA_EMPTY; + return; + } + + elog->area_state = ELOG_AREA_HAS_CONTENT; + + /* Validate the header */ + if (!elog_is_header_valid(elog->staging_header)) { + elog->header_state = ELOG_HEADER_INVALID; + return; + } + + elog->header_state = ELOG_HEADER_VALID; + elog_update_event_buffer_state(elog); +} + +/* + * Initialize a new ELOG descriptor + */ +static void elog_init_descriptor(struct elog_descriptor *elog, + elog_descriptor_type type, + u8 *buffer, u32 size, + struct elog_header *header) +{ + elog_debug("elog_init_descriptor(type=%u buffer=0x%p size=%u)\n", + type, buffer, size); + + elog->type = type; + elog->area_state = ELOG_AREA_UNDEFINED; + elog->header_state = ELOG_HEADER_INVALID; + elog->event_buffer_state = ELOG_EVENT_BUFFER_OK; + elog->backing_store = buffer; + elog->total_size = size; + + /* Get staging header from backing store */ + elog->staging_header = header; + memcpy(header, buffer, sizeof(struct elog_header)); + + /* Data starts immediately after header */ + elog->data = &buffer[sizeof(struct elog_header)]; + elog->data_size = size - sizeof(struct elog_header); + + elog->next_event_offset = 0; + elog->last_event_offset = 0; + elog->last_event_size = 0; + elog->event_count = 0; + + elog_validate_and_fill(elog); +} + +/* + * Re-initialize an existing ELOG descriptor + */ +static void elog_reinit_descriptor(struct elog_descriptor *elog) +{ + elog_debug("elog_reinit_descriptor()\n"); + elog_init_descriptor(elog, elog->type, elog->backing_store, + elog->total_size, elog->staging_header); +} + +/* + * Create ELOG descriptor data structures for all ELOG areas. + */ +static int elog_setup_descriptors(u32 flash_base, u32 area_size) +{ + struct elog_header *staging_header; + u8 *area; + + elog_debug("elog_setup_descriptors(base=0x%08x size=%u)\n", + flash_base, area_size); + + /* Prepare flash descriptors */ + if (flash_base == 0) { + printk(BIOS_ERR, "ELOG: Invalid flash base\n"); + return -1; + } + + staging_header = malloc(sizeof(struct elog_header)); + if (!staging_header) { + printk(BIOS_ERR, "ELOG: Unable to allocate header\n"); + return -1; + } + + area = elog_flash_offset_to_address(flash_base); + if (!area) { + printk(BIOS_ERR, "ELOG: Unable to determine flash address\n"); + return -1; + } + elog_init_descriptor(elog_get_flash(), ELOG_DESCRIPTOR_FLASH, + area, area_size, staging_header); + + /* Initialize the memory area to look like a cleared flash area */ + area = malloc(area_size); + if (!area) { + printk(BIOS_ERR, "ELOG: Unable to allocate mem area\n"); + return -1; + } + memset(area, ELOG_TYPE_EOL, area_size); + elog_init_descriptor(elog_get_mem(), ELOG_DESCRIPTOR_MEMORY, + area, area_size, (struct elog_header *)area); + + return 0; +} + +static void elog_flash_erase_area(void) +{ + struct elog_descriptor *elog = elog_get_flash(); + + elog_debug("elog_flash_erase_area()\n"); + + elog_flash_erase(elog->backing_store, elog->total_size); + elog_reinit_descriptor(elog); +} + +static void elog_prepare_empty(struct elog_descriptor *elog, + u8 *data, u32 data_size) +{ + struct elog_header *header; + + elog_debug("elog_prepare_empty(%u bytes)\n", data_size); + + if (!elog_is_area_clear(elog)) + return; + + /* Write out the header */ + header = elog->staging_header; + header->magic = ELOG_SIGNATURE; + header->version = ELOG_VERSION; + header->header_size = sizeof(struct elog_header); + header->reserved[0] = ELOG_TYPE_EOL; + header->reserved[1] = ELOG_TYPE_EOL; + elog_flash_write(elog->backing_store, (u8*)header, + header->header_size); + + /* Write out the data */ + if (data) + elog_flash_write(elog->data, data, data_size); + + elog_reinit_descriptor(elog); + + /* Clear the log if corrupt */ + if (!elog_is_area_valid(elog)) + elog_flash_erase_area(); +} + +static int elog_sync_flash_to_mem(void) +{ + struct elog_descriptor *mem = elog_get_mem(); + struct elog_descriptor *flash = elog_get_flash(); + + elog_debug("elog_sync_flash_to_mem()\n"); + + /* Fill with empty pattern first */ + memset(mem->backing_store, ELOG_TYPE_EOL, mem->total_size); + + /* Copy the header to memory */ + memcpy(mem->backing_store, flash->backing_store, + sizeof(struct elog_header)); + + /* Copy the valid flash contents to memory */ + memcpy(mem->data, flash->data, flash->next_event_offset); + + elog_reinit_descriptor(mem); + + return elog_is_area_valid(mem) ? 0 : -1; +} + +static int elog_sync_mem_to_flash(void) +{ + struct elog_descriptor *mem = elog_get_mem(); + struct elog_descriptor *flash = elog_get_flash(); + u8 *src, *dest; + u32 size; + + elog_debug("elog_sync_mem_to_flash()\n"); + + /* + * In the case of a BIOS flash the active area will be cleared. + * One can catch this case and log the proper shutdown event by + * checking if the active flash elog is empty. Note that if the + * header size changes we will have corrupted the flash area. + * However that will be corrected on the next boot. + */ + if (elog_is_area_clear(flash)) { + elog_prepare_empty(flash, + (u8*)elog_get_last_event_base(mem), + mem->last_event_size); + elog_sync_flash_to_mem(); + return 0; + } + + /* Calculate the destination and source bases */ + dest = (u8*)elog_get_next_event_base(flash); + src = (u8*)elog_get_event_base(mem, flash->next_event_offset); + + /* Calculate how much data to sync */ + size = mem->next_event_offset - flash->next_event_offset; + + /* Write the log data */ + elog_flash_write(dest, src, size); + + /* Update descriptor */ + flash->event_count = mem->event_count; + flash->next_event_offset = mem->next_event_offset; + flash->last_event_offset = mem->last_event_offset; + flash->last_event_size = mem->last_event_size; + + return 0; +} + +/* + * Called during ELOG entry handler to prepare state for flash. + */ +static int elog_flash_area_bootstrap(void) +{ + struct elog_descriptor *elog = elog_get_flash(); + + elog_debug("elog_flash_area_bootstrap()\n"); + + switch (elog->area_state) { + case ELOG_AREA_UNDEFINED: + printk(BIOS_ERR, "ELOG: flash area undefined\n"); + return -1; + + case ELOG_AREA_EMPTY: + /* Write a new header with no data */ + elog_prepare_empty(elog, NULL, 0); + break; + + case ELOG_AREA_HAS_CONTENT: + break; + } + + if (elog->header_state == ELOG_HEADER_INVALID) { + /* If the header is invalid no events can be salvaged + * so erase the entire area. */ + printk(BIOS_ERR, "ELOG: flash area header invalid\n"); + elog_flash_erase_area(); + elog_prepare_empty(elog, NULL, 0); + } + + if (elog->event_buffer_state == ELOG_EVENT_BUFFER_CORRUPTED) { + /* Wipe the source flash area */ + elog_flash_erase_area(); + elog_prepare_empty(elog, elog_get_mem()->data, + elog_get_mem()->next_event_offset); + } + + return 0; +} + +/* + * Shrink the log, deleting old entries and moving the + * remining ones to the front of the log. + */ +static int elog_shrink(void) +{ + struct elog_descriptor *mem = elog_get_mem(); + struct event_header *event; + u16 discard_count = 0; + u16 offset = 0; + + elog_debug("elog_shrink()\n"); + + if (mem->next_event_offset < CONFIG_ELOG_SHRINK_SIZE) + return 0; + + while (1) { + /* Next event has exceeded constraints */ + if (offset > CONFIG_ELOG_SHRINK_SIZE) + break; + + event = elog_get_event_base(mem, offset); + + /* Reached the end of the area */ + if (!event || event->type == ELOG_TYPE_EOL) + break; + + offset += event->length; + discard_count++; + } + + /* Erase flash area */ + elog_flash_erase_area(); + + /* Write new flash area */ + elog_prepare_empty(elog_get_flash(), + (u8*)elog_get_event_base(mem, offset), + mem->next_event_offset - offset); + + /* Update memory area from flash */ + if (elog_sync_flash_to_mem() < 0) { + printk(BIOS_ERR, "Unable to update memory area from flash\n"); + return -1; + } + + /* Add clear event */ + elog_add_event_word(ELOG_TYPE_LOG_CLEAR, offset); + + return 0; +} + +/* + * Initialize the SPI bus and probe for a flash chip + */ +static int elog_spi_init(void) +{ + elog_debug("elog_spi_init()\n"); + + /* Prepare SPI subsystem */ + spi_init(); + + /* Look for flash chip */ + elog_spi = spi_flash_probe(0, 0, 0, 0); + + return elog_spi ? 0 : -1; +} + +/* + * Clear the entire event log + */ +int elog_clear(void) +{ + struct elog_descriptor *flash = elog_get_flash(); + + elog_debug("elog_clear()\n"); + + /* Erase flash area */ + elog_flash_erase_area(); + + /* Prepare new empty area */ + elog_prepare_empty(flash, NULL, 0); + + /* Update memory area from flash */ + if (elog_sync_flash_to_mem() < 0) + return -1; + + /* Log the clear event */ + elog_add_event_word(ELOG_TYPE_LOG_CLEAR, flash->total_size); + + return 0; +} + +/* + * Event log main entry point + */ +int elog_init(void) +{ + if (elog_initialized) + return 0; + + elog_debug("elog_init()\n"); + + /* Find SPI flash chip for backing store */ + if (elog_spi_init() < 0) { + printk(BIOS_ERR, "ELOG: Unable to find SPI flash\n"); + return -1; + } + + /* Setup descriptors for flash and memory areas */ + if (elog_setup_descriptors(CONFIG_ELOG_FLASH_BASE, + CONFIG_ELOG_AREA_SIZE) < 0) { + printk(BIOS_ERR, "ELOG: Unable to initialize descriptors\n"); + return -1; + } + + /* Bootstrap the flash area */ + if (elog_flash_area_bootstrap() < 0) { + printk(BIOS_ERR, "ELOG: Unable to bootstrap flash area\n"); + return -1; + } + + /* Initialize the memory area */ + if (elog_sync_flash_to_mem() < 0) { + printk(BIOS_ERR, "ELOG: Unable to initialize memory area\n"); + return -1; + } + + elog_initialized = 1; + + printk(BIOS_INFO, "ELOG: MEM @0x%p FLASH @0x%p\n", + elog_get_mem()->backing_store, + elog_get_flash()->backing_store); + + printk(BIOS_INFO, "ELOG: areas are %d bytes, full threshold %d," + " shrink size %d\n", CONFIG_ELOG_AREA_SIZE, + CONFIG_ELOG_FULL_THRESHOLD, CONFIG_ELOG_SHRINK_SIZE); + + /* Log a clear event if necessary */ + if (elog_get_flash()->event_count == 0) + elog_add_event_word(ELOG_TYPE_LOG_CLEAR, + elog_get_flash()->total_size); + + return 0; +} + +/* + * Populate timestamp in event header with current time + */ +static void elog_fill_timestamp(struct event_header *event) +{ + event->second = cmos_read(RTC_CLK_SECOND); + event->minute = cmos_read(RTC_CLK_MINUTE); + event->hour = cmos_read(RTC_CLK_HOUR); + event->day = cmos_read(RTC_CLK_DAYOFMONTH); + event->month = cmos_read(RTC_CLK_MONTH); + event->year = cmos_read(RTC_CLK_YEAR); + + /* Basic sanity check of expected ranges */ + if (event->month > 0x12 || event->day > 0x31 || event->hour > 0x23 || + event->minute > 0x59 || event->second > 0x59) { + event->year = 0; + event->month = 0; + event->day = 0; + event->hour = 0; + event->minute = 0; + event->second = 0; + } +} + +/* + * Add an event to the memory area + */ +static int elog_add_event_mem(u8 event_type, void *data, u8 data_size) +{ + struct event_header *event; + struct elog_descriptor *mem = elog_get_mem(); + u8 event_size; + + elog_debug("elog_add_event_mem(type=%X)\n", event_type); + + /* Make sure ELOG structures are initialized */ + if (elog_init() < 0) + return -1; + + /* Header + Data + Checksum */ + event_size = sizeof(*event) + data_size + 1; + if (event_size > MAX_EVENT_SIZE) { + printk(BIOS_ERR, "ELOG: Event(%X) data size too " + "big (%d)\n", event_type, event_size); + return -1; + } + + /* Make sure event data can fit */ + if ((mem->next_event_offset + event_size) >= mem->data_size) { + printk(BIOS_ERR, "ELOG: Event(%X) does not fit\n", + event_type); + return -1; + } + + /* Fill out event data */ + event = elog_get_next_event_base(mem); + event->type = event_type; + event->length = event_size; + elog_fill_timestamp(event); + + if (data_size) + memcpy(&event[1], data, data_size); + + /* Zero the checksum byte and then compute checksum */ + elog_update_checksum(event, 0); + elog_update_checksum(event, -(elog_checksum_event(event))); + + /* Update memory descriptor parameters */ + mem->event_count++; + mem->last_event_offset = mem->next_event_offset; + mem->last_event_size = event_size; + mem->next_event_offset += event_size; + + printk(BIOS_INFO, "ELOG: Event(%X) added with size %d\n", + event_type, event_size); + return 0; +} + +void elog_add_event_raw(u8 event_type, void *data, u8 data_size) +{ + elog_debug("elog_add_event_raw(type=%X)\n", event_type); + + /* Add event to the memory area */ + if (elog_add_event_mem(event_type, data, data_size) < 0) { + printk(BIOS_ERR, "Unable to add event to memory area\n"); + return; + } + + /* Sync the memory buffer to flash */ + elog_sync_mem_to_flash(); + + /* Shrink the log if we are getting too full */ + if (elog_get_mem()->next_event_offset >= CONFIG_ELOG_FULL_THRESHOLD) + elog_shrink(); +} + +void elog_add_event(u8 event_type) +{ + elog_add_event_raw(event_type, NULL, 0); +} + +void elog_add_event_byte(u8 event_type, u8 data) +{ + elog_add_event_raw(event_type, &data, sizeof(data)); +} + +void elog_add_event_word(u8 event_type, u16 data) +{ + elog_add_event_raw(event_type, &data, sizeof(data)); +} + +void elog_add_event_dword(u8 event_type, u32 data) +{ + elog_add_event_raw(event_type, &data, sizeof(data)); +} + +void elog_add_event_wake(u8 source, u32 instance) +{ + struct elog_event_data_wake wake = { + .source = source, + .instance = instance + }; + elog_add_event_raw(ELOG_TYPE_WAKE_SOURCE, &wake, sizeof(wake)); +} diff --git a/src/drivers/elog/elog_internal.h b/src/drivers/elog/elog_internal.h new file mode 100644 index 0000000..2a6a0b7 --- /dev/null +++ b/src/drivers/elog/elog_internal.h @@ -0,0 +1,76 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA + */ + +#ifndef ELOG_INTERNAL_H_ +#define ELOG_INTERNAL_H_ + +/* ELOG header */ +struct elog_header { + u32 magic; + u8 version; + u8 header_size; + u8 reserved[2]; +} __attribute__ ((packed)); + +/* ELOG related constants */ +#define ELOG_SIGNATURE 0x474f4c45 /* 'ELOG' */ +#define ELOG_VERSION 1 + +typedef enum elog_descriptor_type { + ELOG_DESCRIPTOR_UNKNOWN, + ELOG_DESCRIPTOR_MEMORY, + ELOG_DESCRIPTOR_FLASH, +} elog_descriptor_type; + +typedef enum elog_area_state { + ELOG_AREA_UNDEFINED, /* Initial boot strap state */ + ELOG_AREA_EMPTY, /* Entire area is empty */ + ELOG_AREA_HAS_CONTENT, /* Area has some content */ +} elog_area_state; + +typedef enum elog_header_state { + ELOG_HEADER_INVALID, + ELOG_HEADER_VALID, +} elog_header_state; + +typedef enum elog_event_buffer_state { + ELOG_EVENT_BUFFER_OK, + ELOG_EVENT_BUFFER_CORRUPTED, +} elog_event_buffer_state; + +/* + * Internal handler for event log buffers + */ +struct elog_descriptor { + elog_descriptor_type type; + elog_area_state area_state; + elog_header_state header_state; + elog_event_buffer_state event_buffer_state; + struct elog_header *staging_header; + void *backing_store; + u8 *data; + u16 total_size; + u16 data_size; + u16 next_event_offset; + u16 last_event_offset; + u16 last_event_size; + u16 event_count; +}; + +#endif /* ELOG_INTERNAL_H_ */ diff --git a/src/include/elog.h b/src/include/elog.h new file mode 100644 index 0000000..c6599a2 --- /dev/null +++ b/src/include/elog.h @@ -0,0 +1,119 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA + */ + +#ifndef ELOG_H_ +#define ELOG_H_ + +#if CONFIG_ELOG + +/* SMI command code for GSMI event logging */ +#define ELOG_GSMI_APM_CNT 0xEF + +#define MAX_EVENT_SIZE 0x7F + +/* End of log */ +#define ELOG_TYPE_EOL 0xFF + +/* + * Standard SMBIOS event log types below 0x80 + */ +#define ELOG_TYPE_UNDEFINED_EVENT 0x00 +#define ELOG_TYPE_SINGLE_BIT_ECC_MEM_ERR 0x01 +#define ELOG_TYPE_MULTI_BIT_ECC_MEM_ERR 0x02 +#define ELOG_TYPE_MEM_PARITY_ERR 0x03 +#define ELOG_TYPE_BUS_TIMEOUT 0x04 +#define ELOG_TYPE_IO_CHECK 0x05 +#define ELOG_TYPE_SW_NMI 0x06 +#define ELOG_TYPE_POST_MEM_RESIZE 0x07 +#define ELOG_TYPE_POST_ERR 0x08 +#define ELOG_TYPE_PCI_PERR 0x09 +#define ELOG_TYPE_PCI_SERR 0x0A +#define ELOG_TYPE_CPU_FAIL 0x0B +#define ELOG_TYPE_EISA_TIMEOUT 0x0C +#define ELOG_TYPE_CORRECTABLE_MEMLOG_DIS 0x0D +#define ELOG_TYPE_LOG_DISABLED 0x0E +#define ELOG_TYPE_UNDEFINED_EVENT2 0x0F +#define ELOG_TYPE_SYS_LIMIT_EXCEED 0x10 +#define ELOG_TYPE_ASYNC_HW_TIMER_EXPIRED 0x11 +#define ELOG_TYPE_SYS_CONFIG_INFO 0x12 +#define ELOG_TYPE_HDD_INFO 0x13 +#define ELOG_TYPE_SYS_RECONFIG 0x14 +#define ELOG_TYPE_CPU_ERROR 0x15 +#define ELOG_TYPE_LOG_CLEAR 0x16 +#define ELOG_TYPE_BOOT 0x17 + +/* + * Extended defined OEM event types start at 0x80 + */ + +/* OS/kernel events */ +#define ELOG_TYPE_OS_EVENT 0x81 + +/* Last event from coreboot */ +#define ELOG_TYPE_OS_BOOT 0x90 + +/* Embedded controller event */ +#define ELOG_TYPE_EC_EVENT 0x91 + +/* Power */ +#define ELOG_TYPE_POWER_FAIL 0x92 +#define ELOG_TYPE_SUS_POWER_FAIL 0x93 +#define ELOG_TYPE_PWROK_FAIL 0x94 +#define ELOG_TYPE_SYS_PWROK_FAIL 0x95 +#define ELOG_TYPE_POWER_ON 0x96 +#define ELOG_TYPE_POWER_BUTTON 0x97 +#define ELOG_TYPE_POWER_BUTTON_OVERRIDE 0x98 + +/* Reset */ +#define ELOG_TYPE_RESET_BUTTON 0x99 +#define ELOG_TYPE_SYSTEM_RESET 0x9a +#define ELOG_TYPE_RTC_RESET 0x9b +#define ELOG_TYPE_TCO_RESET 0x9c + +/* Sleep/Wake */ +#define ELOG_TYPE_ACPI_ENTER 0x9d +#define ELOG_TYPE_ACPI_WAKE 0x9e +#define ELOG_TYPE_WAKE_SOURCE 0x9f +#define ELOG_WAKE_SOURCE_PCIE 0x00 +#define ELOG_WAKE_SOURCE_PME 0x01 +#define ELOG_WAKE_SOURCE_PME_INTERNAL 0x02 +#define ELOG_WAKE_SOURCE_RTC 0x03 +#define ELOG_WAKE_SOURCE_GPIO 0x04 +#define ELOG_WAKE_SOURCE_SMBUS 0x05 +struct elog_event_data_wake { + u8 source; + u32 instance; +} __attribute__ ((packed)); + +/* Chrome OS related events */ +#define ELOG_TYPE_CROS_DEVELOPER_MODE 0xa0 +#define ELOG_TYPE_CROS_RECOVERY_MODE 0xa1 + +extern int elog_init(void); +extern int elog_clear(void); +extern void elog_add_event_raw(u8 event_type, void *data, u8 data_size); +extern void elog_add_event(u8 event_type); +extern void elog_add_event_byte(u8 event_type, u8 data); +extern void elog_add_event_word(u8 event_type, u16 data); +extern void elog_add_event_dword(u8 event_type, u32 data); +extern void elog_add_event_wake(u8 source, u32 instance); + +#endif /* !CONFIG_ELOG */ + +#endif /* ELOG_H_ */

1 0

Patch merged into coreboot/master: 6a75755 SandyBridge: Add another PCI device ID for northbridge
by gerrit＠coreboot.org 23 Jul '12

23 Jul '12

the following patch was just integrated into master: commit 6a757558cd940fa2ed98b7ede00296f6dff6a6c8 Author: Walter Murphy <wmurphy(a)google.com> Date: Mon Apr 23 11:08:03 2012 -0700 SandyBridge: Add another PCI device ID for northbridge Change-Id: I153579561f7eed6d4befd74ff39e1a5e778d0e46 Signed-off-by: Walter Murphy <wmurphy(a)google.com> Build-Tested: build bot (Jenkins) at Tue Jul 24 00:02:42 2012, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Tue Jul 24 00:01:58 2012, giving +2 See http://review.coreboot.org/1269 for details. -gerrit

1 0

← Newer
1
...
23
24
25
26
27
28
29
...
64
Older →

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

2009

2008

2007

2006

2005

2004

2003

2002

coreboot July 2012