coreboot July 2012

coreboot@coreboot.org

35 participants
639 discussions

usb stick payload?
by Motiejus Jakštys 23 Jul '12

23 Jul '12

Hi, I have thinkpad X60s with coreboot and with only one payload: SATA hard drive. I would like to add a "boot from usb stick" option. However, can't find the payload (i.e. source to generate the necessary coreboot ELF file). Wiki mentions that I need the coreboot payload ELF, doesn't mention where to get it. :) I would appreciate some directions. Thanks, Motiejus Jakštys

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New patch to review for coreboot: 295cc98 Fix function generating GPIO state based vector
by Stefan Reinauer 23 Jul '12

23 Jul '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1291 -gerrit commit 295cc9865b194e5cfe126d6f7fd56187078325dc Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Tue Jun 19 04:56:24 2012 +0000 Fix function generating GPIO state based vector The function was too eager shifting stuff around, this change corrects the problem. Change-Id: I4c13dbe86cb627835dae05bb74af9867c28e143d Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> --- src/southbridge/intel/bd82x6x/gpio.c | 1 - 1 files changed, 0 insertions(+), 1 deletions(-) diff --git a/src/southbridge/intel/bd82x6x/gpio.c b/src/southbridge/intel/bd82x6x/gpio.c index 2ba34ea..25eda9a 100644 --- a/src/southbridge/intel/bd82x6x/gpio.c +++ b/src/southbridge/intel/bd82x6x/gpio.c @@ -93,7 +93,6 @@ unsigned get_gpios(const int *gpio_num_array) while (bitmask && ((gpio = *gpio_num_array++) != -1)) { - vector <<= 1; if (get_gpio(gpio)) vector |= bitmask; bitmask <<= 1;

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New patch to review for coreboot: 055e26e Drop (empty) sandybridge_late_initialization()
by Stefan Reinauer 23 Jul '12

23 Jul '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1290 -gerrit commit 055e26eaeff8c4f2558d7dbadbbc7e4953eee260 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Mon Jun 18 15:43:50 2012 -0700 Drop (empty) sandybridge_late_initialization() The function is empty (a left-over from i945) and should be removed. Change-Id: I91e573b5e37cb9133ea1037aef7e6daf3c292864 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/mainboard/intel/emeraldlake2/romstage.c | 5 +---- src/mainboard/samsung/lumpy/romstage.c | 5 +---- src/mainboard/samsung/stumpy/romstage.c | 5 +---- src/northbridge/intel/sandybridge/early_init.c | 5 ----- 4 files changed, 3 insertions(+), 17 deletions(-) diff --git a/src/mainboard/intel/emeraldlake2/romstage.c b/src/mainboard/intel/emeraldlake2/romstage.c index aba89d4..f8ef17d 100644 --- a/src/mainboard/intel/emeraldlake2/romstage.c +++ b/src/mainboard/intel/emeraldlake2/romstage.c @@ -312,11 +312,8 @@ void main(unsigned long bist) rcba_config(); post_code(0x3d); - /* Initialize the internal PCIe links before we go into stage2 */ - sandybridge_late_initialization(); - - post_code(0x3e); quick_ram_check(); + post_code(0x3e); MCHBAR16(SSKPD) = 0xCAFE; #if CONFIG_EARLY_CBMEM_INIT diff --git a/src/mainboard/samsung/lumpy/romstage.c b/src/mainboard/samsung/lumpy/romstage.c index 82856f6..09cbd2a 100644 --- a/src/mainboard/samsung/lumpy/romstage.c +++ b/src/mainboard/samsung/lumpy/romstage.c @@ -330,11 +330,8 @@ void main(unsigned long bist) rcba_config(); post_code(0x3c); - /* Initialize the internal PCIe links before we go into stage2 */ - sandybridge_late_initialization(); - - post_code(0x3e); quick_ram_check(); + post_code(0x3e); MCHBAR16(SSKPD) = 0xCAFE; diff --git a/src/mainboard/samsung/stumpy/romstage.c b/src/mainboard/samsung/stumpy/romstage.c index 10a9d7b..68f6260 100644 --- a/src/mainboard/samsung/stumpy/romstage.c +++ b/src/mainboard/samsung/stumpy/romstage.c @@ -335,11 +335,8 @@ void main(unsigned long bist) rcba_config(); post_code(0x3c); - /* Initialize the internal PCIe links before we go into stage2 */ - sandybridge_late_initialization(); - - post_code(0x3e); quick_ram_check(); + post_code(0x3e); MCHBAR16(SSKPD) = 0xCAFE; #if CONFIG_EARLY_CBMEM_INIT diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c index f052fbc..48faf5f 100644 --- a/src/northbridge/intel/sandybridge/early_init.c +++ b/src/northbridge/intel/sandybridge/early_init.c @@ -158,8 +158,3 @@ void sandybridge_early_initialization(int chipset_type) sandybridge_setup_graphics(); } - -void sandybridge_late_initialization(void) -{ -} -

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New patch to review for coreboot: f135193 More descriptive error messages in Sandybridge raminit code
by Stefan Reinauer 23 Jul '12

23 Jul '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1289 -gerrit commit f1351932d41879cf8b71e8586667ba1ab5ac70c7 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Mon Jun 18 14:38:40 2012 -0700 More descriptive error messages in Sandybridge raminit code MRC returns specific error codes; print the according error message if we know what it means. Change-Id: Iaaf1512b9d577d4291fccfb94d879043ab5b11b5 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/northbridge/intel/sandybridge/raminit.c | 13 +++++++++++-- 1 files changed, 11 insertions(+), 2 deletions(-) diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index 0df86d6..bb8b25c 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -249,8 +249,17 @@ void sdram_initialize(struct pei_data *pei_data) "call *%%ecx\n\t" :"=a" (rv) : "c" (entry), "a" (pei_data)); if (rv) { - printk(BIOS_ERR, "MRC returned %x\n", rv); - die("Nonzero MRC return value\n"); + switch (rv) { + case -1: + printk(BIOS_ERR, "PEI version mismatch."); + break; + case -2: + printk(BIOS_ERR, "Invalid memory frequency.\n"); + break; + default: + printk(BIOS_ERR, "MRC returned %x.\n", rv); + } + die("Nonzero MRC return value.\n"); } } else { die("UEFI PEI System Agent not found.\n");

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New patch to review for coreboot: f1a5f90 Rename cache_lbmem() to cache_ramstage()
by Stefan Reinauer 23 Jul '12

23 Jul '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1288 -gerrit commit f1a5f90801465fde0dd0e556767249a244378ab9 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Fri Jun 15 15:34:24 2012 -0700 Rename cache_lbmem() to cache_ramstage() ... and don't require it to specify a cache type. This function is only used on romcc boards, and should go away (because all boards should be switched to CAR) Change-Id: Ic32ca3be1afffc773c72c140e88b338d48a0c8ca Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/cpu/x86/mtrr/earlymtrr.c | 6 +++--- src/northbridge/intel/e7520/raminit.c | 2 +- src/northbridge/intel/e7525/raminit.c | 2 +- src/northbridge/intel/i3100/raminit.c | 2 +- src/northbridge/intel/i3100/raminit_ep80579.c | 2 +- 5 files changed, 7 insertions(+), 7 deletions(-) diff --git a/src/cpu/x86/mtrr/earlymtrr.c b/src/cpu/x86/mtrr/earlymtrr.c index 7a1f51d..593f066 100644 --- a/src/cpu/x86/mtrr/earlymtrr.c +++ b/src/cpu/x86/mtrr/earlymtrr.c @@ -21,11 +21,11 @@ static void set_var_mtrr( } #if !defined(CONFIG_CACHE_AS_RAM) || !CONFIG_CACHE_AS_RAM -static void cache_lbmem(int type) +static void cache_ramstage(void) { - /* Enable caching for 0 - 1MB using variable mtrr */ + /* Enable caching for lower 1MB and ram stage using variable mtrr */ disable_cache(); - set_var_mtrr(0, 0x00000000, CONFIG_RAMTOP, type); + set_var_mtrr(0, 0x00000000, CONFIG_RAMTOP, MTRR_TYPE_WRBACK); enable_cache(); } diff --git a/src/northbridge/intel/e7520/raminit.c b/src/northbridge/intel/e7520/raminit.c index d226085..191c077 100644 --- a/src/northbridge/intel/e7520/raminit.c +++ b/src/northbridge/intel/e7520/raminit.c @@ -1334,5 +1334,5 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) pci_write_config16(PCI_DEV(0, 0x00, 0), MCHSCRB, data16); /* The memory is now setup, use it */ - cache_lbmem(MTRR_TYPE_WRBACK); + cache_ramstage(); } diff --git a/src/northbridge/intel/e7525/raminit.c b/src/northbridge/intel/e7525/raminit.c index b5895bc..c491a7e 100644 --- a/src/northbridge/intel/e7525/raminit.c +++ b/src/northbridge/intel/e7525/raminit.c @@ -1307,5 +1307,5 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) pci_write_config16(ctrl->f0, MCHSCRB, data16); /* The memory is now setup, use it */ - cache_lbmem(MTRR_TYPE_WRBACK); + cache_ramstage(); } diff --git a/src/northbridge/intel/i3100/raminit.c b/src/northbridge/intel/i3100/raminit.c index 050df95..b453e8b 100644 --- a/src/northbridge/intel/i3100/raminit.c +++ b/src/northbridge/intel/i3100/raminit.c @@ -1198,6 +1198,6 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) /* The memory is now setup, use it */ #if !CONFIG_CACHE_AS_RAM - cache_lbmem(MTRR_TYPE_WRBACK); + cache_ramstage(); #endif } diff --git a/src/northbridge/intel/i3100/raminit_ep80579.c b/src/northbridge/intel/i3100/raminit_ep80579.c index 79fc5f7..5fe206f 100644 --- a/src/northbridge/intel/i3100/raminit_ep80579.c +++ b/src/northbridge/intel/i3100/raminit_ep80579.c @@ -772,7 +772,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) pci_write_config32(ctrl->f0, DRC, drc); /* The memory is now set up--use it */ - cache_lbmem(MTRR_TYPE_WRBACK); + cache_ramstage(); } static inline int memory_initialized(void)

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New patch to review for coreboot: 8e599ec Print PCI ID of PCH during boot up
by Stefan Reinauer 23 Jul '12

23 Jul '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1287 -gerrit commit 8e599ec930891a7d93a0830b466f15a3d4d084fe Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Mon Jun 18 11:26:25 2012 -0700 Print PCI ID of PCH during boot up Right now, if we have an unknown PCH, coreboot will print something like this: PCH type: Unknown rev id 4 Instead, it should also print the PCI ID of the device, so we can add it to the list of known PCHes. Change-Id: Ib0b96e287c36d2895d1287b1734ca13d75e7985a Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- .../intel/sandybridge/report_platform.c | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/northbridge/intel/sandybridge/report_platform.c b/src/northbridge/intel/sandybridge/report_platform.c index d59cfe9..18dffc2 100644 --- a/src/northbridge/intel/sandybridge/report_platform.c +++ b/src/northbridge/intel/sandybridge/report_platform.c @@ -92,8 +92,8 @@ static void report_pch_info(void) break; } } - printk (BIOS_DEBUG, "PCH type: %s rev id %x\n", - pch_type, pci_read_config8(PCH_LPC_DEV, 8)); + printk (BIOS_DEBUG, "PCH type: %s, device id: %x, rev id %x\n", + pch_type, dev_id, pci_read_config8(PCH_LPC_DEV, 8)); } void report_platform_info(void)

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New patch to review for coreboot: 831243e Implement stack overflow checking for the BSP
by Stefan Reinauer 23 Jul '12

23 Jul '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1286 -gerrit commit 831243ee6459d48974caa0adc739eef740377122 Author: Ronald G. Minnich <rminnich(a)chromium.org> Date: Tue Jun 12 16:29:32 2012 -0700 Implement stack overflow checking for the BSP Previous patches implemented stack overflow checking for the APs. This patch builds on the BSP stack poisoning patch to implement stack overflow checking for the BSP, and also prints out maximum stack usage. It reveals that our 32K stack is ridiculously oversized, especially now that the lzma decoder doesn't use a giant 16K on-stack array. Break the stack checking out into a separate function, which we will later use for the APs. CPU0: stack from 00180000 to 00188000:Lowest stack address 00187ad8 To test failure, change the DEADBEEF stack poison value in c_start.S to something else. Then we should get an error like this: Stack overrun on BSP.Increase stack from current 32768 bytes CPU0: stack from 00180000 to 00188000:Lowest stack address 00180000 Separate the act of loading from the act of starting the payload. This allows us better error management and reporting of stack use. Now we see: CPU0: stack from 00180000 to 00188000:Lowest stack address 00187ad8 Tested for both success and failure on Link. At the same time, feel free to carefully check my manipulation of _estack. Change-Id: Ibb09738b15ec6a5510ac81e45dd82756bfa5aac2 Signed-off-by: Ronald G. Minnich <rminnich(a)chromium.org> --- src/boot/hardwaremain.c | 17 +++++++++++++- src/boot/selfboot.c | 10 +------- src/include/cbfs.h | 1 + src/include/lib.h | 8 ++++++- src/lib/Makefile.inc | 1 + src/lib/stack.c | 51 +++++++++++++++++++++++++++++++++++++++++++++++ 6 files changed, 77 insertions(+), 11 deletions(-) diff --git a/src/boot/hardwaremain.c b/src/boot/hardwaremain.c index d78b859..bb7f264 100644 --- a/src/boot/hardwaremain.c +++ b/src/boot/hardwaremain.c @@ -35,6 +35,7 @@ it with the version available from LANL. #include <boot/tables.h> #include <boot/elf.h> #include <cbfs.h> +#include <lib.h> #if CONFIG_HAVE_ACPI_RESUME #include <arch/acpi.h> #endif @@ -143,7 +144,19 @@ void hardwaremain(int boot_complete) lb_mem = write_tables(); timestamp_add_now(TS_LOAD_PAYLOAD); - cbfs_load_payload(lb_mem, CONFIG_CBFS_PREFIX "/payload"); - printk(BIOS_ERR, "Boot failed.\n"); + + void *payload; + payload = cbfs_load_payload(lb_mem, CONFIG_CBFS_PREFIX "/payload"); + if (! payload) + die("Could not find a payload\n"); + + printk(BIOS_DEBUG, "Got a payload\n"); + /* Before we go off to run the payload, see if + * we stayed within our bounds. + */ + checkstack(&_estack, 0); + + selfboot(lb_mem, payload); + printk(BIOS_EMERG, "Boot failed"); } diff --git a/src/boot/selfboot.c b/src/boot/selfboot.c index 3c31023..fd5b382 100644 --- a/src/boot/selfboot.c +++ b/src/boot/selfboot.c @@ -494,7 +494,7 @@ static int load_self_segments( return 1; } -static int selfboot(struct lb_memory *mem, struct cbfs_payload *payload) +int selfboot(struct lb_memory *mem, struct cbfs_payload *payload) { u32 entry=0; struct segment head; @@ -532,13 +532,7 @@ void *cbfs_load_payload(struct lb_memory *lb_mem, const char *name) struct cbfs_payload *payload; payload = (struct cbfs_payload *)cbfs_find_file(name, CBFS_TYPE_PAYLOAD); - if (payload == NULL) - return (void *) -1; - printk(BIOS_DEBUG, "Got a payload\n"); - selfboot(lb_mem, payload); - printk(BIOS_EMERG, "SELFBOOT RETURNED!\n"); - - return (void *) -1; + return payload; } diff --git a/src/include/cbfs.h b/src/include/cbfs.h index 1483177..b33e932 100644 --- a/src/include/cbfs.h +++ b/src/include/cbfs.h @@ -57,5 +57,6 @@ void *cbfs_load_stage(const char *name); int cbfs_execute_stage(const char *name); void *cbfs_load_optionrom(u16 vendor, u16 device, void * dest); int run_address(void *f); +int selfboot(struct lb_memory *mem, struct cbfs_payload *payload); #endif diff --git a/src/include/lib.h b/src/include/lib.h index ea09887..b2f38a8 100644 --- a/src/include/lib.h +++ b/src/include/lib.h @@ -21,7 +21,7 @@ #ifndef __LIB_H__ #define __LIB_H__ - +#include <stdint.h> #ifndef __ROMCC__ /* romcc doesn't support prototypes. */ #ifndef __PRE_RAM__ /* Conflicts with romcc_io.h */ @@ -40,6 +40,12 @@ void ram_check(unsigned long start, unsigned long stop); int ram_check_nodie(unsigned long start, unsigned long stop); void quick_ram_check(void); +/* Defined in src/lib/stack.c */ +int checkstack(void *top_of_stack, int stacksize); + +/* currently defined by a ldscript */ +extern u8 _estack; + /* Defined in romstage.c */ #if CONFIG_CPU_AMD_GEODE_LX void cache_as_ram_main(void); diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 7c081ac..a3235a2 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -39,6 +39,7 @@ ramstage-y += version.c ramstage-y += cbfs.c ramstage-y += lzma.c #ramstage-y += lzmadecode.c +ramstage-y += stack.c ramstage-y += gcc.c ramstage-y += clog2.c ramstage-y += cbmem.c diff --git a/src/lib/stack.c b/src/lib/stack.c new file mode 100644 index 0000000..3f04b63 --- /dev/null +++ b/src/lib/stack.c @@ -0,0 +1,51 @@ +/* +This software and ancillary information (herein called SOFTWARE ) +called LinuxBIOS is made available under the terms described +here. The SOFTWARE has been approved for release with associated +LA-CC Number 00-34 . Unless otherwise indicated, this SOFTWARE has +been authored by an employee or employees of the University of +California, operator of the Los Alamos National Laboratory under +Contract No. W-7405-ENG-36 with the U.S. Department of Energy. The +U.S. Government has rights to use, reproduce, and distribute this +SOFTWARE. The public may copy, distribute, prepare derivative works +and publicly display this SOFTWARE without charge, provided that this +Notice and any statement of authorship are reproduced on all copies. +Neither the Government nor the University makes any warranty, express +or implied, or assumes any liability or responsibility for the use of +this SOFTWARE. If SOFTWARE is modified to produce derivative works, +such modified SOFTWARE should be clearly marked, so as not to confuse +it with the version available from LANL. + */ +/* Copyright 2000, Ron Minnich, Advanced Computing Lab, LANL + * rminnich(a)lanl.gov + */ + +#include <lib.h> +#include <console/console.h> + +int checkstack(void *top_of_stack, int core) +{ + int i; + u32 *stack = (u32 *) (top_of_stack - CONFIG_STACK_SIZE); + + if (stack[0] != 0xDEADBEEF){ + printk(BIOS_ERR, "Stack overrun on CPU%d." + "Increase stack from current %d bytes\n", + CONFIG_STACK_SIZE, core); + return -1; + } + + for(i = 0; i < CONFIG_STACK_SIZE/sizeof(stack[0]); i++){ + if (stack[i] == 0xDEADBEEF) + continue; + printk(BIOS_SPEW, "CPU%d: stack from %p to %p:", + core, + stack, + &stack[CONFIG_STACK_SIZE/sizeof(stack[0])]); + printk(BIOS_SPEW, "Lowest stack address %p\n", &stack[i]); + return -1; + } + + return 0; + +}

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New patch to review for coreboot: f67f26f Add uartmem_init prototype.
by Stefan Reinauer 23 Jul '12

23 Jul '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1285 -gerrit commit f67f26faa266db1314055283d10791f024b1018a Author: Marc Jones <marc.jones(a)se-eng.com> Date: Wed Jun 13 20:48:36 2012 -0600 Add uartmem_init prototype. The oxpcie ramstage code calls uartmem_init after the PCI memory allocation, but hte function was static and didn't have a prototype. Change-Id: Iabc1a3d248aeaed29aaaa22504defac97c572326 Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> --- src/console/uart8250mem_console.c | 2 +- src/include/uart8250.h | 1 + 2 files changed, 2 insertions(+), 1 deletions(-) diff --git a/src/console/uart8250mem_console.c b/src/console/uart8250mem_console.c index 923df99..ed77237 100644 --- a/src/console/uart8250mem_console.c +++ b/src/console/uart8250mem_console.c @@ -23,7 +23,7 @@ static u32 uart_bar = 0; -static void uartmem_init(void) +void uartmem_init(void) { uart_bar = uart_mem_init(); } diff --git a/src/include/uart8250.h b/src/include/uart8250.h index 71b9a5f..8457530 100644 --- a/src/include/uart8250.h +++ b/src/include/uart8250.h @@ -125,6 +125,7 @@ void uart8250_tx_flush(unsigned base_port); */ void uart8250_init(unsigned base_port, unsigned divisor); void uart_init(void); +void uartmem_init(void); /* and the same for memory mapped uarts */ unsigned char uart8250_mem_rx_byte(unsigned base_port);

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New patch to review for coreboot: 8d5a1dd Fix automatic ME detection in finalize
by Stefan Reinauer 23 Jul '12

23 Jul '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1284 -gerrit commit 8d5a1ddb04733d2094ea934bec72005497b46b94 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Wed Jun 13 16:31:50 2012 -0700 Fix automatic ME detection in finalize The ME needs to be talked to through the PCIe memory mapped config space. Change-Id: Ic2c5a572a126722a08a82d95df13d11507586c6b Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/southbridge/intel/bd82x6x/me.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c index 0c40ab4..25b88b9 100644 --- a/src/southbridge/intel/bd82x6x/me.c +++ b/src/southbridge/intel/bd82x6x/me.c @@ -533,7 +533,7 @@ static void intel_me7_finalize_smm(void) void intel_me_finalize_smm(void) { - u32 did = pci_read_config32(PCH_ME_DEV, PCI_VENDOR_ID); + u32 did = pcie_read_config32(PCH_ME_DEV, PCI_VENDOR_ID); switch (did) { case 0x80861c3a: intel_me7_finalize_smm();

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New patch to review for coreboot: d58843d ChromeOS: Remove board specific acpi_get_vdat_info()
by Stefan Reinauer 23 Jul '12

23 Jul '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1283 -gerrit commit d58843d71be629039188456cb256c96de1cc5499 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Wed Jun 13 13:17:03 2012 -0700 ChromeOS: Remove board specific acpi_get_vdat_info() The function acpi_get_vdat_info() was moved to the ChromeOS vendor code, and is no longer required to be present for each board. Hence, remove it. Change-Id: I3dc8dbb6119ceffa057373bad7c0058ac0d40eb8 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/mainboard/intel/emeraldlake2/acpi_tables.c | 8 -------- src/mainboard/samsung/lumpy/acpi_tables.c | 6 ------ src/mainboard/samsung/stumpy/acpi_tables.c | 9 --------- 3 files changed, 0 insertions(+), 23 deletions(-) diff --git a/src/mainboard/intel/emeraldlake2/acpi_tables.c b/src/mainboard/intel/emeraldlake2/acpi_tables.c index 01d4b54..e32fc5b 100644 --- a/src/mainboard/intel/emeraldlake2/acpi_tables.c +++ b/src/mainboard/intel/emeraldlake2/acpi_tables.c @@ -318,11 +318,3 @@ unsigned long write_acpi_tables(unsigned long start) printk(BIOS_INFO, "ACPI: done.\n"); return current; } - -#if CONFIG_CHROMEOS -void acpi_get_vdat_info(void **vdat_addr, uint32_t *vdat_size) -{ - *vdat_addr = &gnvs_->chromeos.vdat; - *vdat_size = sizeof(gnvs_->chromeos.vdat); -} -#endif diff --git a/src/mainboard/samsung/lumpy/acpi_tables.c b/src/mainboard/samsung/lumpy/acpi_tables.c index 46fdf31..71b0c59 100644 --- a/src/mainboard/samsung/lumpy/acpi_tables.c +++ b/src/mainboard/samsung/lumpy/acpi_tables.c @@ -315,9 +315,3 @@ unsigned long write_acpi_tables(unsigned long start) printk(BIOS_INFO, "ACPI: done.\n"); return current; } - -void acpi_get_vdat_info(void **vdat_addr, uint32_t *vdat_size) -{ - *vdat_addr = &gnvs_->chromeos.vdat; - *vdat_size = sizeof(gnvs_->chromeos.vdat); -} diff --git a/src/mainboard/samsung/stumpy/acpi_tables.c b/src/mainboard/samsung/stumpy/acpi_tables.c index 68da59d..5654460 100644 --- a/src/mainboard/samsung/stumpy/acpi_tables.c +++ b/src/mainboard/samsung/stumpy/acpi_tables.c @@ -319,12 +319,3 @@ unsigned long write_acpi_tables(unsigned long start) printk(BIOS_INFO, "ACPI: done.\n"); return current; } - -#if CONFIG_CHROMEOS -void acpi_get_vdat_info(void **vdat_addr, uint32_t *vdat_size) -{ - *vdat_addr = &gnvs_->chromeos.vdat; - *vdat_size = sizeof(gnvs_->chromeos.vdat); -} -#endif -

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coreboot July 2012