coreboot July 2012

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New patch to review for coreboot: d4fe2ff chromeos: Pass pointer to ChromeOS ACPI structure instead of VB Shared Data
by Stefan Reinauer 23 Jul '12

23 Jul '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1282 -gerrit commit d4fe2ff5ff318f6125f3aa23d862e37d554f6ff3 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Wed Jun 13 13:12:19 2012 -0700 chromeos: Pass pointer to ChromeOS ACPI structure instead of VB Shared Data coreboot used to pass some information to u-boot in the coreboot table and other information in a modified flat device tree. Since the FDT code was never upstreamed and removed from our tree, u-boot was changed to get the information it needs from the coreboot table alone. However, in the process of this change only the vboot shared data structure was passed on by coreboot, so when u-boot tried to update the ChromeOS specific ACPI entries, it would accidently overwrite the vboot data. This patch passes on the ChromeOS specific ACPI data structure instead of the vboot shared data. Another change to u-boot will teach it how to get to the vboot shared data from there. Change-Id: Ifbb64eafc0d9967887b4cdeebf97d0c4ce019290 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/arch/x86/include/arch/acpi.h | 4 ---- src/vendorcode/google/chromeos/gnvs.c | 9 ++++++++- src/vendorcode/google/chromeos/gnvs.h | 1 + 3 files changed, 9 insertions(+), 5 deletions(-) diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index 8c8106d..0b2cbf4 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -523,8 +523,4 @@ void generate_cpu_entries(void); #endif /* CONFIG_GENERATE_ACPI_TABLES */ -#if CONFIG_CHROMEOS -void acpi_get_vdat_info(void **vdat_addr, uint32_t *vdat_size); -#endif /* CONFIG_CHROMEOS */ - #endif /* __ASM_ACPI_H */ diff --git a/src/vendorcode/google/chromeos/gnvs.c b/src/vendorcode/google/chromeos/gnvs.c index 024dbf8..aaca95a 100644 --- a/src/vendorcode/google/chromeos/gnvs.c +++ b/src/vendorcode/google/chromeos/gnvs.c @@ -23,7 +23,7 @@ #include <console/console.h> #include "gnvs.h" -chromeos_acpi_t *vboot_data; +chromeos_acpi_t *vboot_data = NULL; static u32 me_hash_saved[8]; void chromeos_init_vboot(chromeos_acpi_t *chromeos) @@ -41,7 +41,14 @@ void chromeos_set_me_hash(u32 *hash, int len) /* Copy to NVS or save until it is ready */ if (vboot_data) + /* This does never happen! */ memcpy(vboot_data->mehh, hash, len*sizeof(u32)); else memcpy(me_hash_saved, hash, len*sizeof(u32)); } + +void acpi_get_vdat_info(void **vdat_addr, uint32_t *vdat_size) +{ + *vdat_addr = vboot_data; + *vdat_size = sizeof(*vboot_data); +} diff --git a/src/vendorcode/google/chromeos/gnvs.h b/src/vendorcode/google/chromeos/gnvs.h index 6dd740f..4067494 100644 --- a/src/vendorcode/google/chromeos/gnvs.h +++ b/src/vendorcode/google/chromeos/gnvs.h @@ -64,5 +64,6 @@ typedef struct { extern chromeos_acpi_t *vboot_data; void chromeos_init_vboot(chromeos_acpi_t *chromeos); void chromeos_set_me_hash(u32*, int); +void acpi_get_vdat_info(void **vdat_addr, uint32_t *vdat_size); #endif

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New patch to review for coreboot: 9853ad3 Make ACPI code detect Sandy/Ivy Bridge dynamically
by Stefan Reinauer 23 Jul '12

23 Jul '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1281 -gerrit commit 9853ad32f03481fad470412470684730678cc689 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Mon Jun 11 15:38:15 2012 -0700 Make ACPI code detect Sandy/Ivy Bridge dynamically On systems with socketed CPUs we want to be able to drop in a Sandy Bridge or Ivy Bridge CPU without recompiling the firmware. Hence, detect the north bridge dynamically. In order for this to work, we need Ivy Bridge MRC and coreboot configured for Ivy Bridge. Change-Id: I635bef2c61d47d36a3fdd87f8ecb6e69097ba969 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/northbridge/intel/sandybridge/acpi.c | 4 +++- src/northbridge/intel/sandybridge/sandybridge.h | 8 ++------ 2 files changed, 5 insertions(+), 7 deletions(-) diff --git a/src/northbridge/intel/sandybridge/acpi.c b/src/northbridge/intel/sandybridge/acpi.c index d1174d6..10b1a68 100644 --- a/src/northbridge/intel/sandybridge/acpi.c +++ b/src/northbridge/intel/sandybridge/acpi.c @@ -36,7 +36,9 @@ unsigned long acpi_fill_mcfg(unsigned long current) u32 pciexbar_reg; int max_buses; - dev = dev_find_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_NB, 0); + dev = dev_find_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_SB, 0); + if (!dev) + dev = dev_find_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_IB, 0); if (!dev) return current; diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index 7e12416..f8617de 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -199,12 +199,8 @@ struct ied_header { u8 reserved[34]; } __attribute__ ((packed)); -#if CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE -#define PCI_DEVICE_ID_NB 0x0104 -#endif -#if CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE -#define PCI_DEVICE_ID_NB 0x0154 -#endif +#define PCI_DEVICE_ID_SB 0x0104 +#define PCI_DEVICE_ID_IB 0x0154 #ifdef __SMM__ void intel_sandybridge_finalize_smm(void);

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New patch to review for coreboot: 2f91fad Cougar/Panther Point: Compile in ME7 and ME8 code at the same time
by Stefan Reinauer 23 Jul '12

23 Jul '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1280 -gerrit commit 2f91fad6bebbd00b60f1b0fd1d7501a0400e04f1 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Mon Jun 11 15:15:46 2012 -0700 Cougar/Panther Point: Compile in ME7 and ME8 code at the same time In the short term there might be devices with Sandy Bridge CPUs on mainboards with Panther Point PCHes. While this configuration option is perfectly valid, coreboot currently ties Sandy Bridge to Cougar Point and Ivy Bridge to Panther Point. One occurence is in the ME handling code. To make coreboot most flexible, compile both ME handlers into coreboot and decide at runtime which one to use. Change-Id: Icffe2930873f67c99c3f73e37e7a967f4f002b88 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/southbridge/intel/bd82x6x/Makefile.inc | 8 +++----- src/southbridge/intel/bd82x6x/me.c | 23 ++++++++++++++++++++--- src/southbridge/intel/bd82x6x/me.h | 5 +---- src/southbridge/intel/bd82x6x/me_8.x.c | 8 +++++--- 4 files changed, 29 insertions(+), 15 deletions(-) diff --git a/src/southbridge/intel/bd82x6x/Makefile.inc b/src/southbridge/intel/bd82x6x/Makefile.inc index f086426..11a6b08 100644 --- a/src/southbridge/intel/bd82x6x/Makefile.inc +++ b/src/southbridge/intel/bd82x6x/Makefile.inc @@ -17,9 +17,6 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -me-src-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) += me.c -me-src-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) += me_8.x.c - driver-y += pch.c driver-y += azalia.c driver-y += lpc.c @@ -27,7 +24,8 @@ driver-y += pci.c driver-y += pcie.c driver-y += sata.c driver-y += usb_ehci.c -driver-y += $(me-src-y) +driver-y += me.c +driver-y += me_8.x.c driver-y += smbus.c ramstage-y += me_status.c @@ -37,7 +35,7 @@ ramstage-y += watchdog.c ramstage-y += spi.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c $(me-src-y) finalize.c +smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c me.c me_8.x.c finalize.c romstage-y += early_usb.c early_smbus.c early_me.c me_status.c gpio.c romstage-$(CONFIG_USBDEBUG) += usb_debug.c diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c index 1b7b262..0c40ab4 100644 --- a/src/southbridge/intel/bd82x6x/me.c +++ b/src/southbridge/intel/bd82x6x/me.c @@ -353,8 +353,9 @@ static inline int mei_sendrecv(struct mei_header *mei, struct mkhi_header *mkhi, return 0; } +#ifdef __SMM__ /* Send END OF POST message to the ME */ -int mkhi_end_of_post(void) +static int mkhi_end_of_post(void) { struct mkhi_header mkhi = { .group_id = MKHI_GROUP_ID_GEN, @@ -376,6 +377,7 @@ int mkhi_end_of_post(void) printk(BIOS_INFO, "ME: END OF POST message successful\n"); return 0; } +#endif #if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) && !defined(__SMM__) /* Get ME firmware version */ @@ -460,6 +462,7 @@ static int mkhi_get_fwcaps(void) } #endif +#if CONFIG_CHROMEOS && 0 /* DISABLED */ /* Tell ME to issue a global reset */ int mkhi_global_reset(void) { @@ -490,10 +493,10 @@ int mkhi_global_reset(void) printk(BIOS_ERR, "ME: Global Reset failed\n"); return -1; } +#endif #ifdef __SMM__ - -void intel_me_finalize_smm(void) +static void intel_me7_finalize_smm(void) { struct me_hfs hfs; u32 reg32; @@ -528,6 +531,20 @@ void intel_me_finalize_smm(void) RCBA32_OR(FD2, PCH_DISABLE_MEI1); } +void intel_me_finalize_smm(void) +{ + u32 did = pci_read_config32(PCH_ME_DEV, PCI_VENDOR_ID); + switch (did) { + case 0x80861c3a: + intel_me7_finalize_smm(); + break; + case 0x80861e3a: + intel_me8_finalize_smm(); + break; + default: + printk(BIOS_ERR, "No finalize handler for ME %08x.\n", did); + } +} #else /* !__SMM__ */ /* Determine the path that we should take based on ME status */ diff --git a/src/southbridge/intel/bd82x6x/me.h b/src/southbridge/intel/bd82x6x/me.h index 53964a2..aaeb24d 100644 --- a/src/southbridge/intel/bd82x6x/me.h +++ b/src/southbridge/intel/bd82x6x/me.h @@ -248,14 +248,11 @@ void intel_early_me_status(void); int intel_early_me_init(void); int intel_early_me_uma_size(void); int intel_early_me_init_done(u8 status); -#else -/* ME Kernel Host Interface Messages */ -int mkhi_end_of_post(void); -int mkhi_global_reset(void); #endif #ifdef __SMM__ void intel_me_finalize_smm(void); +void intel_me8_finalize_smm(void); #endif typedef struct { u32 major_version : 16; diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c index c7a69fe..32f660e 100644 --- a/src/southbridge/intel/bd82x6x/me_8.x.c +++ b/src/southbridge/intel/bd82x6x/me_8.x.c @@ -357,7 +357,7 @@ static inline int mei_sendrecv(struct mei_header *mei, struct mkhi_header *mkhi, } /* Send END OF POST message to the ME */ -int mkhi_end_of_post(void) +static int mkhi_end_of_post(void) { struct mkhi_header mkhi = { .group_id = MKHI_GROUP_ID_GEN, @@ -457,8 +457,9 @@ static void me_print_fwcaps(mbp_fw_caps *caps_section) } #endif +#if CONFIG_CHROMEOS && 0 /* DISABLED */ /* Tell ME to issue a global reset */ -int mkhi_global_reset(void) +static int mkhi_global_reset(void) { struct me_global_reset reset = { .request_origin = GLOBAL_RESET_BIOS_POST, @@ -486,10 +487,11 @@ int mkhi_global_reset(void) printk(BIOS_ERR, "ME: Global Reset failed\n"); return -1; } +#endif #ifdef __SMM__ -void intel_me_finalize_smm(void) +void intel_me8_finalize_smm(void) { struct me_hfs hfs; u32 reg32;

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New patch to review for coreboot: a68e3d1 Fix ME hash functions on Panther Point/Cougar Point
by Stefan Reinauer 23 Jul '12

23 Jul '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1279 -gerrit commit a68e3d1880817916d1f58413340d672cf8341dd9 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Mon Jun 11 14:13:09 2012 -0700 Fix ME hash functions on Panther Point/Cougar Point - On Cougar Point there may have been stack corruption during the ME hash verification - On Panther Point the ME firmware hash was not passed on to the OS Change-Id: I73fc10db63ecff939833fb856a6da1e394155043 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/southbridge/intel/bd82x6x/me.c | 2 +- src/southbridge/intel/bd82x6x/me_8.x.c | 16 +++++++++------- 2 files changed, 10 insertions(+), 8 deletions(-) diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c index a1ae06d..1b7b262 100644 --- a/src/southbridge/intel/bd82x6x/me.c +++ b/src/southbridge/intel/bd82x6x/me.c @@ -621,7 +621,7 @@ static int intel_mei_setup(device_t dev) static int intel_me_extend_valid(device_t dev) { struct me_heres status; - u32 extend[] = {0}; + u32 extend[8] = {0}; int i, count = 0; pci_read_dword_ptr(dev, &status, PCI_ME_HERES); diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c index 1bb2ce3..c7a69fe 100644 --- a/src/southbridge/intel/bd82x6x/me_8.x.c +++ b/src/southbridge/intel/bd82x6x/me_8.x.c @@ -49,6 +49,7 @@ #if CONFIG_CHROMEOS #include <vendorcode/google/chromeos/chromeos.h> +#include <vendorcode/google/chromeos/gnvs.h> #endif #ifndef __SMM__ @@ -622,7 +623,7 @@ static int intel_mei_setup(device_t dev) static int intel_me_extend_valid(device_t dev) { struct me_heres status; - u32 extend; + u32 extend[8] = {0}; int i, count = 0; pci_read_dword_ptr(dev, &status, PCI_ME_HERES); @@ -651,16 +652,17 @@ static int intel_me_extend_valid(device_t dev) return -1; } - /* - * TODO(dlaurie) Verify the hash against a saved good value. - */ - for (i = 0; i < count; ++i) { - extend = pci_read_config32(dev, PCI_ME_HER(i)); - printk(BIOS_DEBUG, "%08x", extend); + extend[i] = pci_read_config32(dev, PCI_ME_HER(i)); + printk(BIOS_DEBUG, "%08x", extend[i]); } printk(BIOS_DEBUG, "\n"); +#if CONFIG_CHROMEOS + /* Save hash in NVS for the OS to verify */ + chromeos_set_me_hash(extend, count); +#endif + return 0; }

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New patch to review for coreboot: 428cab4 Move GGL0001 ACPI code to generic ChromeOS code
by Stefan Reinauer 23 Jul '12

23 Jul '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1278 -gerrit commit 428cab4ee82c28829af13fad56db22914530ee68 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Thu Jun 7 15:38:44 2012 -0700 Move GGL0001 ACPI code to generic ChromeOS code The only difference in this code on all our platforms is the array describing the GPIOs. Hence, only keep that array in the mainboard ChromeOS directory and move everything else to generic ChromeOS ACPI code. Change-Id: I9fc75842af64530c1255bea1c5f803c5316d6da6 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/mainboard/intel/emeraldlake2/acpi/chromeos.asl | 100 +----------------- src/mainboard/intel/emeraldlake2/dsdt.asl | 1 + src/mainboard/samsung/lumpy/acpi/chromeos.asl | 99 +----------------- src/mainboard/samsung/lumpy/dsdt.asl | 1 + src/mainboard/samsung/stumpy/acpi/chromeos.asl | 100 +----------------- src/mainboard/samsung/stumpy/dsdt.asl | 1 + src/vendorcode/google/chromeos/acpi/chromeos.asl | 109 ++++++++++++++++++++ 7 files changed, 127 insertions(+), 284 deletions(-) diff --git a/src/mainboard/intel/emeraldlake2/acpi/chromeos.asl b/src/mainboard/intel/emeraldlake2/acpi/chromeos.asl index 6a61b0d..307e2e2 100644 --- a/src/mainboard/intel/emeraldlake2/acpi/chromeos.asl +++ b/src/mainboard/intel/emeraldlake2/acpi/chromeos.asl @@ -17,98 +17,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -Device (CRHW) -{ - Name(_HID, EISAID("GGL0001")) - - Method(_STA, 0, Serialized) - { - Return (0xb) - } - - Method(CHSW, 0, Serialized) - { - Name (WSHC, Package() { VBT3 }) - Return (WSHC) - } - - Method(FWID, 0, Serialized) - { - Name (DIW1, "") - ToString(VBT5, 63, DIW1) - Name (DIWF, Package() { DIW1 }) - Return(DIWF) - } - - Method(FRID, 0, Serialized) - { - Name (DIR1, "") - ToString(VBT6, 63, DIR1) - Name (DIRF, Package() { DIR1 }) - Return (DIRF) - } - - Method(HWID, 0, Serialized) - { - Name (DIW0, "") - ToString(VBT4, 255, DIW0) - Name (DIWH, Package() { DIW0 }) - Return (DIWH) - } - - Method(BINF, 0, Serialized) - { - Name (FNIB, Package() { VBT0, VBT1, VBT2, VBT7, VBT8 }) - Return (FNIB) - } - - Method(GPIO, 0, Serialized) - { - Name(OIPG, Package() { - Package() { 0x001, 0, 22, "CougarPoint" }, // recovery button - Package() { 0x002, 1, 57, "CougarPoint" }, // developer switch - Package() { 0x003, 0, 48, "CougarPoint" }, // firmware write protect - }) - Return (OIPG) - - } - - Method(VBNV, 0, Serialized) - { - Name(VNBV, Package() { - // See src/vendorcode/google/chromeos/Kconfig - // for the definition of these: - CONFIG_VBNV_OFFSET, - CONFIG_VBNV_SIZE - }) - Return(VNBV) - } - - Method(VDAT, 0, Serialized) - { - Name(TAD0,"") - ToBuffer(CHVD, TAD0) - Name (TADV, Package() { TAD0 }) - Return (TADV) - } - - Method(FMAP, 0, Serialized) - { - Name(PAMF, Package() { VBT9 }) - Return(PAMF) - } - - Method(MECK, 0, Serialized) - { - Name(HASH, Package() { MEHH }) - Return(HASH) - } - - Method(MLST, 0, Serialized) - { - Name(TSLM, Package() { "CHSW", "FWID", "HWID", "FRID", "BINF", - "GPIO", "VBNV", "VDAT", "FMAP", "MECK" - }) - Return (TSLM) - } -} +Name(OIPG, Package() { + Package() { 0x001, 0, 22, "CougarPoint" }, // recovery button + Package() { 0x002, 1, 57, "CougarPoint" }, // developer switch + Package() { 0x003, 0, 48, "CougarPoint" }, // firmware write protect +}) diff --git a/src/mainboard/intel/emeraldlake2/dsdt.asl b/src/mainboard/intel/emeraldlake2/dsdt.asl index 9af312a..b67082e 100644 --- a/src/mainboard/intel/emeraldlake2/dsdt.asl +++ b/src/mainboard/intel/emeraldlake2/dsdt.asl @@ -49,6 +49,7 @@ DefinitionBlock( } #include "acpi/chromeos.asl" + #include <vendorcode/google/chromeos/acpi/chromeos.asl> /* Chipset specific sleep states */ #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> diff --git a/src/mainboard/samsung/lumpy/acpi/chromeos.asl b/src/mainboard/samsung/lumpy/acpi/chromeos.asl index fc7be20..fbe98c9 100644 --- a/src/mainboard/samsung/lumpy/acpi/chromeos.asl +++ b/src/mainboard/samsung/lumpy/acpi/chromeos.asl @@ -17,98 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -Device (CRHW) -{ - Name(_HID, EISAID("GGL0001")) +Name(OIPG, Package() { + Package() { 0x001, 0, 42, "CougarPoint" }, // recovery button + Package() { 0x002, 1, 17, "CougarPoint" }, // developer switch + Package() { 0x003, 1, 24, "CougarPoint" }, // firmware write protect +}) - Method(_STA, 0, Serialized) - { - Return (0xb) - } - - Method(CHSW, 0, Serialized) - { - Name (WSHC, Package() { VBT3 }) - Return (WSHC) - } - - Method(FWID, 0, Serialized) - { - Name (DIW1, "") - ToString(VBT5, 63, DIW1) - Name (DIWF, Package() { DIW1 }) - Return(DIWF) - } - - Method(FRID, 0, Serialized) - { - Name (DIR1, "") - ToString(VBT6, 63, DIR1) - Name (DIRF, Package() { DIR1 }) - Return (DIRF) - } - - Method(HWID, 0, Serialized) - { - Name (DIW0, "") - ToString(VBT4, 255, DIW0) - Name (DIWH, Package() { DIW0 }) - Return (DIWH) - } - - Method(BINF, 0, Serialized) - { - Name (FNIB, Package() { VBT0, VBT1, VBT2, VBT7, VBT8 }) - Return (FNIB) - } - - Method(GPIO, 0, Serialized) - { - Name(OIPG, Package() { - Package() { 0x001, 0, 42, "CougarPoint" }, // recovery button - Package() { 0x002, 1, 17, "CougarPoint" }, // developer switch - Package() { 0x003, 1, 24, "CougarPoint" }, // firmware write protect - }) - Return (OIPG) - - } - - Method(VBNV, 0, Serialized) - { - Name(VNBV, Package() { - // See src/vendorcode/google/chromeos/Kconfig - // for the definition of these: - CONFIG_VBNV_OFFSET, - CONFIG_VBNV_SIZE - }) - Return(VNBV) - } - - Method(VDAT, 0, Serialized) - { - Name(TAD0,"") - ToBuffer(CHVD, TAD0) - Name (TADV, Package() { TAD0 }) - Return (TADV) - } - - Method(FMAP, 0, Serialized) - { - Name(PAMF, Package() { VBT9 }) - Return(PAMF) - } - - Method(MECK, 0, Serialized) - { - Name(HASH, Package() { MEHH }) - Return(HASH) - } - - Method(MLST, 0, Serialized) - { - Name(TSLM, Package() { "CHSW", "FWID", "HWID", "FRID", "BINF", - "GPIO", "VBNV", "VDAT", "FMAP", "MECK" - }) - Return (TSLM) - } -} diff --git a/src/mainboard/samsung/lumpy/dsdt.asl b/src/mainboard/samsung/lumpy/dsdt.asl index 94adfda..c1c9685 100644 --- a/src/mainboard/samsung/lumpy/dsdt.asl +++ b/src/mainboard/samsung/lumpy/dsdt.asl @@ -52,6 +52,7 @@ DefinitionBlock( } #include "acpi/chromeos.asl" + #include <vendorcode/google/chromeos/acpi/chromeos.asl> /* Chipset specific sleep states */ #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> diff --git a/src/mainboard/samsung/stumpy/acpi/chromeos.asl b/src/mainboard/samsung/stumpy/acpi/chromeos.asl index f517b16..739e0d4 100644 --- a/src/mainboard/samsung/stumpy/acpi/chromeos.asl +++ b/src/mainboard/samsung/stumpy/acpi/chromeos.asl @@ -17,98 +17,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -Device (CRHW) -{ - Name(_HID, EISAID("GGL0001")) - - Method(_STA, 0, Serialized) - { - Return (0xb) - } - - Method(CHSW, 0, Serialized) - { - Name (WSHC, Package() { VBT3 }) - Return (WSHC) - } - - Method(FWID, 0, Serialized) - { - Name (DIW1, "") - ToString(VBT5, 63, DIW1) - Name (DIWF, Package() { DIW1 }) - Return(DIWF) - } - - Method(FRID, 0, Serialized) - { - Name (DIR1, "") - ToString(VBT6, 63, DIR1) - Name (DIRF, Package() { DIR1 }) - Return (DIRF) - } - - Method(HWID, 0, Serialized) - { - Name (DIW0, "") - ToString(VBT4, 255, DIW0) - Name (DIWH, Package() { DIW0 }) - Return (DIWH) - } - - Method(BINF, 0, Serialized) - { - Name (FNIB, Package() { VBT0, VBT1, VBT2, VBT7, VBT8 }) - Return (FNIB) - } - - Method(GPIO, 0, Serialized) - { - Name(OIPG, Package() { - Package() { 0x001, 0, 42, "CougarPoint" }, // recovery button - Package() { 0x002, 1, 17, "CougarPoint" }, // developer switch - Package() { 0x003, 1, 68, "CougarPoint" }, // firmware write protect - }) - Return (OIPG) - - } - - Method(VBNV, 0, Serialized) - { - Name(VNBV, Package() { - // See src/vendorcode/google/chromeos/Kconfig - // for the definition of these: - CONFIG_VBNV_OFFSET, - CONFIG_VBNV_SIZE - }) - Return(VNBV) - } - - Method(VDAT, 0, Serialized) - { - Name(TAD0,"") - ToBuffer(CHVD, TAD0) - Name (TADV, Package() { TAD0 }) - Return (TADV) - } - - Method(FMAP, 0, Serialized) - { - Name(PAMF, Package() { VBT9 }) - Return(PAMF) - } - - Method(MECK, 0, Serialized) - { - Name(HASH, Package() { MEHH }) - Return(HASH) - } - - Method(MLST, 0, Serialized) - { - Name(TSLM, Package() { "CHSW", "FWID", "HWID", "FRID", "BINF", - "GPIO", "VBNV", "VDAT", "FMAP", "MECK" - }) - Return (TSLM) - } -} +Name(OIPG, Package() { + Package() { 0x001, 0, 42, "CougarPoint" }, // recovery button + Package() { 0x002, 1, 17, "CougarPoint" }, // developer switch + Package() { 0x003, 1, 68, "CougarPoint" }, // firmware write protect +}) diff --git a/src/mainboard/samsung/stumpy/dsdt.asl b/src/mainboard/samsung/stumpy/dsdt.asl index 63aa47e..608827a 100644 --- a/src/mainboard/samsung/stumpy/dsdt.asl +++ b/src/mainboard/samsung/stumpy/dsdt.asl @@ -50,6 +50,7 @@ DefinitionBlock( } #include "acpi/chromeos.asl" + #include <vendorcode/google/chromeos/acpi/chromeos.asl> /* Chipset specific sleep states */ #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> diff --git a/src/vendorcode/google/chromeos/acpi/chromeos.asl b/src/vendorcode/google/chromeos/acpi/chromeos.asl new file mode 100644 index 0000000..278296c --- /dev/null +++ b/src/vendorcode/google/chromeos/acpi/chromeos.asl @@ -0,0 +1,109 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +Device (CRHW) +{ + Name(_HID, EISAID("GGL0001")) + + Method(_STA, 0, Serialized) + { + Return (0xb) + } + + Method(CHSW, 0, Serialized) + { + Name (WSHC, Package() { VBT3 }) + Return (WSHC) + } + + Method(FWID, 0, Serialized) + { + Name (DIW1, "") + ToString(VBT5, 63, DIW1) + Name (DIWF, Package() { DIW1 }) + Return(DIWF) + } + + Method(FRID, 0, Serialized) + { + Name (DIR1, "") + ToString(VBT6, 63, DIR1) + Name (DIRF, Package() { DIR1 }) + Return (DIRF) + } + + Method(HWID, 0, Serialized) + { + Name (DIW0, "") + ToString(VBT4, 255, DIW0) + Name (DIWH, Package() { DIW0 }) + Return (DIWH) + } + + Method(BINF, 0, Serialized) + { + Name (FNIB, Package() { VBT0, VBT1, VBT2, VBT7, VBT8 }) + Return (FNIB) + } + + Method(GPIO, 0, Serialized) + { + Return (OIPG) + + } + + Method(VBNV, 0, Serialized) + { + Name(VNBV, Package() { + // See src/vendorcode/google/chromeos/Kconfig + // for the definition of these: + CONFIG_VBNV_OFFSET, + CONFIG_VBNV_SIZE + }) + Return(VNBV) + } + + Method(VDAT, 0, Serialized) + { + Name(TAD0,"") + ToBuffer(CHVD, TAD0) + Name (TADV, Package() { TAD0 }) + Return (TADV) + } + + Method(FMAP, 0, Serialized) + { + Name(PAMF, Package() { VBT9 }) + Return(PAMF) + } + + Method(MECK, 0, Serialized) + { + Name(HASH, Package() { MEHH }) + Return(HASH) + } + + Method(MLST, 0, Serialized) + { + Name(TSLM, Package() { "CHSW", "FWID", "HWID", "FRID", "BINF", + "GPIO", "VBNV", "VDAT", "FMAP", "MECK" + }) + Return (TSLM) + } +}

1 0

New patch to review for coreboot: 07e941b Fix MRC cache update delays
by Stefan Reinauer 23 Jul '12

23 Jul '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1277 -gerrit commit 07e941bfd3b775f6f3f03768d886a6b735d73d2d Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Wed Jun 6 13:24:32 2012 -0700 Fix MRC cache update delays When no valid MRC cache area is found, the mrc_cache data structure was used without prior initialization. This sometimes caused a long delay when booting because compute_ip_checksum would checksum up to 4GB of memory. Change-Id: I6a0ca1aa618838bbc3d042be425700fc34b427f2 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/northbridge/intel/sandybridge/Kconfig | 18 +++++++++++++ src/northbridge/intel/sandybridge/mrccache.c | 36 ++++++++++++++++---------- 2 files changed, 40 insertions(+), 14 deletions(-) diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig index 67b3def..7dfd10d 100644 --- a/src/northbridge/intel/sandybridge/Kconfig +++ b/src/northbridge/intel/sandybridge/Kconfig @@ -78,6 +78,24 @@ config CACHE_MRC_SIZE_KB int default 512 +# FIXME: build from rom size +config MRC_CACHE_BASE + hex + default 0xff800000 + +config MRC_CACHE_LOCATION + hex + default 0x370000 + +config MRC_CACHE_SIZE + hex + default 0x10000 + +config MRC_CACHE_ALIGNMENT + hex + default 0x1000 + + config DCACHE_RAM_BASE hex default 0xff7e0000 diff --git a/src/northbridge/intel/sandybridge/mrccache.c b/src/northbridge/intel/sandybridge/mrccache.c index d774ff0..00b3bdd 100644 --- a/src/northbridge/intel/sandybridge/mrccache.c +++ b/src/northbridge/intel/sandybridge/mrccache.c @@ -118,17 +118,22 @@ struct mrc_data_container *find_current_mrc_cache(void) * from having no cache area at all */ return mrc_cache; - } else { - /* Search for the last filled entry in the region */ - while (is_mrc_cache(mrc_next)) { - entry_id++; - mrc_cache = mrc_next; - mrc_next = next_mrc_block(mrc_cache); - /* Stay in the mrc data region */ - if ((void*)mrc_next >= (void*)(mrc_region + region_size)) - break; - } - entry_id--; + } + + /* Search for the last filled entry in the region */ + while (is_mrc_cache(mrc_next)) { + entry_id++; + mrc_cache = mrc_next; + mrc_next = next_mrc_block(mrc_cache); + /* Stay in the mrc data region */ + if ((void*)mrc_next >= (void*)(mrc_region + region_size)) + break; + } + entry_id--; + + if (entry_id == -1) { + printk(BIOS_ERR, "%s: No valid MRC cache found.\n", __func__); + return NULL; } /* Verify checksum */ @@ -150,6 +155,7 @@ struct mrc_data_container *find_current_mrc_cache(void) #if !defined(__PRE_RAM__) void update_mrc_cache(void) { + printk(BIOS_DEBUG, "Updating MRC cache data.\n"); struct mrc_data_container *current = cbmem_find(CBMEM_ID_MRCDATA); if (!current) { printk(BIOS_ERR, "No MRC cache in cbmem. Can't update flash.\n"); @@ -166,12 +172,14 @@ void update_mrc_cache(void) // 0. compare MRC data to last mrc-cache block (exit if same) struct mrc_data_container *cache; if ((cache = find_current_mrc_cache()) == NULL) { - printk(BIOS_DEBUG, "Failure looking for current last block\n"); + printk(BIOS_DEBUG, "Failure looking for current last block.\n"); return; } - if ((cache->mrc_data_size == current->mrc_data_size) && (memcmp(cache, current, cache->mrc_data_size) == 0)) { - printk(BIOS_DEBUG, "MRC data in flash is up to date. No update.\n"); + if ((cache->mrc_data_size == current->mrc_data_size) && + (memcmp(cache, current, cache->mrc_data_size) == 0)) { + printk(BIOS_DEBUG, + "MRC data in flash is up to date. No update.\n"); return; }

1 0

New patch to review for coreboot: 3f49a21 Remove code that enables/disables VMX in coreboot on chromebooks.
by Stefan Reinauer 23 Jul '12

23 Jul '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1276 -gerrit commit 3f49a21848c62581852fe5de99a65a094c92c212 Author: Ronald G. Minnich <rminnich(a)chromium.org> Date: Tue Jun 5 14:08:10 2012 -0700 Remove code that enables/disables VMX in coreboot on chromebooks. There are several reasons for this: 1. It's a core setting, not a platform setting, which is bizarre. But, we disable vmx via an SMI, and that only happens on core 0. Hence, the code did not correctly make the same settings on all cores- one had them disabled, the others were in an unknown state. When (e.g.) kvm started on a vmx-enabled core, then moved to a vmx-disabled core, the processor would reset *very* quickly. Changing this would be messy. 2. On the CPU on link, there is something about trying to set the lock bit that is getting a GPF. 3. It's the wrong place and time to set it. Once controlled, they can't be changed in the kernel. The kernel is what should control this feature, not the BIOS, as we have learned time and time again. If somebody is in as root and can start a VM, you have a lot more to worry about than someone starting a guest virtual machine. Change-Id: I4f36093f1b68207251584066ccb9a6bcfeec767e Signed-off-by: Ronald G. Minnich <rminnich(a)chromium.org> --- src/cpu/intel/model_206ax/Kconfig | 4 --- src/cpu/intel/model_206ax/finalize.c | 1 - src/cpu/intel/model_206ax/model_206ax_init.c | 38 -------------------------- 3 files changed, 0 insertions(+), 43 deletions(-) diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig index 1b1b8ee..6c70993 100644 --- a/src/cpu/intel/model_206ax/Kconfig +++ b/src/cpu/intel/model_206ax/Kconfig @@ -21,10 +21,6 @@ config SMM_TSEG_SIZE hex default 0x800000 -config ENABLE_VMX - bool "Enable VMX for virtualization" - default n - endif if CPU_INTEL_MODEL_206AX diff --git a/src/cpu/intel/model_206ax/finalize.c b/src/cpu/intel/model_206ax/finalize.c index 9de94c4..68cef8d 100644 --- a/src/cpu/intel/model_206ax/finalize.c +++ b/src/cpu/intel/model_206ax/finalize.c @@ -43,7 +43,6 @@ static void msr_set_bit(unsigned reg, unsigned bit) void intel_model_206ax_finalize_smm(void) { - msr_set_bit(IA32_FEATURE_CONTROL, 0); msr_set_bit(MSR_PMG_CST_CONFIG_CONTROL, 15); /* Lock AES-NI only if supported */ diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c index d60c237..b88d7d4 100644 --- a/src/cpu/intel/model_206ax/model_206ax_init.c +++ b/src/cpu/intel/model_206ax/model_206ax_init.c @@ -119,41 +119,6 @@ static const uint32_t microcode_updates[] = { #include "x06_microcode.h" }; -static void enable_vmx(void) -{ - struct cpuid_result regs; - msr_t msr; - int enable = CONFIG_ENABLE_VMX; - - msr = rdmsr(IA32_FEATURE_CONTROL); - - if (msr.lo & (1 << 0)) { - printk(BIOS_ERR, "VMX is locked, so enable_vmx will do nothing\n"); - /* VMX locked. If we set it again we get an illegal - * instruction - */ - return; - } - - regs = cpuid(1); - printk(BIOS_DEBUG, "%s VMX\n", enable ? "Enabling" : "Disabling"); - if (regs.ecx & CPUID_VMX) { - if (enable) - msr.lo |= (1 << 2); - else - msr.lo &= ~(1 << 2); - - if (regs.ecx & CPUID_SMX) { - if (enable) - msr.lo |= (1 << 1); - else - msr.lo &= ~(1 << 1); - } - } - - wrmsr(IA32_FEATURE_CONTROL, msr); -} - /* Convert time in seconds to POWER_LIMIT_1_TIME MSR value */ static const u8 power_limit_time_sec_to_msr[] = { [0] = 0x00, @@ -456,9 +421,6 @@ static void model_206ax_init(device_t cpu) enable_lapic_tpr(); setup_lapic(); - /* Enable virtualization if enabled in CMOS */ - enable_vmx(); - /* Configure C States */ configure_c_states();

1 0

New patch to review for coreboot: 104f855 malloc/memalign: Remove unneeded linker check
by Stefan Reinauer 23 Jul '12

23 Jul '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1275 -gerrit commit 104f85537f63a2ace2176c70cdc1b6a4ae6f2334 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Wed Jun 6 13:43:52 2012 -0700 malloc/memalign: Remove unneeded linker check This check got in the code when some Linux distros shipped broken linkers around 1999. Since then, the code around that check was changed, and it does not make sense anymore to have this check. Change-Id: I37c6b690d72f55c18ba4c34e8541a6a441e5e67a Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/lib/malloc.c | 4 ---- 1 files changed, 0 insertions(+), 4 deletions(-) diff --git a/src/lib/malloc.c b/src/lib/malloc.c index bf8a15a..d2011a1 100644 --- a/src/lib/malloc.c +++ b/src/lib/malloc.c @@ -21,10 +21,6 @@ void *memalign(size_t boundary, size_t size) MALLOCDBG("%s Enter, boundary %zu, size %zu, free_mem_ptr %p\n", __func__, boundary, size, free_mem_ptr); - /* Overzealous linker check */ - if (free_mem_ptr <= 0) - die("Error! memalign: Free_mem_ptr <= 0"); - free_mem_ptr = (void *)ALIGN((unsigned long)free_mem_ptr, boundary); p = free_mem_ptr;

1 0

New patch to review for coreboot: df4917d Remove unused free() function
by Stefan Reinauer 23 Jul '12

23 Jul '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1274 -gerrit commit df4917d5d02ea8636c6c20ee1a312301712e7406 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Wed Jun 6 13:42:09 2012 -0700 Remove unused free() function Since coreboot is running very short, we don't free memory. Hence, drop (dummy) free() Change-Id: I6e2737f07c6b9f73ebfad7d124b97a57cb7454a3 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/include/stdlib.h | 1 - src/lib/malloc.c | 6 ------ 2 files changed, 0 insertions(+), 7 deletions(-) diff --git a/src/include/stdlib.h b/src/include/stdlib.h index bd0ee30..bb57ab3 100644 --- a/src/include/stdlib.h +++ b/src/include/stdlib.h @@ -14,7 +14,6 @@ #if !defined(__PRE_RAM__) void *memalign(size_t boundary, size_t size); void *malloc(size_t size); -void free(void *ptr); #endif #endif /* STDLIB_H */ diff --git a/src/lib/malloc.c b/src/lib/malloc.c index 4115738..bf8a15a 100644 --- a/src/lib/malloc.c +++ b/src/lib/malloc.c @@ -49,9 +49,3 @@ void *malloc(size_t size) { return memalign(sizeof(u64), size); } - -void free(void *where) -{ - /* Don't care */ - MALLOCDBG("free %p\n", where); -}

1 0

New patch to review for coreboot: 5056b5b SPI flash layer: remove unused function spi_flash_free()
by Stefan Reinauer 23 Jul '12

23 Jul '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1273 -gerrit commit 5056b5bb37bc1b86e901fe5738df27ca568c8cb8 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Wed Jun 6 13:40:12 2012 -0700 SPI flash layer: remove unused function spi_flash_free() We don't ever free memory in coreboot, hence drop spi_flash_free() and spi_free_slave() Change-Id: I0ca3f78574ceb4516e7d33c06ab1a58abfb3b0ec Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/drivers/spi/spi_flash.c | 7 ------- src/include/spi.h | 7 ------- src/include/spi_flash.h | 1 - src/southbridge/intel/bd82x6x/spi.c | 6 ------ 4 files changed, 0 insertions(+), 21 deletions(-) diff --git a/src/drivers/spi/spi_flash.c b/src/drivers/spi/spi_flash.c index 0b859f3..6cec611 100644 --- a/src/drivers/spi/spi_flash.c +++ b/src/drivers/spi/spi_flash.c @@ -297,12 +297,5 @@ err_manufacturer_probe: err_read_id: spi_release_bus(spi); err_claim_bus: - spi_free_slave(spi); return NULL; } - -void spi_flash_free(struct spi_flash *flash) -{ - spi_free_slave(flash->spi); - free(flash); -} diff --git a/src/include/spi.h b/src/include/spi.h index bb84258..bee851e 100644 --- a/src/include/spi.h +++ b/src/include/spi.h @@ -84,13 +84,6 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, unsigned int max_hz, unsigned int mode); /*----------------------------------------------------------------------- - * Free any memory associated with a SPI slave. - * - * slave: The SPI slave - */ -void spi_free_slave(struct spi_slave *slave); - -/*----------------------------------------------------------------------- * Claim the bus and prepare it for communication with a given slave. * * This must be called before doing any transfers with a SPI slave. It diff --git a/src/include/spi_flash.h b/src/include/spi_flash.h index 2a1dcd4..b84bd96 100644 --- a/src/include/spi_flash.h +++ b/src/include/spi_flash.h @@ -68,7 +68,6 @@ struct spi_flash { struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs, unsigned int max_hz, unsigned int spi_mode); -void spi_flash_free(struct spi_flash *flash); static inline int spi_flash_read(struct spi_flash *flash, u32 offset, size_t len, void *buf) diff --git a/src/southbridge/intel/bd82x6x/spi.c b/src/southbridge/intel/bd82x6x/spi.c index ccc530d..4cd9af0 100644 --- a/src/southbridge/intel/bd82x6x/spi.c +++ b/src/southbridge/intel/bd82x6x/spi.c @@ -280,12 +280,6 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, return slave; } -void spi_free_slave(struct spi_slave *_slave) -{ - ich_spi_slave *slave = (ich_spi_slave *)_slave; - free(slave); -} - /* * Check if this device ID matches one of supported Intel PCH devices. *

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coreboot July 2012