coreboot July 2012

coreboot@coreboot.org

35 participants
639 discussions

New patch to review for coreboot: e5ef86a Add correct bios callout into read event routine
by Zheng Bao 23 Jul '12

23 Jul '12

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1266 -gerrit commit e5ef86aa853de415e2254db14d11d9c8ab80332f Author: zbao <fishbaozi(a)gmail.com> Date: Mon Jul 23 19:57:43 2012 +0800 Add correct bios callout into read event routine Read event routine didn't get the correct BIOS callout. So it could not get the heap address. Then it would creat many warning in serial port. Change-Id: Ia35601bda1579c7f726ed767d7be78713ac185d2 Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: zbao <fishbaozi(a)gmail.com> --- src/mainboard/amd/parmer/agesawrapper.c | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mainboard/amd/parmer/agesawrapper.c b/src/mainboard/amd/parmer/agesawrapper.c index ff36750..6f44d46 100644 --- a/src/mainboard/amd/parmer/agesawrapper.c +++ b/src/mainboard/amd/parmer/agesawrapper.c @@ -423,7 +423,7 @@ agesawrapper_amdinitlate ( Status = AmdInitLate(AmdLateParams); /* CDIT table is not created. */ if (Status != AGESA_SUCCESS) { - /* agesawrapper_amdreadeventlog(AmdLateParams->StdHeader.HeapStatus); */ + agesawrapper_amdreadeventlog(AmdLateParams->StdHeader.HeapStatus); ASSERT(Status == AGESA_SUCCESS); } @@ -752,7 +752,7 @@ agesawrapper_amdreadeventlog ( &(AmdEventParams.StdHeader)); AmdEventParams.StdHeader.AltImageBasePtr = 0; - AmdEventParams.StdHeader.CalloutPtr = NULL; + AmdEventParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; AmdEventParams.StdHeader.Func = 0; AmdEventParams.StdHeader.ImageBasePtr = 0; AmdEventParams.StdHeader.HeapStatus = HeapStatus;

1 0

New patch to review for coreboot: 07f5c00 Remove the misleading 0x100 from the limit.
by Zheng Bao 23 Jul '12

23 Jul '12

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1265 -gerrit commit 07f5c00117ba96dbd1688c120af1f7288d178c92 Author: zbao <fishbaozi(a)gmail.com> Date: Mon Jul 23 19:52:58 2012 +0800 Remove the misleading 0x100 from the limit. I dont known if missed something, but why an extra 0x100 was added to limit? My board would get the wrong memory table entry 7f000000-7fffffff as RAM, which is higher than TOM. coreboot memory table: 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES 1. 0000000000001000-000000000009ffff: RAM 2. 00000000000c0000-000000005e13efff: RAM 3. 000000005e13f000-000000005effffff: CONFIGURATION TABLES 4. 000000005f000000-000000007effffff: RESERVED 5. 000000007f000000-000000007fffffff: RAM 6. 00000000a0000000-00000000afffffff: RESERVED Change-Id: I3848ed5f23001e5bd61a19833650fe13df26eef3 Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: zbao <fishbaozi(a)gmail.com> --- src/northbridge/amd/agesa/family15tn/northbridge.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index 12aab33..8ad7841 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -790,7 +790,7 @@ static void domain_set_resources(device_t dev) if (!(d.mask & 1)) continue; basek = ((resource_t)(d.base & 0x1fffff00)) << 9; // could overflow, we may lost 6 bit here - limitk = ((resource_t)((d.mask + 0x00000100) & 0x1fffff00)) << 9 ; + limitk = ((resource_t)(d.mask & 0x1fffff00)) << 9 ; sizek = limitk - basek;

1 0

New patch to review for coreboot: 07b7335 Limit the device field to 5 bits.
by Zheng Bao 23 Jul '12

23 Jul '12

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1264 -gerrit commit 07b7335678dc7d91b1c554f2c03e8ba5ef10f600 Author: zbao <fishbaozi(a)gmail.com> Date: Mon Jul 23 19:49:40 2012 +0800 Limit the device field to 5 bits. The field device in PCI_ADDRESS only takes 5 bits. So if the device number is more than 32, it will truncated to 5 bits. Before this patch, other pci devices will be incorrectly probed as processor node. Change-Id: I64dcd4f4fda7b7080a9905dce580feb829584b94 Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: zbao <fishbaozi(a)gmail.com> --- src/northbridge/amd/agesa/family15tn/northbridge.c | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index bc3877f..12aab33 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -120,8 +120,8 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi static device_t get_node_pci(u32 nodeid, u32 fn) { -#if MAX_NODE_NUMS == 64 - if (nodeid < 32) { +#if MAX_NODE_NUMS + CONFIG_CDB >= 32 + if ((CONFIG_CDB + nodeid) < 32) { return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB + nodeid, fn)); } else { return dev_find_slot(CONFIG_CBB-1, PCI_DEVFN(CONFIG_CDB + nodeid - 32, fn));

1 0

New patch to review for coreboot: 4e390b1 Change multiply ONE_MB to bit shifting.
by Zheng Bao 23 Jul '12

23 Jul '12

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1263 -gerrit commit 4e390b13b760ca44be993d40fc653bfcb487588c Author: zbao <fishbaozi(a)gmail.com> Date: Mon Jul 23 19:44:29 2012 +0800 Change multiply ONE_MB to bit shifting. 2048 * ONE_MB will cause warning, src/northbridge/amd/agesa/family15tn/northbridge.c:667:50: warning: integer overflow in expression [-Woverflow] I guess it will change the data type to signed integer. I think the bit shifting is better. Change-Id: I823f7ead1f7d622bf653cb3bf2ae2343f5e76805 Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: zbao <fishbaozi(a)gmail.com> --- src/northbridge/amd/agesa/family15tn/northbridge.c | 18 +++++++++--------- 1 files changed, 9 insertions(+), 9 deletions(-) diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index c7a87db..bc3877f 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -636,7 +636,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) } #endif -#define ONE_MB 0x100000 +#define ONE_MB_SHIFT 20 void setup_uma_memory(void) { @@ -663,13 +663,13 @@ void setup_uma_memory(void) * >=1G 256M * <1G 64M */ - sys_mem = msr.lo + 16 * ONE_MB; // Ignore 16MB allocated for C6 when finding UMA size - if ((msr2.hi & 0x0000000F) || (sys_mem >= 2048 * ONE_MB)) { - uma_memory_size = 512 * ONE_MB; - } else if (sys_mem >= 1024 * ONE_MB) { - uma_memory_size = 256 * ONE_MB; + sys_mem = msr.lo + (16 << ONE_MB_SHIFT); // Ignore 16MB allocated for C6 when finding UMA size + if ((msr2.hi & 0x0000000F) || (sys_mem >= 2048 << ONE_MB_SHIFT)) { + uma_memory_size = 512 << ONE_MB_SHIFT; + } else if (sys_mem >= 1024 << ONE_MB_SHIFT) { + uma_memory_size = 256 << ONE_MB_SHIFT; } else { - uma_memory_size = 64 * ONE_MB; + uma_memory_size = 64 << ONE_MB_SHIFT; } uma_memory_base = msr.lo - uma_memory_size; /* TOP_MEM1 */ @@ -678,8 +678,8 @@ void setup_uma_memory(void) /* TODO: TOP_MEM2 */ #else - uma_memory_size = 256 * ONE_MB; /* 256M recommended UMA */ - uma_memory_base = 768 * ONE_MB; /* 1GB system memory supported */ + uma_memory_size = 256 << ONE_MB_SHIFT; /* 256M recommended UMA */ + uma_memory_base = 768 << ONE_MB_SHIFT; /* 1GB system memory supported */ #endif }

1 0

New patch to review for coreboot: c3b4a5e sync the northbridge.c with other family.
by Zheng Bao 23 Jul '12

23 Jul '12

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1262 -gerrit commit c3b4a5e90ef23b10d37fa89d0a633982d5a329cd Author: zbao <fishbaozi(a)gmail.com> Date: Mon Jul 23 19:41:03 2012 +0800 sync the northbridge.c with other family. Change-Id: Ice4d0202590fca0169dcda2770ca6add166b5c13 Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: zbao <fishbaozi(a)gmail.com> --- src/mainboard/amd/parmer/devicetree.cb | 5 +- src/mainboard/amd/parmer/mainboard.c | 4 +- src/northbridge/amd/agesa/family15tn/northbridge.c | 43 +++++++++++++++----- 3 files changed, 38 insertions(+), 14 deletions(-) diff --git a/src/mainboard/amd/parmer/devicetree.cb b/src/mainboard/amd/parmer/devicetree.cb index 376e017..4a59b51 100644 --- a/src/mainboard/amd/parmer/devicetree.cb +++ b/src/mainboard/amd/parmer/devicetree.cb @@ -25,7 +25,7 @@ chip northbridge/amd/agesa/family15tn/root_complex device pci_domain 0 on subsystemid 0x1022 0x1410 inherit chip northbridge/amd/agesa/family15tn # CPU side of HT root complex -# device pci 18.0 on # northbridge + device pci 18.0 on # northbridge chip northbridge/amd/agesa/family15tn # PCI side of HT root complex device pci 0.0 on end # Root Complex device pci 1.0 on end # Internal Graphics P2P bridge 0x9804 @@ -37,6 +37,7 @@ chip northbridge/amd/agesa/family15tn/root_complex device pci 6.0 on end # PCIE Slot1 x1 device pci 7.0 on end # LAN device pci 8.0 off end # NB/SB Link P2P bridge + end end chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus device pci 10.0 on end # XHCI HC0 @@ -74,7 +75,7 @@ chip northbridge/amd/agesa/family15tn/root_complex register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE register "gpp_configuration" = "4" end #southbridge/amd/hudson - device pci 18.0 on end +# device pci 18.0 on end #device pci 18.0 on end device pci 18.1 on end device pci 18.2 on end diff --git a/src/mainboard/amd/parmer/mainboard.c b/src/mainboard/amd/parmer/mainboard.c index b16be36..bf04d30 100644 --- a/src/mainboard/amd/parmer/mainboard.c +++ b/src/mainboard/amd/parmer/mainboard.c @@ -55,8 +55,8 @@ int add_mainboard_resources(struct lb_memory *mem) /* UMA is removed from system memory in the northbridge code, but * in some circumstances we want the memory mentioned as reserved. */ - /* TODO: Check out why it is commented. */ -#if 0 /* (CONFIG_GFXUMA == 1) */ + /* TODO: Check out why it was commented. */ +#if CONFIG_GFXUMA printk(BIOS_INFO, "uma_memory_start=0x%llx, uma_memory_size=0x%llx \n", uma_memory_base, uma_memory_size); lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base, diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index dc04afd..c7a87db 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -399,7 +399,7 @@ static void create_vga_resource(device_t dev, unsigned nodeid) * we only deal with the 'first' vga card */ for (link = dev->link_list; link; link = link->next) { if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { -#if CONFIG_MULTIPLE_VGA_ADAPTERS == 1 +#if CONFIG_MULTIPLE_VGA_ADAPTERS extern device_t vga_pri; // the primary vga device, defined in device.c printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, link->secondary,link->subordinate); @@ -447,12 +447,35 @@ static void northbridge_init(struct device *dev) { } +static unsigned scan_chains(device_t dev, unsigned max) +{ + unsigned nodeid; + struct bus *link; + device_t io_hub = NULL; + u32 next_unitid = 0x18; + nodeid = amdfam15_nodeid(dev); + if (nodeid == 0) { + for (link = dev->link_list; link; link = link->next) { + //if (link->link_num == sblink) { /* devicetree put IO Hub on link_lsit[sblink] */ + if (link->link_num == 0) { /* devicetree put IO Hub on link_lsit[0] */ + io_hub = link->children; + if (!io_hub || !io_hub->enabled) { + die("I can't find the IO Hub, or IO Hub not enabled, please check the device tree.\n"); + } + /* Now that nothing is overlapping it is safe to scan the children. */ + max = pci_scan_bus(link, 0x00, ((next_unitid - 1) << 3) | 7, 0); + } + } + } + return max; +} + static struct device_operations northbridge_operations = { .read_resources = read_resources, .set_resources = set_resources, .enable_resources = pci_dev_enable_resources, .init = northbridge_init, - .scan_bus = 0, /*scan_chains, */ + .scan_bus = scan_chains, .enable = 0, .ops_pci = 0, }; @@ -508,7 +531,7 @@ static void domain_read_resources(device_t dev) /* FIXME: do we need to check extend conf space? I don't believe that much preset value */ -#if CONFIG_PCI_64BIT_PREF_MEM == 0 +#if !CONFIG_PCI_64BIT_PREF_MEM pci_domain_read_resources(dev); #else @@ -663,7 +686,7 @@ void setup_uma_memory(void) static void domain_set_resources(device_t dev) { -#if CONFIG_PCI_64BIT_PREF_MEM == 1 +#if CONFIG_PCI_64BIT_PREF_MEM struct resource *io, *mem1, *mem2; struct resource *res; #endif @@ -676,7 +699,7 @@ static void domain_set_resources(device_t dev) u32 reset_memhole = 1; #endif -#if CONFIG_PCI_64BIT_PREF_MEM == 1 +#if CONFIG_PCI_64BIT_PREF_MEM for (link = dev->link_list; link; link = link->next) { /* Now reallocate the pci resources memory with the @@ -791,10 +814,10 @@ static void domain_set_resources(device_t dev) ram_resource(dev, (idx | i), basek, pre_sizek); idx += 0x10; sizek -= pre_sizek; -#if CONFIG_WRITE_HIGH_TABLES==1 +#if CONFIG_WRITE_HIGH_TABLES if (high_tables_base==0) { /* Leave some space for ACPI, PIRQ and MP tables */ -#if CONFIG_GFXUMA == 1 +#if CONFIG_GFXUMA high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE; #else high_tables_base = (mmio_basek * 1024) - HIGH_MEMORY_SIZE; @@ -818,12 +841,12 @@ static void domain_set_resources(device_t dev) ram_resource(dev, (idx | i), basek, sizek); idx += 0x10; -#if CONFIG_WRITE_HIGH_TABLES==1 +#if CONFIG_WRITE_HIGH_TABLES printk(BIOS_DEBUG, "node %d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", i, mmio_basek, basek, limitk); if (high_tables_base==0) { /* Leave some space for ACPI, PIRQ and MP tables */ -#if CONFIG_GFXUMA == 1 +#if CONFIG_GFXUMA high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE; #else high_tables_base = (limitk * 1024) - HIGH_MEMORY_SIZE; @@ -1018,7 +1041,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) * otherwise the device under it will not be scanned */ int linknum; -#if CONFIG_HT3_SUPPORT==1 +#if CONFIG_HT3_SUPPORT linknum = 8; #else linknum = 4;

1 0

minilzma.o
by Ali Tavakkoli 23 Jul '12

23 Jul '12

hi i want to use coreboot compiler on Ubuntu 12.04 during "make" procedure, it shows "Error 127",that says cannot find minilzma.o i found minilzma.cc in one of coreboot directory but i can't find minilzma.o in *cbfstool* directory please help me I'm a Linux beginner sorry for poor English ------- AliMohammad

1 0

New patch to review for coreboot: caea002 Re-run the git-describe if it fails at first try.
by Zheng Bao 23 Jul '12

23 Jul '12

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1261 -gerrit commit caea00287693097c2b3724485892526357e64d13 Author: zbao <fishbaozi(a)gmail.com> Date: Mon Jul 23 12:11:59 2012 +0800 Re-run the git-describe if it fails at first try. Old rev (1.6.6, in my case) git-describe doesn't take the --dirty and says error. Remove the --dirty at second try. Change-Id: Id6c6f9889ab20fb7c2b238f8c0bbe20134757369 Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: zbao <fishbaozi(a)gmail.com> --- Makefile.inc | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index 176ff67..ca1e066 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -19,7 +19,7 @@ ####################################################################### # misleadingly named, this is the coreboot version -export KERNELVERSION := $(shell if [ -d "$(top)/.git" -a -f "`which git`" ]; then git describe --dirty; else echo unknown; fi) +export KERNELVERSION := $(shell if [ -d "$(top)/.git" -a -f "`which git`" ]; then git describe --dirty 2>/dev/null || git describe; else echo unknown; fi) ####################################################################### # Basic component discovery

1 0

test rigs
by David Griffith 22 Jul '12

22 Jul '12

Would someone please recommnend a test chassis convenient for dinking around with Coreboot? -- David Griffith dave(a)661.org

2 1

Patch merged into coreboot/master: db5db28 i945: Disable IGD if plugin VGA is preferred
by gerrit＠coreboot.org 22 Jul '12

22 Jul '12

the following patch was just integrated into master: commit db5db2847ffb26c4e8181166498ae6353c65ec9c Author: Patrick Georgi <patrick.georgi(a)secunet.com> Date: Fri Jul 20 12:37:06 2012 +0200 i945: Disable IGD if plugin VGA is preferred It's shut down, but UMA memory is not reclaimed. A later extension could optionally do the magic register dance that allows initialization of IGD as secondary graphics device. Change-Id: I2a92bb71755005b886a8e1825325c678a9991bf2 Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> See http://review.coreboot.org/1252 for details. -gerrit

1 0

Patch merged into coreboot/master: 7abfd04 AMD CPUs: Updated CPU list in powernow_acpi.c
by gerrit＠coreboot.org 22 Jul '12

22 Jul '12

the following patch was just integrated into master: commit 7abfd04cf614e9edd79929478d5fb6e365c04bbf Author: Jukka Rantala <jukka.rantala(a)gmail.com> Date: Fri Jul 20 02:10:16 2012 +0300 AMD CPUs: Updated CPU list in powernow_acpi.c Updated P state table to make frequency scaling work. Added these CPUs: http://support.amd.com/us/Processor_TechDocs/30430.pdf Also wrote a Python script for parsing AMD docs, but not sure where to put it: http://pastebin.com/1dSvkXwc Change-Id: I8f08111b73b9be551f3f59d2acb15051ccf36c1e Signed-off-by: Jukka Rantala <jukka.rantala(a)gmail.com> See http://review.coreboot.org/1244 for details. -gerrit

1 0

← Newer
1
...
29
30
31
32
33
34
35
...
64
Older →

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

2009

2008

2007

2006

2005

2004

2003

2002

coreboot July 2012