coreboot July 2012

coreboot@coreboot.org

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639 discussions

New patch to review for coreboot: 1989fd3 MTRR: drop repetetive debug message
by Stefan Reinauer 23 Jul '12

23 Jul '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1272 -gerrit commit 1989fd38fdd5695c188f3c188b0176d748f70fdd Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Wed Jun 6 13:46:26 2012 -0700 MTRR: drop repetetive debug message It's not really useful anymore I guess, and it makes the log files harder to read. Hence dropping it. Change-Id: If4c3e8b40ae491ca527ef62f8145206960f6579d Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/cpu/x86/mtrr/mtrr.c | 2 -- 1 files changed, 0 insertions(+), 2 deletions(-) diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c index 77fdb6f..fdc7aa6 100644 --- a/src/cpu/x86/mtrr/mtrr.c +++ b/src/cpu/x86/mtrr/mtrr.c @@ -114,8 +114,6 @@ static void set_var_mtrr( base.hi = basek >> 22; base.lo = basek << 10; - printk(BIOS_SPEW, "ADDRESS_MASK_HIGH=%#x\n", address_mask_high); - if (sizek < 4*1024*1024) { mask.hi = address_mask_high; mask.lo = ~((sizek << 10) -1);

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New patch to review for coreboot: 6503114 Shrink the stack sizes we need in coreboot
by Stefan Reinauer 23 Jul '12

23 Jul '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1271 -gerrit commit 6503114554ab8585d0b296d06d9520d16e1df658 Author: Ronald G. Minnich <rminnich(a)chromium.org> Date: Tue Jun 5 15:13:21 2012 -0700 Shrink the stack sizes we need in coreboot We accomplish this goal by getting rid of the huge auto array in the ram stage. This will in turn let us reduce CONFIG_STACK_SIZE. We have to leave it on the stack in CAR as that's the simple way to keep it private. It does not matter then as there is only one core that is active. Change-Id: Ie37a057ccae088b7f3bb4aab6de2713e64d96df6 Signed-off-by: Ronald G. Minnich <rminnich(a)chromium.org> --- src/lib/lzma.c | 5 +++++ 1 files changed, 5 insertions(+), 0 deletions(-) diff --git a/src/lib/lzma.c b/src/lib/lzma.c index bc38f35..f0b88c1 100644 --- a/src/lib/lzma.c +++ b/src/lib/lzma.c @@ -23,6 +23,11 @@ unsigned long ulzma(unsigned char * src, unsigned char * dst) int res; CLzmaDecoderState state; SizeT mallocneeds; +#if !defined(__PRE_RAM__) + /* in ramstage, this can go in BSS */ + static +#endif + /* in pre-ram, it must go on the stack */ unsigned char scratchpad[15980]; memcpy(properties, src, LZMA_PROPERTIES_SIZE);

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New patch to review for coreboot: 32c4db4 Make memalign print useful messages on failure
by Stefan Reinauer 23 Jul '12

23 Jul '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1270 -gerrit commit 32c4db41bfa7a53adfbfcc2a4f1d4baf124c70fc Author: Ronald G. Minnich <rminnich(a)chromium.org> Date: Thu May 31 16:02:26 2012 -0700 Make memalign print useful messages on failure Brevity is the soul of wit, except for error messages; then it's a sign of witlessness. I can say this because this error message may be my fault, although it is lost in the 20th century code base so who knows. Anyway, when memalign dies, it's not a bad idea to have a lot of information about what went wrong. So instead of the terse single bit of "something failed" this patch changes things to be a bit more useful. Change-Id: I8851502297e0ae9773912839ebfdf4f9574c8087 Signed-off-by: Ronald G. Minnich <rminnich(a)chromium.org> --- src/lib/malloc.c | 11 +++++++++-- 1 files changed, 9 insertions(+), 2 deletions(-) diff --git a/src/lib/malloc.c b/src/lib/malloc.c index 2e700f7..4115738 100644 --- a/src/lib/malloc.c +++ b/src/lib/malloc.c @@ -18,7 +18,7 @@ void *memalign(size_t boundary, size_t size) { void *p; - MALLOCDBG("%s Enter, boundary %ld, size %ld, free_mem_ptr %p\n", + MALLOCDBG("%s Enter, boundary %zu, size %zu, free_mem_ptr %p\n", __func__, boundary, size, free_mem_ptr); /* Overzealous linker check */ @@ -30,8 +30,15 @@ void *memalign(size_t boundary, size_t size) p = free_mem_ptr; free_mem_ptr += size; - if (free_mem_ptr >= free_mem_end_ptr) + if (free_mem_ptr >= free_mem_end_ptr) { + printk(BIOS_ERR, "memalign(boundary=%zu, size=%zu): failed: ", + boundary, size); + printk(BIOS_ERR, "Tried to round up free_mem_ptr %p to %p\n", + p, free_mem_ptr); + printk(BIOS_ERR, "but free_mem_end_ptr is %p\n", + free_mem_end_ptr); die("Error! memalign: Out of memory (free_mem_ptr >= free_mem_end_ptr)"); + } MALLOCDBG("memalign %p\n", p);

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New patch to review for coreboot: 6a75755 SandyBridge: Add another PCI device ID for northbridge
by Stefan Reinauer 23 Jul '12

23 Jul '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1269 -gerrit commit 6a757558cd940fa2ed98b7ede00296f6dff6a6c8 Author: Walter Murphy <wmurphy(a)google.com> Date: Mon Apr 23 11:08:03 2012 -0700 SandyBridge: Add another PCI device ID for northbridge Change-Id: I153579561f7eed6d4befd74ff39e1a5e778d0e46 Signed-off-by: Walter Murphy <wmurphy(a)google.com> --- src/northbridge/intel/sandybridge/northbridge.c | 6 ++++++ 1 files changed, 6 insertions(+), 0 deletions(-) diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index b261c9d..756aacf 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -441,6 +441,12 @@ static struct device_operations mc_ops = { .ops_pci = &intel_pci_ops, }; +static const struct pci_driver mc_driver_0100 __pci_driver = { + .ops = &mc_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x0100, +}; + static const struct pci_driver mc_driver __pci_driver = { .ops = &mc_ops, .vendor = PCI_VENDOR_ID_INTEL,

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New patch to review for coreboot: 696dc0b Fixes to enable RC6 on IvyBridge
by Stefan Reinauer 23 Jul '12

23 Jul '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1268 -gerrit commit 696dc0b6d66d34d0c15798f365387ff8f1436e17 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Fri May 25 10:04:17 2012 -0700 Fixes to enable RC6 on IvyBridge - The unneeded poll on non-MT force-wake bit was timing out and causing the gma_pm_init_pre_vbios() function to exit early so it was not preparing PM registers properly. I changed the gtt_poll() calls to not return on timeout unless it can't proceed so we don't see half-initialized registers. - RC6+ (Deep Render Standby) is not working reliably so we can just enable RC6 in the BIOS and let the kernel decide if it wants to enable RC6+ later. This Kernel message is new in kernel 3.4: [drm] Enabling RC6 states: RC6 on, RC6p off, RC6pp off Change-Id: I69d005ba56be8c7684a4ea1133a1d761f7c07acc Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/northbridge/intel/sandybridge/gma.c | 59 +++++++++++-------------------- 1 files changed, 21 insertions(+), 38 deletions(-) diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c index 499f347..9a8b631 100644 --- a/src/northbridge/intel/sandybridge/gma.c +++ b/src/northbridge/intel/sandybridge/gma.c @@ -374,19 +374,11 @@ static void gma_pm_init_pre_vbios(struct device *dev) if (bridge_silicon_revision() < IVB_STEP_C0) { /* 1: Enable force wake */ gtt_write(0xa18c, 0x00000001); - if (!gtt_poll(0x130090, (1 << 0), (1 << 0))) - return; + gtt_poll(0x130090, (1 << 0), (1 << 0)); } else { gtt_write(0xa180, 1 << 5); gtt_write(0xa188, 0xffff0001); - if (!gtt_poll(0x130040, (1 << 0), (1 << 0))) - return; - /* - * HACK: also poll on 0x130090, for some reason graphics does - * not work on all SKUs unless this register is polled at boot. - */ - if (!gtt_poll(0x130090, (1 << 0), (1 << 0))) - return; + gtt_poll(0x130040, (1 << 0), (1 << 0)); } if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) { @@ -432,7 +424,7 @@ static void gma_pm_init_pre_vbios(struct device *dev) gtt_write_powermeter(ivb_pm_gt2_17w); } else if ((tdp >= 25) && (tdp <= 35)) { /* 25W-35W */ - printk(BIOS_DEBUG, "IVB GT2 35W " + printk(BIOS_DEBUG, "IVB GT2 25W-35W " "Power Meter Weights\n"); gtt_write_powermeter(ivb_pm_gt2_35w); } else { @@ -472,8 +464,7 @@ static void gma_pm_init_pre_vbios(struct device *dev) reg32 &= 0xf; reg32 |= (1 << 1); gtt_write(0x941c, reg32); - if (!gtt_poll(0x941c, (1 << 1), (0 << 1))) - return; + gtt_poll(0x941c, (1 << 1), (0 << 1)); } if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_IVB) { @@ -489,15 +480,13 @@ static void gma_pm_init_pre_vbios(struct device *dev) } /* 7 */ - if (!gtt_poll(0x138124, (1 << 31), (0 << 31))) - return; - gtt_write(0x138128, 0x00000029); /* Mailbox Data */ - gtt_write(0x138124, 0x80000004); /* Mailbox Cmd for RC6 VID */ - if (!gtt_poll(0x138124, (1 << 31), (0 << 31))) - return; - gtt_write(0x138124, 0x8000000a); /* Mailbox Cmd to clear RC6 count */ - if (!gtt_poll(0x138124, (1 << 31), (0 << 31))) - return; + if (gtt_poll(0x138124, (1 << 31), (0 << 31))) { + gtt_write(0x138128, 0x00000029); /* Mailbox Data */ + gtt_write(0x138124, 0x80000004); /* Mailbox Cmd for RC6 VID */ + if (gtt_poll(0x138124, (1 << 31), (0 << 31))) + gtt_write(0x138124, 0x8000000a); + gtt_poll(0x138124, (1 << 31), (0 << 31)); + } /* 8 */ gtt_write(0xa090, 0x00000000); /* RC Control */ @@ -530,8 +519,13 @@ static void gma_pm_init_pre_vbios(struct device *dev) /* 11a: Enable Render Standby (RC6) */ if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_IVB) { - /* on IVB: also enable DeepRenderStandby */ - gtt_write(0xa090, 0x88060000); /* HW RC Control */ + /* + * IvyBridge should also support DeepRenderStandby. + * + * Unfortunately it does not work reliably on all SKUs so + * disable it here and it can be enabled by the kernel. + */ + gtt_write(0xa090, 0x88040000); /* HW RC Control */ } else { gtt_write(0xa090, 0x88040000); /* HW RC Control */ } @@ -566,22 +560,11 @@ static void gma_pm_init_post_vbios(struct device *dev) /* 15: Deassert Force Wake */ if (bridge_silicon_revision() < IVB_STEP_C0) { gtt_write(0xa18c, gtt_read(0xa18c) & ~1); - if (!gtt_poll(0x130090, (1 << 0), (0 << 0))) { - return; - } + gtt_poll(0x130090, (1 << 0), (0 << 0)); } else { gtt_write(0xa188, 0x1fffe); - if (!gtt_poll(0x130040, (1 << 0), (0 << 0))) { - return; - } - /* - * HACK: also poll on 0x130090, for some reason graphics does - * not work on all SKUs unless this register is polled at boot. - */ - if (!gtt_poll(0x130090, (1 << 0), (0 << 0))) { - return; - } - gtt_write(0xa188, gtt_read(0xa188) | 1); + if (gtt_poll(0x130040, (1 << 0), (0 << 0))) + gtt_write(0xa188, gtt_read(0xa188) | 1); } /* 16: SW RC Control */

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Patch merged into coreboot/master: d74f2d2 Re-initialize Local APIC timer on APs
by gerrit＠coreboot.org 23 Jul '12

23 Jul '12

the following patch was just integrated into master: commit d74f2d22cc0c7c9d72be2fdf329baf44dbbbdb21 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Tue Jul 10 15:19:23 2012 -0700 Re-initialize Local APIC timer on APs In order to be able to use udelay in code running on AP cores the timer has to be initialized on the according local APICs or the system will just hang when udelay is used. Change-Id: I776bc96aa6d876ff2582d0c05cbc9c7611cb06b5 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> See http://review.coreboot.org/1267 for details. -gerrit

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New patch to review for coreboot: d74f2d2 Re-initialize Local APIC timer on APs
by Stefan Reinauer 23 Jul '12

23 Jul '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1267 -gerrit commit d74f2d22cc0c7c9d72be2fdf329baf44dbbbdb21 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Tue Jul 10 15:19:23 2012 -0700 Re-initialize Local APIC timer on APs In order to be able to use udelay in code running on AP cores the timer has to be initialized on the according local APICs or the system will just hang when udelay is used. Change-Id: I776bc96aa6d876ff2582d0c05cbc9c7611cb06b5 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/cpu/x86/lapic/apic_timer.c | 4 +++- 1 files changed, 3 insertions(+), 1 deletions(-) diff --git a/src/cpu/x86/lapic/apic_timer.c b/src/cpu/x86/lapic/apic_timer.c index a4106d4..1fd0c60 100644 --- a/src/cpu/x86/lapic/apic_timer.c +++ b/src/cpu/x86/lapic/apic_timer.c @@ -79,7 +79,9 @@ void udelay(u32 usecs) { u32 start, value, ticks; - if (!timer_fsb) + if (!timer_fsb || (lapic_read(LAPIC_LVTT) & + (LAPIC_LVT_TIMER_PERIODIC | LAPIC_LVT_MASKED)) != + (LAPIC_LVT_TIMER_PERIODIC | LAPIC_LVT_MASKED)) init_timer(); /* Calculate the number of ticks to run, our FSB runs at timer_fsb Mhz */

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Patch merged into coreboot/master: 2758498 AMD and GFXUMA: drop redundant use of lb_add_memory_range()
by gerrit＠coreboot.org 23 Jul '12

23 Jul '12

the following patch was just integrated into master: commit 27584986fb9c8be478d635fb0c456c293ceac62b Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Jul 10 14:26:43 2012 +0300 AMD and GFXUMA: drop redundant use of lb_add_memory_range() Use of uma_resource() in AMD northbridge code created a memory resource marked as reserved. Such resources are removed from system memory in write_coreboot_table(). Change-Id: Ib5e49e851d6622d8ece9d6d612e245b3962b9167 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Build-Tested: build bot (Jenkins) at Tue Jul 17 16:24:24 2012, giving +1 Reviewed-By: Rudolf Marek <r.marek(a)assembler.cz> at Mon Jul 23 17:44:13 2012, giving +2 See http://review.coreboot.org/1233 for details. -gerrit

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usb stick payload?
by Motiejus Jakštys 23 Jul '12

23 Jul '12

Hi, I have thinkpad X60s with coreboot and with only one payload: SATA hard drive. I would like to add a "boot from usb stick" option. However, can't find the payload (i.e. source to generate the necessary coreboot ELF file). Wiki mentions that I need the coreboot payload ELF, doesn't mention where to get it. :) I would appreciate some directions. Thanks, Motiejus Jakštys

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Trac reminder: list of new ticket(s)
by coreboot tracker 23 Jul '12

23 Jul '12

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coreboot July 2012